CN113471285B - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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CN113471285B
CN113471285B CN202010238785.1A CN202010238785A CN113471285B CN 113471285 B CN113471285 B CN 113471285B CN 202010238785 A CN202010238785 A CN 202010238785A CN 113471285 B CN113471285 B CN 113471285B
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side wall
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CN113471285A (zh
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张黎
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Abstract

本发明涉及一种半导体结构的制备方法，提供衬底；于衬底上形成至少一对第一侧壁；采用原位水汽氧化工艺于第一侧壁的两侧侧壁形成第二侧壁，并于各对中的两第一侧壁之间的衬底上形成栅氧化层；于栅氧化层的表面形成栅极层。由于第二侧壁通过原位水汽氧化形成，因此第二侧壁的击穿电压更高且第二侧壁内产生的缺陷更少，且第一侧壁的两侧均形成有第二侧壁，一方面提高了第一侧壁与第二侧壁降低栅极漏电流的能力，另一方面，第一侧壁两侧均形成有第二侧壁使得第一侧壁两侧第二侧壁在厚度上可以降低，从而减小了第二侧壁中出现缺陷的可能性，从而进一步的提高第一侧壁与第二侧壁降低栅极漏电流的能力，提高器件的可靠性和使用寿命。

Description

半导体结构及其制备方法
技术领域
本发明涉及半导体领域，特别是涉及半导体结构及其制备方法。
背景技术
随着CMOS器件尺寸不断减小到次微米级，正如摩尔定律的预测，在高效率、高密度集成电路中的晶体管数量上升到几千万个，随之而来的是栅极侧壁厚度和栅氧化层厚度等的不断减小，现有工艺中的栅极侧壁中的侧壁氧化层一般采用原子层沉积(ALD)工艺形成，原子层沉积工艺形成侧壁氧化层内具有较多缺陷，击穿电压较低，这将导致栅极漏电流增加，这对器件的可靠性及使用寿命都有很大的影响。
发明内容
基于此，有必要针对上述问题，提供一种半导体结构及其制备方法，其具有减小栅极漏电流的效果。
一种半导体结构的制备方法，
提供衬底；
于所述衬底上形成至少一对第一侧壁，各对中的两所述第一侧壁之间存在间距；
采用原位水汽氧化工艺于所述第一侧壁的两侧侧壁形成第二侧壁，并于各对中的两所述第一侧壁之间的衬底上形成栅氧化层；
于所述栅氧化层的表面形成栅极层。
通过上述技术方案，由于第二侧壁通过原位水汽氧化形成，因此第二侧壁的击穿电压更高且第二侧壁内产生的缺陷更少，且第一侧壁的两侧均形成有第二侧壁，一方面提高了第一侧壁与第二侧壁降低栅极漏电流的能力，另一方面，第一侧壁两侧均形成有第二侧壁使得第一侧壁两侧第二侧壁在厚度上可以降低，从而减小了第二侧壁中出现缺陷的可能性，从而进一步的提高第一侧壁与第二侧壁降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
在其中一个实施例中，于所述衬底上形成所述第一侧壁包括：
于所述衬底上形成牺牲层；
于所述牺牲层内形成侧壁凹槽；
于所述侧壁凹槽内形成第一侧壁；
去除所述牺牲层。
在其中一个实施例中，所述第一侧壁包括含硅介电层。
在其中一个实施例中，所述第一侧壁包括氮化硅层或二氧化硅层；所述第二侧壁包二氧化硅层。
在其中一个实施例中，所述衬底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构于所述衬底内隔离出若干个有源区；所述第一侧壁、所述第二侧壁及所述栅氧化层均位于所述有源区上。
在其中一个实施例中，形成所述栅极层后还包括于所述栅极层的表面形成顶层介质层的步骤。
在其中一个实施例中，所述顶层介质层包括氮化硅层或氧化硅层。
在其中一个实施例中，采用所述原位水汽氧化工艺形成所述第二侧壁的反应温度为包括800℃～1100℃，反应压力包括6Torr～20Torr。
在其中一个实施例中，采用所述原位水汽氧化工艺形成所述第二侧壁的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体。
在其中一个实施例中，所述混合气体中所述氢气的体积浓度为1％～33％。
在其中一个实施例中，所述半导体结构基于上述半导体结构的制备方法制备而成。
附图说明
图1本发明一个实施例展示半导体结构的制备方法流程图；
图2为本发明另一个实施例展示半导体结构的制备方法流程图；
图3为本发明的一个实施例于衬底上形成牺牲层后的截面结构示意图；
图4为本发明的一个实施例形成光刻胶层后的截面结构示意图；
图5为本发明的一个实施例形成侧壁凹槽后的截面结构示意图；
图6为本发明的一个实施例形成第一侧壁后的截面结构示意图；
图7为本发明的一个实施例去除牺牲层后的截面结构示意图；
图8为本发明的另一个实施例于衬底上形成牺牲层后的截面结构示意图；
图9为本发明的另一个实施例形成第一侧壁材料层后的截面结构示意图；
图10为本发明的另一个实施例去除衬底上表面及牺牲层上表面的第一侧壁材料层后的截面结构示意图；
图11为本发明的另一个实施例去除牺牲层后的截面结构示意图；
图12为本发明的一个实施例形成第二侧壁和栅氧化层后的截面结构示意图；
图13为本发明的另一个实施例形成第二侧壁后的截面结构示意图；
图14为本发明的另一个实施例形成栅氧化层后的截面结构示意图；
图15为本发明的一个实施例形成栅极层后的截面结构示意图；
图16为本发明的一个实施例形成顶层介质层后的截面结构示意图；其中，图16为本发明一个实施例展示半导体结构的截面结构示意图。
附图标记：10、衬底；11、第一侧壁；12、第二侧壁；13、栅氧化层；14、栅极层；15、牺牲层；16、侧壁凹槽；17、光刻胶层；18、顶层介质层；19、浅沟槽隔离结构；20、第一侧壁材料层。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
本发明提供了一种半导体结构的制备方法，如图1所示，具体包括以下步骤：
步骤S10：提供衬底10。
步骤S20：于衬底10上形成至少一对第一侧壁11，各对中的两第一侧壁11 之间存在间距。
步骤S30：采用原位水汽氧化工艺于第一侧壁11的两侧侧壁形成第二侧壁 12，并于各对中的两第一侧壁11之间的衬底10上形成栅氧化层13。
步骤S40：于栅氧化层13的表面形成栅极层14。
在一个可选的实施例中，对于步骤S10，如图3所示，具体的，衬底10可以为硅衬底、绝缘体上硅衬底或者包括III族、IV族和V族的其他半导体材料。衬底10内形成有浅沟槽隔离结构19，浅沟槽隔离结构19于衬底10内隔离出若干个有源区，有源区可以为掺杂有掺杂离子的区域，譬如，N型离子或P型离子等等；若干个有源区于衬底10内间隔排布。
在一个可选的实施例中，对于步骤S20，具体的包括以下步骤：
步骤S201：于衬底10上形成牺牲层15，如图3所示；
步骤S202：于牺牲层15内形成侧壁凹槽16，如图5所示；
步骤S203：于侧壁凹槽16内形成第一侧壁11，如图6所示；
步骤S204：去除牺牲层15，如图7所示。
上述步骤中，如图4所示，通过在牺牲层15上形成光刻胶层17，并通过曝光显影对光刻胶层17进行图形化处理，暴露出部分牺牲层15，通过干法刻蚀去除暴露的牺牲层15从而得到两个侧壁凹槽16。牺牲层15可以为氧化层，牺牲层15与第一侧壁11的材质有较高的刻蚀选择比，第一侧壁11的材质可以为沉积形成的含硅介电层，在一个可选的实施例中，第一侧壁11包括氮化硅层或二氧化硅层，当第一侧壁11为氮化硅层时，牺牲层15可以为二氧化硅层，在形成第一侧壁11后采用湿法刻蚀工艺去除牺牲层15。两个第一侧壁11之间存在间距，间距的大小根据后续工艺中所得的栅极层14的大小而定，两个第一侧壁 11位于栅极层14的两端。
在一个其他可选的实施例中，对于步骤S20，具体的包括以下步骤：
步骤S201：于衬底10上形成牺牲层15，如图8所示。
步骤S202：于牺牲层15的上表面、牺牲层15的侧壁及衬底10的上表面形成第一侧壁材料层20，如图9所述。
步骤S203：去除牺牲层15上表面及衬底10上表面的第一侧壁材料层20，保留牺牲层15侧壁上的第一侧壁材料层20以形成第一侧壁11，如图10所示。
步骤S204：去除牺牲层15，如图11所示。
具体的，可以通过沉积工艺在衬底10的上表面形成牺牲层15，牺牲层15 的材质可以为氧化物，如二氧化硅。第一侧壁材料层20同样可通过沉积工艺形成于衬底10的上表面、牺牲层15的上表面和牺牲层15的侧壁上，第一侧壁材料层20的材质可以为含硅介电层。在一个可选的实施例中，第一侧壁材料层20 的材质包括氮化硅层或二氧化硅层，其中牺牲层15与第一侧壁材料层20之间具有较大的刻蚀选择比，当第一侧壁材料层20的材质为氮化硅层时，牺牲层15 可以为二氧化硅层。在去除牺牲层15上表面及衬底10上表面的第一侧壁材料层20时可以通过干法刻蚀工艺，对于牺牲层15上表面的第一侧壁材料层20还可以通过化学机械研磨工艺去除，牺牲层15则可通过湿法刻蚀工艺去除。去除牺牲层15后得到的两个第一侧壁11之间存在间距，间距的大小根据后续工艺中所得的栅极层14的大小而定，两个第一侧壁11位于栅极层14的两端。
在一个可选的实施例中，对于步骤S30，如图12所示，采用的原位水汽氧化工艺形成第二侧壁12的温度包括800℃～1100℃，在一个可选的实施例中，形成第二侧壁12的温度可以为800℃、900℃、1000℃或1100℃。原位水汽氧化工艺的反应压力包括6Torr～20Torr，在一个可选的实施例中，采用的反应压力可以为6Torr、8Torr、12Torr或20Torr。在采用原位水汽氧化(ISSG)工艺形成第二侧壁12的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体，其中，氢气的体积浓度为1％～33％，在一个可选的实施例中，氢气的体积浓度可以采用1％、10％、20％或33％。
在第一侧壁11的两侧形成第二侧壁12的同时还于一对第一侧壁11之间形成栅氧化层13，在一个可选的实施例中，第二侧壁12与栅氧化层13的材质均为氧化物，可以为二氧化硅。第二侧壁12与栅氧化层13可以采用同一原位水汽氧化工艺形成。第一侧壁11的厚度大小大于第二侧壁的12的厚度大小。
在其他可选的实施例中，如图13和图14所示，先于第一侧壁11的两侧通过原位水汽氧化工艺形成第二侧壁12，再通过原位水汽氧化工艺或其他工艺，如沉积工艺，于两第一侧壁11之间的衬底10上表面形成栅氧化层13，第二侧壁12与栅氧化层13的材质均为氧化物，可以同为二氧化硅。
对于步骤S40，如图15所示，具体的，于一对第一侧壁11之间的栅氧化层 13上表面沉积多晶硅或金属以形成栅极层14，并栅极层14填充于一对第一侧壁11上的第二侧壁12之间，且栅极层14的上表面低于第一侧壁11的上表面。
如图2所示，在一个可选的实施例中，步骤S40之后还包括步骤S50；
步骤S50：于栅极层14的表面形成顶层介质层18，如图16所示。
对于步骤S50，具体的，通过沉积工艺于 栅极层14的上表面沉积氮化硅或氧化硅以形成顶层介质材料层，经过平坦化工艺后形成顶层介质层18，顶层介质层18的上表面与第一侧壁11的上表面平齐。
通过上述半导体结构的制备方法，由于第二侧壁12通过原位水汽氧化形成，因此第二侧壁12的击穿电压更高且第二侧壁12内产生的缺陷更少，且第一侧壁11的两侧均形成有第二侧壁12，一方面提高了第一侧壁11与第二侧壁12降低栅极漏电流的能力，另一方面，第一侧壁11两侧均形成有第二侧壁12使得第一侧壁11两侧第二侧壁12在厚度上可以降低，从而减小了第二侧壁12中出现缺陷的可能性，从而进一步的提高第一侧壁11与第二侧壁12降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
本发明还提供了一种半导体结构，如图16所示，该半导体结构基于上述半导体结构的制备方法制备而成，包括衬底10，衬底可以为硅衬底、绝缘体上硅衬底或者包括III族、IV族和V族的其他半导体材料。衬底10内形成有浅沟槽隔离结构19，浅沟槽隔离结构19于衬底10内隔离出若干个有源区，有源区可以为掺杂有掺杂离子的区域，譬如，N型离子或P型离子等等；若干个有源区于衬底10内间隔排布。
有源区上形成有至少一对第一侧壁11，且各对中的第一侧壁11之间存在间距，第一侧壁11的材质可以为沉积形成的含硅介电层，在一个可选的实施例中，第一侧壁11包括氮化硅层或二氧化硅层。
第一侧壁11的两侧均形成有第二侧壁12，且一对第一侧壁11之间的有源区上形成有栅氧化层13，第二侧壁12与栅氧化层13相连，第二侧壁12与栅氧化层13的材质均为氧化物，在一个可选的实施例中可以为二氧化硅。第二侧壁 12与栅氧化层13可以采用同一原位水汽氧化工艺形成。
栅氧化层13的上表面通过沉积多晶硅形成有栅极层14，栅极层14填充于一对第一侧壁11上的第二侧壁12之间，且栅极层14的上表面低于第一侧壁11 的上表面。
在其可选的实施例中，栅极层14的上表面还形成有顶层介质层18，顶层介质层18的材料可以为氮化硅或氧化硅，对栅极层14起到保护作用。
通过上述半导体结构，第一侧壁11的两侧均形成有第二侧壁12，一方面提高了第一侧壁11与第二侧壁12降低栅极漏电流的能力，另一方面，第一侧壁 11两侧均形成有第二侧壁12使得第一侧壁11两侧第二侧壁12在厚度上可以降低，从而减小了第二侧壁12中出现缺陷的可能性，从而进一步的提高第一侧壁 11与第二侧壁12降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (11)

1.一种半导体结构的制备方法，其特征在于，
提供衬底；
于所述衬底上形成至少一对第一侧壁，各对中的两所述第一侧壁之间存在间距；
采用原位水汽氧化工艺于所述第一侧壁的两侧侧壁形成第二侧壁，并于各对中的两所述第一侧壁之间的衬底上形成栅氧化层；
于所述栅氧化层的表面形成栅极层。
2.根据权利要求1所述的半导体结构的制备方法，其特征在于，于所述衬底上形成所述第一侧壁包括：
于所述衬底上形成牺牲层；
于所述牺牲层上形成第一侧壁；
去除所述牺牲层。
3.根据权利要求2所述的半导体结构的制备方法，其特征在于，于所述牺牲层上形成所述第一侧壁包括：
于所述牺牲层内形成侧壁凹槽；
于所述侧壁凹槽内形成第一侧壁。
4.根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第一侧壁包括含硅介电层。
5.根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第一侧壁包括氮化硅层或二氧化硅层；所述第二侧壁包括二氧化硅层。
6.根据权利要求1所述的半导体结构的制备方法，其特征在于，形成所述栅极层后还包括于所述栅极层的表面形成顶层介质层的步骤。
7.根据权利要求6所述的半导体结构的制备方法，其特征在于，所述顶层介质层包括氮化硅层或氧化硅层。
8.根据权利要求1至7中任一项所述的半导体结构的制备方法，其特征在于，
采用所述原位水汽氧化工艺形成所述第二侧壁的反应温度为包括800℃～1100℃，反应压力包括6Torr～20Torr。
9.根据权利要求1至7中任一项所述的半导体结构的制备方法，其特征在于，
采用所述原位水汽氧化工艺形成所述第二侧壁的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体。
10.根据权利要求9所述的半导体结构的制备方法，其特征在于，
所述混合气体中所述氢气的体积浓度为1％～33％。
11.一种半导体结构，其特征在于，所述半导体结构基于权利要求1至10中任一项半导体结构的制备方法制备而成。
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