WO2021185062A1 - 半导体结构及形成方法 - Google Patents

半导体结构及形成方法 Download PDF

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Publication number
WO2021185062A1
WO2021185062A1 PCT/CN2021/078515 CN2021078515W WO2021185062A1 WO 2021185062 A1 WO2021185062 A1 WO 2021185062A1 CN 2021078515 W CN2021078515 W CN 2021078515W WO 2021185062 A1 WO2021185062 A1 WO 2021185062A1
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WIPO (PCT)
Prior art keywords
bit line
dielectric layer
line contact
contact window
forming
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PCT/CN2021/078515
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English (en)
French (fr)
Inventor
宛伟
Original Assignee
长鑫存储技术有限公司
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Priority to US17/370,323 priority Critical patent/US20210335795A1/en
Publication of WO2021185062A1 publication Critical patent/WO2021185062A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • This application relates to the field of semiconductor devices and manufacturing, in particular to a semiconductor structure and a method of forming it.
  • Dynamic Random Access Memory (English: Dynamic Random Access Memory, referred to as: DRAM) is a kind of semiconductor memory widely used in products such as mobile phones, computers and automobiles.
  • DRAM Dynamic Random Access Memory
  • the feature size of integrated circuit devices continues to shrink, and the critical size of DRAM is getting smaller and smaller, and the difficulty of manufacturing is correspondingly increasing.
  • related technologies for DRAM manufacturing will continue to be smaller.
  • the electrical requirements of DRAM products are very strict.
  • the embodiments of the present application provide a semiconductor structure and a forming method.
  • backfilling the etching defects at the bottom of the bit line contact window the distance between the bit line contact window and the buried word line structure is increased, and the etching defects are avoided.
  • the resulting short-circuit between the bit line contact window and the buried word line structure increase in parasitic capacitance, or decrease in electrical performance of the DRAM due to a strong electric field.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate.
  • the semiconductor substrate has formed an isolation structure, an active region, and a buried word line structure.
  • a first dielectric layer is formed on the top of the line structure; the position of the bit line contact opening is determined on the top surface of the semiconductor substrate and the top surface of the first dielectric layer, the bit line contact opening at least exposes a part of the active area, and the bit line contact opening at least Part of the first dielectric layer or part of the isolation structure is also exposed; according to the position of the bit line contact opening, the active region, the first dielectric layer and the isolation structure exposed by the bit line contact opening are etched until the active region is etched to A bit line contact window is formed at a predetermined depth; a second dielectric layer is formed on the surface of the isolation structure and the surface of the first dielectric layer whose depth is greater than the surface of the active region in the bit line contact window.
  • the embodiment of the present application improves the method for forming the bit line contact window.
  • the position of the bit line contact opening is determined on the semiconductor substrate, and the semiconductor substrate exposed by the bit line contact opening is etched to the predetermined position.
  • the dielectric layer compensates for this part of the etching defect, increases the distance between the bit line contact window and the buried word line structure, and avoids the bit line contact window and the buried word line structure caused by the etching defect There may be short-circuiting or DRAM electrical performance degradation caused by strong electric fields.
  • the top surface of the second dielectric layer is flush with the preset depth.
  • determining the position of the bit line contact opening on the top surface of the semiconductor substrate and the top surface of the first dielectric layer includes: forming a third dielectric layer on the top surface of the semiconductor substrate and the top surface of the first dielectric layer; The bit line contact opening is formed in the third dielectric layer.
  • forming the bit line contact opening in the third dielectric layer specifically includes: forming a mask layer on the top surface of the third dielectric layer, and forming an etching pattern required for subsequent formation of the bit line contact opening on the mask layer; wherein, The orthographic projection of the etching pattern on the semiconductor substrate covers the active area between adjacent buried word line structures; according to the etching pattern, the third dielectric layer is etched to form a bit line contact opening.
  • the edge topography of the bit line contact window is improved by the etching pattern in the mask layer, so that the orthographic projection of the bit line contact window on the surface of the semiconductor substrate can completely cover the area between adjacent buried word line structures.
  • Source area When the gap is filled with silicon nitride later, the bit line contact window can completely isolate the active area and the capacitive contact window, which solves the problem of short-circuiting between the capacitive contact window and the active area.
  • the method further includes: etching and removing the mask layer on the top surface of the third dielectric layer.
  • the etching pattern is rectangular.
  • forming a mask layer on the top surface of the third dielectric layer, and forming an etching pattern required for subsequent formation of bit line contact openings on the mask layer specifically including: forming a sub-mask layer on the top surface of the third dielectric layer; An anti-reflection layer is formed on the top surface of the sub-mask layer; a photoresist is formed on the top surface of the anti-reflection layer; an etching pattern is formed on the photoresist.
  • the thickness of the sub-mask layer is 30 nm to 150 nm; the thickness of the photoresist is 50 nm to 250 nm; and the thickness of the third dielectric layer is 50 nm to 300 nm.
  • forming the second dielectric layer on the surface of the isolation structure whose depth is greater than the surface of the active region in the bit line contact window and the surface of the first dielectric layer includes: filling the bit line contact window to form a second dielectric intermediate layer; The layer is etched back to form a second dielectric layer; wherein the etch back is a second dielectric intermediate layer whose etching depth is smaller than the surface of the active region.
  • the filling is non-conformal filling.
  • the embodiment of the present application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate has formed an isolation structure, an active area, and a buried word line structure, and a first dielectric layer is formed on the top of the buried word line structure ; Bit line contact window, the bit line contact window is located in a predetermined depth of the semiconductor substrate; wherein the bit line contact window exposes at least part of the active area, and the bit line contact window also exposes at least part of the first dielectric layer or part of the isolation structure;
  • the second dielectric layer is located at the bottom of the bit line contact window and has a depth greater than the surface of the isolation structure or the surface of the first dielectric layer that is greater than the surface of the active area in the bit line contact window.
  • the embodiment of the present application increases the distance between the bit line contact window and the buried word line structure through the second dielectric layer, and avoids the bit line contact window and the buried word line structure caused by etching defects.
  • the problem of short-circuiting, increased parasitic capacitance, or degradation of DRAM electrical performance due to strong electric fields may occur between the type word line structures.
  • the orthographic projection of the bit line contact window on the semiconductor substrate covers the active area between adjacent buried word line structures.
  • the edge morphology of the bit line contact window is improved, and the orthographic projection of the formed bit line contact window on the semiconductor substrate can completely cover the active area, so that the subsequent gap filling process can be completely isolated by the bit line contact window.
  • the active area and the capacitive contact window avoid possible short-circuit problems between the active area and the capacitive contact window.
  • FIG. 1 is a schematic top view of a semiconductor substrate related to an embodiment of the application
  • FIG. 2 is a schematic top view of a semiconductor structure after forming a bit line contact window and a capacitor contact window according to an embodiment of the application;
  • 3 to 7 are schematic cross-sectional views of the semiconductor structure in the direction perpendicular to the bit line in the semiconductor forming method according to an embodiment of the application;
  • FIGS. 8 to 12 are schematic cross-sectional views of the semiconductor structure in a direction parallel to the bit line in the semiconductor forming method according to an embodiment of the application;
  • FIGS. 13-16 are cross-sectional schematic diagrams of the backfill process of the semiconductor structure perpendicular to the bit line direction according to an embodiment of the application;
  • 17-20 are cross-sectional schematic diagrams of the backfill process of the semiconductor structure parallel to the bit line direction according to an embodiment of the application;
  • 21 and 22 are schematic diagrams of a semiconductor structure related to another embodiment of the application.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate has formed an isolation structure, an active region, and a buried word line structure, and the buried word A first dielectric layer is formed on the top of the line structure; the position of the bit line contact opening is determined on the top surface of the semiconductor substrate and the top surface of the first dielectric layer; according to the position of the bit line contact opening, the exposed bit line contact opening is etched The active region, the first dielectric layer and the isolation structure are etched until the active region is etched to a predetermined depth to form a bit line contact window; the second dielectric layer is formed to have an isolation structure with a depth greater than the surface of the active region in the bit line contact window The surface and the surface of the first dielectric layer.
  • FIG. 1 is a schematic top view of the semiconductor substrate involved in this embodiment
  • FIG. 2 is a schematic top view of the semiconductor structure after forming a bit line contact window and a capacitor contact window in this embodiment
  • FIGS. 3 to 7 are the semiconductor structure involved in this embodiment.
  • FIGS. 8 to 12 are schematic cross-sectional views of the semiconductor structure in the direction parallel to the bit line in the semiconductor forming method according to this embodiment.
  • FIGS. 13 to 16 are The cross-sectional schematic diagram of the backfill process of the semiconductor structure in the direction perpendicular to the bit line involved in this embodiment.
  • FIGS. 17-20 are cross-sectional schematic diagrams of the backfill process of the semiconductor structure in the direction parallel to the bit line involved in this embodiment.
  • the implementation details of the method for forming the semiconductor structure will be described in detail.
  • FIG. 1 shows the layout of the active region 103 and the buried word line structure 106 in the semiconductor substrate 101.
  • FIG. 2 the figure shows the positional relationship between the bit line contact window 105, the capacitive contact window 104 and the buried word line structure 106 formed by the embodiment of the present application, and the bit line contact window 105 completely covers the buried word The active region 103 between the line structures 106.
  • the orthographic projection of the formed bit line contact window 105 on the semiconductor substrate 101 can completely cover the active region 103, so that the bit line contact window 105 can completely isolate the active region 103 and the capacitive contact window 104 when filling the gap later, avoiding This solves the possible short-circuit problem between the active region 103 and the capacitive contact window 104.
  • bit line contact window 105 and the capacitor contact window 104 are shown as rectangles, just to cut off the active area 103 on the top plane, so as to facilitate those skilled in the art to understand the solution. It does not constitute a limitation to this solution; in practical applications, the bit line contact window 105 and the capacitor contact window 104 can be set to be oval, circular, or trapezoidal, etc., but as long as it conforms to the position of the bit line contact window 105 on the semiconductor substrate 101
  • the orthographic projection completely covers the active area 103, that is, it is within the protection scope of the present application.
  • FIGS. 3-11 The cross-sectional schematic diagrams perpendicular to the buried word line structure 106 are shown in FIGS. 3-11.
  • the semiconductor substrate structure provided in the figures is a schematic structural diagram, which is intended to let those skilled in the art understand the implementation method of this solution, and does not constitute Restrictions on this program.
  • the semiconductor forming method includes:
  • the semiconductor substrate 101 has formed an isolation structure 111, an active region (not shown), and a buried word line structure 106.
  • a first dielectric layer 107 is formed on the top of the buried word line structure 106;
  • the situation where the top surface of the first dielectric layer 107 is flush with the top surface of the semiconductor substrate 101 is described in detail; it is clear to those skilled in the art that the top surface of the first dielectric layer 107 defined in the embodiment is flush with the semiconductor substrate 101.
  • the fact that the top surface of the substrate 101 is flush does not limit the composition of the present application, but is only for clearly introducing the implementation process of the solution.
  • the material of the semiconductor substrate 101 includes silicon, silicon carbide, gallium arsenide, aluminum nitride, or zinc oxide; in this embodiment, the semiconductor substrate 101 is formed of silicon material, and this embodiment uses silicon material as The semiconductor substrate 101 is for the convenience of those skilled in the art to understand the subsequent forming method, and does not constitute a limitation. In the actual application process, a suitable material of the semiconductor substrate 101 can be selected according to requirements.
  • the buried word line structure 106 is located in the semiconductor substrate 101, the top of the buried word line structure 106 has a first dielectric layer 107, and the top surface of the first dielectric layer 107 is flush with the top surface of the semiconductor substrate 101
  • the active region (not shown) defined by the isolation structure 111 includes a portion between the buried word line structure 106.
  • the isolation structure 111 uses a shallow trench isolation trench.
  • S102, a third dielectric layer 201 is formed on the top surface of the semiconductor substrate 101 and the top surface of the first dielectric layer 107.
  • the third dielectric layer 201 is formed, and then the bit line contact opening 401 is formed in the third dielectric layer 201 as an example for description, which does not constitute a limitation to the solution.
  • the position of the bit line contact opening can be determined directly on the top surface of the semiconductor substrate and the top surface of the first dielectric layer, and the position of the bit line contact opening is directly etched to form the bit line contact window in the subsequent process.
  • the material of the third dielectric layer 201 may be silicon nitride, silicon oxide, or silicon oxynitride.
  • the thickness of the third dielectric layer 201 is 50 nm to 300 nm, such as 100 nm, 150 nm, 200 nm, or 250 nm.
  • bit line contact opening 401 is formed in the third dielectric layer 201, and the bit line contact opening 401 exposes at least a part of the active region (not shown) and a part of the first dielectric layer 107.
  • a mask layer 301 is formed on the top surface of the third dielectric layer 201, and an etching pattern required for subsequent formation of the bit line contact opening 401 is formed on the mask layer 301.
  • the orthographic projection of the etching pattern on the semiconductor substrate 101 is located between the adjacent buried word line structures 106 and completely covers the active area between the adjacent buried word line structures.
  • the mask layer 301 includes a sub-mask layer 311, an anti-reflection layer 321 and a photoresist 331.
  • a sub-mask layer 311 is formed on the top surface of the third dielectric layer 201
  • an anti-reflection layer 321 is formed on the top surface of the sub-mask layer 311
  • a photoresist 331 is formed on the top surface of the anti-reflection layer 321; the etching pattern is formed in On the photoresist 331.
  • the material of the sub-mask layer 311 includes carbon, silicon, silicon oxide, or silicon nitride.
  • the thickness of the sub-mask layer 311 is 30 nm to 150 nm, such as 50 nm, 80 nm, 100 nm, or 130 nm;
  • the thickness of the resist is 50 nm to 250 nm, such as 100 nm, 150 nm, or 200 nm.
  • the third dielectric layer 201 is etched to form a bit line contact opening 401; the mask layer 301 on the top surface of the third dielectric layer 201 is etched and removed; that is, the structure shown in FIG. 5 is formed.
  • the etching is performed through the etching pattern on the photoresist 331, the anti-reflective layer 321, the sub-mask layer 311, and the third dielectric layer 201 are sequentially etched to form openings, and then the remaining photoresist 331 is etched away
  • the anti-reflective layer 321 and the sub-mask layer 311 form a bit line contact opening 401.
  • the bit line contact opening 401 only reduces the height of the opening, and its bottom structure does not change.
  • the mask layer 301 on the top surface of the third dielectric layer 201 can be etched and removed after the bit line contact opening 401 is formed by etching, or it can be etched after the bit line contact window 105 is formed by subsequent etching. Etching and removal.
  • the mask layer 301 on the top surface of the third dielectric layer 201 is etched to remove the mask layer 301 and then the mask layer 301 is etched to remove the mask layer 301 as an example for description, which does not constitute a limitation of the present application.
  • the active region (not shown) at the bottom of the bit line contact opening 401 and the first dielectric layer 107 are etched to a predetermined depth to form a bit line contact window 105.
  • the partially buried word line structure 106 is located in the isolation structure 111. While transferring the etching pattern on the photoresist 331 to the surface of the semiconductor substrate 101, due to the position The bottom of the line contact opening 401 has a part of the surface of the first dielectric layer 107, a part of the surface of the semiconductor substrate 101, and a part of the surface of the isolation structure 111. Due to the different selection ratios of etching materials (usually the etching materials have an etching effect on silicon oxide and silicon nitride). The rate is greater than that of silicon).
  • the etching rate of the first dielectric layer 107 and the isolation structure 111 is greater than that of the semiconductor substrate 101.
  • voids namely, etching defects 501, will be formed.
  • the distance between the bit line contact 105 and the buried word line structure 106 formed by the post-filling is too close, resulting in a short circuit between the bit line contact 105 and the buried word line structure 106 or electrical power caused by a strong electric field. The problem of performance degradation.
  • S105-1 filling the bit line contact window to form a second dielectric intermediate layer 601;
  • a second dielectric intermediate layer 601 is formed on the top surface of the third dielectric layer 201 and the bit line contact window 105.
  • the material of the second dielectric intermediate layer 601 is usually silicon oxide.
  • bit line contact window 105 is filled with non-conformal filling.
  • bit line contact window may also be filled with a conformal filling method.
  • the second dielectric intermediate layer 601 is etched back to form a second dielectric layer 602; wherein, the etch back is the second dielectric intermediate layer 601 whose etching depth is smaller than the surface of the active region (not shown).
  • the second dielectric intermediate layer 601 on the top surface of the third dielectric layer 201 is etched, and the second dielectric intermediate layer 601 in the bit line contact window 105 is etched to the surface of the active area to form the second dielectric layer 602.
  • the etching rate is the same.
  • the bit line contact opening 401 is etched to expose the surface of the semiconductor substrate 101 at the bottom of the bit line contact opening, an etching defect is originally formed
  • the position of 501 is filled with the second dielectric layer 602, at this time, the short circuit between the bit line contact 105 and the buried word line structure 106 caused by the etching defect 501 or the electrical performance degradation caused by the strong electric field are avoided. The problem.
  • the second dielectric intermediate layer 601 is then etched back; at this time, since the material to be etched is the same material, the etching rate is the same and the etching is The bottom surface of the semiconductor substrate 101 is relatively flat, and the etching stops when the surface of the semiconductor substrate 101 is exposed by the etching.
  • the etching rate is the same, the part where the etching defect was originally formed and filled by the second dielectric intermediate layer 601 is not removed by the etching;
  • backfilling the etching defect 501 caused by the previous alignment problem the distance between the bit line contact 105 and the buried word line structure 106 is increased, and the bit line contact 105 and the buried word are avoided.
  • the second dielectric layer on the surface of the isolation structure whose depth is greater than the surface of the active region and the surface of the first dielectric layer it further includes: forming a second dielectric layer whose depth is greater than the preset depth. The surface of the active region, the surface of the isolation structure and the surface of the first dielectric layer; wherein the top surface of the second dielectric layer is flush with the preset depth. In this way, the distance between the bit line contact window and the buried word line structure is further increased.
  • FIGS. 12 to 20 The cross-sectional schematic diagrams parallel to the buried word line structure 106 are shown in FIGS. 12 to 20.
  • the semiconductor substrate structure provided in the figures is a schematic structural diagram to let those skilled in the art understand the implementation method of the solution, and does not constitute limited.
  • the semiconductor forming method includes: the parts similar to the above-mentioned vertical to the buried word line structure 106 will not be repeated, and the details are as follows:
  • the semiconductor substrate 101 has a plurality of isolation structures 111, and an active region (not shown) defined by the isolation structures 111 is located in the semiconductor substrate 101.
  • a third dielectric layer 201 is formed on the top surface of the semiconductor substrate 101 and the top surface of the first dielectric layer 107.
  • bit line contact opening 401 is formed in the third dielectric layer 201, and the bit line contact opening 401 exposes at least a part of the active region (not shown) and a part of the isolation structure 111.
  • a mask layer 301 is formed on the top surface of the third dielectric layer 201, and an etching pattern required for subsequent formation of the bit line contact opening 401 is formed on the mask layer 301.
  • the orthographic projection of the etching pattern on the semiconductor substrate 101 is located between the adjacent buried word line structures 106 and completely covers the active area between the adjacent buried word line structures 106.
  • the mask layer 301 includes a sub-mask layer 311, an anti-reflection layer 321 and a photoresist 331.
  • a sub-mask layer 311 is formed on the top surface of the third dielectric layer 201
  • an anti-reflection layer 321 is formed on the top surface of the sub-mask layer 311
  • a photoresist 331 is formed on the top surface of the anti-reflection layer 321; the etching pattern is formed in On the photoresist 331.
  • the third dielectric layer 201 is etched to form a bit line contact opening 401; the mask layer 301 on the top surface of the third dielectric layer 201 is etched and removed; that is, the structure shown in FIG. 14 is formed.
  • the etching is performed through the etching pattern on the photoresist 331, and the anti-reflective layer 321, the sub-mask layer 311, the third dielectric layer 201 and part of the semiconductor substrate 101 are sequentially etched away to form openings, and then the etching The remaining photoresist 331, the anti-reflection layer 321 and the sub-mask layer 311 are removed to form a bit line contact opening 401.
  • the mask layer 301 on the top surface of the third dielectric layer 201 can be etched and removed after the bit line contact opening 401 is formed by etching, or it can be etched after the bit line contact window 105 is formed by subsequent etching. Etching and removal.
  • the mask layer 301 on the top surface of the third dielectric layer 201 is etched to remove the mask layer 301 and then the mask layer 301 is etched to remove the mask layer 301 as an example for description, which does not constitute a limitation of the present application.
  • the active region at the bottom of the bit line contact opening 401 and the isolation structure 111 are etched to a predetermined depth to form a bit line contact window 105.
  • the conductor is not aligned when transferring the etching pattern to the semiconductor substrate 101, so that the bottom of the formed bit line contact opening 401 exposes part of the isolation structure 111 Part of the surface, due to the different selection ratios of the etching materials (usually the etching rate of the etching materials on silicon oxide and silicon nitride is greater than that of silicon materials), when the bottom of the bit line contact opening 401 is formed, the isolation structure 111 is etched The rate is greater than that of the semiconductor substrate 101.
  • etching defects 501 may be formed, or due to the influence of drilling, etching defects 501 may also be formed, resulting in the bit line contact 105 formed by the post filling and the buried word line structure The distance of 106 is too short, resulting in short-circuiting between the bit line contact window 105 and the buried word line structure 106 or the problem of electrical performance degradation caused by a strong electric field.
  • a second dielectric layer 602 on the surface of the isolation structure 111 and the surface of the first dielectric layer 107 whose depth is greater than the surface of the active region.
  • a part of the active region immediately adjacent to the layer 107 may be over-etched, resulting in the active region depth at the edge position may be greater than the preset depth, that is, greater than the surface depth of the active region in the middle region of the bit line contact 105. It should be noted that the preset depth should be less than the thickness of the first dielectric layer 107.
  • S105-1 filling the bit line contact window to form a second dielectric intermediate layer 601;
  • a second dielectric intermediate layer 601 is formed on the top surface of the third dielectric layer 201 and the bit line contact window 105.
  • the material of the second dielectric intermediate layer 601 is usually silicon oxide.
  • the second dielectric intermediate layer 601 is etched back to form a second dielectric layer 602; wherein, the etch back is the second dielectric intermediate layer 601 whose etching depth is smaller than the surface of the active region.
  • the second dielectric intermediate layer 601 on the top surface of the third dielectric layer 201 is etched, and the second dielectric intermediate layer 601 in the bit line contact window 105 is etched to a preset height to form the second dielectric layer 602.
  • a capacitor contact window 104 is subsequently formed. Refer to FIG. 2 for a schematic top view of the semiconductor structure of the bit line contact window 105.
  • the bit line contact window 105 completely covers the active area between the adjacent buried word line structures 106.
  • the capacitive contact window 104 covers the active area at the edge of the buried word line structure 106, and the bit line contact window 105 and the capacitive contact window 104 cover all the active areas, ensuring that silicon nitride can be used to fill the gap in the future.
  • a short circuit occurs between the active area contacted by the bit line contact window 105 and the capacitive contact window 104.
  • the orthographic projection of the formed bit line contact 105 on the semiconductor substrate 101 can completely cover the active area 103, so that when silicon nitride is used to fill the gap later, the active area 103 can be completely isolated by the bit line contact 105.
  • the capacitive contact window 104 With the capacitive contact window 104, the possible short-circuit problem between the active area 103 and the capacitive contact window 104 is avoided; at the same time, the forming method and the manufacturing process are simple and stable, which saves costs.
  • FIG. 2 for a schematic top view thereof, and refer to FIGS. 21 and 22 for a schematic cross-sectional view thereof, including:
  • the semiconductor substrate 101 has formed an isolation structure 111, an active region (not shown), and a buried word line structure 106, and a first dielectric layer 107 is formed on the top of the buried word line structure 106;
  • the buried word line structure 106 is located in the semiconductor substrate 101, the top of the buried word line structure 106 has a first dielectric layer 107, and the top surface of the first dielectric layer 107 is flush with the top surface of the semiconductor substrate 101
  • the active region (not shown) defined by the isolation structure 111 is located between the buried word line structure 106.
  • the isolation structure 111 uses a shallow trench isolation trench.
  • the material of the semiconductor substrate 101 includes silicon, germanium, silicon-on-insulator, silicon carbide, gallium arsenide, aluminum nitride, or zinc oxide; in this embodiment, the semiconductor substrate 101 is formed of silicon material.
  • the embodiment uses silicon material as the semiconductor substrate 101 to facilitate the understanding of subsequent formation methods by those skilled in the art, and does not constitute a limitation. In the actual application process, a suitable material for the semiconductor substrate 101 can be selected according to requirements.
  • this embodiment is described by taking the semiconductor substrate not including the third dielectric layer as an example, and does not constitute a limitation to the solution, that is, in this embodiment, the semiconductor structure does not include the third dielectric layer. That is, a semiconductor structure is formed by determining the position of the bit line contact opening on the top surface of the semiconductor substrate 101 and the top surface of the first dielectric layer 107 and forming the bit line contact window 105 by etching the position of the bit line contact opening. In other embodiments, referring to FIGS.
  • the semiconductor substrate 101 further includes: a third dielectric layer 201 located on the top surface of the semiconductor substrate 101 and the top surface of the first dielectric layer 107;
  • the material can be silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the third dielectric layer 201 is 50 nm to 300 nm.
  • the bit line contact window 105 is located in the semiconductor substrate 101 with a predetermined depth; wherein the bit line contact window 105 exposes at least part of the active area, and the bit line contact window 105 also exposes at least part of the first dielectric layer 107 ⁇ Partial isolation structure 111.
  • the second dielectric layer 602 is located on the surface of the isolation structure 111 or the surface of the first dielectric layer 107 that is located at the bottom of the bit line contact window 105 and is deeper than the surface of the active region.
  • the orthographic projection of the bit line contact window on the semiconductor substrate covers the active area between adjacent buried word line structures 106.
  • the bit line contact window completely covers the active area between the adjacent buried word line structure 106
  • the capacitive contact window 104 covers the active area at the edge of the buried word line structure 106
  • the bit line contact window 105 and the capacitive contact window 104 All the active areas are covered to ensure that when silicon nitride is used to fill the gap in the future, it can be ensured that the active area that should be in contact with the bit line contact 105 and the capacitor contact 104 are short-circuited.
  • the orthographic projection of the bit line contact window formed on the semiconductor substrate can completely cover the active area, so that when silicon nitride is used to fill the gap later, the active area and the capacitor contact window can be completely isolated by the bit line contact window, avoiding This solves the possible short-circuit problem between the active area and the capacitive contact window.

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Abstract

一种半导体结构及形成方法，其形成方法包括：提供半导体衬底(101)，半导体衬底(101)已形成隔离结构(111)、有源区(103)和埋入式字线结构(106)，埋入式字线结构(106)顶部形成有第一介质层(107)；在半导体衬底(101)的顶部表面和第一介质层(107)的顶部表面确定位线接触开口(401)的位置；依据位线接触开口(401)的位置，刻蚀位线接触开口(401)所暴露出的有源区(103)、第一介质层(107)和隔离结构(111)，直至将有源区(103)刻蚀至预设深度形成位线接触窗(105)；形成第二介质层(602)于深度大于位线接触窗(105)内有源区(103)表面的隔离结构(111)表面和第一介质层(107)表面。

Description

半导体结构及形成方法
交叉引用
本申请引用于2020年3月16日递交的名称为“半导体结构及形成方法”
的第202010180648.7号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体器件及制造领域，特别涉及一种半导体结构及形成方法。
背景技术
动态随机存储器(英文：Dynamic Random Access Memory，简称:DRAM)是一种广泛应用于手机、电脑和汽车等产品中的半导体存储器。随着科技的发展，集成电路器件特征尺寸的不断缩小，DRAM的关键尺寸也越来越小，相应地制造难度也越来越大，未来与DRAM制造的相关技术将在会继续往更小的尺寸发展，这对DRAM产品的电性要求非常严格。
然而，申请人发现，随着DRAM的关键尺寸也越来越小，在现有DRAM制造方法中，各个导电部件之间可能会出现短接的问题。
发明内容
本申请实施例提供一种半导体结构及形成方法，通过回填位线接触窗底部的刻蚀缺陷，增大了位线接触窗与埋入式字线结构间的间距，避免了因刻蚀缺陷而导致的位线接触窗口与埋入式字线结构之间可能出现的短接、寄生电容增大或因强电场而造成的DRAM电性能下降的问题。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法， 包括：提供半导体衬底，半导体衬底已形成隔离结构、有源区和埋入式字线结构，埋入式字线结构顶部形成有第一介质层；在半导体衬底的顶部表面和第一介质层的顶部表面确定位线接触开口的位置，位线接触开口至少暴露部分有源区，且位线接触开口至少还暴露部分第一介质层或部分隔离结构；依据位线接触开口的位置，刻蚀位线接触开口所暴露出的有源区、第一介质层和隔离结构，直至将有源区刻蚀至预设深度形成位线接触窗；形成第二介质层于深度大于位线接触窗内有源区表面的隔离结构表面和第一介质层表面。
相对于相关技术而言，本申请实施例对位线接触窗的形成方法进行改进，在半导体衬底上确定位线接触开口的位置，刻蚀位线接触开口所暴露出的半导体衬底至预设深度形成位线接触窗；在这一过程中，可能由于刻蚀材料的刻蚀选择比不同，导致位线接触窗底部的部分半导体衬底的刻蚀深度大于预设深度；通过回填第二介质层，弥补这部分刻蚀缺陷，增大了位线接触窗与埋入式字线结构间的间距，避免了因刻蚀缺陷而导致的位线接触窗口与埋入式字线结构之间可能出现的短接或因强电场而造成的DRAM电性能下降的问题。
另外，形成第二介质层于深度大于位线接触窗内有源区表面的隔离结构表面和第一介质层表面后，还包括：形成第二介质层于深度大于预设深度的有源区表面、隔离结构表面和第一介质层表面。
另外，第二介质层的顶部表面与预设深度齐平。
另外，在半导体衬底的顶部表面和第一介质层的顶部表面确定位线接触开口的位置，包括：在半导体衬底的顶部表面和第一介质层的顶部表面形成第三介质层；在所述第三介质层中形成所述位线接触开口。
另外，在第三介质层中形成位线接触开口，具体包括：在第三介质层顶 部表面形成掩膜层，在掩膜层上形成后续形成位线接触开口所需的刻蚀图案；其中，刻蚀图案在半导体衬底上的正投影覆盖相邻埋入式字线结构之间的有源区；依据刻蚀图案，刻蚀第三介质层形成位线接触开口。通过掩膜层中的刻蚀图案对位线接触窗的边缘形貌进行改进，使得位线接触窗在半导体衬底表面上的正投影能完全覆盖相邻埋入式字线结构之间的有源区；在后续用氮化硅填充间隙时，位线接触窗可以完全隔离有源区与电容接触窗，解决了电容接触窗和有源区之间短接的问题。
另外，刻蚀形成位线接触开口后或刻蚀形成位线接触窗后，还包括：刻蚀去除第三介质层顶部表面的掩膜层。
另外，刻蚀图案为矩形。
另外，在第三介质层顶部表面形成掩膜层，在掩膜层上形成后续形成位线接触开口所需的刻蚀图案，具体包括：在第三介质层顶部表面形成子掩膜层；在子掩膜层顶部表面形成抗反射层；在抗反射层顶部表面形成光刻胶；在光刻胶上形成刻蚀图案。
另外，子掩膜层的厚度为30nm～150nm；光刻胶的厚度为50nm～250nm；第三介质层的厚度为50nm～300nm。
另外，形成第二介质层于深度大于位线接触窗内有源区表面的隔离结构表面和第一介质层表面，具体包括：填充位线接触窗形成第二介质中间层；对第二介质中间层进行回刻蚀，形成第二介质层；其中回刻蚀为刻蚀深度小于有源区表面的第二介质中间层。另外，填充为非保形填充。
本申请实施例还提供了一种半导体结构，包括：半导体衬底，半导体衬底已形成隔离结构、有源区和埋入式字线结构，埋入式字线结构顶部形成有第 一介质层；位线接触窗，位线接触窗位于预设深度的半导体衬底中；其中，位线接触窗至少暴露部分有源区，位线接触窗至少还暴露部分第一介质层或部分隔离结构；第二介质层，位于位线接触窗底部且深度大于位线接触窗内有源区表面的隔离结构表面或第一介质层表面。
相对于相关技术而言，本申请实施例通过第二介质层增大了位线接触窗与埋入式字线结构间的间距，避免了因刻蚀缺陷而导致的位线接触窗口与埋入式字线结构之间可能出现的短接、寄生电容增大或因强电场而造成的DRAM电性能下降的问题。
另外，位线接触窗在半导体衬底上的正投影覆盖相邻埋入式字线结构之间的有源区。对位线接触窗的边缘形貌进行改进，形成的位线接触窗在半导体衬底上的正投影能完全覆盖有源区，使得后续在填充间隙的过程中，通过位线接触窗可以完全隔离有源区与电容接触窗，避免了有源区与电容接触窗之间的可能造成的短接问题。
附图说明
图1为本申请一实施例涉及的半导体衬底的俯视示意图；
图2为本申请一实施例形成位线接触窗和电容接触窗后的半导体结构的俯视示意图；
图3～图7为本申请一实施例涉及的半导体形成方法中垂直于位线方向上的半导体结构的剖面示意图；
图8～图12为本申请一实施例涉及的半导体形成方法中平行于位线方向上的半导体结构的剖面示意图；
图13～图16为本申请一实施例涉及的垂直于位线方向上的半导体结构回 填过程的剖面示意图；
图17～图20为本申请一实施例涉及的平行于位线方向上的半导体结构回填过程的剖面示意图；
图21和图22为本申请另一实施例涉及的半导体结构的示意图。
具体实施方式
随着DRAM的关键尺寸也越来越小，在现有DRAM制造方法中，各个导电部件之间可能会出现短接的问题。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供半导体衬底，半导体衬底已形成隔离结构、有源区和埋入式字线结构，埋入式字线结构顶部形成有第一介质层；在半导体衬底的顶部表面和第一介质层的顶部表面确定位线接触开口的位置；依据位线接触开口的位置，刻蚀位线接触开口所暴露出的有源区、第一介质层和隔离结构，直至将有源区刻蚀至预设深度形成位线接触窗；形成第二介质层于深度大于位线接触窗内有源区表面的隔离结构表面和第一介质层表面。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例涉及的半导体衬底的俯视示意图，图2为本实施例形成 位线接触窗和电容接触窗后的半导体结构的俯视示意图，图3～图7为本实施例涉及的半导体形成方法中垂直于位线方向上的半导体结构的剖面示意图，图8～图12为本实施例涉及的半导体形成方法中平行于位线方向上的半导体结构的剖面示意图，图13～图16为本实施例涉及的垂直于位线方向上的半导体结构回填过程的剖面示意图，图17～图20为本实施例涉及的平行于位线方向上的半导体结构回填过程的剖面示意图，下面对本实施例的半导体结构的形成方法的实现细节进行具体说明。
本实施例涉及的半导体形成方法形成的半导体结构，参考图1，该图表示，半导体衬底101中有源区103与埋入式字线结构106的布局。参考图2，该图表示，采用本申请实施例形成的位线接触窗105，电容接触窗104与埋入式字线结构106之间的位置关系，位线接触窗口105完全覆盖埋入式字线结构106之间的有源区103。
形成的位线接触窗105在半导体衬底101上的正投影能完全覆盖有源区103，使得后续在填充间隙时，位线接触窗105可以完全隔离有源区103与电容接触窗104，避免了有源区103与电容接触窗104之间的可能造成的短接问题。
需要说明的是，在本实施例中，位线接触窗105和电容接触窗104的图示为矩形，仅仅是为了在俯视平面上截断有源区103，从而便于本领域技术人员理解本方案，并不构成对本方案的限定；在实际应用中，位线接触窗105和电容接触窗104可以设置为椭圆形、圆形或梯形等，但只要符合位线接触窗105在半导体衬底101上的正投影完全覆盖有源区103，即在本申请的保护范围内。
垂直于埋入式字线结构106的剖面示意图如图3～图11所示，图中提供的半导体衬底结构为结构示意图，是为了让本领域技术人员了解本方案的实现 方法，并不构成对本方案的限定。该半导体形成方法包括：
S101，提供半导体衬底101。
半导体衬底101已形成隔离结构111、有源区(未图示)和埋入式字线结构106，埋入式字线结构106顶部形成有第一介质层107；需要说明的是，在本实施例中对第一介质层107的顶部表面与半导体衬底101的顶部表面齐平的情况进行详细描述；本领域技术人员清楚，在实施例中限定的第一介质层107的顶部表面与半导体衬底101的顶部表面齐平并不对构成对本申请的限定，只是为了清楚的介绍本方案的实施流程。
需要说明的是，半导体衬底101的材料包括硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中半导体衬底101采用硅材料形成，本实施例采用硅材料作为半导体衬底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的半导体衬底101的材料。
参考图3，埋入式字线结构106位于半导体衬底101内，埋入式字线结构106顶部具有第一介质层107，第一介质层107的顶部表面与半导体衬底101的顶部表面齐平；通过隔离结构111限定的有源区(未图示)包括位于埋入式字线结构106之间的部分，在本实施例中，隔离结构111采用浅沟道隔离槽。
参考图4，S102，在半导体衬底101的顶部表面和第一介质层107的顶部表面形成第三介质层201。
需要说明的是，本实施例是以形成第三介质层201，然后在第三介质层201中形成位线接触开口401为例进行说明，并不构成对本方案的限定，在其他实施例中，可以直接在半导体衬底的顶部表面和第一介质层的顶部表面确定 位线接触开口的位置，后续过程中直接通过位线接触开口的位置刻蚀形成位线接触窗。
具体地，第三介质层201的材料可以为氮化硅、氧化硅或氮氧化硅，在本实施例中，第三介质层201的厚度为50nm～300nm，例如100nm、150nm、200nm或者250nm。
参考图5，S103，在第三介质层201中形成位线接触开口401，位线接触开口401至少暴露部分有源区(未图示)和部分第一介质层107。
具体地，参考图6，S103-1，在第三介质层201顶部表面形成掩膜层301，在掩膜层301上形成后续形成位线接触开口401所需的刻蚀图案。
需要说明的是，刻蚀图案在半导体衬底101上的正投影位于相邻埋入式字线结构106之间，且完全覆盖相邻埋入式字线结构之间的有源区。
在本实施例中，参考图7，掩膜层301包括子掩膜层311、抗反射层321和光刻胶331。具体地，在第三介质层201顶部表面形成子掩膜层311，在子掩膜层311顶部表面形成抗反射层321，在抗反射层321顶部表面形成光刻胶331；刻蚀图案形成于光刻胶331上。具体地，子掩膜层311的材料包括碳、硅、氧化硅或氮化硅，在本实施例中，子掩膜层311的厚度为30nm～150nm，例如50nm、80nm、100nm或者130nm；光刻胶的厚度为50nm～250nm，例如100nm、150nm或者200nm。
S103-2，依据刻蚀图案，刻蚀第三介质层201形成位线接触开口401；刻蚀去除第三介质层201顶部表面的掩膜层301；即形成图5所示的结构。
具体地，通过光刻胶331上的刻蚀图案进行刻蚀，依次刻蚀掉抗反射层321、子掩膜层311和第三介质层201形成开口，再刻蚀掉剩余的光刻胶331、 抗反射层321和子掩膜层311，形成位线接触开口401，位线接触开口401相比于开口而言，仅仅是将开口高度进行了缩减，其底部构造并不会发生变化。
需要说明的是，刻蚀去除第三介质层201顶部表面的掩膜层301，可以在刻蚀形成位线接触开口401后刻蚀去除，也可以在后续刻蚀形成位线接触窗105后刻蚀去除，本实施例以刻蚀去除第三介质层201顶部表面的掩膜层301后刻蚀去除掩膜层301为例进行描述，并不构成对本申请的限定。
参考图8，S104，刻蚀位线接触开口401底部的有源区(未图示)和第一介质层107至预设深度形成位线接触窗105。
参考图9，由于前期的结构设计因素，部分埋入式字线结构106位于隔离结构111中，在将光刻胶331上的刻蚀图案转移到半导体衬底101表面的同时，由于此时位线接触开口401底部具有部分第一介质层107表面、部分半导体衬底101表面和部分隔离结构111表面，由于刻蚀材料的选择比不同(通常刻蚀材料对氧化硅、氮化硅的刻蚀速率要大于硅材料)，在形成位线接触开口401底部时，对第一介质层107和隔离结构111的刻蚀速率要大于半导体衬底101，此时会形成空隙，即刻蚀缺陷501，导致后期填充形成的位线接触窗105与埋入式字线结构106的距离过近，从而导致位线接触窗105与埋入式字线结构106之间的短接或因强电场而造成的电性能下降的问题。
S105，形成第二介质层602于深度大于有源区(未图示)表面的隔离结构111表面和第一介质层107表面。需要说明的是，预设深度应小于第一介质层107的底部表面。
具体地，S105-1，填充所述位线接触窗形成第二介质中间层601；
参考图10，在第三介质层201的顶部表面以及位线接触窗105中形成第 二介质中间层601，第二介质中间层601的材料通常采用氧化硅。
需要说明的是，在本实施例中，填充位线接触窗105采用非保形填充，在其他实施例中，也可以采用保形填充的方式填充位线接触窗。
S105-2，对第二介质中间层601进行回刻蚀，形成第二介质层602；其中，回刻蚀为刻蚀深度小于有源区(未图示)表面的第二介质中间层601。
参考图11，刻蚀第三介质层201顶部表面的第二介质中间层601，刻蚀位线接触窗105中的第二介质中间层601直至有源区表面，形成第二介质层602。
由于此时被刻蚀材料都为第二介质中间层601，其刻蚀速率一致，当刻蚀位线接触开口401暴露出位线接触开口底部的半导体衬底101表面时，原先形成刻蚀缺陷501的位置被第二介质层602填充，此时避免了因为刻蚀缺陷501导致的位线接触窗105与埋入式字线结构106之间的短接或因强电场而造成的电性能下降的问题。
通过向位线接触开口401中填充第二介质中间层601，再对第二介质中间层601进行回刻蚀；此时由于被刻蚀的材料是同一种材料，刻蚀速率相同且刻蚀出的底面较为平整，当刻蚀暴露出半导体衬底101表面时停止刻蚀，由于刻蚀速率相同，原先形成刻蚀缺陷的位置被第二介质中间层601填充的部分并没有被刻蚀清除；通过回填因前期的对准问题而造成的刻蚀缺陷501，从而增大了位线接触窗105与埋入式字线结构106之间的距离，避免了位线接触窗105与埋入式字线结构106之间的短接或因强电场而造成的电性能下降的问题。
需要说明的是，在其他实施例中，形成第二介质层于深度大于有源区表面的隔离结构表面和第一介质层表面后，还包括：形成第二介质层于深度大于预设深度的有源区表面、隔离结构表面和第一介质层表面；其中，第二介质层 的顶部表面与所述预设深度齐平。通过这种方式进一步增大了位线接触窗与埋入式字线结构之间的距离。
平行于埋入式字线结构106的剖面示意图如图12～图20所示，图中提供的半导体衬底结构为结构示意图，是为了让本领域技术人员了解本方案的实现方法，并不构成限定。该半导体形成方法包括：与上述垂直于埋入式字线结构106相似部分不再赘述，具体如下：
S101，提供半导体衬底101。
参考图12，半导体衬底101内具有多个隔离结构111，通过隔离结构111限定的有源区(未图示)，位于半导体衬底101内。
参考图13，S102，在半导体衬底101的顶部表面和第一介质层107的顶部表面形成第三介质层201。
参考图14，S103，在第三介质层201中形成位线接触开口401，位线接触开口401至少暴露部分有源区(未图示)和部分隔离结构111。
具体地，参考图15，S103-1，在第三介质层201顶部表面形成掩膜层301，在掩膜层301上形成后续形成位线接触开口401所需的刻蚀图案。
需要说明的是，刻蚀图案在半导体衬底101上的正投影位于相邻埋入式字线结构106之间，且完全覆盖相邻埋入式字线结构106之间的有源区。
在本实施例中，参考图16，掩膜层301包括子掩膜层311、抗反射层321和光刻胶331。具体地，在第三介质层201顶部表面形成子掩膜层311，在子掩膜层311顶部表面形成抗反射层321，在抗反射层321顶部表面形成光刻胶331；刻蚀图案形成于光刻胶331上。
S103-2，依据刻蚀图案，刻蚀第三介质层201形成位线接触开口401； 刻蚀去除第三介质层201顶部表面的掩膜层301；即形成图14所示结构。
具体地，通过光刻胶331上的刻蚀图案进行刻蚀，依次刻蚀掉抗反射层321、子掩膜层311、第三介质层201和部分半导体衬底101以形成开口，再刻蚀掉剩余的光刻胶331、抗反射层321和子掩膜层311，形成位线接触开口401。
需要说明的是，刻蚀去除第三介质层201顶部表面的掩膜层301，可以在刻蚀形成位线接触开口401后刻蚀去除，也可以在后续刻蚀形成位线接触窗105后刻蚀去除，本实施例以刻蚀去除第三介质层201顶部表面的掩膜层301后刻蚀去除掩膜层301为例进行描述，并不构成对本申请的限定。
参考图17，S104，刻蚀位线接触开口401底部的有源区和隔离结构111至预设深度形成位线接触窗105。
参考图18，因半导体结构制造工艺前期的对准问题，导体将刻蚀图案转移到半导体衬底101上时并没有对准，从而形成的位线接触开口401底部暴露出了部分隔离结构111的部分表面，由于刻蚀材料的选择比不同(通常刻蚀材料对氧化硅、氮化硅的刻蚀速率要大于硅材料)，在形成位线接触开口401底部时，对隔离结构111的刻蚀速率要大于半导体衬底101，此时会形成刻蚀缺陷501，或者由于钻蚀的影响，也可能会形成刻蚀缺陷501，导致后期填充形成的位线接触窗105与埋入式字线结构106的距离过近，从而导致位线接触窗105与埋入式字线结构106之间的短接或因强电场而造成的电性能下降的问题。
S105，形成第二介质层602于深度大于有源区表面的隔离结构111表面和第一介质层107表面，此处由于光刻未对准或钻蚀的影响，与隔离结构111或第一介质层107紧邻的有源区可能会有部分被过蚀刻，导致边缘位置的有源区深度可能大于预设深度，也即大于位线接触窗105内中间区域有源区的表面 深度。需要说明的是，预设深度应小于第一介质层107的厚度。
具体地，S105-1，填充所述位线接触窗形成第二介质中间层601；
参考图19，在第三介质层201的顶部表面以及位线接触窗105中形成第二介质中间层601，第二介质中间层601的材料通常采用氧化硅。
S105-2，对第二介质中间层601进行回刻蚀，形成第二介质层602；其中，回刻蚀为刻蚀深度小于有源区表面的第二介质中间层601。
参考图20，刻蚀第三介质层201顶部表面的第二介质中间层601，刻蚀位线接触窗105中的第二介质中间层601直至预设高度，形成第二介质层602。
在形成位线接触窗105之后，后续还形成电容接触窗104，其半导体结构的俯视示意图参考图2，位线接触窗105完全覆盖相邻埋入式字线结构106之间的有源区，电容接触窗104覆盖埋入式字线结构106边缘的有源区，位线接触窗105和电容接触窗104覆盖全部的有源区，保证后续在采用氮化硅填充间隙时能够保证本应与位线接触窗105接触的有源区与电容接触窗104之间发生短接。
相对于相关技术而言，通过回填位线接触窗底部的刻蚀缺陷，增大了位线接触窗与埋入式字线结构间的间距，避免了因刻蚀缺陷而导致的位线接触窗口与埋入式字线结构之间可能出现的短接或因强电场而造成的DRAM电性能下降的问题。
同时，形成的位线接触窗105在半导体衬底101上的正投影能完全覆盖有源区103，使得后续在采用氮化硅填充间隙时，通过位线接触窗105可以完全隔离有源区103与电容接触窗104，避免了有源区103与电容接触窗104之间的可能造成的短接问题；同时其形成方法其制备工艺简单稳定，节约成本。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种半导体结构，其俯视示意图参考图2，以及其剖面示意图参考图21和图22所示，包括：
半导体衬底101，半导体衬底101已形成隔离结构111、有源区(未图示)和埋入式字线结构106，埋入式字线结构106顶部形成有第一介质层107；
具体地，埋入式字线结构106位于半导体衬底101内，埋入式字线结构106顶部具有第一介质层107，第一介质层107的顶部表面与半导体衬底101的顶部表面齐平；通过隔离结构111限定的有源区(未图示)位于埋入式字线结构106的之间，在本实施例中，隔离结构111采用浅沟道隔离槽。
需要说明的是，半导体衬底101的材料包括硅、锗、绝缘体上硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中半导体衬底101采用硅材料形成，本实施例采用硅材料作为半导体衬底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的半导体衬底101的材料。
需要说明的是，本实施例是以半导体衬底不包括第三介质层为例进行说明，并不构成对本方案的限定，即在本实施例中，半导体结构中不包括第三介质层。即通过在半导体衬底101的顶部表面和第一介质层107的顶部表面确定位线接触开口的位置通过位线接触开口的位置刻蚀形成位线接触窗105的方式形成的半导体结构。在其他实施例中，参考图11和图20，半导体衬底101还 包括：第三介质层201，位于半导体衬底101的顶部表面和第一介质层107的顶部表面；第三介质层201的材料可以为氮化硅、氧化硅或氮氧化硅。其中，第三介质层201的厚度为50nm～300nm。
位线接触窗105，位线接触窗105位于预设深度的半导体衬底101中；其中，位线接触窗105至少暴露部分有源区，位线接触窗105至少还暴露部分第一介质层107或部分隔离结构111。
第二介质层602，位于位线接触窗105底部且深度大于有源区表面的隔离结构111表面或第一介质层107表面。
参考图2，在本实施例中，位线接触窗在半导体衬底上的正投影覆盖相邻埋入式字线结构106之间的有源区。位线接触窗完全覆盖相邻埋入式字线结构106之间的有源区，电容接触窗104覆盖埋入式字线结构106边缘的有源区，位线接触窗105和电容接触窗104覆盖全部的有源区，保证后续在采用氮化硅填充间隙时能够保证本应与位线接触窗105接触的有源区与电容接触窗104之间发生短接。
与相关技术相比，通过回填因前期造成的刻蚀缺陷，从而增大了位线接触窗与埋入式字线结构之间的距离，避免了位线接触窗与埋入式字线结构之间的短接或因强电场而造成的电性能下降的问题。
同时形成的位线接触窗在半导体衬底上的正投影能完全覆盖有源区，使得后续在采用氮化硅填充间隙时，通过位线接触窗可以完全隔离有源区与电容接触窗，避免了有源区与电容接触窗之间的可能造成的短接问题。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上 述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种半导体结构的形成方法，其中，包括：
    提供半导体衬底，所述半导体衬底已形成隔离结构、有源区和埋入式字线结构，所述埋入式字线结构的顶部表面形成有第一介质层；
    在所述半导体衬底的顶部表面和所述第一介质层的顶部表面确定位线接触开口的位置；所述位线接触开口至少暴露部分有源区，且所述位线接触开口至少还暴露部分所述第一介质层或部分所述隔离结构；
    依据所述位线接触开口的位置，刻蚀所述位线接触开口所暴露出的所述有源区、所述第一介质层和所述隔离结构，直至将所述有源区刻蚀至预设深度形成位线接触窗；
    形成第二介质层于深度大于所述位线接触窗内有源区表面的所述隔离结构表面和所述第一介质层表面。
  2. 如权利要求1所述的半导体结构的形成方法，其中，所述形成第二介质层于深度大于所述位线接触窗内有源区表面的所述隔离结构表面和所述第一介质层表面后，还包括：形成第二介质层于深度大于所述预设深度的所述有源区表面、所述隔离结构表面和所述第一介质层表面。
  3. 如权利要求2所述的半导体结构的形成方法，其中，所述第二介质层的顶部表面与所述预设深度齐平。
  4. 如权利要求1所述的半导体结构的形成方法，其中，所述在所述半导体衬底的顶部表面和所述第一介质层的顶部表面确定位线接触开口的位置，包括：
    在所述半导体衬底的顶部表面和所述第一介质层的顶部表面形成第三介质层；在所述第三介质层中形成所述位线接触开口。
  5. 如权利要求4所述的半导体结构的形成方法，其中，所述在所述第三介质层中形成位线接触开口，具体包括：
    在所述第三介质层顶部表面形成掩膜层，在所述掩膜层上形成后续形成所述位线接触开口所需的刻蚀图案；其中，所述刻蚀图案在所述半导体衬底上的正投影覆盖相邻所述埋入式字线结构之间的有源区；
    依据所述刻蚀图案，刻蚀所述第三介质层形成位线接触开口。
  6. 如权利要求5所述的半导体结构的形成方法，其中，刻蚀形成所述位线接触开口后或刻蚀形成所述位线接触窗后，还包括：刻蚀去除所述第三介质层顶部表面的所述掩膜层。
  7. 如权利要求5所述的半导体结构的形成方法，其中，所述刻蚀图案为矩形。
  8. 如权利要求5所述的半导体结构的形成方法，其中，所述在所述第三介质层顶部表面形成掩膜层，在所述掩膜层上形成后续形成位线接触开口所需的刻蚀图案，具体包括：
    在所述第三介质层顶部表面形成子掩膜层；在所述子掩膜层顶部表面形成抗反射层；在所述抗反射层顶部表面形成光刻胶；
    在所述光刻胶上形成所述刻蚀图案。
  9. 如权利要求8所述的半导体结构的形成方法，其中，所述子掩膜层的厚度为30nm～150nm。
  10. 如权利要求8所述的半导体结构的形成方法，其中，所述光刻胶的厚度为50nm～250nm。
  11. 如权利要求4所述的半导体结构的形成方法，其中，所述第三介质层的厚度为50nm～300nm。
  12. 如权利要求1所述的半导体结构的形成方法，其中，所述形成第二介质层于深度大于所述位线接触窗内有源区表面的所述隔离结构表面和所述第一介质层表面，具体包括：
    填充所述位线接触窗形成第二介质中间层；
    对所述第二介质中间层进行回刻蚀，形成所述第二介质层；其中所述回刻蚀为刻蚀深度小于所述有源区表面的第二介质中间层。
  13. 如权利要求12所述的半导体结构的形成方法，其中，所述填充为非保形填充。
  14. 一种半导体结构，其中，包括：
    半导体衬底，所述半导体衬底已形成隔离结构、有源区和埋入式字线结构，所述埋入式字线结构顶部形成有第一介质层；
    位线接触窗，所述位线接触窗位于预设深度的所述半导体衬底中；其中，所述位线接触窗至少暴露部分所述有源区，所述位线接触窗至少还暴露部分所述第一介质层或部分所述隔离结构；
    第二介质层，位于所述位线接触窗底部且深度大于所述位线接触窗内有源区表面的所述隔离结构表面或所述第一介质层表面。
  15. 如权利要求14所述的半导体结构，其中，所述位线接触窗在所述半导体衬底上的正投影覆盖相邻所述埋入式字线结构之间的有源区。
PCT/CN2021/078515 2020-03-16 2021-03-01 半导体结构及形成方法 WO2021185062A1 (zh)

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