WO2021103604A1 - 显示面板、其制备方法及显示装置 - Google Patents

显示面板、其制备方法及显示装置 Download PDF

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Publication number
WO2021103604A1
WO2021103604A1 PCT/CN2020/103831 CN2020103831W WO2021103604A1 WO 2021103604 A1 WO2021103604 A1 WO 2021103604A1 CN 2020103831 W CN2020103831 W CN 2020103831W WO 2021103604 A1 WO2021103604 A1 WO 2021103604A1
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Prior art keywords
electrically connected
layer
conductive layer
transmission line
electrode
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PCT/CN2020/103831
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English (en)
French (fr)
Inventor
张洁
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/263,257 priority Critical patent/US11723246B2/en
Publication of WO2021103604A1 publication Critical patent/WO2021103604A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a preparation method thereof, and a display device.
  • the display panel can be configured in various smart terminals such as mobile phones, tablet computers, TVs, smart wearable devices, and information query machines in public halls to better realize human-computer interaction.
  • a circuit is provided in the display panel, and a storage capacitor is usually provided in the circuit. Since the storage capacitor needs to implement storage and voltage stabilization functions, the storage capacitor occupies a larger area, which reduces the space for other components in the display panel. Therefore, how to reduce the occupied area of the storage capacitor without reducing the capacitance value of the storage capacitor is an urgent technical problem to be solved by those skilled in the art.
  • An embodiment of the present disclosure provides a display panel, including: a base substrate, a driving circuit on the base substrate, the driving circuit including a storage capacitor; the display panel further includes: sequentially stacked on the substrate The first conductive layer, the second conductive layer and the third conductive layer on the substrate; wherein the first conductive layer, the second conductive layer and the third conductive layer are arranged in different layers;
  • the first conductive layer includes a first electrode layer
  • the second conductive layer includes a second electrode layer
  • the third conductive layer includes a third electrode layer
  • the orthographic projection of the first electrode layer on the base substrate, the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the third electrode layer on the base substrate all have intersections. Overlap area
  • the first electrode layer and the third electrode layer are electrically connected to each other to serve as a first electrode of the storage capacitor, and the second electrode layer serves as a second electrode of the storage capacitor.
  • the display panel further includes: a first insulating layer located between the first conductive layer and the second conductive layer, and located between the second conductive layer and the second conductive layer.
  • the second insulating layer between the third conductive layers, the third insulating layer located on the side of the third conductive layer away from the base substrate, and the third insulating layer located on the side of the third insulating layer away from the base substrate Fourth conductive layer;
  • the second conductive layer includes a first connection trace that is insulated from the second electrode layer; the fourth conductive layer includes a second connection trace;
  • One end of the second connection trace is electrically connected to the third electrode layer through a first via hole that penetrates the third insulating layer, and the other end of the second connection trace is electrically connected to the third electrode layer through the second insulation layer.
  • the second via hole and the third insulating layer are electrically connected to the first connection trace, and the first connection trace is connected to the first electrode layer through the third via hole penetrating the first insulation layer.
  • the orthographic projection of the second via on the base substrate and the orthographic projection of the third via on the base substrate do not overlap.
  • the display panel further includes: a scan driving circuit and a light emitting control circuit located in the non-display area, and a pixel circuit located in the display area;
  • the driving circuit is at least one of the scan driving circuit, the light emission control circuit, and the pixel circuit.
  • the display panel further includes: a plurality of light-emitting control signal lines located in the display area, and a plurality of light-emitting control signal transmission lines located in the non-display area; wherein, One of the light-emitting control signal transmission lines is electrically connected to one of the light-emitting control signal lines, and the first signal output terminal of the light-emitting control circuit is electrically connected to each of the light-emitting control signal transmission lines;
  • the light emitting control signal transmission line is located on the first conductive layer.
  • the first insulating layer includes a buffer layer located between the first conductive layer and the second conductive layer, and a buffer layer located between the buffer layer and the second conductive layer. Gate insulating layer between layers;
  • the second conductive layer includes a third connection trace
  • the light emission control circuit includes a light emission control transistor
  • the output terminal of the light emission control transistor passes through a fourth pass through the second insulating layer and the third insulating layer.
  • the hole is electrically connected to the third connection trace
  • the third connection trace is electrically connected to the light emitting control signal transmission line through a fifth via hole penetrating the buffer layer and the gate insulating layer, so that the The light emission control signal transmission line and the output terminal of the light emission control transistor are electrically connected through the third connecting wire.
  • the orthographic projection of the fourth via on the base substrate and the orthographic projection of the fifth via on the base substrate do not overlap.
  • the display panel further includes: a first signal drive line and a first transmission line located in the non-display area; wherein, the first signal drive line is located in the fourth conductive line. Layer; the first transmission line is electrically connected to the light-emitting control circuit;
  • the first transmission line includes a first sub-transmission line and a second sub-transmission line; wherein, the first sub-transmission line is located in the first conductive layer, and the second sub-transmission line is located in the second conductive layer;
  • the first signal driving line is electrically connected to the second sub-transmission line through a sixth via hole penetrating the second insulating layer and the third insulating layer
  • the second sub-transmission line is electrically connected to the second sub-transmission line through the first insulating layer.
  • the seventh via of the layer is electrically connected to the first sub-transmission line, so that the first signal driving line and the light-emitting control circuit are electrically connected through the first sub-transmission line and the second sub-transmission line.
  • the orthographic projection of the sixth via on the base substrate and the orthographic projection of the seventh via on the base substrate do not overlap.
  • the light emission control transistor is a double-gate transistor, and the light emission control transistor includes a first bottom gate and a first top gate electrically connected to each other;
  • the first bottom gate is located on the first conductive layer, and the first top gate is located on the second conductive layer.
  • the display panel further includes: a second signal driving line and a second transmission line located in the non-display area;
  • the second transmission line includes a third sub-transmission line and a fourth sub-transmission line; wherein, the third sub-transmission line is located in the first conductive layer, and the fourth sub-transmission line is located in the second conductive layer;
  • the second signal driving line is electrically connected to the fourth sub-transmission line through an eighth via hole penetrating the second insulating layer and the third insulating layer, and the fourth sub-transmission line is electrically connected to the fourth sub-transmission line through the first insulating layer.
  • the ninth via hole of the layer is electrically connected to the third sub-transmission line, so that the second signal driving line and the scan driving circuit are electrically connected through the third sub-transmission line and the fourth sub-transmission line.
  • the orthographic projection of the eighth via on the base substrate and the orthographic projection of the ninth via on the base substrate do not overlap.
  • the scan driving circuit includes a scan control transistor
  • the scan control transistor is a double-gate transistor, and the scan control transistor includes a second bottom gate and a second top gate electrically connected to each other;
  • the second bottom gate is located on the first conductive layer, and the second top gate is located on the second conductive layer.
  • the light-emitting control circuit is located on the side of the scan driving circuit away from the display area, and the light-emitting control signal transmission line is on the front projection of the base substrate and the The orthographic projection of the scan driving circuit on the base substrate has an overlapping area.
  • the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • the embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display panel, including:
  • the first conductive layer includes a first electrode layer
  • the second conductive layer includes a second electrode layer
  • the third conductive layer includes a third electrode layer
  • the orthographic projection of the first electrode layer on the base substrate, the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the third electrode layer on the base substrate all have intersections. Overlap area
  • the first electrode layer and the third electrode layer are electrically connected to each other to serve as a first electrode of the storage capacitor, and the second electrode layer serves as a second electrode of the storage capacitor.
  • the second conductive layer includes a first connection trace that is insulated from the second electrode layer
  • the method further includes: forming a first insulating layer having a third via hole; wherein the first connecting wire passes through the first insulating layer.
  • a third via hole of an insulating layer is electrically connected to the first electrode layer;
  • the method further includes: forming a second insulating layer;
  • the method further includes:
  • a fourth conductive layer is formed; wherein the fourth conductive layer includes a second connection trace; and one end of the second connection trace is electrically connected to the third electrode layer through the first via, the The other end of the second connection trace is electrically connected to the first connection trace through the second via hole.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a light emitting control circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the layout structure of a light-emitting control circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view of the layout structure shown in FIG. 3 along the AA' direction;
  • Fig. 5 is a schematic cross-sectional view of the layout structure shown in Fig. 3 along the BB' direction;
  • Fig. 6 is a schematic cross-sectional structure view along the CC' direction in the schematic layout structure shown in Fig. 3;
  • FIG. 7 is a schematic cross-sectional view of the layout structure shown in FIG. 3 along the DD' direction;
  • FIG. 8 is a schematic structural diagram of a scan driving circuit provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a layout structure of a scan driving circuit provided by an embodiment of the disclosure.
  • Fig. 10 is a schematic cross-sectional view of the layout structure shown in Fig. 9 along the AA' direction;
  • Fig. 11 is a schematic cross-sectional view of the layout structure shown in Fig. 9 along the BB' direction;
  • Fig. 12 is a schematic cross-sectional view of the layout structure shown in Fig. 9 along the CC' direction;
  • FIG. 13 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of the layout structure of the light emitting control circuit and the scan driving circuit provided by the embodiments of the disclosure.
  • the display panel may include: a base substrate 10, a driving circuit located on the base substrate 10, the driving circuit includes a storage capacitor; the display panel further includes: sequentially stacked on the base substrate 10 The first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 of, wherein the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 are arranged in different layers.
  • the first conductive layer 100 includes a first electrode layer
  • the second conductive layer 200 includes a second electrode layer
  • the third conductive layer 300 includes a third electrode layer; the orthographic projection of the first electrode layer on the base substrate 10, the second Both the orthographic projection of the electrode layer on the base substrate 10 and the orthographic projection of the third electrode layer on the base substrate 10 have overlapping areas.
  • the first electrode layer and the third electrode layer are electrically connected to each other as a first electrode of the storage capacitor, and the second electrode layer is used as a second electrode of the storage capacitor.
  • the first conductive layer includes the first electrode layer
  • the second conductive layer includes the second electrode layer
  • the third conductive layer includes the third electrode layer
  • the first electrode layer is on the substrate.
  • the orthographic projection of the substrate, the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the third electrode layer on the base substrate all have overlapping areas.
  • the first electrode layer and the third electrode layer can be electrically connected to each other as one electrode of the storage capacitor, and the second electrode layer can be used as the other electrode of the storage capacitor, so that the storage capacitor can be formed by a sandwich capacitor, which can improve the performance of the storage capacitor. Capacitance value.
  • the first electrode layer and the second electrode may have a facing area to form one sub-capacitor of the storage capacitor; and the second electrode and the third electrode may have a facing area to form the other sub-capacitor of the storage capacitor.
  • the storage capacitor is formed by connecting the two sub-capacitors in parallel to increase the capacitance value of the storage capacitor.
  • the facing area S of the storage capacitor can be reduced, so that the occupied area of the first electrode layer, the second electrode layer, and the third electrode layer of the storage capacitor on the base substrate 10 can be increased. It can be reduced, and the space occupied by the storage capacitor can be saved. Furthermore, since the occupied area of the storage capacitor is reduced, the space can be avoided. After the avoided space is integrated, other components can be set, for example, sub-pixel spx can be set, so that the resolution of the display panel can be improved; or, it can be set Sensors to improve the sensing ability of the display panel and so on.
  • the display panel may include a display area AA.
  • the display area AA may include a plurality of pixel units PX.
  • Each pixel unit PX may include a plurality of sub-pixels spx.
  • the pixel unit PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In this way, red, green and blue can be mixed to achieve color display.
  • the pixel unit PX may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In this way, red, green, blue and white can be mixed to achieve color display.
  • the light-emitting color of the sub-pixel spx in the pixel unit PX can be designed and determined according to the actual application environment, which is not limited here.
  • the display panel may be an electroluminescence display panel.
  • the sub-pixel spx may include a light-emitting element and a pixel circuit for driving the light-emitting element to emit light.
  • the light-emitting element includes an anode, a light-emitting layer, and a cathode that are stacked.
  • the light emitting element may include: at least one of organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED).
  • the display panel provided by the embodiment of the present disclosure may further include multiple gate lines, multiple light-emitting control signal lines, and multiple data lines.
  • the pixel circuits in a row of sub-pixels spx may be electrically connected to a gate line and a light emission control signal line
  • the pixel circuits in a column of sub-pixels spx may be electrically connected to a data line.
  • the display panel further includes a non-display area BB surrounding the display area AA.
  • the display panel may further include: a first signal driving line 11 and a second signal located in the non-display area BB.
  • the first signal driving line 11 can transmit a signal to the light-emitting control circuit 14 to drive the light-emitting control circuit 14 to generate a light-emitting control signal, and provide the light-emitting control signal to the light-emitting control signal line.
  • the second signal driving line 12 may transmit a signal to the scan driving circuit 13 to drive the scan driving circuit 13 to generate a scan signal and provide the scan signal to the gate line.
  • the light emitting control circuit 14 may be located on the side of the scan driving circuit 13 away from the display area AA.
  • the light-emitting control circuit 14 can also be located on the side of the scan driving circuit 13 facing the display area AA, which will not be repeated here.
  • the driving circuit may be configured as the light-emitting control circuit 14.
  • the storage capacitor in the light-emitting control circuit 14 can be set in the manner of a sandwich capacitor, thereby reducing the occupied area of the light-emitting control circuit 14.
  • the light emission control circuit 14 may include: a plurality of cascaded first shift registers.
  • the first input signal terminal IN1 of the first shift register of the first stage is electrically connected to the light-emitting trigger signal terminal.
  • the first input signal terminal IN1 of the first shift register of the next stage is electrically connected to the cascade signal output terminal GP of the first shift register of the previous stage.
  • the first signal output terminal GO of each first shift register is used to output a light-emitting control signal.
  • the first shift register may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a light-emitting control transistor T1 ⁇ T12.
  • the gate of the light emission control transistor T1 is electrically connected to the first clock signal terminal CK1
  • the first electrode of the light emission control transistor T1 is electrically connected to the first input signal terminal IN1
  • the second electrode of the light emission control transistor T1 is electrically connected to the first node PD_in. Electric connection.
  • the gate of the light emission control transistor T2 is electrically connected to the first node PD_in, the first electrode of the light emission control transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the light emission control transistor T2 is electrically connected to the second node PU.
  • the gate of the light emission control transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the light emission control transistor T3 is electrically connected to the first reference signal terminal VGL, and the second electrode of the light emission control transistor T3 is electrically connected to the second node PU .
  • the gate of the light emission control transistor T4 is electrically connected to the second node PU, the first electrode of the light emission control transistor T4 is electrically connected to the second reference signal terminal VGH, and the second electrode of the light emission control transistor T4 is electrically connected to the fourth node U4.
  • the gate of the light emission control transistor T5 is electrically connected to the third node PD_out, the first electrode of the light emission control transistor T5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the light emission control transistor T5 is electrically connected to the fourth node U4.
  • the gate of the light emission control transistor T6 is electrically connected to the second node PU, the first electrode of the light emission control transistor T6 is electrically connected to the second reference signal terminal VGH, and the second electrode of the light emission control transistor T6 is electrically connected to the first electrode of the light emission control transistor T7. Electric connection.
  • the gate of the light emission control transistor T7 is electrically connected to the second clock signal terminal CK2, and the second electrode of the light emission control transistor T7 is electrically connected to the first node PD_in.
  • the gate of the light emission control transistor T8 is electrically connected to the first reference signal terminal VGL, the first electrode of the light emission control transistor T8 is electrically connected to the first node PD_in, and the second electrode of the light emission control transistor T8 is electrically connected to the third node PD_out.
  • the gate of the light emission control transistor T9 is electrically connected to the fourth node U4, the first electrode of the light emission control transistor T9 is electrically connected to the second reference signal terminal VGH, and the second electrode of the light emission control transistor T9 is electrically connected to the fifth node PD_ox.
  • the gate of the light emission control transistor T10 is electrically connected to the first control signal terminal, the first electrode of the light emission control transistor T10 is electrically connected to the first reference signal terminal VGL, and the second electrode of the light emission control transistor T10 is electrically connected to the fifth node PD_ox.
  • the gate of the light emission control transistor T11 is electrically connected to the fourth node U4, the first electrode of the light emission control transistor T11 is electrically connected to the second reference signal terminal VGH, and the second electrode of the light emission control transistor T11 is electrically connected to the first signal output terminal GO .
  • the gate of the light emission control transistor T12 is electrically connected to the fifth node PD_ox, the first electrode of the light emission control transistor T12 is electrically connected to the first reference signal terminal VGL, and the second electrode of the light emission control transistor T12 is electrically connected to the first signal output terminal GO .
  • the first electrode of the first capacitor C1 is electrically connected to the fourth node U4, and the second electrode of the first capacitor C1 is electrically connected to the gate of the light emitting control transistor T5.
  • the first electrode of the second capacitor C2 is electrically connected to the second reference signal terminal VGH, and the second electrode of the second capacitor C2 is electrically connected to the gate of the light emitting control transistor T4.
  • the first electrode of the third capacitor C3 is electrically connected to the second control signal terminal, and the second electrode of the third capacitor C3 is electrically connected to the gate of the light emitting control transistor T12.
  • the first electrode of the fourth capacitor C4 is electrically connected to the first reference signal terminal VGL, and the second electrode of the fourth capacitor C4 is electrically connected to the gate of the light emitting control transistor T12.
  • the cascade signal output terminal GP is electrically connected to the fourth node U4.
  • the first signal driving line 11 may include: a first clock line ck1, a second clock line ck2, a first control line cb1, and a second control line cb1.
  • the second reference signal terminal VGH is electrically connected to the second reference line vgh.
  • first clock signal terminal CK1 of the first shift register of the odd-numbered stage and the second clock signal terminal CK2 of the first shift register of the even-numbered stage are both electrically connected to the first clock line ck1, and the first shift of the odd-numbered stage
  • the second clock signal terminal CK2 of the register and the first clock signal terminal CK1 of the first shift register of an even number stage are both electrically connected to the second clock line ck2.
  • At least one of the light-emitting control transistors T1 to T12 may be a double-gate transistor.
  • the light emission control transistors T1 to T12 may be all double gate transistors.
  • the light emission control transistors T1 to T12 may include a first bottom gate and a first top gate electrically connected to each other; and the first bottom gate is located on the first conductive layer 100, and the first top gate is located on the second conductive layer 200 .
  • the working process of the above-mentioned light-emitting control circuit can be basically the same as that in the related art, and will not be repeated here.
  • the light emission control circuit may also be a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the layout of the light emitting control circuit 14 on the base substrate 10.
  • FIG. 4 is a schematic cross-sectional structure diagram along the AA' direction in the layout diagram shown in FIG. 3.
  • Fig. 5 is a schematic cross-sectional structure view along the BB' direction in the layout schematic shown in Fig. 3.
  • FIG. 7 is a schematic cross-sectional structure diagram along the CC' direction in the layout diagram shown in FIG. 3.
  • FIG. 7 is a schematic cross-sectional structure diagram along the DD' direction in the layout diagram shown in FIG. 3.
  • the active semiconductor layer 500, the first conductive layer 100, the second conductive layer 200, the third conductive layer 300, and the fourth conductive layer 400 in the above-mentioned light emitting control circuit 14 are illustrated in conjunction with FIGS. 3 to 7 Schematic diagram of the relationship.
  • the display panel may further include: a buffer layer 111 between the first conductive layer 100 and the active semiconductor layer 500, and a gate insulating layer 112 between the buffer layer 111 and the second conductive layer 200, The second insulating layer 120 is located between the second conductive layer 200 and the third conductive layer 300, and the third insulating layer 130 is located between the third conductive layer 300 and the fourth conductive layer 400.
  • the storage capacitor may include at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4.
  • the storage capacitor may include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. That is to say, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can all be formed in the form of interlayer capacitors.
  • the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can all be formed in the form of interlayer capacitors as an example for description.
  • the first conductive layer 100 may include: the first bottom gates of the emission control transistors T1 to T12, and the first electrode of the first capacitor C1 Layer, the first electrode layer of the second capacitor C2, the first electrode layer of the third capacitor C3, and the first electrode layer of the fourth capacitor C4.
  • FIG. 4 shows the first bottom gate T8-L1 of the light emission control transistor T8, and the first electrode layer C1-1 of the first capacitor C1.
  • FIG. 5 shows the first bottom gate T6-L1 of the light emission control transistor T6 and the first electrode layer C2-1 of the second capacitor C2.
  • FIG. 7 shows the first bottom gate T7-L1 of the light emission control transistor T7.
  • the active semiconductor layer 500 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 500 can be used to fabricate the active layers of the aforementioned light-emitting control transistors T1 to T12, and each active layer can include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active layers of part of the transistors may be integrally provided.
  • the active semiconductor layer 500 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 4 shows the active layer T8-S of the emission control transistor T8.
  • FIG. 5 shows the active layer T4-S of the light emission control transistor T4 and the active layer T6-S of the light emission control transistor T6.
  • FIG. 7 shows the active layer T7-S of the light emission control transistor T7.
  • the second conductive layer 200 may include: the first top gate of the light emission control transistors T1 to T12, and the second electrode of the first capacitor C1 Layer, the second electrode layer of the second capacitor C2, the second electrode layer of the third capacitor C3, and the second electrode layer of the fourth capacitor C4.
  • FIG. 4 shows the first top gate T8-G1 of the light emission control transistor T8, and the second electrode layer C1-2 of the first capacitor C1.
  • FIG. 5 shows the first top gate T6-G1 of the light emission control transistor T6 and the second electrode layer C2-2 of the second capacitor C2.
  • FIG. 7 shows the first top gate T7-G1 of the light emission control transistor T7.
  • the third conductive layer 300 may include: a third electrode layer of the first capacitor C1, a third electrode layer of the second capacitor C2, and a third electrode layer of the second capacitor C2.
  • FIG. 4 shows the third electrode layer C1-3 of the first capacitor C1.
  • FIG. 5 shows the third electrode layer C2-3 of the second capacitor C2.
  • the fourth conductive layer 400 may include: a first signal driving line 11 (for example: a first clock line ck1, a second clock line ck2, The first control line cb1, the second control line cb2, the first reference line vgl, the second reference line vgh), and the connecting portion for electrically connecting the light-emitting control transistors T1 to T12 and the first capacitors C1 to C4 .
  • FIG. 4 shows the connecting portions T8-C1 for electrically connecting the light emitting control transistor T8 and the first capacitor C1, and the connecting portions T4-T5 for electrically connecting the light emitting control transistors T4 and T5.
  • one end of the connecting portion T8-C1 is electrically connected to the active layer of the light-emitting control transistor T8 through a via hole penetrating the gate insulating layer 112, the second insulating layer 120, and the third insulating layer 130.
  • the other end of the connecting portion T8-C1 is electrically connected to the second electrode layer C1-2 of the first capacitor C1 through a via hole penetrating the second insulating layer 120 and the third insulating layer 130.
  • FIG. 5 shows the connection portion T4-C2 that electrically connects the light-emission control transistor T4 and the second capacitor C2, and the connection portion T6-C2 that electrically connects the light-emission control transistor T6 and the second capacitor C2.
  • one end of the connecting portion T4-C2 is electrically connected to the active layer T4-S of the light-emitting control transistor T4 through a via hole penetrating the gate insulating layer 112, the second insulating layer 120, and the third insulating layer 130.
  • connection portion T6-C2 is electrically connected to the active layer T6-S of the light-emitting control transistor T6 through a via hole penetrating the gate insulating layer 112, the second insulating layer 120, and the third insulating layer 130.
  • the second conductive layer 200 may further include: a first connection trace arranged to be insulated from the second electrode layer; and the fourth conductive layer 400 may also It may include a second connection trace; and, one end of the second connection trace is electrically connected to the third electrode layer through the first via hole penetrating the third insulating layer 130, and the other end of the second connection trace is passed through the second insulation layer.
  • the second via holes of the layer 120 and the third insulating layer 130 are electrically connected to the first connection trace, and the first connection trace is electrically connected to the first electrode layer through the third via hole penetrating the first insulation layer 110, so that the second The one electrode layer and the third electrode layer are electrically connected through the first connecting wire and the second connecting wire.
  • the number of first via holes may be at least two.
  • the second connection trace can be electrically connected to the third electrode layer by using a plurality of first vias, so that when the second connection trace and the third electrode layer cannot be electrically connected by using part of the first vias, the second connection trace and the third electrode layer cannot be electrically connected.
  • the remaining first via holes can be used to realize electrical connection.
  • the number of first via holes may be two.
  • the first via hole can also be provided in multiple, which is not limited here.
  • the number of second via holes may be at least two.
  • the second connection trace can be electrically connected to the first connection trace by using multiple second vias, so that the second connection trace and the first connection trace cannot be electrically connected by using part of the second via holes.
  • It can also use the remaining second vias to achieve electrical connection.
  • the number of second via holes may be two.
  • the second via hole can also be provided in multiple, which is not limited here.
  • the number of third via holes may be at least two.
  • the first connection trace can be electrically connected to the first electrode layer by using a plurality of third vias, so that when the first connection trace and the first electrode layer cannot be electrically connected by using part of the third vias, the first connection trace can be electrically connected to the first electrode layer.
  • the remaining third via holes can be used for electrical connection.
  • the number of third via holes may be two.
  • the third via hole can also be provided in multiple, which is not limited here.
  • the orthographic projection of the first electrode layer C1-1 on the base substrate 10 the orthographic projection of the second electrode layer C1-2 on the base substrate 10
  • the third The electrode layers C1-3 all have overlapping areas on the orthographic projection of the base substrate 10.
  • One end of the second connecting wire 22-1 is electrically connected to the third electrode layer C1-3 through the two first vias 31-1 penetrating through the third insulating layer 130, and the other end of the second connecting wire 22-1 passes through
  • the two second vias 32-1 penetrating through the second insulating layer 120 and the third insulating layer 130 are electrically connected to the first connecting trace 21-1, and the first connecting trace 21-1 passes through the first insulating layer 110
  • the two third via holes 33-1 are electrically connected to the first electrode layer C1-1, so that the first electrode layer C1-1 and the third electrode layer C1-3 are connected to the second through the first connection trace 21-1
  • the wiring 22-1 is electrically connected to form a first electrode of the first capacitor C1, thereby forming a first capacitor C1 in a sandwich capacitor mode.
  • the second connecting wire 22-1 and the connecting portion T4-T5 may be provided as an integral structure. Of course, the present disclosure includes but is not limited to this.
  • the orthographic projection of the first electrode layer C2-1 on the base substrate 10 the orthographic projection of the second electrode layer C2-2 on the base substrate 10
  • the third The electrode layer C2-3 has an overlapping area on the orthographic projection of the base substrate 10.
  • One end of the second connecting wire 22-2 is electrically connected to the third electrode layer C2-3 through the two first vias 31-2 penetrating the third insulating layer 130, and the other end of the second connecting wire 22-2 passes through
  • the two second vias 32-2 penetrating through the second insulating layer 120 and the third insulating layer 130 are electrically connected to the first connecting trace 21-2, and the first connecting trace 21-2 passes through the first insulating layer 110
  • the two third via holes 33-2 are electrically connected to the first electrode layer C2-1, so that the first electrode layer C2-1 and the third electrode layer C2-3 are connected to the second through the first connection trace 21-2
  • the wiring 22-2 is electrically connected to form the first electrode of the second capacitor C2, thereby forming the second capacitor C2 in the form of a sandwich capacitor.
  • the second connecting wire 22-2 and the connecting portion T6-C2 may be provided as an integral structure. Of course, the present disclosure includes but is not limited to this.
  • the implementation manners thereof can be set with reference to the above-mentioned implementation manners, and will not be repeated here.
  • the orthographic projection of the second via on the base substrate 10 and the orthographic projection of the third via on the base substrate 10 may not overlap.
  • the orthographic projection of the second via 32-1 on the base substrate 10 and the orthographic projection of the third via 33-1 on the base substrate 10 do not overlap.
  • the orthographic projection of the second via 32-2 on the base substrate 10 and the orthographic projection of the third via 33-2 on the base substrate 10 do not overlap. In this way, the problem of abnormal electrical connection caused by too deep vias can be avoided.
  • the display panel may further include: a plurality of light-emitting control signal transmission lines EM-S located in the non-display area BB; among them, one light-emitting control signal
  • the transmission line EM-S is electrically connected to a light emission control signal line
  • the first signal output terminal GO of the light emission control circuit 14 is electrically connected to each light emission control signal transmission line EM-S.
  • the emission control signal transmission line EM-S is located in the first conductive layer 100.
  • the second poles of the light-emitting control transistors T11 and T12 are electrically connected by the connecting portions T11-T12, so as to serve as the first signal output terminal GO.
  • the connecting portions T11-T12 are electrically connected to the emission control signal transmission line EM-S located in the first conductive layer 100 to output the emission control signal to the emission control signal line through the emission control signal transmission line EM-S.
  • the second conductive layer 200 includes a third connecting trace 23, and the output terminal of the light-emitting control transistor passes through the second insulating layer 120 and the third insulating layer 120.
  • the fourth via 34 of the insulating layer 130 is electrically connected to the third connecting trace 23, and the third connecting trace 23 is electrically connected to the light emitting control signal transmission line EM-S through the fifth via 35 penetrating the buffer layer 111 and the gate insulating layer 112. Connected so that the emission control signal transmission line EM-S and the output end of the emission control transistor are electrically connected through the third connecting wire 23.
  • the mutually electrically connected second poles of the light-emission control transistors T11 and T12 may be used as the output terminal of the light-emission control transistor.
  • the connecting portions T11-T1 are electrically connected to the third connecting wire 23 through the fourth via 34.
  • the number of fourth via holes 34 may be provided at least two.
  • the connection portion T11-T1 can be electrically connected to the third connection trace 23 by using a plurality of fourth via holes 34, so that the connection portion T11-T1 and the third connection trace 23 cannot be electrically connected by using part of the fourth via hole 34.
  • the remaining fourth via holes 34 can also be used to realize electrical connection.
  • the fourth via 34 may be provided in two.
  • the fourth via 34 can also be provided in multiple, which is not limited here.
  • At least two fifth via holes 35 may be provided.
  • the third connection trace 23 can be electrically connected to the light-emitting control signal transmission line EM-S by using a plurality of fifth vias 35, so that part of the fifth vias are adopted in the third connection trace 23 and the light-emitting control signal transmission line EM-S.
  • the remaining fifth vias 35 can also be used to implement the electrical connection.
  • the number of the fifth via 35 may be two.
  • the fifth via 35 can also be provided in multiple, which is not limited here.
  • the orthographic projection of the fourth via 34 on the base substrate 10 and the orthographic projection of the fifth via 35 on the base substrate 10 can be made Do not overlap. In this way, the problem of abnormal electrical connection caused by too deep vias can be avoided.
  • the display panel may further include: a first transmission line located in the non-display area BB; wherein the first transmission line is electrically connected to the light-emitting control circuit 14.
  • the first transmission line includes a first sub-transmission line 41 and a second sub-transmission line 42; wherein, the first sub-transmission line 41 is located in the first conductive layer 100, and the second sub-transmission line 42 is located in the second conductive layer 200.
  • the first signal driving line 11 is electrically connected to the second sub-transmission line 42 through the sixth via 36 penetrating the second insulating layer 120 and the third insulating layer 130, and the second sub-transmission line 42 passes through the second sub-transmission line 42 penetrating the first insulating layer 110.
  • the seven via holes 37 are electrically connected to the first sub-transmission line 41, so that the first signal driving line 11 and the light-emitting control circuit 14 are electrically connected through the first sub-transmission line 41 and the second sub-transmission line 42.
  • the number of sixth via holes 36 may be set to at least two.
  • the first signal driving line 11 can be electrically connected to the second sub-transmission line 42 by using a plurality of sixth vias 36, so that the first signal driving line 11 and the second sub-transmission line 42 cannot be electrically connected by using part of the sixth vias 36.
  • the remaining sixth via holes 36 can also be used for electrical connection.
  • the number of sixth via holes 36 may be two.
  • the sixth via 36 can also be provided in multiple, which is not limited here.
  • the number of seventh via holes 37 may be set to at least two.
  • the second sub-transmission line 42 can be electrically connected to the first sub-transmission line 41 by using a plurality of seventh vias 37, so that the second sub-transmission line 42 and the first sub-transmission line 41 cannot be electrically connected by using part of the seventh vias 37.
  • the remaining seventh via holes 37 can also be used to achieve electrical connection.
  • the number of seventh via holes 37 may be set to two.
  • the seventh via hole 37 can also be provided in multiple, which is not limited here.
  • the orthographic projection of the sixth via 36 on the base substrate 10 and the orthographic projection of the seventh via 37 on the base substrate 10 may not overlap. In this way, the problem of abnormal electrical connection caused by too deep vias can be avoided.
  • the first clock line ck1, the second clock line ck2, the first control line cb1, the second control line cb2, and at least one of the first reference line vgl and the second reference line vgh may be the above-mentioned first transmission line.
  • the way is electrically connected to the light-emitting control circuit 14.
  • the second clock line ck2 as an example, as shown in FIGS.
  • the first transmission line electrically connected to the second clock line ck2 includes a first sub-transmission line 41 and a second sub-transmission line 42, and the second clock line ck2
  • the second sub-transmission line 42 is electrically connected to the second sub-transmission line 42 through the two sixth via holes 36, and the second sub-transmission line 42 is electrically connected to the first sub-transmission line 41 through the two seventh via holes 37, so that the second clock line ck2 and the light emitting control circuit
  • the first bottom gate T7-L1 and the first top gate T7-G1 of the light emission control transistor T7 in 14 are electrically connected, and the first top gate T7-G1 of the light emission control transistor T7 is also connected to the light emission control transistor T7 through the connection part T7-75.
  • the first electrode of the light emitting control transistor T5 is electrically connected.
  • the implementation of the first clock line ck1, the first control line cb1, the second control line cb2, the first reference line vgl, and the second reference line vgh can refer to the implementation of the second clock line ck2 described above, which will not be repeated here. .
  • the driving circuit may also be configured as the scan driving circuit 13.
  • the storage capacitor in the scan driving circuit 13 can be set in the manner of a sandwich capacitor, thereby reducing the occupied area of the scan driving circuit 13.
  • the scan driving circuit 13 may include a plurality of second shift registers connected in cascade.
  • the second input signal terminal IN2 of the second shift register of the first stage is electrically connected to the frame trigger signal terminal.
  • the second input signal terminal IN2 of the second shift register of the next stage is connected to the previous stage
  • the scan signal output terminal SO of the second shift register is electrically connected.
  • the scan signal output terminal SO of each second shift register is used to output a scan signal.
  • the second shift register may include: a fifth capacitor C5, a sixth capacitor C6, and scan control transistors T13 to T20.
  • the gate of the scan control transistor T13 is electrically connected to the third clock signal terminal CKB1
  • the first electrode of the scan control transistor T13 is electrically connected to the second input signal terminal IN2
  • the second electrode of the scan control transistor T13 is electrically connected to the sixth node PD_in1 Electric connection.
  • the gate of the scan control transistor T14 is electrically connected to the sixth node PD_in1, the first electrode of the scan control transistor T14 is electrically connected to the third clock signal terminal CKB1, and the second electrode of the scan control transistor T14 is electrically connected to the seventh node PU1.
  • the gate of the scan control transistor T15 is electrically connected to the third clock signal terminal CKB1, the first electrode of the scan control transistor T15 is electrically connected to the third reference signal terminal VSS, and the second electrode of the scan control transistor T15 is electrically connected to the seventh node PU1 .
  • the gate of the scan control transistor T16 is electrically connected to the seventh node PU1, the first electrode of the scan control transistor T16 is electrically connected to the fourth reference signal terminal VDD, and the second electrode of the scan control transistor T16 is electrically connected to the scan signal output terminal SO.
  • the gate of the scan control transistor T17 is electrically connected to the eighth node PD_out1, the first electrode of the scan control transistor T17 is electrically connected to the fourth clock signal terminal CKB2, and the second electrode of the scan control transistor T17 is electrically connected to the scan signal output terminal SO.
  • the gate of the scan control transistor T18 is electrically connected to the seventh node PU1, the first electrode of the scan control transistor T18 is electrically connected to the fourth reference signal terminal VDD, and the second electrode of the scan control transistor T18 is electrically connected to the first electrode of the scan control transistor T19. Electric connection.
  • the gate of the scan control transistor T19 is electrically connected to the fourth clock signal terminal CKB2, and the second electrode of the scan control transistor T19 is electrically connected to the sixth node PD_in1.
  • the gate of the scan control transistor T20 is electrically connected to the third reference signal terminal VSS, the first electrode of the scan control transistor T20 is electrically connected to the sixth node PD_in1, and the second electrode of the scan control transistor T20 is electrically connected to the eighth node PD_out1.
  • the first electrode of the fifth capacitor C5 is electrically connected to the scan signal output terminal SO, and the second electrode of the fifth capacitor C5 is electrically connected to the gate of the scan control transistor T17.
  • the first electrode of the sixth capacitor C6 is electrically connected to the fourth reference signal terminal VDD, and the second electrode of the sixth capacitor C6 is electrically connected to the gate of the scan control transistor T16.
  • the second signal driving line 12 may include: a third clock line ck3, a fourth clock line ck4, and a third reference line vddvss And a fourth reference line; wherein the third reference signal terminal VSS of all the second shift registers is electrically connected to the third reference line vss, and the fourth reference signal terminal VDD of all the second shift registers is electrically connected to the fourth reference line vdd electrical connection.
  • the third clock signal terminal CKB1 of the second shift register of the odd-numbered stage and the fourth clock signal terminal CKB2 of the second shift register of the even-numbered stage are electrically connected to the third clock line ck3, and the second shift of the odd-numbered stage
  • the second clock signal terminal CKB2 of the register and the first clock signal terminal CKB1 of the second shift register of an even number stage are both electrically connected to the fourth clock line ck4.
  • the scan control transistors T13 to T20 may be a double gate transistor.
  • the scan control transistors T13 to T20 may be all double gate transistors.
  • the scan control transistors T13 to T20 may include a second bottom gate and a second top gate electrically connected to each other; and the second bottom gate is located on the first conductive layer 100, and the second top gate is located on the second conductive layer 200 .
  • the working process of the above-mentioned scan driving circuit 13 may be basically the same as that in the related art, and will not be repeated here. It should be noted that, in the embodiment of the present disclosure, the scan driving circuit 13 may be a structure including other numbers of transistors in addition to the structure shown in FIG. 8, which is not limited in the embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the layout of the scan driving circuit 13 on the base substrate 10.
  • FIG. 10 is a schematic cross-sectional structure view along the AA' direction in the layout schematic diagram shown in FIG. 9.
  • Fig. 11 is a schematic cross-sectional structure view along the BB' direction in the layout schematic shown in Fig. 10.
  • Fig. 12 is a schematic cross-sectional structure diagram along the CC' direction in the layout diagram shown in Fig. 10.
  • the active semiconductor layer 500, the first conductive layer 100, the second conductive layer 200, the third conductive layer 300, and the fourth conductive layer 400 of the scan driving circuit 13 are connected to the active semiconductor layer 500 and the second conductive layer of the light emission control circuit 14, respectively.
  • the first conductive layer 100, the second conductive layer 200, the third conductive layer 300, and the fourth conductive layer 400 are arranged in the same layer and the same material, and the details are not repeated here.
  • the storage capacitor may include at least one of the fifth capacitor C5 and the sixth capacitor C6.
  • the storage capacitor may include a fifth capacitor C5 and a sixth capacitor C6. That is to say, the fifth capacitor C5 and the sixth capacitor C6 can both be formed by a sandwich capacitor. In the following description, both the fifth capacitor C5 and the sixth capacitor C6 can be formed by a sandwich capacitor as an example.
  • the first conductive layer 100 may further include: the second bottom gates of the scan control transistors T13 to T20, and the first conductive layer of the fifth capacitor C5 The electrode layer, the first electrode layer of the sixth capacitor C6.
  • FIG. 10 shows the first electrode layer C5-1 of the fifth capacitor C5.
  • FIG. 11 shows the first electrode layer C6-1 of the sixth capacitor C6 and the second bottom gate T16-L1 of the scan driving transistor T16.
  • the active semiconductor layer 500 can be used to fabricate the active layers of the scan control transistors T13 to T20, and each active layer can include a source electrode. Region, drain region, and channel region between source region and drain region.
  • the active layers of part of the transistors may be integrally provided.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 11 shows the active layer T18-S of the scan driving transistor T18.
  • the second conductive layer 200 may further include: the second top gate of the scan control transistors T13 to T20, and the second top gate of the fifth capacitor C5.
  • FIG. 10 shows the second electrode layer C5-2 of the fifth capacitor C5 and the first connection wiring 21-5.
  • FIG. 11 shows the second electrode layer C6-2 of the sixth capacitor C6 and the first connection wiring 21-6, and the second top gate T16-G1 of the scan driving transistor T16.
  • the third conductive layer 300 may further include: a third electrode layer of the fifth capacitor C5 and a third electrode layer of the sixth capacitor C6.
  • FIG. 10 shows the third electrode layer C5-3 of the fifth capacitor C5.
  • FIG. 11 shows the third electrode layer C6-3 of the sixth capacitor C6.
  • the fourth conductive layer 400 may further include: a second signal driving line 12 (for example: the third clock line ck3, the fourth clock line ck4 , The third reference line vss, the fourth reference line vdd), used to electrically connect the scan control transistors T13 to T20, the fifth capacitor C5, the sixth capacitor C6, and the second connection lines 22-5 and 22 -6.
  • FIG. 10 shows the second connection wiring 22-5 and the connection portions T17-C5 that electrically connect the scan control transistor T17 and the fifth capacitor C5C5, and one end of the connection portion T17-C5 passes through the gate insulating layer 112.
  • the vias of the second insulating layer 120 and the third insulating layer 130 are electrically connected to the active layer of the scan control transistor T17.
  • the second connecting wire 22-5 and the connecting portion T17-C5 are an integral structure.
  • the orthographic projection of the first electrode layer C5-1 on the base substrate 10 the orthographic projection of the second electrode layer C5-2 on the base substrate 10
  • the third The electrode layer C5-3 has an overlapping area on the orthographic projection of the base substrate 10.
  • One end of the second connecting wire 22-5 is electrically connected to the third electrode layer C5-3 through the four first vias 31-5 penetrating through the third insulating layer 130, and the other end of the second connecting wire 22-5 passes through
  • the two second vias 32-5 penetrating through the second insulating layer 120 and the third insulating layer 130 are electrically connected to the first connecting trace 21-5, and the first connecting trace 21-5 passes through the first insulating layer 110
  • the two third vias 33-5 are electrically connected to the first electrode layer C5-1, so that the first electrode layer C5-1 and the third electrode layer C5-3 are connected to the second through the first connection trace 21-5
  • the wiring 22-5 is electrically connected to form the first electrode of the fifth capacitor C5, thereby forming the fifth capacitor C5 in a sandwich capacitor manner.
  • the orthographic projection of the first electrode layer C6-1 on the base substrate 10 the orthographic projection of the second electrode layer C6-2 on the base substrate 10
  • the third The electrode layer C6-3 has an overlapping area on the orthographic projection of the base substrate 10.
  • One end of the second connecting wire 22-6 is electrically connected to the third electrode layer C6-3 through the two first vias 31-6 penetrating through the third insulating layer 130, and the other end of the second connecting wire 22-6 passes through
  • the two second vias 32-6 penetrating through the second insulating layer 120 and the third insulating layer 130 are electrically connected to the first connecting trace 21-6, and the first connecting trace 21-6 passes through the first insulating layer 110
  • the two third via holes 33-6 are electrically connected to the first electrode layer C6-1, so that the first electrode layer C6-1 and the third electrode layer C6-3 are connected to the second through the first connection trace 21-6
  • the wiring 22-6 is electrically connected to form the first electrode of the sixth capacitor C6, thereby forming the sixth capacitor C6 in the form of a sandwich capacitor.
  • the orthographic projection of the second via 32-5 on the base substrate 10 and the orthographic projection of the third via 33-5 on the base substrate 10 do not overlap.
  • the orthographic projection of the second via 32-6 on the base substrate 10 and the orthographic projection of the third via 33-6 on the base substrate 10 do not overlap. In this way, the problem of abnormal electrical connection caused by too deep vias can be avoided.
  • the display panel may further include: a second transmission line located in the non-display area BB; wherein the first transmission line is electrically connected to the scan driving circuit 13.
  • the second transmission line includes a third sub-transmission line 43 and a fourth sub-transmission line 44; wherein, the third sub-transmission line 43 is located in the first conductive layer 100, and the fourth sub-transmission line 44 is located in the second conductive layer 200.
  • the second signal driving line 12 is electrically connected to the fourth sub-transmission line 44 through the eighth via 38 penetrating the second insulating layer 120 and the third insulating layer 130, and the fourth sub-transmission line 44 passes through the first insulating layer 110.
  • the nine vias 39 are electrically connected to the third sub-transmission line 43, so that the second signal driving line 12 and the scan driving circuit 13 are electrically connected through the third sub-transmission line 43 and the fourth sub-transmission line 44.
  • the number of eighth via 38 may be set to at least two.
  • the second signal driving line 12 can be electrically connected to the fourth sub-transmission line 44 by using a plurality of eighth vias 38, so that the second signal driving line 12 and the fourth sub-transmission line 44 cannot be electrically connected by using part of the eighth via 38.
  • the remaining eighth via 38 can also be used for electrical connection.
  • the eighth via 38 may be provided in two.
  • the eighth via 38 can also be provided in multiple, which is not limited here.
  • the number of ninth via holes 39 may be set to at least two.
  • the fourth sub-transmission line 44 can be electrically connected to the third sub-transmission line 43 by using a plurality of ninth vias 39, so that the fourth sub-transmission line 44 and the third sub-transmission line 43 cannot be electrically connected by part of the ninth via 39.
  • the remaining ninth via 39 can also be used to achieve electrical connection.
  • the number of ninth via holes 39 may be two.
  • the ninth via 39 can also be provided in multiple, which is not limited here.
  • the orthographic projection of the eighth via 38 on the base substrate 10 and the orthographic projection of the ninth via 39 on the base substrate 10 may not overlap. In this way, the problem of abnormal electrical connection caused by too deep vias can be avoided.
  • At least one of the third clock line ck3, the fourth clock line ck4, the third reference line vss, and the fourth reference line vdd may be electrically connected to the scan driving circuit 13 in the manner of the second transmission line described above.
  • the third clock line ck3 as an example, as shown in FIGS.
  • the second transmission line electrically connected to the third clock line ck3 includes a third sub-transmission line 43 and a fourth sub-transmission line 44, and the third clock line ck3
  • the fourth sub-transmission line 44 is electrically connected to the fourth sub-transmission line 44 through the two eighth via holes 38, and the fourth sub-transmission line 44 is electrically connected to the third sub-transmission line 43 through the two ninth via holes 39, so that the third clock line ck3 and the scan driving circuit
  • the second bottom gate and the second top gate of the scan control transistor T15 in 13 are electrically connected.
  • the implementation manners of the fourth clock line ck4, the third reference line vss, and the fourth reference line can refer to the implementation manner of the third clock line ck3 described above, and details are not described herein.
  • the driving circuit may also be configured as a pixel circuit.
  • the storage capacitor in the pixel circuit can be set by a sandwich capacitor, thereby reducing the area occupied by the pixel circuit.
  • the pixel circuit 0121 may include: a pixel driving circuit 0122, a first light emission control circuit 123, a second light emission control circuit 124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129.
  • the pixel driving circuit 0122 includes a control terminal, a first terminal and a second terminal, and is configured to provide the light-emitting element 0120 with a driving current for driving the light-emitting element 0120 to emit light.
  • the first light-emitting control circuit 123 is connected to the first terminal of the pixel driving circuit 0122 and the first power supply terminal PVDD, and is configured to realize the on or off of the connection between the pixel driving circuit 0122 and the first power supply terminal PVDD
  • the second light-emitting control circuit 124 is electrically connected to the second end of the pixel driving circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120, and is configured to realize on or off the connection between the pixel driving circuit 0122 and the light-emitting element 0120 open.
  • the data writing circuit 0126 is electrically connected to the first terminal of the pixel driving circuit 0122, and is configured to write the data signal into the storage circuit 0127 under the control of the scan signal; the storage circuit 0127 and the control terminal of the pixel driving circuit 0122 and the first terminal
  • the power supply terminal PVDD is electrically connected and is configured to store data signals;
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the pixel drive circuit 0122, and is configured to perform threshold compensation on the pixel drive circuit 0122;
  • the reset circuit 0129 and The control terminal of the pixel drive circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120 are electrically connected, and are configured to apply electrodes to the control terminal of the pixel drive circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120 under the control of a reset control signal Perform a reset.
  • the pixel driving circuit 0122 includes a driving transistor T01
  • the control terminal of the pixel driving circuit 0122 includes the gate of the driving transistor T01
  • the first terminal of the pixel driving circuit 0122 includes the first of the driving transistor T01.
  • the second terminal of the pixel driving circuit 0122 includes the second terminal of the driving transistor T01.
  • the data writing circuit 0126 includes a data writing transistor T02
  • the storage circuit 0127 includes a seventh capacitor C7
  • the threshold compensation circuit 0128 includes a threshold compensation transistor T03
  • the first light emission control circuit 123 includes a first The light emission control transistor T04
  • the second light emission control circuit 124 includes a second light emission control transistor T05
  • the reset circuit 0129 includes a first reset transistor T06 and a second reset transistor T07.
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal. Reset control signal.
  • the first pole of the data writing transistor T02 is electrically connected to the first pole of the driving transistor T01
  • the second pole of the data writing transistor T02 is configured to be electrically connected to the data line Vd to receive the data signal
  • the gate of T02 is configured to be electrically connected to the gate line GA to receive the scan signal
  • the first electrode of the seventh capacitor C7 is electrically connected to the first power supply terminal PVDD
  • the second electrode of the seventh capacitor C7 is electrically connected to the gate of the driving transistor T01
  • the first pole of the threshold compensation transistor T03 is electrically connected to the second pole of the driving transistor T01
  • the second pole of the threshold compensation transistor T03 is electrically connected to the gate of the driving transistor T01
  • the gate of the threshold compensation transistor T03 is configured as
  • the first electrode of the first reset transistor T06 is electrically connected to the gate line GA to receive the scan signal
  • the first electrode of the first reset transistor T06 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset
  • one of the first power supply terminal PVDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal PVDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the pixel circuit in the sub-pixel spx may be a structure including other numbers of transistors in addition to the structure shown in FIG. 13, which is not limited in the embodiment of the present disclosure. .
  • the storage capacitor may include a seventh capacitor. That is to say, the seventh capacitor can be formed by a sandwich capacitor. It should be noted that the implementation of the first capacitor C1 to form a sandwich capacitor can refer to the foregoing implementation of the first capacitor C1 to the sixth capacitor C6, which is not repeated here.
  • the light emission control signal transmission line EM-S can be The orthographic projection of the base substrate 10 and the orthographic projection of the scan driving circuit on the base substrate 10 have an overlapping area.
  • the orthographic projection of the emission control signal transmission line EM-S on the base substrate 10 can be compared with the scanning control transistor T17 in the second shift register of the upper stage and the scanning of the second shift register of the next stage.
  • the connection portion T17-T1 of the control transistor T1 has an overlapping area on the orthographic projection of the base substrate 10.
  • the emission control signal transmission line EM-S of the emission control circuit 14 is located in the first conductive layer, since the distance between the first conductive layer and the fourth conductive layer is relatively long, the scanning driving effect of the emission control signal transmission line EM-S can be reduced. Signal interference from the circuit.
  • embodiments of the present disclosure also provide a method for manufacturing the above-mentioned display panel, which may include the following steps:
  • a first conductive layer 100, a second conductive layer 200, and a third conductive layer 300 are sequentially formed on the base substrate 10 to form a driving circuit on the base substrate 10; wherein, the first conductive layer 100 includes a first electrode layer , The second conductive layer 200 includes a second electrode layer, and the third conductive layer 300 includes a third electrode layer; the orthographic projection of the first electrode layer on the base substrate 10, the orthographic projection of the second electrode layer on the base substrate 10, and the first The three electrode layers all have overlapping areas on the orthographic projection of the base substrate 10; the first electrode layer and the third electrode layer are electrically connected to each other as the first electrode of the storage capacitor, and the second electrode layer is used as the second electrode of the storage capacitor.
  • the second conductive layer 200 includes a first connection trace that is insulated from the second electrode layer.
  • the first conductive layer 100 and before forming the second conductive layer 200 may further include: forming a first insulating layer 110 with a third via; wherein, The first connection trace is electrically connected to the first electrode layer through a third via hole penetrating the first insulating layer 110.
  • the second conductive layer 200 and before forming the third conductive layer 300 may further include: forming the second insulating layer 120.
  • the third conductive layer 300 may further include:
  • a fourth conductive layer 400 is formed; wherein, the fourth conductive layer 400 includes a second connection trace; and one end of the second connection trace is electrically connected to the third electrode layer through the first via hole, and the other end of the second connection trace It is electrically connected to the first connection trace through the second via hole.
  • the above-mentioned patterning process may be used to form various structures in the first conductive layer 100 to the fourth conductive layer 400, and an etching process may be used to form the above-mentioned via holes.
  • the patterning process may only include a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns; the photolithography process means including The process of film formation, exposure, development and other processes uses photoresist, mask, exposure machine, etc. to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the present disclosure.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the first conductive layer includes the first electrode layer
  • the second conductive layer includes the second electrode layer
  • the third conductive layer includes the third electrode layer
  • the orthographic projection of the first electrode layer on the base substrate, the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the third electrode layer on the base substrate all have overlapping areas.
  • the first electrode layer and the third electrode layer can be electrically connected to each other as one electrode of the storage capacitor, and the second electrode layer can be used as the other electrode of the storage capacitor, so that the storage capacitor can be formed by a sandwich capacitor, which can improve the performance of the storage capacitor. Capacitance value.
  • the first electrode layer and the second electrode may have a facing area to form one sub-capacitor of the storage capacitor; and the second electrode and the third electrode may have a facing area to form the other sub-capacitor of the storage capacitor.
  • the storage capacitor is formed by connecting the two sub-capacitors in parallel to increase the capacitance value of the storage capacitor.

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Abstract

本公开公开了一种显示面板、其制备方法及显示装置，通过使第一导电层包括第一电极层，第二导电层包括第二电极层以及第三导电层包括第三电极层，并且使第一电极层在衬底基板的正投影、第二电极层在衬底基板的正投影以及第三电极层在衬底基板的正投影均具有交叠区域。这样可以使第一电极层和第三电极层相互电连接作为存储电容的一个电极，第二电极层作为存储电容的另一个电极，从而可以采用夹层电容的方式形成存储电容，可以提高存储电容的电容值。

Description

显示面板、其制备方法及显示装置
相关申请的交叉引用
本公开要求在2019年11月29日提交中国专利局、申请号为201911205633.5、申请名称为“一种显示面板、其制备方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板、其制备方法及显示装置。
背景技术
随着显示技术的快速发展，各种类型的显示面板逐渐进入市场，且得到了广泛的应用。例如，显示面板可配置于手机、平板电脑、电视、智能穿戴设备、公共场所大厅的信息查询机等各种智能终端，以更好地实现人机交互。一般显示面板中会设置有电路，电路中通常设置有存储电容。由于存储电容需要实现存储和稳压功能，使得存储电容的占用面积较大，从而导致显示面板内设置其他元件的空间减低。因此，如何在不减小存储电容的电容值的情况下，降低存储电容的占用面积，是本领域技术人员亟待解决的技术问题。
发明内容
本公开实施例提供了一种显示面板，包括：衬底基板，位于所述衬底基板上的驱动电路，所述驱动电路包括存储电容；所述显示面板还包括：依次层叠位于所述衬底基板上的第一导电层、第二导电层以及第三导电层；其中，所述第一导电层、所述第二导电层以及所述第三导电层异层设置；
所述第一导电层包括第一电极层，所述第二导电层包括第二电极层，所述第三导电层包括第三电极层；
所述第一电极层在所述衬底基板的正投影、所述第二电极层在所述衬底基板的正投影以及所述第三电极层在所述衬底基板的正投影均具有交叠区域；
所述第一电极层和所述第三电极层相互电连接作为所述存储电容的第一电极，所述第二电极层作为所述存储电容的第二电极。
可选地，在本公开实施例中，所述显示面板还包括：位于所述第一导电层和所述第二导电层之间的第一绝缘层，位于所述第二导电层与所述第三导电层之间的第二绝缘层，位于所述第三导电层背离所述衬底基板一侧的第三绝缘层，以及位于所述第三绝缘层背离所述衬底基板一侧的第四导电层；
所述第二导电层包括与所述第二电极层绝缘设置的第一连接走线；所述第四导电层包括第二连接走线；
所述第二连接走线的一端通过贯穿所述第三绝缘层的第一过孔与所述第三电极层电连接，所述第二连接走线的另一端通过贯穿所述第二绝缘层和所述第三绝缘层的第二过孔与所述第一连接走线电连接，所述第一连接走线通过贯穿所述第一绝缘层的第三过孔与所述第一电极层电连接，以使所述第一电极层和所述第三电极层通过所述第一连接走线和所述第二连接走线电连接。
可选地，在本公开实施例中，所述第一过孔设置为至少两个；和/或，
所述第二过孔设置为至少两个；和/或，
所述第三过孔设置为至少两个。
可选地，在本公开实施例中，所述第二过孔在所述衬底基板的正投影和所述第三过孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述显示面板还包括：位于非显示区中的扫描驱动电路和发光控制电路以及位于显示区中的像素电路；
所述驱动电路为所述扫描驱动电路、所述发光控制电路以及所述像素电路中的至少一种。
可选地，在本公开实施例中，所述显示面板还包括：位于所述显示区中的多条发光控制信号线，以及位于所述非显示区中的多条发光控制信号传输线；其中，一条所述发光控制信号传输线与一条所述发光控制信号线电连接， 所述发光控制电路的第一信号输出端分别与各所述发光控制信号传输线电连接；
所述发光控制信号传输线位于所述第一导电层。
可选地，在本公开实施例中，所述第一绝缘层包括位于所述第一导电层与所述第二导电层之间的缓冲层、以及位于所述缓冲层与所述第二导电层之间的栅绝缘层；
所述第二导电层包括第三连接走线，所述发光控制电路包括发光控制晶体管，所述发光控制晶体管的输出端通过贯穿所述第二绝缘层和所述第三绝缘层的第四过孔与所述第三连接走线电连接，所述第三连接走线通过贯穿所述缓冲层和所述栅绝缘层的第五过孔与所述发光控制信号传输线电连接，以使所述发光控制信号传输线与所述发光控制晶体管的输出端，通过所述第三连接走线电连接。
可选地，在本公开实施例中，所述第四过孔设置为至少两个；和/或，
所述第五过孔设置为至少两个；和/或，
所述第四过孔在所述衬底基板的正投影和所述第五过孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述显示面板还包括：位于所述非显示区的第一信号驱动线和第一传输线；其中，所述第一信号驱动线位于所述第四导电层；所述第一传输线与所述发光控制电路电连接；
所述第一传输线包括第一子传输线和第二子传输线；其中，所述第一子传输线位于所述第一导电层，所述第二子传输线位于所述第二导电层；
所述第一信号驱动线通过贯穿所述第二绝缘层和所述第三绝缘层的第六过孔与所述第二子传输线电连接，所述第二子传输线通过贯穿所述第一绝缘层的第七过孔与所述第一子传输线电连接，使得所述第一信号驱动线和所述发光控制电路，通过所述第一子传输线和所述第二子传输线电连接。
可选地，在本公开实施例中，所述第六过孔设置为至少两个；和/或，
所述第七过孔设置为至少两个；和/或，
所述第六过孔在所述衬底基板的正投影与所述第七过孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述发光控制晶体管为双栅型晶体管，且所述发光控制晶体管包括相互电连接的第一底栅极和第一顶栅极；
所述第一底栅极位于所述第一导电层，所述第一顶栅极位于所述第二导电层。
可选地，在本公开实施例中，所述显示面板还包括：位于所述非显示区的第二信号驱动线和第二传输线；
所述第二传输线包括第三子传输线和第四子传输线；其中，所述第三子传输线位于所述第一导电层，所述第四子传输线位于所述第二导电层；
所述第二信号驱动线通过贯穿所述第二绝缘层和所述第三绝缘层的第八过孔与所述第四子传输线电连接，所述第四子传输线通过贯穿所述第一绝缘层的第九过孔与所述第三子传输线电连接，使得所述第二信号驱动线和所述扫描驱动电路，通过所述第三子传输线和所述第四子传输线电连接。
可选地，在本公开实施例中，所述第八过孔设置为至少两个；和/或，
所述第九过孔设置为至少两个；和/或，
所述第八过孔在所述衬底基板的正投影与所述第九过孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述扫描驱动电路包括扫描控制晶体管；
所述扫描控制晶体管为双栅型晶体管，且所述扫描控制晶体管包括相互电连接的第二底栅极和第二顶栅极；
所述第二底栅极位于所述第一导电层，所述第二顶栅极位于所述第二导电层。
可选地，在本公开实施例中，所述发光控制电路位于所述扫描驱动电路背离所述显示区的一侧，且，所述发光控制信号传输线在所述衬底基板的正投影与所述扫描驱动电路在所述衬底基板上的正投影具有交叠区域。
本公开实施例还提供了一种显示装置，包括上述显示面板。
本公开实施例还提供了一种上述显示面板的制备方法，包括：
在衬底基板上依次形成第一导电层、第二导电层以及第三导电层，以形成位于所述衬底基板上的驱动电路；
其中，所述第一导电层包括第一电极层，所述第二导电层包括第二电极层，所述第三导电层包括第三电极层；
所述第一电极层在所述衬底基板的正投影、所述第二电极层在所述衬底基板的正投影以及所述第三电极层在所述衬底基板的正投影均具有交叠区域；
所述第一电极层和所述第三电极层相互电连接作为所述存储电容的第一电极，所述第二电极层作为所述存储电容的第二电极。
可选地，在本公开实施例中，所述第二导电层包括与所述第二电极层绝缘设置的第一连接走线；
在形成所述第一导电层之后，且在形成所述第二导电层之前，还包括：形成具有第三过孔的第一绝缘层；其中，所述第一连接走线通过贯穿所述第一绝缘层的第三过孔与所述第一电极层电连接；
在形成所述第二导电层之后，且在形成所述第三导电层之前，还包括：形成第二绝缘层；
在形成所述第三导电层之后，还包括：
形成第三绝缘层、贯穿所述第三绝缘层的第一过孔以及贯穿所述第二绝缘层和所述第三绝缘层的第二过孔；
形成第四导电层；其中，所述第四导电层包括第二连接走线；且所述第二连接走线的一端通过所述第一过孔与所述第三电极层电连接，所述第二连接走线的另一端通过所述第二过孔与所述第一连接走线电连接。
附图说明
图1为本公开实施例提供的显示面板的结构示意图；
图2为本公开实施例提供的发光控制电路的结构示意图；
图3为本公开实施例提供的发光控制电路的布局结构示意图；
图4为图3所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图5为图3所示的布局结构示意图中沿BB’方向上的剖视结构示意图；
图6为图3所示的布局结构示意图中沿CC’方向上的剖视结构示意图；
图7为图3所示的布局结构示意图中沿DD’方向上的剖视结构示意图；
图8为本公开实施例提供的扫描驱动电路的结构示意图；
图9为本公开实施例提供的扫描驱动电路的布局结构示意图；
图10为图9所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图11为图9所示的布局结构示意图中沿BB’方向上的剖视结构示意图；
图12为图9所示的布局结构示意图中沿CC’方向上的剖视结构示意图；
图13为本公开实施例提供的像素电路的结构示意图；
图14为本公开实施例提供的发光控制电路和扫描驱动电路的布局结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在具体实施时，本公开实施例中，显示面板可以包括：衬底基板10，位于衬底基板10上的驱动电路，驱动电路包括存储电容；显示面板还包括：依次层叠位于衬底基板10上的第一导电层100、第二导电层200以及第三导电层300；其中，第一导电层100、第二导电层200以及第三导电层300异层设置。并且，第一导电层100包括第一电极层，第二导电层200包括第二电极层，第三导电层300包括第三电极层；第一电极层在衬底基板10的正投影、第二电极层在衬底基板10的正投影以及第三电极层在衬底基板10的正投影均具有交叠区域。以及，第一电极层和第三电极层相互电连接作为存储电容的第一电极，第二电极层作为存储电容的第二电极。
本公开实施例提供的驱动电路，通过使第一导电层包括第一电极层，第二导电层包括第二电极层以及第三导电层包括第三电极层，并且使第一电极层在衬底基板的正投影、第二电极层在衬底基板的正投影以及第三电极层在衬底基板的正投影均具有交叠区域。这样可以使第一电极层和第三电极层相互电连接作为存储电容的一个电极，第二电极层作为存储电容的另一个电极，从而可以采用夹层电容的方式形成存储电容，可以提高存储电容的电容值。
也就是说，可以使第一电极层和第二电极具有正对面积，以形成存储电容的一个子电容；以及使第二电极和第三电极具有正对面积，以形成存储电容的另一个子电容。通过使这两个子电容采用并联的方式形成存储电容，以提高存储电容的电容值。
并且，根据存储电容的电容值C满足的公式：C＝εS/4πkd可知，若存储电容的电容值为固定值，由于采用夹层电容的方式形成的存储电容，可以提高存储电容的电容值，因此，在电容值固定的情况下，可以减小存储电容的正对面积S，从而可以使形成存储电容的第一电极层、第二电极层以及第三电极层在衬底基板10上的占用面积降低，进而可以节省存储电容占用的空间。 进一步地，由于存储电容的占用面积降低，可以避让出空间，在将这些避让的空间整合后，可以设置其他元件，例如可以设置子像素spx，从而可以提高显示面板的分辨率；或者，可以设置传感器，以提高显示面板的感应能力等等。
在具体实施时，如图1所示，显示面板可以包括显示区AA。其中，显示区AA可以包括多个像素单元PX。每个像素单元PX可以包括多个子像素spx。示例性地，像素单元PX可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元PX也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元PX中的子像素spx的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，显示面板可以是电致发光显示面板。在本公开实施例中，子像素spx可以包括发光元件以及用于驱动发光元件发光的像素电路。其中，发光元件包括层叠设置的阳极、发光层以及阴极。进一步地，发光元件可以包括：有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。
进一步地，在具体实施时，本公开实施例提供的显示面板还可以包括多条栅线、多条发光控制信号线以及多条数据线。示例性地，一行子像素spx中的像素电路可以对应电连接一条栅线和一条发光控制信号线，一列子像素spx中的像素电路可以电连接一条数据线。
在具体实施时，如图1所示，显示面板还包括围绕显示区AA的非显示区BB。在本公开实施例中，为了向栅线输入扫描信号，以及为了向发光控制信号线输入发光控制信号，显示面板还可以包括：位于非显示区BB中的第一信号驱动线11、第二信号驱动线12、扫描驱动电路13以及发光控制电路14。其中，第一信号驱动线11可以向发光控制电路14传输信号，以驱动发光控制电路14产生发光控制信号，并将发光控制信号提供给发光控制信号线。第二信号驱动线12可以向扫描驱动电路13传输信号，以驱动扫描驱动电路13 产生扫描信号，并将扫描信号提供给栅线。
在具体实施时，在本公开实施例中，如图1所示，可以使发光控制电路14位于扫描驱动电路13背离显示区AA的一侧。当然，也可以使发光控制电路14位于扫描驱动电路13面向显示区AA的一侧，在此不作赘述。
在具体实施时，在本公开实施例中，可以使驱动电路设置为发光控制电路14。这样可以使发光控制电路14中的存储电容采用夹层电容的方式进行设置，从而降低发光控制电路14的占用面积。
在具体实施时，在本公开实施例中，发光控制电路14可以包括：多个级联的第一移位寄存器。第一级第一移位寄存器的第一输入信号端IN1与发光触发信号端电连接。其余第一移位寄存器中，下一级第一移位寄存器的第一输入信号端IN1与上一级第一移位寄存器的级联信号输出端GP电连接。并且，每一个第一移位寄存器的第一信号输出端GO用于输出发光控制信号。
在具体实施时，在本公开实施例中，如图2所示，第一移位寄存器可以包括：第一电容C1、第二电容C2、第三电容C3、第四电容C4，以及发光控制晶体管T1～T12。其中，发光控制晶体管T1的栅极与第一时钟信号端CK1电连接，发光控制晶体管T1的第一极与第一输入信号端IN1电连接，发光控制晶体管T1的第二极与第一节点PD_in电连接。
发光控制晶体管T2的栅极与第一节点PD_in电连接，发光控制晶体管T2的第一极与第一时钟信号端CK1电连接，发光控制晶体管T2的第二极与第二节点PU电连接。
发光控制晶体管T3的栅极与第一时钟信号端CK1电连接，发光控制晶体管T3的第一极与第一参考信号端VGL电连接，发光控制晶体管T3的第二极与第二节点PU电连接。
发光控制晶体管T4的栅极与第二节点PU电连接，发光控制晶体管T4的第一极与第二参考信号端VGH电连接，发光控制晶体管T4的第二极与第四节点U4电连接。
发光控制晶体管T5的栅极与第三节点PD_out电连接，发光控制晶体管 T5的第一极与第二时钟信号端CK2电连接，发光控制晶体管T5的第二极与第四节点U4电连接。
发光控制晶体管T6的栅极与第二节点PU电连接，发光控制晶体管T6的第一极与第二参考信号端VGH电连接，发光控制晶体管T6的第二极与发光控制晶体管T7的第一极电连接。
发光控制晶体管T7的栅极与第二时钟信号端CK2电连接，发光控制晶体管T7的第二极与第一节点PD_in电连接。
发光控制晶体管T8的栅极与第一参考信号端VGL电连接，发光控制晶体管T8的第一极与第一节点PD_in电连接，发光控制晶体管T8的第二极与第三节点PD_out电连接。
发光控制晶体管T9的栅极与第四节点U4电连接，发光控制晶体管T9的第一极与第二参考信号端VGH电连接，发光控制晶体管T9的第二极与第五节点PD_ox电连接。
发光控制晶体管T10的栅极与第一控制信号端电连接，发光控制晶体管T10的第一极与第一参考信号端VGL电连接，发光控制晶体管T10的第二极与第五节点PD_ox电连接。
发光控制晶体管T11的栅极与第四节点U4电连接，发光控制晶体管T11的第一极与第二参考信号端VGH电连接，发光控制晶体管T11的第二极与第一信号输出端GO电连接。
发光控制晶体管T12的栅极与第五节点PD_ox电连接，发光控制晶体管T12的第一极与第一参考信号端VGL电连接，发光控制晶体管T12的第二极与第一信号输出端GO电连接。
第一电容C1的第一电极与第四节点U4电连接，第一电容C1的第二电极与发光控制晶体管T5的栅极电连接。
第二电容C2的第一电极与第二参考信号端VGH电连接，第二电容C2的第二电极与发光控制晶体管T4的栅极电连接。
第三电容C3的第一电极与第二控制信号端电连接，第三电容C3的第二 电极与发光控制晶体管T12的栅极电连接。
第四电容C4的第一电极与第一参考信号端VGL电连接，第四电容C4的第二电极与发光控制晶体管T12的栅极电连接。
级联信号输出端GP与第四节点U4电连接。
在具体实施时，在本公开实施例中，结合图1至图3所示，第一信号驱动线11可以包括：第一时钟线ck1、第二时钟线ck2、第一控制线cb1、第二控制线cb2、第一参考线vgl以及第二参考线vgh；其中，所有的第一移位寄存器的第一参考信号端VGL与第一参考线vgl电连接，所有的第一移位寄存器的第二参考信号端VGH与第二参考线vgh电连接。并且，奇数级的第一移位寄存器的第一时钟信号端CK1与偶数级的第一移位寄存器的第二时钟信号端CK2均与第一时钟线ck1电连接，奇数级的第一移位寄存器的第二时钟信号端CK2与偶数级的第一移位寄存器的第一时钟信号端CK1均与第二时钟线ck2电连接。
在具体实施时，在本公开实施例中，发光控制晶体管T1～T12中的至少一个可以为双栅型晶体管。示例性地，可以使发光控制晶体管T1～T12均为双栅型晶体管。其中，发光控制晶体管T1～T12可以包括相互电连接的第一底栅极和第一顶栅极；并且第一底栅极位于第一导电层100，第一顶栅极位于第二导电层200。
在具体实施时，上述发光控制电路的工作过程可以与相关技术中的基本相同，在此不作赘述。需要说明的是，在本公开实施例中，发光控制电路除了可以为图2所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
图3为上述发光控制电路14在衬底基板10上的布局(Layout)示意图。图4为图3所示的布局示意图中沿AA’方向的剖视结构示意图。图5为图3所示的布局示意图中沿BB’方向的剖视结构示意图。图7为图3所示的布局示意图中沿CC’方向的剖视结构示意图。图7为图3所示的布局示意图中沿DD’方向的剖视结构示意图。其中，结合图3至图7示意出了上述发光控制电 路14中的有源半导体层500、第一导电层100、第二导电层200、第三导电层300以及第四导电层400的层叠位置关系的示意图。并且，需要说明的是，显示面板还可以包括：位于第一导电层100和有源半导体层500之间的缓冲层111、位于缓冲层111与第二导电层200之间的栅绝缘层112，位于第二导电层200与第三导电层300之间的第二绝缘层120，以及位于第三导电层300与第四导电层400之间的第三绝缘层130。
在具体实施时，在本公开实施例中，存储电容可以包括第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个。示例性地，存储电容可以包括第一电容C1、第二电容C2、第三电容C3以及第四电容C4。也就是说，第一电容C1、第二电容C2、第三电容C3以及第四电容C4可以均采用夹层电容的方式形成。下面均以第一电容C1、第二电容C2、第三电容C3以及第四电容C4可以均采用夹层电容的方式形成为例进行说明。
在具体实施时，在本公开实施例中，结合图3至图7所示，第一导电层100可以包括：发光控制晶体管T1～T12的第一底栅极，第一电容C1的第一电极层、第二电容C2的第一电极层、第三电容C3的第一电极层以及第四电容C4的第一电极层。例如，图4示出了发光控制晶体管T8的第一底栅极T8-L1，第一电容C1的第一电极层C1-1。图5示出了发光控制晶体管T6的第一底栅极T6-L1，第二电容C2的第一电极层C2-1。图7示出了发光控制晶体管T7的第一底栅极T7-L1。
在具体实施时，在本公开实施例中，结合图3至图7所示，有源半导体层500可采用半导体材料图案化形成。有源半导体层500可用于制作上述的发光控制晶体管T1～T12的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，部分晶体管的有源层可以一体设置。示例性地，有源半导体层500可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。例如，图4示出了发光控制晶体管T8的有源层T8-S。图5示出了发光控制晶体管T4的有源层T4-S，发光控制晶体管T6的有源层T6-S。 图7示出了发光控制晶体管T7的有源层T7-S。
在具体实施时，在本公开实施例中，结合图3至图7所示，第二导电层200可以包括：发光控制晶体管T1～T12的第一顶栅极，第一电容C1的第二电极层、第二电容C2的第二电极层、第三电容C3的第二电极层以及第四电容C4的第二电极层。例如，图4示出了发光控制晶体管T8的第一顶栅极T8-G1，第一电容C1的第二电极层C1-2。图5示出了发光控制晶体管T6的第一顶栅极T6-G1，第二电容C2的第二电极层C2-2。图7示出了发光控制晶体管T7的第一顶栅极T7-G1。
在具体实施时，在本公开实施例中，结合图3至图5所示，第三导电层300可以包括：第一电容C1的第三电极层、第二电容C2的第三电极层、第三电容C3的第三电极层以及第四电容C4的第三电极层。例如，图4示出了第一电容C1的第三电极层C1-3。图5示出了第二电容C2的第三电极层C2-3。
在具体实施时，在本公开实施例中，结合图3至图7所示，第四导电层400可以包括：第一信号驱动线11(例如：第一时钟线ck1、第二时钟线ck2、第一控制线cb1、第二控制线cb2，第一参考线vgl、第二参考线vgh)，以及用于使发光控制晶体管T1～T12和第一电容C1至第四电容C4电连接的连接部。例如，图4示出了使发光控制晶体管T8和第一电容C1电连接的连接部T8-C1，使发光控制晶体管T4和T5电连接的连接部T4-T5。其中，连接部T8-C1的一端通过贯穿栅绝缘层112、第二绝缘层120以及第三绝缘层130的过孔与发光控制晶体管T8的有源层电连接。连接部T8-C1的另一端通过贯穿第二绝缘层120和第三绝缘层130的过孔与第一电容C1的第二电极层C1-2电连接。
图5示出了使发光控制晶体管T4和第二电容C2电连接的连接部T4-C2，使发光控制晶体管T6和第二电容C2电连接的连接部T6-C2。其中，连接部T4-C2的一端通过贯穿栅绝缘层112、第二绝缘层120以及第三绝缘层130的过孔与发光控制晶体管T4的有源层T4-S电连接。连接部T6-C2通过贯穿栅绝缘层112、第二绝缘层120和第三绝缘层130的过孔与发光控制晶体管T6 的有源层T6-S电连接。
在具体实施时，在本公开实施例中，结合图3至图7所示，第二导电层200还可以包括：与第二电极层绝缘设置的第一连接走线；第四导电层400还可以包括第二连接走线；并且，第二连接走线的一端通过贯穿第三绝缘层130的第一过孔与第三电极层电连接，第二连接走线的另一端通过贯穿第二绝缘层120和第三绝缘层130的第二过孔与第一连接走线电连接，第一连接走线通过贯穿第一绝缘层110的第三过孔与第一电极层电连接，以使第一电极层和第三电极层通过第一连接走线和第二连接走线电连接。
进一步地，在具体实施时，可以使第一过孔设置为至少两个。这样可以使第二连接走线采用多个第一过孔与第三电极层电连接，从而在第二连接走线和第三电极层采用部分第一过孔不能实现电连接的情况下，还可以使其采用其余第一过孔实现电连接。示例性地，第一过孔可以设置为两个。当然，第一过孔也可以设置为多个，在此不作限定。
进一步地，在具体实施时，可以使第二过孔设置为至少两个。这样可以使第二连接走线采用多个第二过孔与第一连接走线电连接，从而在第二连接走线和第一连接走线采用部分第二过孔不能实现电连接的情况下，还可以使其采用其余第二过孔实现电连接。示例性地，第二过孔可以设置为两个。当然，第二过孔也可以设置为多个，在此不作限定。
进一步地，在具体实施时，可以使第三过孔设置为至少两个。这样可以使第一连接走线采用多个第三过孔与第一电极层电连接，从而在第一连接走线和第一电极层采用部分第三过孔不能实现电连接的情况下，还可以使其采用其余第三过孔实现电连接。示例性地，第三过孔可以设置为两个。当然，第三过孔也可以设置为多个，在此不作限定。
示例性地，如图4所示，针对第一电容C1，第一电极层C1-1在衬底基板10的正投影、第二电极层C1-2在衬底基板10的正投影以及第三电极层C1-3在衬底基板10的正投影均具有交叠区域。第二连接走线22-1的一端通过贯穿第三绝缘层130的两个第一过孔31-1与第三电极层C1-3电连接，第二 连接走线22-1的另一端通过贯穿第二绝缘层120和第三绝缘层130的两个第二过孔32-1与第一连接走线21-1电连接，第一连接走线21-1通过贯穿第一绝缘层110的两个第三过孔33-1与第一电极层C1-1电连接，以使第一电极层C1-1和第三电极层C1-3通过第一连接走线21-1和第二连接走线22-1电连接，以形成第一电容C1的第一电极，从而形成夹层电容方式的第一电容C1。需要说明的是，第二连接走线22-1和连接部T4-T5可以设置为一体结构。当然，本公开包括但不限于此。
示例性地，如图5所示，针对第二电容C2，第一电极层C2-1在衬底基板10的正投影、第二电极层C2-2在衬底基板10的正投影以及第三电极层C2-3在衬底基板10的正投影均具有交叠区域。第二连接走线22-2的一端通过贯穿第三绝缘层130的两个第一过孔31-2与第三电极层C2-3电连接，第二连接走线22-2的另一端通过贯穿第二绝缘层120和第三绝缘层130的两个第二过孔32-2与第一连接走线21-2电连接，第一连接走线21-2通过贯穿第一绝缘层110的两个第三过孔33-2与第一电极层C2-1电连接，以使第一电极层C2-1和第三电极层C2-3通过第一连接走线21-2和第二连接走线22-2电连接，以形成第二电容C2的第一电极，从而形成夹层电容方式的第二电容C2。需要说明的是，第二连接走线22-2和连接部T6-C2可以设置为一体结构。当然，本公开包括但不限于此。
示例性地，针对第三电容C3和第四电容C4，其实施方式可参照上述实施方式进行设置，在此不作赘述。
进一步地，在具体实施时，可以使第二过孔在衬底基板10的正投影和第三过孔在衬底基板10的正投影不交叠。示例性地，如图3与图4所示，第二过孔32-1在衬底基板10的正投影和第三过孔33-1在衬底基板10的正投影不交叠。如图3与图5所示，第二过孔32-2在衬底基板10的正投影和第三过孔33-2在衬底基板10的正投影不交叠。这样可以避免由于过孔过深导致的不能正常电连接的问题。
在具体实施时，在本公开实施例中，如图3与图6所示，显示面板还可 以包括：位于非显示区BB中的多条发光控制信号传输线EM-S；其中，一条发光控制信号传输线EM-S与一条发光控制信号线电连接，发光控制电路14的第一信号输出端GO分别与各发光控制信号传输线EM-S电连接。并且，发光控制信号传输线EM-S位于第一导电层100。示例性地，发光控制晶体管T11和T12的第二极采用连接部T11-T12进行电连接，以作为第一信号输出端GO。并且，连接部T11-T12与位于第一导电层100的发光控制信号传输线EM-S电连接，以通过发光控制信号传输线EM-S向发光控制信号线输出发光控制信号。
在具体实施时，在本公开实施例中，如图3与图6所示，第二导电层200包括第三连接走线23，发光控制晶体管的输出端通过贯穿第二绝缘层120和第三绝缘层130的第四过孔34与第三连接走线23电连接，第三连接走线23通过贯穿缓冲层111和栅绝缘层112的第五过孔35与发光控制信号传输线EM-S电连接，以使发光控制信号传输线EM-S与发光控制晶体管的输出端，通过第三连接走线23电连接。示例性地，可以将发光控制晶体管T11和T12的相互电连接的第二极作为上述发光控制晶体管的输出端。也就是说，连接部T11-T1通过第四过孔34与第三连接走线23电连接。
在具体实施时，在本公开实施例中，如图3与图6所示，可以使第四过孔34设置为至少两个。这样可以使连接部T11-T1采用多个第四过孔34与第三连接走线23电连接，从而在连接部T11-T1和第三连接走线23采用部分第四过孔34不能实现电连接的情况下，还可以使其采用其余第四过孔34实现电连接。示例性地，第四过孔34可以设置为两个。当然，第四过孔34也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，如图3与图6所示，可以使第五过孔35设置为至少两个。这样可以使第三连接走线23采用多个第五过孔35与发光控制信号传输线EM-S电连接，从而在第三连接走线23和发光控制信号传输线EM-S采用部分第五过孔35不能实现电连接的情况下，还可以使其采用其余第五过孔35实现电连接。示例性地，第五过孔35可以设置为两个。 当然，第五过孔35也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，如图3与图6所示，可以使第四过孔34在衬底基板10的正投影和第五过孔35在衬底基板10的正投影不交叠。这样可以避免由于过孔过深导致的不能正常电连接的问题。
在具体实施时，在本公开实施例中，如图3与图7所示，显示面板还可以包括：位于非显示区BB的第一传输线；其中，第一传输线与发光控制电路14电连接。第一传输线包括第一子传输线41和第二子传输线42；其中，第一子传输线41位于第一导电层100，第二子传输线42位于第二导电层200。并且，第一信号驱动线11通过贯穿第二绝缘层120和第三绝缘层130的第六过孔36与第二子传输线42电连接，第二子传输线42通过贯穿第一绝缘层110的第七过孔37与第一子传输线41电连接，使得第一信号驱动线11和发光控制电路14，通过第一子传输线41和第二子传输线42电连接。
在具体实施时，在本公开实施例中，可以使第六过孔36设置为至少两个。这样可以使第一信号驱动线11采用多个第六过孔36与第二子传输线42电连接，从而在第一信号驱动线11和第二子传输线42采用部分第六过孔36不能实现电连接的情况下，还可以使其采用其余第六过孔36实现电连接。示例性地，第六过孔36可以设置为两个。当然，第六过孔36也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，可以使第七过孔37设置为至少两个。这样可以使第二子传输线42采用多个第七过孔37与第一子传输线41电连接，从而在第二子传输线42和第一子传输线41采用部分第七过孔37不能实现电连接的情况下，还可以使其采用其余第七过孔37实现电连接。示例性地，第七过孔37可以设置为两个。当然，第七过孔37也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，可以使第六过孔36在衬底基板10的正投影与第七过孔37在衬底基板10的正投影不交叠。这样可以避免由于过孔过深导致的不能正常电连接的问题。
示例性地，可以使第一时钟线ck1、第二时钟线ck2、第一控制线cb1、第二控制线cb2，第一参考线vgl、第二参考线vgh中的至少一个采用上述第一传输线的方式与发光控制电路14电连接。例如，以第二时钟线ck2为例，如图3与图7所示，与第二时钟线ck2电连接的第一传输线包括第一子传输线41和第二子传输线42，第二时钟线ck2通过两个第六过孔36与第二子传输线42电连接，第二子传输线42通过两个第七过孔37与第一子传输线41电连接，以使第二时钟线ck2和发光控制电路14中的发光控制晶体管T7的第一底栅极T7-L1和第一顶栅极T7-G1电连接，并且发光控制晶体管T7的第一顶栅极T7-G1还通过连接部T7-75与发光控制晶体管T5的第一极电连接。当然，第一时钟线ck1、第一控制线cb1、第二控制线cb2，第一参考线vgl、第二参考线vgh的实施方式可以参照上述第二时钟线ck2的实施方式，在此不作赘述。
在具体实施时，在本公开实施例中，驱动电路也可以设置为扫描驱动电路13。这样可以使扫描驱动电路13中的存储电容采用夹层电容的方式进行设置，从而降低扫描驱动电路13的占用面积。
在具体实施时，在本公开实施例中，扫描驱动电路13可以包括：多个级联的第二移位寄存器。第一级第二移位寄存器的第二输入信号端IN2与帧触发信号端电连接，其余第二移位寄存器中，下一级第二移位寄存器的第二输入信号端IN2与上一级第二移位寄存器的扫描信号输出端SO电连接。并且，每一个第二移位寄存器的扫描信号输出端SO用于输出扫描信号。
在具体实施时，在本公开实施例中，如图8所示，第二移位寄存器可以包括：第五电容C5、第六电容C6，以及扫描控制晶体管T13～T20。其中，扫描控制晶体管T13的栅极与第三时钟信号端CKB1电连接，扫描控制晶体管T13的第一极与第二输入信号端IN2电连接，扫描控制晶体管T13的第二极与第六节点PD_in1电连接。
扫描控制晶体管T14的栅极与第六节点PD_in1电连接，扫描控制晶体管T14的第一极与第三时钟信号端CKB1电连接，扫描控制晶体管T14的第二 极与第七节点PU1电连接。
扫描控制晶体管T15的栅极与第三时钟信号端CKB1电连接，扫描控制晶体管T15的第一极与第三参考信号端VSS电连接，扫描控制晶体管T15的第二极与第七节点PU1电连接。
扫描控制晶体管T16的栅极与第七节点PU1电连接，扫描控制晶体管T16的第一极与第四参考信号端VDD电连接，扫描控制晶体管T16的第二极与扫描信号输出端SO电连接。
扫描控制晶体管T17的栅极与第八节点PD_out1电连接，扫描控制晶体管T17的第一极与第四时钟信号端CKB2电连接，扫描控制晶体管T17的第二极与扫描信号输出端SO电连接。
扫描控制晶体管T18的栅极与第七节点PU1电连接，扫描控制晶体管T18的第一极与第四参考信号端VDD电连接，扫描控制晶体管T18的第二极与扫描控制晶体管T19的第一极电连接。
扫描控制晶体管T19的栅极与第四时钟信号端CKB2电连接，扫描控制晶体管T19的第二极与第六节点PD_in1电连接。
扫描控制晶体管T20的栅极与第三参考信号端VSS电连接，扫描控制晶体管T20的第一极与第六节点PD_in1电连接，扫描控制晶体管T20的第二极与第八节点PD_out1电连接。
第五电容C5的第一电极与扫描信号输出端SO电连接，第五电容C5的第二电极与扫描控制晶体管T17的栅极电连接。
第六电容C6的第一电极与第四参考信号端VDD电连接，第六电容C6的第二电极与扫描控制晶体管T16的栅极电连接。
在具体实施时，在本公开实施例中，结合图1、图8以及图9所示，第二信号驱动线12可以包括：第三时钟线ck3、第四时钟线ck4、第三参考线vddvss以及第四参考线；其中，所有的第二移位寄存器的第三参考信号端VSS与第三参考线vss电连接，所有的第二移位寄存器的第四参考信号端VDD与第四参考线vdd电连接。并且，奇数级的第二移位寄存器的第三时钟信号端CKB1 与偶数级的第二移位寄存器的第四时钟信号端CKB2均与第三时钟线ck3电连接，奇数级的第二移位寄存器的第二时钟信号端CKB2与偶数级的第二移位寄存器的第一时钟信号端CKB1均与第四时钟线ck4电连接。
在具体实施时，在本公开实施例中，扫描控制晶体管T13～T20中的至少一个可以为双栅型晶体管。示例性地，可以使扫描控制晶体管T13～T20均为双栅型晶体管。其中，扫描控制晶体管T13～T20可以包括相互电连接的第二底栅极和第二顶栅极；并且第二底栅极位于第一导电层100，第二顶栅极位于第二导电层200。
在具体实施时，上述扫描驱动电路13的工作过程可以与相关技术中的基本相同，在此不作赘述。需要说明的是，在本公开实施例中，扫描驱动电路13除了可以为图8所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
图9为上述扫描驱动电路13在衬底基板10上的布局(Layout)示意图。图10为图9所示的布局示意图中沿AA’方向的剖视结构示意图。图11为图10所示的布局示意图中沿BB’方向的剖视结构示意图。图12为图10所示的布局示意图中沿CC’方向的剖视结构示意图。其中，扫描驱动电路13的有源半导体层500、第一导电层100、第二导电层200、第三导电层300以及第四导电层400分别与发光控制电路14的有源半导体层500、第一导电层100、第二导电层200、第三导电层300以及第四导电层400同层同材料设置，具体在此不作赘述。
在具体实施时，在本公开实施例中，存储电容可以包括第五电容C5和第六电容C6中的至少一个。示例性地，存储电容可以包括第五电容C5和第六电容C6。也就是说，第五电容C5和第六电容C6可以均采用夹层电容的方式形成。下面均以第五电容C5和第六电容C6可以均采用夹层电容的方式形成为例进行说明。
在具体实施时，在本公开实施例中，结合图9至图11所示，第一导电层100还可以包括：扫描控制晶体管T13～T20的第二底栅极，第五电容C5的第 一电极层、第六电容C6的第一电极层。例如，图10示出了第五电容C5的第一电极层C5-1。图11示出了第六电容C6的第一电极层C6-1，扫描驱动晶体管T16的第二底栅极T16-L1。
在具体实施时，在本公开实施例中，结合图9至图11所示，有源半导体层500可用于制作上述的扫描控制晶体管T13～T20的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，部分晶体管的有源层可以一体设置。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。例如，图11示出了扫描驱动晶体管T18的有源层T18-S。
在具体实施时，在本公开实施例中，结合图9至图11所示，第二导电层200还可以包括：扫描控制晶体管T13～T20的第二顶栅极，第五电容C5的第二电极层、第六电容C6的第二电极层、第一连接走线21-5和21-6。例如，图10示出了第五电容C5的第二电极层C5-2和第一连接走线21-5。图11示出了第六电容C6的第二电极层C6-2和第一连接走线21-6，扫描驱动晶体管T16的第二顶栅极T16-G1。
在具体实施时，在本公开实施例中，结合图9至图11所示，第三导电层300还可以包括：第五电容C5的第三电极层、第六电容C6的第三电极层。例如，图10示出了第五电容C5的第三电极层C5-3。图11示出了第六电容C6的第三电极层C6-3。
在具体实施时，在本公开实施例中，结合图9至图11所示，第四导电层400还可以包括：第二信号驱动线12(例如：第三时钟线ck3、第四时钟线ck4、第三参考线vss、第四参考线vdd)，用于使扫描控制晶体管T13～T20、第五电容C5、第六电容C6电连接的连接部，以及第二连接走线22-5和22-6。例如，图10示出了第二连接走线22-5以及使扫描控制晶体管T17和第五电容C5C5电连接的连接部T17-C5，并且，连接部T17-C5的一端通过贯穿栅绝缘层112、第二绝缘层120以及第三绝缘层130的过孔与扫描控制晶体管T17的有源层电连接。其中，第二连接走线22-5和连接部T17-C5为一体结构。
示例性地，如图10所示，针对第五电容C5，第一电极层C5-1在衬底基板10的正投影、第二电极层C5-2在衬底基板10的正投影以及第三电极层C5-3在衬底基板10的正投影均具有交叠区域。第二连接走线22-5的一端通过贯穿第三绝缘层130的四个第一过孔31-5与第三电极层C5-3电连接，第二连接走线22-5的另一端通过贯穿第二绝缘层120和第三绝缘层130的两个第二过孔32-5与第一连接走线21-5电连接，第一连接走线21-5通过贯穿第一绝缘层110的两个第三过孔33-5与第一电极层C5-1电连接，以使第一电极层C5-1和第三电极层C5-3通过第一连接走线21-5和第二连接走线22-5电连接，以形成第五电容C5的第一电极，从而形成夹层电容方式的第五电容C5。
示例性地，如图11所示，针对第六电容C6，第一电极层C6-1在衬底基板10的正投影、第二电极层C6-2在衬底基板10的正投影以及第三电极层C6-3在衬底基板10的正投影均具有交叠区域。第二连接走线22-6的一端通过贯穿第三绝缘层130的两个第一过孔31-6与第三电极层C6-3电连接，第二连接走线22-6的另一端通过贯穿第二绝缘层120和第三绝缘层130的两个第二过孔32-6与第一连接走线21-6电连接，第一连接走线21-6通过贯穿第一绝缘层110的两个第三过孔33-6与第一电极层C6-1电连接，以使第一电极层C6-1和第三电极层C6-3通过第一连接走线21-6和第二连接走线22-6电连接，以形成第六电容C6的第一电极，从而形成夹层电容方式的第六电容C6。
示例性地，如图9与图10所示，第二过孔32-5在衬底基板10的正投影和第三过孔33-5在衬底基板10的正投影不交叠。如图9与图11所示，第二过孔32-6在衬底基板10的正投影和第三过孔33-6在衬底基板10的正投影不交叠。这样可以避免由于过孔过深导致的不能正常电连接的问题。
在具体实施时，在本公开实施例中，如图9与图12所示，显示面板还可以包括：位于非显示区BB的第二传输线；其中，第一传输线与扫描驱动电路13电连接。第二传输线包括第三子传输线43和第四子传输线44；其中，第三子传输线43位于第一导电层100，第四子传输线44位于第二导电层200。并且，第二信号驱动线12通过贯穿第二绝缘层120和第三绝缘层130的第八 过孔38与第四子传输线44电连接，第四子传输线44通过贯穿第一绝缘层110的第九过孔39与第三子传输线43电连接，使得第二信号驱动线12和扫描驱动电路13，通过第三子传输线43和第四子传输线44电连接。
在具体实施时，在本公开实施例中，可以使第八过孔38设置为至少两个。这样可以使第二信号驱动线12采用多个第八过孔38与第四子传输线44电连接，从而在第二信号驱动线12和第四子传输线44采用部分第八过孔38不能实现电连接的情况下，还可以使其采用其余第八过孔38实现电连接。示例性地，第八过孔38可以设置为两个。当然，第八过孔38也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，可以使第九过孔39设置为至少两个。这样可以使第四子传输线44采用多个第九过孔39与第三子传输线43电连接，从而在第四子传输线44和第三子传输线43采用部分第九过孔39不能实现电连接的情况下，还可以使其采用其余第九过孔39实现电连接。示例性地，第九过孔39可以设置为两个。当然，第九过孔39也可以设置为多个，在此不作限定。
在具体实施时，在本公开实施例中，可以使第八过孔38在衬底基板10的正投影与第九过孔39在衬底基板10的正投影不交叠。这样可以避免由于过孔过深导致的不能正常电连接的问题。
示例性地，可以使第三时钟线ck3、第四时钟线ck4、第三参考线vss、第四参考线vdd中的至少一个采用上述第二传输线的方式与扫描驱动电路13电连接。例如，以第三时钟线ck3为例，如图9与图12所示，与第三时钟线ck3电连接的第二传输线包括第三子传输线43和第四子传输线44，第三时钟线ck3通过两个第八过孔38与第四子传输线44电连接，第四子传输线44通过两个第九过孔39与第三子传输线43电连接，以使第三时钟线ck3和扫描驱动电路13中的扫描控制晶体管T15的第二底栅极和第二顶栅极电连接。当然，第四时钟线ck4、第三参考线vss、第四参考线的实施方式可以参照上述第三时钟线ck3的实施方式，在此不作赘述。
在具体实施时，在本公开实施例中，驱动电路也可以设置为像素电路。这样可以使像素电路中的存储电容采用夹层电容的方式进行设置，从而降低像素电路的占用面积。
如图13所示，像素电路0121可以包括：像素驱动电路0122、第一发光控制电路123、第二发光控制电路124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。其中，像素驱动电路0122包括控制端、第一端和第二端，且被配置为发光元件0120提供驱动发光元件0120发光的驱动电流。例如，第一发光控制电路123与像素驱动电路0122的第一端和第一电源端PVDD连接，且被配置为实现像素驱动电路0122和第一电源端PVDD之间的连接导通或断开，第二发光控制电路124与像素驱动电路0122的第二端和发光元件0120的第一发光电压施加电极电连接，且被配置为实现像素驱动电路0122和发光元件0120之间的连接导通或断开。数据写入电路0126与像素驱动电路0122的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路0127；存储电路0127与像素驱动电路0122的控制端和第一电源端PVDD电连接，且被配置为存储数据信号；阈值补偿电路0128与像素驱动电路0122的控制端和第二端电连接，且被配置为对像素驱动电路0122进行阈值补偿；复位电路0129与像素驱动电路0122的控制端和发光元件0120的第一发光电压施加电极电连接，且配置为在复位控制信号的控制下对像素驱动电路0122的控制端和发光元件0120的第一发光电压施加电极进行复位。
示例性地，结合图13所示，像素驱动电路0122包括：驱动晶体管T01，像素驱动电路0122的控制端包括驱动晶体管T01的栅极，像素驱动电路0122的第一端包括驱动晶体管T01的第一极，像素驱动电路0122的第二端包括驱动晶体管T01的第二极。
示例性地，结合图13所示，数据写入电路0126包括数据写入晶体管T02，存储电路0127包括第七电容C7，阈值补偿电路0128包括阈值补偿晶体管T03，第一发光控制电路123包括第一发光控制晶体管T04，第二发光控制电路124 包括第二发光控制晶体管T05，复位电路0129包括第一复位晶体管T06和第二复位晶体管T07，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
具体地，数据写入晶体管T02的第一极与驱动晶体管T01的第一极电连接，数据写入晶体管T02的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T02的栅极被配置为与栅线GA电连接以接收扫描信号；第七电容C7的第一极与第一电源端PVDD电连接，第七电容C7的第二极与驱动晶体管T01的栅极电连接；阈值补偿晶体管T03的第一极与驱动晶体管T01的第二极电连接，阈值补偿晶体管T03的第二极与驱动晶体管T01的栅极电连接，阈值补偿晶体管T03的栅极被配置为与栅线GA电连接以接收扫描信号；第一复位晶体管T06的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T06的第二极与驱动晶体管T01的栅极电连接，第一复位晶体管T06的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T07的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T07的第二极与发光元件120的第一发光电压施加电极电连接，第二复位晶体管T07的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T04的第一极与第一电源端PVDD电连接，第一发光控制晶体管T04的第二极与驱动晶体管T01的第一极电连接，第一发光控制晶体管T04的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号；第二发光控制晶体管T05的第一极与驱动晶体管T01的第二极电连接，第二发光控制晶体管T05的第二极与发光元件120的第一发光电压施加电极电连接，第二发光控制晶体管T05的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号；发光元件120的第二发光电压施加电极与第二电源端VSS电连接。其中，第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端PVDD和第二电源端VSS之一为高压端，另一个 为低压端。例如，如图13所示的实施例中，第一电源端PVDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
需要说明的是，在本公开实施例中，子像素spx中的像素电路除了可以为图13所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
在具体实施时，在本公开实施例中，存储电容可以包括第七电容。也就是说，第七电容可以均采用夹层电容的方式形成。需要说明的是，第一电容C1形成夹层电容的实施方式可以参见上述形成第一电容C1至第六电容C6的实施方式，在此不作赘述。
进一步地，在具体实施时，在本公开实施例中，如图14所示，在发光控制电路14位于扫描驱动电路13背离显示区AA的一侧时，可以使发光控制信号传输线EM-S在衬底基板10的正投影与扫描驱动电路在衬底基板10上的正投影具有交叠区域。例如，如图14所示，发光控制信号传输线EM-S在衬底基板10的正投影可以与上一级第二移位寄存器中的扫描控制晶体管T17与下一级第二移位寄存器的扫描控制晶体管T1的连接部T17-T1在衬底基板10的正投影具有交叠区域。这样由于发光控制电路14的发光控制信号传输线EM-S位于第一导电层，由于第一导电层与第四导电层之间的距离较远，从而可以降低发光控制信号传输线EM-S对扫描驱动电路的信号干扰。
基于同一发明构思，本公开实施例还提供了一种上述显示面板的制备方法，可以包括如下步骤：
在衬底基板10上依次形成第一导电层100、第二导电层200以及第三导电层300，以形成位于衬底基板10上的驱动电路；其中，第一导电层100包括第一电极层，第二导电层200包括第二电极层，第三导电层300包括第三电极层；第一电极层在衬底基板10的正投影、第二电极层在衬底基板10的正投影以及第三电极层在衬底基板10的正投影均具有交叠区域；第一电极层 和第三电极层相互电连接作为存储电容的第一电极，第二电极层作为存储电容的第二电极。
在具体实施时，在本公开实施例中，第二导电层200包括与第二电极层绝缘设置的第一连接走线。
在具体实施时，在本公开实施例中，在形成第一导电层100之后，且在形成第二导电层200之前，还可以包括：形成具有第三过孔的第一绝缘层110；其中，第一连接走线通过贯穿第一绝缘层110的第三过孔与第一电极层电连接。
在具体实施时，在本公开实施例中，在形成第二导电层200之后，且在形成第三导电层300之前，还可以包括：形成第二绝缘层120。
在具体实施时，在本公开实施例中，在形成第三导电层300之后，还可以包括：
形成第三绝缘层130、贯穿第三绝缘层130的第一过孔以及贯穿第二绝缘层120和第三绝缘层130的第二过孔；
形成第四导电层400；其中，第四导电层400包括第二连接走线；且第二连接走线的一端通过第一过孔与第三电极层电连接，第二连接走线的另一端通过第二过孔与第一连接走线电连接。
需要说明的是，第一绝缘层110至第三绝缘层130还具有的其余过孔可以参见上述描述内容，在此不作赘述。
当然，第一导电层100至第四导电层400还包括的其余结构可以参见上述描述内容，在此不作赘述。
上述可以采用构图工艺形成第一导电层100至第四导电层400中的各种结构，以及采用刻蚀工艺形成上述过孔。需要说明的是，构图工艺可只包括光刻工艺，或，可以包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。在具体实施时，可根据本公开中所形成的结构选择相应的构图工艺。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板、其制备方法及显示装置，通过使第一导电层包括第一电极层，第二导电层包括第二电极层以及第三导电层包括第三电极层，并且使第一电极层在衬底基板的正投影、第二电极层在衬底基板的正投影以及第三电极层在衬底基板的正投影均具有交叠区域。这样可以使第一电极层和第三电极层相互电连接作为存储电容的一个电极，第二电极层作为存储电容的另一个电极，从而可以采用夹层电容的方式形成存储电容，可以提高存储电容的电容值。也就是说，可以使第一电极层和第二电极具有正对面积，以形成存储电容的一个子电容；以及使第二电极和第三电极具有正对面积，以形成存储电容的另一个子电容。通过使这两个子电容采用并联的方式形成存储电容，以提高存储电容的电容值。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种显示面板，包括：衬底基板，位于所述衬底基板上的驱动电路，所述驱动电路包括存储电容；其中，所述显示面板还包括：依次层叠位于所述衬底基板上的第一导电层、第二导电层以及第三导电层；其中，所述第一导电层、所述第二导电层以及所述第三导电层异层设置；
    所述第一导电层包括第一电极层，所述第二导电层包括第二电极层，所述第三导电层包括第三电极层；
    所述第一电极层在所述衬底基板的正投影、所述第二电极层在所述衬底基板的正投影以及所述第三电极层在所述衬底基板的正投影均具有交叠区域；
    所述第一电极层和所述第三电极层相互电连接作为所述存储电容的第一电极，所述第二电极层作为所述存储电容的第二电极。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括：位于所述第一导电层和所述第二导电层之间的第一绝缘层，位于所述第二导电层与所述第三导电层之间的第二绝缘层，位于所述第三导电层背离所述衬底基板一侧的第三绝缘层，以及位于所述第三绝缘层背离所述衬底基板一侧的第四导电层；
    所述第二导电层包括与所述第二电极层绝缘设置的第一连接走线；所述第四导电层包括第二连接走线；
    所述第二连接走线的一端通过贯穿所述第三绝缘层的第一过孔与所述第三电极层电连接，所述第二连接走线的另一端通过贯穿所述第二绝缘层和所述第三绝缘层的第二过孔与所述第一连接走线电连接，所述第一连接走线通过贯穿所述第一绝缘层的第三过孔与所述第一电极层电连接，以使所述第一电极层和所述第三电极层通过所述第一连接走线和所述第二连接走线电连接。
  3. 如权利要求2所述的显示面板，其中，所述第一过孔设置为至少两个；和/或，
    所述第二过孔设置为至少两个；和/或，
    所述第三过孔设置为至少两个。
  4. 如权利要求2所述的显示面板，其中，所述第二过孔在所述衬底基板的正投影和所述第三过孔在所述衬底基板的正投影不交叠。
  5. 如权利要求2-4任一项所述的显示面板，其中，所述显示面板还包括：位于非显示区中的扫描驱动电路和发光控制电路以及位于显示区中的像素电路；
    所述驱动电路为所述扫描驱动电路、所述发光控制电路以及所述像素电路中的至少一种。
  6. 如权利要求5所述的显示面板，其中，所述显示面板还包括：位于所述显示区中的多条发光控制信号线，以及位于所述非显示区中的多条发光控制信号传输线；其中，一条所述发光控制信号传输线与一条所述发光控制信号线电连接，所述发光控制电路的第一信号输出端分别与各所述发光控制信号传输线电连接；
    所述发光控制信号传输线位于所述第一导电层。
  7. 如权利要求6所述的显示面板，其中，所述第一绝缘层包括位于所述第一导电层与所述第二导电层之间的缓冲层、以及位于所述缓冲层与所述第二导电层之间的栅绝缘层；
    所述第二导电层包括第三连接走线，所述发光控制电路包括发光控制晶体管，所述发光控制晶体管的输出端通过贯穿所述第二绝缘层和所述第三绝缘层的第四过孔与所述第三连接走线电连接，所述第三连接走线通过贯穿所述缓冲层和所述栅绝缘层的第五过孔与所述发光控制信号传输线电连接，以使所述发光控制信号传输线与所述发光控制晶体管的输出端，通过所述第三连接走线电连接。
  8. 如权利要求7所述的显示面板，其中，所述第四过孔设置为至少两个；和/或，
    所述第五过孔设置为至少两个；和/或，
    所述第四过孔在所述衬底基板的正投影和所述第五过孔在所述衬底基板 的正投影不交叠。
  9. 如权利要求7所述的显示面板，其中，所述显示面板还包括：位于所述非显示区的第一信号驱动线和第一传输线；其中，所述第一信号驱动线位于所述第四导电层；所述第一传输线与所述发光控制电路电连接；
    所述第一传输线包括第一子传输线和第二子传输线；其中，所述第一子传输线位于所述第一导电层，所述第二子传输线位于所述第二导电层；
    所述第一信号驱动线通过贯穿所述第二绝缘层和所述第三绝缘层的第六过孔与所述第二子传输线电连接，所述第二子传输线通过贯穿所述第一绝缘层的第七过孔与所述第一子传输线电连接，使得所述第一信号驱动线和所述发光控制电路，通过所述第一子传输线和所述第二子传输线电连接。
  10. 如权利要求9所述的显示面板，其中，所述第六过孔设置为至少两个；和/或，
    所述第七过孔设置为至少两个；和/或，
    所述第六过孔在所述衬底基板的正投影与所述第七过孔在所述衬底基板的正投影不交叠。
  11. 如权利要求7-10任一项所述的显示面板，其中，所述发光控制晶体管为双栅型晶体管，且所述发光控制晶体管包括相互电连接的第一底栅极和第一顶栅极；
    所述第一底栅极位于所述第一导电层，所述第一顶栅极位于所述第二导电层。
  12. 如权利要求7所述的显示面板，其中，所述显示面板还包括：位于所述非显示区的第二信号驱动线和第二传输线；
    所述第二传输线包括第三子传输线和第四子传输线；其中，所述第三子传输线位于所述第一导电层，所述第四子传输线位于所述第二导电层；
    所述第二信号驱动线通过贯穿所述第二绝缘层和所述第三绝缘层的第八过孔与所述第四子传输线电连接，所述第四子传输线通过贯穿所述第一绝缘层的第九过孔与所述第三子传输线电连接，使得所述第二信号驱动线和所述 扫描驱动电路，通过所述第三子传输线和所述第四子传输线电连接。
  13. 如权利要求12所述的显示面板，其中，所述第八过孔设置为至少两个；和/或，
    所述第九过孔设置为至少两个；和/或，
    所述第八过孔在所述衬底基板的正投影与所述第九过孔在所述衬底基板的正投影不交叠。
  14. 如权利要求12所述的显示面板，其中，所述扫描驱动电路包括扫描控制晶体管；
    所述扫描控制晶体管为双栅型晶体管，且所述扫描控制晶体管包括相互电连接的第二底栅极和第二顶栅极；
    所述第二底栅极位于所述第一导电层，所述第二顶栅极位于所述第二导电层。
  15. 如权利要求6-10任一项所述的显示面板，其中，所述发光控制电路位于所述扫描驱动电路背离所述显示区的一侧，且，所述发光控制信号传输线在所述衬底基板的正投影与所述扫描驱动电路在所述衬底基板上的正投影具有交叠区域。
  16. 一种显示装置，其中，包括如权利要求1-15任一项所述的显示面板。
  17. 一种如权利要求1-15任一项所述的显示面板的制备方法，其中，包括：
    在衬底基板上依次形成第一导电层、第二导电层以及第三导电层，以形成位于所述衬底基板上的驱动电路；
    其中，所述第一导电层包括第一电极层，所述第二导电层包括第二电极层，所述第三导电层包括第三电极层；
    所述第一电极层在所述衬底基板的正投影、所述第二电极层在所述衬底基板的正投影以及所述第三电极层在所述衬底基板的正投影均具有交叠区域；
    所述第一电极层和所述第三电极层相互电连接作为所述存储电容的第一电极，所述第二电极层作为所述存储电容的第二电极。
  18. 如权利要求17所述的制备方法，其中，所述第二导电层包括与所述第二电极层绝缘设置的第一连接走线；
    在形成所述第一导电层之后，且在形成所述第二导电层之前，还包括：形成具有第三过孔的第一绝缘层；其中，所述第一连接走线通过贯穿所述第一绝缘层的第三过孔与所述第一电极层电连接；
    在形成所述第二导电层之后，且在形成所述第三导电层之前，还包括：形成第二绝缘层；
    在形成所述第三导电层之后，还包括：
    形成第三绝缘层、贯穿所述第三绝缘层的第一过孔以及贯穿所述第二绝缘层和所述第三绝缘层的第二过孔；
    形成第四导电层；其中，所述第四导电层包括第二连接走线；且所述第二连接走线的一端通过所述第一过孔与所述第三电极层电连接，所述第二连接走线的另一端通过所述第二过孔与所述第一连接走线电连接。
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