WO2021090688A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2021090688A1
WO2021090688A1 PCT/JP2020/039593 JP2020039593W WO2021090688A1 WO 2021090688 A1 WO2021090688 A1 WO 2021090688A1 JP 2020039593 W JP2020039593 W JP 2020039593W WO 2021090688 A1 WO2021090688 A1 WO 2021090688A1
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Prior art keywords
semiconductor integrated
integrated circuit
circuit device
tap
output
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Ceased
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PCT/JP2020/039593
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English (en)
French (fr)
Japanese (ja)
Inventor
英俊 田中
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Socionext Inc
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Socionext Inc
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Priority to CN202080074126.7A priority Critical patent/CN114600242B/zh
Priority to JP2021554875A priority patent/JP7610129B2/ja
Publication of WO2021090688A1 publication Critical patent/WO2021090688A1/ja
Priority to US17/735,052 priority patent/US11824055B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Definitions

  • the present disclosure relates to a semiconductor integrated circuit device in which a core region and an I / O region are arranged on a chip, and more particularly to a layout structure of an I / O cell arranged in the I / O region.
  • I / O cells input / output cells
  • signals are input / output to / from the outside of the semiconductor integrated circuit device and power is supplied via the I / O cells. ..
  • Patent Document 1 discloses a semiconductor integrated circuit device in which a diode is provided as an ESD (ElectroStatic Discharge) protection circuit for an external connection terminal and a resistance element as a protection resistor is arranged between an output transistor and an external connection terminal. There is.
  • ESD ElectroStatic Discharge
  • the output transistor is protected from ESD by a diode and a resistance element as ESD protection elements.
  • the occurrence of the latch-up phenomenon due to noise propagating in the well or the substrate cannot be sufficiently suppressed.
  • An object of the present disclosure is to provide a configuration capable of sufficiently suppressing the occurrence of a latch-up phenomenon in a semiconductor integrated circuit device.
  • the output circuit is connected to an external output terminal, a first output transistor that outputs an output signal to the external output terminal, and the external output terminal.
  • the first ESD (ElectoStatic Discharge) protection diode provided and the first protection resistor connected between the first output transistor and the first ESD protection diode are provided, and the first output transistor and the first are provided in a plan view.
  • the first protection resistor is arranged apart from the 1 ESD protection diode, and the first protection resistor is arranged between the first output transistor and the first ESD protection diode. It is divided into a plurality of resistance regions, and a tap for supplying a power supply voltage to a substrate or a well is formed between the resistance regions.
  • the first output transistor is arranged apart from the first ESD protection diode connected to the external output terminal, and the first protection resistor is arranged between them.
  • the noise applied to the external output terminal is attenuated by the first protection resistor before reaching the first output transistor.
  • the first protection resistor is formed by being divided into a plurality of resistance regions, and a tap for supplying a power supply voltage to a substrate or a well is formed between the resistance regions. As a result, the noise applied to the external output terminal is absorbed via the tap. Therefore, it is possible to suppress the propagation of noise that causes the occurrence of the latch-up phenomenon.
  • Circuit configuration diagram of the output circuit according to the first embodiment Example of planar layout structure of output circuit according to the first embodiment
  • Example of layout structure of ESD protection diode Example of layout structure of ESD protection diode
  • Example of layout structure of protection resistor Example of layout structure of protection resistor
  • Example of output transistor layout structure Example of output transistor layout structure
  • Another Example of Planar Layout Structure of Output Circuit According to First Embodiment Circuit configuration diagram of the output circuit according to the second embodiment
  • Example of planar layout structure of output circuit according to the second embodiment (A) and (b) are other examples of the plane layout structure of the output circuit according to the second embodiment.
  • VDDIO and “VSS” refer to the power supply voltage or the power supply itself.
  • the transistor is formed on the P-type substrate and the N-type well.
  • the transistor may be formed on a P-type well or an N-type substrate.
  • FIG. 1 is a plan view schematically showing the overall configuration of the semiconductor integrated circuit device according to the embodiment.
  • the semiconductor integrated circuit device 1 shown in FIG. 1 includes a core region 2 in which an internal core circuit is formed, and an I / O region 3 provided around the core region 2 in which an interface circuit (I / O circuit) is formed. It has.
  • an I / O cell row 10A is provided so as to circularly surround the peripheral portion of the semiconductor integrated circuit device 1.
  • a plurality of I / O cells 10 constituting the interface circuit are arranged in the I / O cell row 10A.
  • a plurality of external connection pads are arranged in the semiconductor integrated circuit device 1.
  • FIG. 2 is a circuit configuration diagram of the output circuit 11 included in the I / O cell 10. Although the actual output circuit includes circuit elements other than those shown in FIG. 2, the description is omitted in FIG.
  • the output circuit 11 shown in FIG. 2 includes an external output terminal OUT, output transistors P1 and N1, ESD (ElectroStatic Discharge) protection diodes D1 and D2, and protection resistors R1 and R2.
  • the output transistor P1 is a P conductive type transistor
  • the output transistor N1 is an N conductive type transistor.
  • the output transistors P1 and N1 output an output signal to the external output terminal OUT according to the signal received by the gate.
  • the source of the output transistor P1 is connected to VDDIO, and the drain is connected to the external output terminal OUT via the protection resistor R1.
  • the source of the output transistor N1 is connected to VSS, and the drain is connected to the external output terminal OUT via the protection resistor R2.
  • the protection resistors R1 and R2 are composed of, for example, wiring resistors, and the wiring is realized by wiring formed on a diffusion layer, a gate wiring layer, or a metal wiring layer, or a combination thereof.
  • the ESD protection diode D1 is provided between VDDIO and the external output terminal OUT, and the ESD protection diode D2 is provided between the VSS and the external output terminal OUT.
  • a current flows through the VDDIO and VSS via the ESD protection diodes D1 and D2, thereby protecting the output transistors P1 and N1.
  • FIG. 3 is a schematic view showing an example of the planar layout structure of the output circuit 11 according to the present embodiment.
  • the X direction (horizontal direction in the drawing) is the direction in which the I / O cells 10 are lined up
  • the Y direction vertical direction in the drawing
  • the upper side of the drawing is the core region 2 side
  • the lower side of the drawing is the chip end side.
  • Each region of FIG. 3 is marked with the same symbols as the corresponding circuit elements in the circuit diagram of FIG.
  • the ESD protection diodes D1 and D2 are arranged at the center in the Y direction.
  • the output transistor P1 is arranged on the upper side of the drawing of the ESD protection diode D1 so as to be separated from the ESD protection diode D1.
  • the output transistor N1 is arranged on the lower side of the drawing of the ESD protection diode D2 so as to be separated from the ESD protection diode D2.
  • the protection resistor R1 is arranged between the output transistor P1 and the ESD protection diode D1.
  • the protection resistor R1 is formed by being divided into a plurality of regions (resistance regions) 21.
  • the protection resistor R1 has a rectangular shape extending in the Y direction, and is divided into four resistance regions 21 arranged in the X direction.
  • a tap region 23 in which a tap for supplying VSS is formed on the P-type substrate is arranged so as to sandwich each resistance region 21.
  • the protection resistor R2 is arranged between the output transistor N1 and the ESD protection diode D2.
  • the protection resistor R2 is formed by being divided into a plurality of regions (resistance regions) 22.
  • the protection resistor R2 has a rectangular shape extending in the Y direction, and is divided into four resistance regions 22 arranged in the X direction.
  • a tap region 24 in which a tap for supplying VDDIO to the N-shaped well is formed is arranged so as to sandwich each resistance region 22.
  • FIG. 4 shows an example of the layout structure of the ESD protection diode D2. However, the wiring layer and the like are not shown.
  • the ESD protection diode D2 is formed in the P substrate region in the central portion.
  • the ESD protection diode D2 includes an anode portion 31 formed by the P conductive type fins 32 and a cathode portion 33a, 33b formed by the N conductive type fins 34a, 34b.
  • the fins 32, 34a, 34b extend in the X direction.
  • the anode portion 31 is connected to VSS, and the cathode portions 33a and 33b are connected to the external output terminal OUT.
  • a diode is formed between the P conductive type fin 32 and the N conductive type fins 34a and 34b.
  • a guard ring 81 is formed around the ESD protection diode D2.
  • the guard ring 81 includes N conductive fins 82 formed in N wells.
  • the fin 82 extends in the X direction.
  • the fin 82 is connected to VDDIO.
  • Dummy gates 41 are formed on the fins 32 of the anode portion 31 and the fins 34a and 34b of the cathode portions 33a and 33b.
  • a dummy gate 42 is formed on the fin 82 of the guard ring 81.
  • the dummy gates 41 and 42 extend in the Y direction.
  • guard ring 81 may not be formed.
  • FIG. 5 shows an example of the layout structure of the ESD protection diode D1. However, the wiring layer and the like are not shown.
  • the ESD protection diode D1 is formed in the N well in the central portion.
  • the ESD protection diode D1 includes a cathode portion 36 formed by N conductive type fins 37 and an anode portion 38a and 38b formed by P conductive type fins 39a and 39b.
  • the fins 37, 39a, 39b extend in the X direction.
  • the cathode portion 36 is connected to VDDIO, and the anode portions 38a and 38b are connected to the external output terminal OUT.
  • a diode is formed between the N conductive type fins 37 and the P conductive type fins 39a and 39b.
  • a guard ring 83 is formed around the ESD protection diode D1.
  • the guard ring 83 includes P conductive type fins 84 formed in the P substrate region.
  • the fin 84 extends in the X direction.
  • the fin 84 is connected to VSS.
  • Dummy gates 43 are formed on the fins 37 of the cathode portion 36 and the fins 39a and 39b of the anode portions 38a and 38b.
  • a dummy gate 44 is formed on the fin 84 of the guard ring 83.
  • the dummy gates 43 and 44 extend in the Y direction.
  • guard ring 83 may not be formed.
  • FIG. 6 shows an example of the layout structure of the protection resistor R2. However, the wiring layer and the like are not shown.
  • the protection resistor R2 is divided into four resistance regions 22 arranged in the X direction.
  • a gate wiring 51 is formed in each resistance region 22, and one or a plurality of resistors are formed by connecting the gate wiring 51 with a wiring (not shown).
  • the gate wiring 51 is formed on the N-shaped well.
  • the tap area 24 is arranged so as to sandwich each resistance area 22.
  • N conductive type fins 52 are formed on N wells, and the fins 52 serve as taps.
  • Each fin 52 extends in the X direction and is connected to VDDIO.
  • a dummy gate 45 extending in the Y direction is formed in each fin 52.
  • the gate wiring 51 constituting the protection resistor is formed on the N-type well, it may be formed on the P-type substrate. Further, the tap in the tap region 24 is a P conductive type fin formed on the P type substrate and may be connected to VSS.
  • FIG. 7 shows an example of the layout structure of the protection resistor R1. However, the wiring layer and the like are not shown.
  • the protection resistor R1 is divided into four resistance regions 21 arranged in the X direction.
  • a gate wiring 53 is formed in each resistance region 21, and one or a plurality of resistors are formed by connecting the gate wiring 53 with a wiring (not shown).
  • the gate wiring 53 is formed on the N-shaped well.
  • the tap area 23 is arranged so as to sandwich each resistance area 21.
  • P conductive type fins 54 are formed on the P type substrate, and the fins 54 serve as taps.
  • Each fin 54 extends in the X direction and is connected to VSS.
  • a dummy gate 46 extending in the Y direction is formed in each fin 54.
  • the gate wiring 53 constituting the protection resistor is formed on the N-type well, it may be formed on the P-type substrate. Further, the tap of the tap region 23 is an N conductive type fin formed on the N type well, and may be connected to VDDIO.
  • the protection resistor is composed of gate wiring, but the present invention is not limited to this, and may be composed of fins, metal wiring, or the like. Alternatively, the resistor may be configured by a combination of gate wiring, fins, metal wiring, and the like.
  • dummy gates 45 and 46 may not be provided.
  • the tap has a diffusion region of a fin structure, but the tap is not limited to this.
  • FIG. 8 shows an example of the layout structure of the output transistor N1. However, the wiring layer and the like are not shown.
  • each in the region of the output transistor N1 in the central portion, each extends in the X direction, and a plurality of N conductive type fins 61 arranged side by side in the Y direction and extend in the Y direction, respectively.
  • a plurality of gate wirings 62 arranged side by side in the X direction are formed.
  • the fins 61 and the gate wiring 62 that overlap in a plan view form a transistor.
  • Each transistor is connected in parallel by wiring (not shown).
  • the drain of each transistor is connected to the external output terminal OUT via the protection resistor R2.
  • a guard ring 85 is formed around the output transistor N1.
  • the guard ring 85 includes P conductive type fins 86 formed on the P substrate.
  • the fin 86 extends in the X direction.
  • the fin 86 is connected to VSS.
  • a dummy gate 47 is formed on the fin 86.
  • the dummy gate 47 may not be provided. Further, the guard ring 85 may not be formed.
  • FIG. 9 shows an example of the layout structure of the output transistor P1. However, the wiring layer and the like are not shown.
  • each in the region of the output transistor P1 in the central portion, each extends in the X direction, and a plurality of P conductive type fins 66 arranged side by side in the Y direction and extend in the Y direction, respectively.
  • a plurality of gate wirings 67 arranged side by side in the X direction are formed.
  • the fins 66 and the gate wiring 67 that overlap in a plan view form a transistor.
  • Each transistor is connected in parallel by wiring (not shown).
  • the drain of each transistor is connected to the external output terminal OUT via the protection resistor R1.
  • a guard ring 87 is formed around the output transistor P1.
  • the guard ring 87 includes N conductive fins 88 formed in N wells.
  • the fin 88 extends in the X direction. Fin 88 is connected to VDDIO.
  • a dummy gate 48 is formed on the fin 88.
  • the dummy gate 48 does not have to be provided. Further, the guard ring 87 may not be formed.
  • the output transistor P1 is arranged apart from the ESD protection diode D1 connected to the external output terminal OUT, and the protection resistor R1 is arranged between them.
  • the output transistor N1 is arranged apart from the ESD protection diode D2 connected to the external output terminal OUT, and the protection resistor R2 is arranged between them.
  • the protection resistor R1 is formed by being divided into a plurality of resistance regions 21, and a tap for supplying VSS to the P-type substrate is formed in the tap region 23 between the resistance regions 21.
  • the protection resistor R2 is formed by being divided into a plurality of resistance regions 22, and a tap for supplying VDDIO to the N-shaped well is formed in the tap region 24 between the resistance regions 22.
  • a tap for supplying VDDIO to the N-shaped well is formed in the tap region 24 between the resistance regions 22.
  • the noise applied to the external output terminal OUT is absorbed via the tap. Therefore, it is possible to suppress the propagation of noise that causes the occurrence of the latch-up phenomenon.
  • the tap areas 23 and 24 are dispersed in a plurality of areas, the effect of absorbing noise can be obtained more uniformly.
  • FIG. 10 is a schematic cross-sectional view of the semiconductor integrated circuit device according to the present embodiment. From the right side of the drawing, the ESD protection diode D2, the protection resistor R2, the well tap portion (protection resistor R2 is not shown), the output transistor N1, and other transistors are arranged in this order.
  • noise is applied to the external output terminal OUT (A in FIG. 10). If this noise is not sufficiently reduced and propagates to the region of the output transistor N1 or another transistor, the propagated noise causes a current to flow through the base of the parasitic bipolar transistor. Due to this, a latch-up phenomenon occurs via the parasitic transistor, and a large current is generated between VDDIO and VSS (B in FIG. 10).
  • the protection resistor R2 interposed between the ESD protection diode D2 and the output transistor N1 separates the diode D2 from the other transistors, and the noise is attenuated. Further, the noise of the external output terminal OUT (A in FIG. 10) is absorbed by the path D in FIG. 10 through the tap provided in the region of the protection resistor R2, and the base node of the parasitic bipolar transistor (C in FIG. 10). ) Potential fluctuations can be suppressed. As a result, noise propagating to the output transistor N1 and other transistor regions can be suppressed, and the occurrence of the latch-up phenomenon can be suppressed.
  • FIG. 11 is a schematic view showing another example of the planar layout structure of the output circuit 11.
  • the protection resistor R1 has a rectangular shape extending in the X direction, and is divided into four resistance regions 21A arranged in the Y direction.
  • a tap region 23A in which a tap for supplying VSS is formed on the P-type substrate is arranged so as to sandwich each resistance region 21A.
  • the protection resistor R2 has a rectangular shape extending in the X direction, and is divided into four resistance regions 22A arranged in the Y direction.
  • a tap region 24A in which a tap for supplying VDDIO to the N-shaped well is formed is arranged so as to sandwich each resistance region 22A.
  • the same action and effect as those in the above-described embodiment can be obtained. That is, the noise applied to the external output terminal OUT is attenuated by the protection resistors R1 and R2 by the time it reaches the output transistors P1 and N1. Further, the noise applied to the external output terminal OUT is absorbed through the taps formed in the tap areas 23A and 24A. Therefore, it is possible to suppress the propagation of noise that causes the occurrence of the latch-up phenomenon. In addition, since the tap regions 23A and 24A are dispersed in a plurality of areas, the effect of absorbing noise can be obtained more uniformly.
  • the protection resistors R1 and R2 are divided in the X direction
  • the protection resistors R1 and R2 are divided in the Y direction, but the division directions are mixed. May be good.
  • the layout may be such that the protection resistor R1 is divided in the X direction and the protection resistor R2 is divided in the Y direction.
  • FIG. 12 is a circuit configuration diagram of the output circuit 12 according to the present embodiment.
  • the circuit configuration of FIG. 12 is almost the same as the circuit configuration of FIG. 2, but the insertion position of the protection resistor is different. That is, in the output circuit 12 of FIG. 12, a protection resistor R3 is provided instead of the protection resistors R1 and R2 in FIG. In FIG. 12, the drains of the output transistors P1 and N1 are connected to each other, and the protection resistor R3 is provided between the external output terminal OUT and the drains of the output transistors P1 and N1.
  • FIG. 13 is a schematic view showing an example of the planar layout structure of the output circuit 12 according to the present embodiment.
  • the X direction (horizontal direction in the drawing) is the direction in which the I / O cells 10 are lined up
  • the Y direction vertical direction in the drawing
  • the upper side of the drawing is the core region 2 side
  • the lower side of the drawing is the chip end side.
  • Each region of FIG. 13 has the same symbols as the corresponding circuit elements in the circuit diagram of FIG.
  • the ESD protection diodes D1 and D2 are arranged adjacent to each other in the Y direction.
  • the output transistors P1 and N1 are arranged adjacent to each other in the Y direction.
  • the ESD protection diodes D1 and D2 are arranged at the bottom of the drawing in the Y direction.
  • the output transistors P1 and N1 are arranged on the upper side of the drawings of the ESD protection diodes D1 and D2 so as to be separated from the ESD protection diodes D1 and D2.
  • the protection resistor R3 is arranged between the output transistors P1 and N1 and the ESD protection diodes D1 and D2.
  • the protection resistor R3 is formed by being divided into a plurality of regions (resistance regions) 121.
  • the protection resistor R3 has a rectangular shape extending in the Y direction, and is divided into four resistance regions 121 arranged in the X direction. Between the resistance regions 121, a tap region 122 in which a tap for supplying VSS to the P-type substrate is formed and a tap region 123 in which a tap for supplying VDDIO to the N-type well is formed are arranged.
  • a tap region 122 in which a tap for supplying VSS to the P-type substrate is formed and a tap region 123 in which a tap for supplying VDDIO to the N-type well is formed are arranged.
  • FIG. 13 the example of FIG.
  • the tap area 122 and the tap area 123 are alternately arranged in the Y direction. That is, in a single region between the resistance regions 121, a tap for supplying VSS to the P-type substrate and a tap for supplying VDDIO to the N-type well are formed.
  • the output transistors P1 and N1 are arranged apart from the ESD protection diodes D1 and D2 connected to the external output terminal OUT, and the protection resistor R3 is arranged between them.
  • the protection resistor R3 is formed by being divided into a plurality of resistance regions 121, and a tap for supplying VSS to the P-type substrate is formed in the tap region 122 between the resistance regions 121, and the resistance regions 121 are formed with each other.
  • a tap for supplying VDDIO to the N-shaped well is formed in the tap region 123 between the two.
  • the noise applied to the external output terminal OUT is absorbed via the tap. Therefore, it is possible to suppress the propagation of noise that causes the occurrence of the latch-up phenomenon.
  • the tap areas 122 and 123 are dispersed in a plurality of areas, the effect of absorbing noise can be obtained more uniformly.
  • the tap area 122 in which the tap for supplying VSS is formed on the P-type substrate functions for noise absorption from the ESD protection diode D1, and the tap area 123 in which the tap for supplying VDDIO to the N-type well is formed. However, it functions for noise absorption from the ESD protection diode D2.
  • the positions of the ESD protection diodes D1 and D2 may be exchanged. Further, the positions of the output transistors P1 and N1 may be exchanged.
  • (Modification example) 14 (a) and 14 (b) are schematic views showing another example of the planar layout structure of the output circuit 12.
  • 123A and 123A are arranged alternately in the X direction.
  • the protection resistor R3 has a rectangular shape extending in the X direction and is divided into four resistance regions 121A arranged in the Y direction. Between the resistance regions 121A, a tap region 122B in which a tap for supplying VSS to the P-type substrate is formed and a tap region 123B in which a tap for supplying VDDIO to the N-type well is formed are arranged. In the example of FIG. 13, the tap area 122B and the tap area 123B are alternately arranged in the X direction.
  • the tap area 122B and the tap area 123B may be alternately arranged in the Y direction.
  • the same action and effect as those in the above-described embodiment can be obtained. That is, the noise applied to the external output terminal OUT is attenuated by the protection resistor R3 by the time it reaches the output transistors P1 and N1. Further, the noise applied to the external output terminal OUT is absorbed through the taps formed in the tap areas 122 and 123. Therefore, it is possible to suppress the propagation of noise that causes the occurrence of the latch-up phenomenon. In addition, since the tap areas 122 and 123 are dispersed in a plurality of areas, the effect of absorbing noise can be obtained more uniformly.
  • the protection resistors R1, R2, and R3 are divided into four resistance regions, but the number of resistance regions is not limited to four.
  • both the P conductive type transistor and the N conductive type output transistor are assumed to be one-stage transistors, but the present invention is not limited to this, and for example, two-stage and three-stage. A plurality of stages of transistors such as the above may be connected in series. Further, the output circuit in the above-described embodiment may be an input / output circuit including an input circuit.
  • the occurrence of the latch-up phenomenon can be sufficiently suppressed in the semiconductor integrated circuit device, which is useful for improving the performance of a semiconductor chip, for example.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2020/039593 2019-11-06 2020-10-21 半導体集積回路装置 Ceased WO2021090688A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202080074126.7A CN114600242B (zh) 2019-11-06 2020-10-21 半导体集成电路装置
JP2021554875A JP7610129B2 (ja) 2019-11-06 2020-10-21 半導体集積回路装置
US17/735,052 US11824055B2 (en) 2019-11-06 2022-05-02 Semiconductor integrated circuit device

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Application Number Priority Date Filing Date Title
JP2019201491 2019-11-06
JP2019-201491 2019-11-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024029040A1 (ja) * 2022-08-04 2024-02-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024047820A1 (ja) * 2022-08-31 2024-03-07 株式会社ソシオネクスト 半導体集積回路装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7610129B2 (ja) * 2019-11-06 2025-01-08 株式会社ソシオネクスト 半導体集積回路装置
CN119650552A (zh) * 2023-09-18 2025-03-18 联华电子股份有限公司 静电防护环结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147282A (ja) * 2008-12-19 2010-07-01 Renesas Technology Corp 半導体集積回路装置
JP2014064044A (ja) * 2014-01-07 2014-04-10 Renesas Electronics Corp 半導体集積回路装置
JP2016072349A (ja) * 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2019043888A1 (ja) * 2017-08-31 2019-03-07 株式会社ソシオネクスト 半導体集積回路装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100307554B1 (ko) * 1998-06-30 2001-11-15 박종섭 Esd 소자를 구비하는 반도체장치
DE10139956A1 (de) * 2001-08-21 2003-03-13 Koninkl Philips Electronics Nv ESD Schutz für CMOS-Ausgangsstufe
US20050179088A1 (en) * 2004-02-17 2005-08-18 Infineon Technologies Ag ESD protective apparatus for a semiconductor circuit having an ESD protective circuit which makes contact with a substrate or guard ring contact
JP2007234718A (ja) * 2006-02-28 2007-09-13 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7564666B2 (en) * 2006-05-02 2009-07-21 Semiconductor Components Industries, L.L.C. Shunt protection circuit and method therefor
US7538997B2 (en) * 2006-05-31 2009-05-26 Alpha & Omega Semiconductor, Ltd. Circuit configurations to reduce snapback of a transient voltage suppressor
US8228651B2 (en) * 2009-07-31 2012-07-24 Hynix Semiconductor Inc. ESD protection circuit
JP2011096897A (ja) * 2009-10-30 2011-05-12 Renesas Electronics Corp 半導体装置及び電子機器
US9087719B2 (en) * 2012-09-28 2015-07-21 Intel Corporation Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection
US9013844B2 (en) * 2013-01-15 2015-04-21 Xilinx, Inc. Circuit for and method of enabling the discharge of electric charge in an integrated circuit
JP6243720B2 (ja) * 2013-02-06 2017-12-06 エスアイアイ・セミコンダクタ株式会社 Ｅｓｄ保護回路を備えた半導体装置
US9054521B2 (en) * 2013-06-25 2015-06-09 Hong Kong Applied Science & Technology Research Institute Company, Ltd. Electro-static-discharge (ESD) protection structure with stacked implant junction transistor and parallel resistor and diode paths to lower trigger voltage and raise holding volatge
US8958189B1 (en) * 2013-08-09 2015-02-17 Infineon Technologies Austria Ag High-voltage semiconductor switch and method for switching high voltages
CN107112281B (zh) * 2015-01-08 2020-11-10 松下半导体解决方案株式会社 半导体装置以及其设计方法
US9871029B2 (en) * 2016-05-06 2018-01-16 Analog Devices Global Bus driver / line driver
JP6841161B2 (ja) * 2017-05-25 2021-03-10 株式会社ソシオネクスト 半導体装置
US11037921B2 (en) * 2019-10-15 2021-06-15 Nanya Technology Corporation Off chip driver structure
JP7610129B2 (ja) * 2019-11-06 2025-01-08 株式会社ソシオネクスト 半導体集積回路装置
JP7342742B2 (ja) * 2020-03-11 2023-09-12 三菱電機株式会社 半導体装置
US20210408786A1 (en) * 2020-06-30 2021-12-30 Qualcomm Incorporated Circuit techniques for enhanced electrostatic discharge (esd) robustness
JP2022163499A (ja) * 2021-04-14 2022-10-26 ローム株式会社 半導体装置
CN115241855B (zh) * 2021-04-23 2025-09-23 澜起科技股份有限公司 基于串联端接匹配的驱动输出电路、芯片及驱动输出方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147282A (ja) * 2008-12-19 2010-07-01 Renesas Technology Corp 半導体集積回路装置
JP2014064044A (ja) * 2014-01-07 2014-04-10 Renesas Electronics Corp 半導体集積回路装置
JP2016072349A (ja) * 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2019043888A1 (ja) * 2017-08-31 2019-03-07 株式会社ソシオネクスト 半導体集積回路装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024029040A1 (ja) * 2022-08-04 2024-02-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024047820A1 (ja) * 2022-08-31 2024-03-07 株式会社ソシオネクスト 半導体集積回路装置

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