JP7610129B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

Info

Publication number
JP7610129B2
JP7610129B2 JP2021554875A JP2021554875A JP7610129B2 JP 7610129 B2 JP7610129 B2 JP 7610129B2 JP 2021554875 A JP2021554875 A JP 2021554875A JP 2021554875 A JP2021554875 A JP 2021554875A JP 7610129 B2 JP7610129 B2 JP 7610129B2
Authority
JP
Japan
Prior art keywords
esd protection
tap
output
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021554875A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2021090688A1 (https=
JPWO2021090688A5 (https=
Inventor
英俊 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Publication of JPWO2021090688A1 publication Critical patent/JPWO2021090688A1/ja
Publication of JPWO2021090688A5 publication Critical patent/JPWO2021090688A5/ja
Application granted granted Critical
Publication of JP7610129B2 publication Critical patent/JP7610129B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2021554875A 2019-11-06 2020-10-21 半導体集積回路装置 Active JP7610129B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019201491 2019-11-06
JP2019201491 2019-11-06
PCT/JP2020/039593 WO2021090688A1 (ja) 2019-11-06 2020-10-21 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JPWO2021090688A1 JPWO2021090688A1 (https=) 2021-05-14
JPWO2021090688A5 JPWO2021090688A5 (https=) 2022-07-07
JP7610129B2 true JP7610129B2 (ja) 2025-01-08

Family

ID=75848200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021554875A Active JP7610129B2 (ja) 2019-11-06 2020-10-21 半導体集積回路装置

Country Status (4)

Country Link
US (1) US11824055B2 (https=)
JP (1) JP7610129B2 (https=)
CN (1) CN114600242B (https=)
WO (1) WO2021090688A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7610129B2 (ja) * 2019-11-06 2025-01-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024029040A1 (ja) * 2022-08-04 2024-02-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024047820A1 (ja) * 2022-08-31 2024-03-07 株式会社ソシオネクスト 半導体集積回路装置
CN119650552A (zh) * 2023-09-18 2025-03-18 联华电子股份有限公司 静电防护环结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147282A (ja) 2008-12-19 2010-07-01 Renesas Technology Corp 半導体集積回路装置
JP2014064044A (ja) 2014-01-07 2014-04-10 Renesas Electronics Corp 半導体集積回路装置
JP2016072349A (ja) 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2019043888A1 (ja) 2017-08-31 2019-03-07 株式会社ソシオネクスト 半導体集積回路装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100307554B1 (ko) * 1998-06-30 2001-11-15 박종섭 Esd 소자를 구비하는 반도체장치
DE10139956A1 (de) * 2001-08-21 2003-03-13 Koninkl Philips Electronics Nv ESD Schutz für CMOS-Ausgangsstufe
US20050179088A1 (en) * 2004-02-17 2005-08-18 Infineon Technologies Ag ESD protective apparatus for a semiconductor circuit having an ESD protective circuit which makes contact with a substrate or guard ring contact
JP2007234718A (ja) * 2006-02-28 2007-09-13 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7564666B2 (en) * 2006-05-02 2009-07-21 Semiconductor Components Industries, L.L.C. Shunt protection circuit and method therefor
US7538997B2 (en) * 2006-05-31 2009-05-26 Alpha & Omega Semiconductor, Ltd. Circuit configurations to reduce snapback of a transient voltage suppressor
US8228651B2 (en) * 2009-07-31 2012-07-24 Hynix Semiconductor Inc. ESD protection circuit
JP2011096897A (ja) * 2009-10-30 2011-05-12 Renesas Electronics Corp 半導体装置及び電子機器
US9087719B2 (en) * 2012-09-28 2015-07-21 Intel Corporation Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection
US9013844B2 (en) * 2013-01-15 2015-04-21 Xilinx, Inc. Circuit for and method of enabling the discharge of electric charge in an integrated circuit
JP6243720B2 (ja) * 2013-02-06 2017-12-06 エスアイアイ・セミコンダクタ株式会社 Esd保護回路を備えた半導体装置
US9054521B2 (en) * 2013-06-25 2015-06-09 Hong Kong Applied Science & Technology Research Institute Company, Ltd. Electro-static-discharge (ESD) protection structure with stacked implant junction transistor and parallel resistor and diode paths to lower trigger voltage and raise holding volatge
US8958189B1 (en) * 2013-08-09 2015-02-17 Infineon Technologies Austria Ag High-voltage semiconductor switch and method for switching high voltages
CN107112281B (zh) * 2015-01-08 2020-11-10 松下半导体解决方案株式会社 半导体装置以及其设计方法
US9871029B2 (en) * 2016-05-06 2018-01-16 Analog Devices Global Bus driver / line driver
JP6841161B2 (ja) * 2017-05-25 2021-03-10 株式会社ソシオネクスト 半導体装置
US11037921B2 (en) * 2019-10-15 2021-06-15 Nanya Technology Corporation Off chip driver structure
JP7610129B2 (ja) * 2019-11-06 2025-01-08 株式会社ソシオネクスト 半導体集積回路装置
JP7342742B2 (ja) * 2020-03-11 2023-09-12 三菱電機株式会社 半導体装置
US20210408786A1 (en) * 2020-06-30 2021-12-30 Qualcomm Incorporated Circuit techniques for enhanced electrostatic discharge (esd) robustness
JP2022163499A (ja) * 2021-04-14 2022-10-26 ローム株式会社 半導体装置
CN115241855B (zh) * 2021-04-23 2025-09-23 澜起科技股份有限公司 基于串联端接匹配的驱动输出电路、芯片及驱动输出方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147282A (ja) 2008-12-19 2010-07-01 Renesas Technology Corp 半導体集積回路装置
JP2014064044A (ja) 2014-01-07 2014-04-10 Renesas Electronics Corp 半導体集積回路装置
JP2016072349A (ja) 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2019043888A1 (ja) 2017-08-31 2019-03-07 株式会社ソシオネクスト 半導体集積回路装置

Also Published As

Publication number Publication date
US20220262787A1 (en) 2022-08-18
JPWO2021090688A1 (https=) 2021-05-14
US11824055B2 (en) 2023-11-21
CN114600242A (zh) 2022-06-07
WO2021090688A1 (ja) 2021-05-14
CN114600242B (zh) 2025-08-29

Similar Documents

Publication Publication Date Title
JP7610129B2 (ja) 半導体集積回路装置
US10692856B2 (en) Semiconductor integrated circuit device
JP3237110B2 (ja) 半導体装置
CN100459117C (zh) 具有静电释放保护单元的集成电路装置
JP2847132B2 (ja) Cmosトランジスター素子の方形型セル
KR20090020528A (ko) 반도체 디바이스
CN202930381U (zh) 半导体集成电路器件
US20080169509A1 (en) Semiconductor device
WO2021090471A1 (ja) 半導体集積回路装置
WO2022215485A1 (ja) 半導体集積回路装置
US20240213770A1 (en) Semiconductor integrated circuit device
JP7323847B2 (ja) 半導体集積回路装置
US20260033012A1 (en) Semiconductor integrated circuit device
US20250192045A1 (en) Semiconductor integrated circuit device
US20250151412A1 (en) Semiconductor integrated circuit device
CN101154657B (zh) 静电放电防护电路的布局结构及其制造方法
JP3383613B2 (ja) 半導体集積回路装置
JP2023110556A (ja) 半導体集積回路
WO2024241869A1 (ja) 半導体集積回路装置
JP3477117B2 (ja) 半導体集積回路装置
JP6118923B2 (ja) 半導体集積回路装置
JP2003318276A (ja) 半導体集積回路装置
JP2004200650A (ja) 静電気放電保護素子

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220419

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230915

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20241119

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20241202

R150 Certificate of patent or registration of utility model

Ref document number: 7610129

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150