WO2021077756A1 - 包括mram底电极制作工艺的制作方法及mram器件 - Google Patents

包括mram底电极制作工艺的制作方法及mram器件 Download PDF

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WO2021077756A1
WO2021077756A1 PCT/CN2020/094439 CN2020094439W WO2021077756A1 WO 2021077756 A1 WO2021077756 A1 WO 2021077756A1 CN 2020094439 W CN2020094439 W CN 2020094439W WO 2021077756 A1 WO2021077756 A1 WO 2021077756A1
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layer
bottom electrode
barrier layer
manufacturing
mram
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PCT/CN2020/094439
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French (fr)
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王雷
李振
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浙江驰拓科技有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

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  • the present disclosure relates to the field of semiconductors, and in particular, to a manufacturing method including a manufacturing process of an MRAM bottom electrode and an MRAM device.
  • Magnetic Random Access Memory is a new type of non-volatile memory. Compared with other current types of memory, it has fast read and write speed, can achieve unlimited erasing and writing, and is easy to compare with current semiconductor technology. Compatibility and other advantages. In addition, the spin transfer torque (Spin Transfer Torque, STT) MRAM that uses the spin current to achieve the magnetic moment reversal can realize the reduction of the size of the memory cell. These advantages make MRAM the main development direction of new memory in the future.
  • the main functional unit in MRAM is the MTJ unit, and its structure mainly includes a magnetic free layer/non-magnetic oxide layer (MgO)/magnetic pinned layer. Driven by an external magnetic field or current, the direction of the magnetic moment of the magnetic free layer is reversed, and the direction of the magnetic moment of the magnetic pinned layer is parallel or anti-parallel, making MRAM appear high and low resistance states, which can be defined as storage states. 0" and "1", so as to realize the storage of information.
  • MgO magnetic free layer/non-magnetic oxide layer
  • the main functional unit MTJ unit has a total of more than ten to twenty layers of different magnetic or non-magnetic film compositions, and the thickness of the multilayer film is required to be less than 1 nm or even several angstroms.
  • the planarization process of the bottom electrode becomes extremely important.
  • the manufacturing process of the bottom electrode includes: sequentially depositing a first barrier layer 2 and a dielectric layer 3 on the metal interconnection layer 1 formed in the previous process to form the structure shown in FIG. 1; The dielectric layer 3 and the first barrier layer 2 are etched to form a bottom through hole 4 on the metal interconnection layer 1 to form the structure shown in FIG. 2; after that, the second barrier layer 5 and the conductive metal are sequentially arranged on the previously formed structure Layer 6, as shown in FIG. 3; after that, remove the conductive metal layer 6 outside the bottom via hole and the second barrier layer 5 on both sides of the bottom via hole to form the structure shown in FIG. 4; after that, the structure formed before The bottom electrode material 7 is set on it to form the structure shown in FIG. 5; finally, part of the bottom electrode material is etched away to form the bottom electrode 7'shown in FIG. 6.
  • the second barrier layer material in this process, involves three different materials, specifically the material of the dielectric layer, the second barrier layer material and the conductive metal material. Due to the process limitations of the different polishing rates of various thin film materials, The simultaneous planarization effect of these three materials is poor. In the mass production of MRAM, the conductive vias formed will have the problem of large difference in surface depression, resulting in poor uniformity of the bottom electrode of the manufactured MRAM and relatively high test accuracy. Poor, more serious may cause open circuit problems and affect yield.
  • the main purpose of the present disclosure is to provide a manufacturing method and MRAM device including the manufacturing process of the MRAM bottom electrode, so as to solve the problem that it is difficult to form a uniform MRAM bottom electrode and an open circuit of the bottom electrode in the prior art.
  • the manufacturing method includes: step S1, providing a substrate, the substrate including a metal interconnection layer, a first barrier layer, and A dielectric layer, forming a bottom through hole in the first barrier layer and the dielectric layer; step S2, on the exposed surface of the dielectric layer on both sides of the bottom through hole and the bottom through hole Cover the second barrier layer and the conductive metal layer in sequence, the conductive metal layer fills the bottom through hole; step S3, the conductive metal layer on the surface of the second barrier layer is removed by a chemical mechanical polishing method, and the conductive metal layer is retained In the second barrier layer, depressions are formed in the bottom through holes; step S4, depositing bottom electrode metal, filling the depressions, and forming a bottom electrode metal prefabrication layer; step S5, removing part of the bottom electrode metal prefabrication by chemical mechanical polishing Layer, forming the bottom electrode metal prefabricated layer with a flat surface; step S6, performing
  • the step S3 includes: stopping the polishing end point at the second barrier layer, and performing polishing after the second barrier layer is detected according to an end point detection method.
  • the thickness of the deposited bottom electrode metal is greater than the depth of the recess.
  • the material of the bottom electrode metal is selected from any one or more of TaN, Ta, TiN and Ti.
  • the material of the conductive metal layer is selected from any one or more of Cu, W and Al.
  • the material of the second barrier layer is selected from any one or more of Ta, TaN, Ti, TiN, Co, and Ru.
  • the material of the dielectric layer is selected from silicon oxide SiO, silicon dioxide SiO2, oxycarbide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, ortho silicon Any one or more of TEOS, low-K medium and ultra-low-K medium.
  • the material of the first barrier layer is silicon oxynitride, silicon nitride, silicon carbonitride or silicon carbide.
  • the manufacturing method further includes: forming a substrate including a CMOS sensor, and the metal interconnection layer is located on the surface of the substrate.
  • an MRAM device including an MRAM bottom electrode, the MRAM bottom electrode being manufactured by any one of the manufacturing methods.
  • the conductive metal material on the surface of the second barrier layer is removed by the chemical mechanical polishing method, and the conductive metal material on the surface of the second barrier layer is stopped.
  • the mechanical polishing process only the conductive metal layer is polished without polishing the second barrier layer, which simplifies the process flow, improves production efficiency and reduces the risk of process stability.
  • the deposited bottom electrode metal preform is chemically mechanically polished to form a bottom electrode metal layer with a flat surface, and further photolithography and etching are performed to obtain an MRAM bottom electrode with a flat surface, which effectively avoids the polishing of the bottom conductive metal layer.
  • the resulting dent problem improves the flatness of the bottom electrode.
  • FIGS. 1 to 6 show schematic structural diagrams of the manufacturing process of MRAM according to an embodiment in the prior art
  • Metal interconnection layer 1. Metal interconnection layer; 2. First barrier layer; 3. Dielectric layer; 4. Bottom via; 5. Second barrier layer; 6. Conductive metal layer; 7. Bottom electrode material; 7', Bottom electrode; 10. Metal interconnection layer; 20. First barrier layer; 21. First barrier layer after etching; 30. Dielectric layer; 31. Dielectric layer after etching; 32. Bottom via hole; 40. Second Barrier layer; 41, the second barrier layer after etching; 50, the conductive metal layer; 51, the polished conductive metal layer; 60, the bottom electrode metal prefabricated layer; 61, the MRAM bottom electrode.
  • the present disclosure proposes a manufacturing method including a manufacturing process of the MRAM bottom electrode.
  • a manufacturing method including a manufacturing process of an MRAM bottom electrode includes:
  • Step S1 a substrate is provided.
  • the substrate includes a metal interconnection layer 10, a first barrier layer 20, and a dielectric layer 30 arranged in sequence.
  • a bottom through hole 32 is formed in the first barrier layer and the dielectric layer, as shown in FIG. 8 Shown
  • Step S2 covering the exposed surface of the dielectric layer on both sides of the bottom through hole 32 and the bottom through hole 32 sequentially with a second barrier layer 40 and a conductive metal layer 50, and the conductive metal layer 50 fills the bottom through hole 32, as shown in Figure 9;
  • Step S3 using a chemical mechanical polishing method to remove the conductive metal layer on the surface of the second barrier layer, leaving the second barrier layer 40, and forming a recess in the bottom through hole 32, as shown in FIG. 10;
  • Step S4 depositing bottom electrode metal, filling the above-mentioned recesses, and forming a bottom electrode metal prefabricated layer 60, as shown in FIG. 11;
  • Step S5 removing part of the bottom electrode metal preform 60 by chemical mechanical polishing to form a bottom electrode metal preform 60 with a flat surface, as shown in FIG. 12;
  • step S6 photolithography and etching are performed on the bottom electrode metal prefabricated layer to obtain an MRAM bottom electrode 61, as shown in FIG. 13.
  • the conductive metal material on the surface of the second barrier layer is removed by the chemical mechanical polishing method, and the conductive metal material is stopped on the second barrier layer, that is, only the conductive metal layer is polished in the chemical mechanical polishing process of the conductive metal layer. Polishing the second barrier layer simplifies the process flow, improves production efficiency and reduces the risk of process stability.
  • the deposited bottom electrode metal preform is chemically mechanically polished to form a bottom electrode metal layer with a flat surface, and further photolithography and etching are performed to obtain an MRAM bottom electrode with a flat surface, which effectively avoids the polishing of the bottom conductive metal layer. The resulting dent problem improves the flatness of the bottom electrode.
  • the step S1 before the step S1, it includes: disposing a first barrier layer on the exposed surface of the metal interconnection layer 10 20; A dielectric layer 30 is provided on the surface of the first barrier layer 20 away from the metal interconnection layer, as shown in FIG. 8, the step S1 further includes: etching and removing part of the first barrier layer 20 and part of the dielectric The electrical layer forms the bottom through hole 32, the remaining first barrier layer forms the etched first barrier layer 21, and the remaining dielectric layer forms the etched dielectric layer 31, as shown in FIG. 9.
  • the step S3 includes: stopping the polishing end point at the second barrier layer, and polishing is performed after the second barrier layer is detected according to an end point detection method.
  • the above method polishes the conductive metal layer until the second barrier layer is exposed, and then further polishes the second barrier layer, so that the conductive metal layer on the surface of the second barrier layer on both sides of the bottom through hole can be completely removed.
  • the thickness of the deposited bottom electrode metal is greater than the depth of the recess.
  • the material of the first barrier layer in the present disclosure is any material that can prevent metal materials from diffusing into the dielectric layer.
  • a suitable material as the material of the first barrier layer can select a suitable material as the material of the first barrier layer according to the actual situation, such as silicon oxynitride. , Silicon nitride, silicon carbon nitride or silicon carbide and other materials.
  • the MRAM may include a plurality of MTJ devices, and each MTJ device corresponds to a metal interconnection layer.
  • the metal interconnection layer includes a plurality of spaced metal interconnection layers, and the bottom through hole corresponds to It is in contact with the above-mentioned metal interconnection layer.
  • the above-mentioned manufacturing method further includes: sequentially arranging a free layer, a reference layer, an insulating barrier layer, and a top electrode on the surface of the above-mentioned bottom electrode.
  • the bottom electrode, the free layer, the reference layer, the insulating barrier layer and the top electrode formed on the metal wire part together constitute the MTJ device.
  • the MTJ device may also include other structural layers. Choose other suitable structural layers in actual situations, for example, pinned layers.
  • the material of the conductive metal layer is selected from any one or more of Cu, W, and Al.
  • the bottom electrode material is selected from any one or more of Ta, TaN, Ti, and TiN.
  • the bottom electrode material is similar to the second barrier material.
  • the above manufacturing method can reduce the etching difficulty of manufacturing the bottom electrode, thereby improving the efficiency of manufacturing the MRAM.
  • the material of the second barrier layer is selected from any one or more of Ta, TaN, Ti, TiN, Co, and Ru.
  • the material of the above-mentioned dielectric layer is selected from silicon oxide, silicon dioxide, oxycarbide, silicon nitride, fluorosilicate glass, phosphosilicate glass, and boron. Any one or more of phosphosilicate glass, tetraethyl orthosilicate, ultra-low-K medium and ultra-low-K medium.
  • the manufacturing method before step S1, further includes: forming a substrate including a CMOS sensor, and the metal wire layer is located on the surface of the substrate.
  • the substrate also includes some other structures formed in the previous process.
  • the material of the metal interconnection layer is Cu.
  • the resistance of Cu is low, which can significantly reduce the RC delay effect.
  • the material of the metal interconnection layer of the present disclosure is not limited to Cu, and can also be other suitable materials. Those skilled in the art can select appropriate metal materials to form the metal interconnection layer according to actual conditions.
  • an MRAM device is provided, and the MRAM device is manufactured by using any of the above-mentioned manufacturing methods.
  • the bottom electrode of the MRAM has better uniformity and is relatively flat, which can ensure better test accuracy and make the performance of the device better.
  • the manufacturing process including the manufacturing process of the MRAM bottom electrode includes:
  • a substrate including a CMOS sensor is formed.
  • the substrate includes a metal interconnection layer 10, a first barrier layer 20 (NBlock) and a dielectric layer 30 (TEOS) arranged in sequence.
  • the metal interconnection layer 10 includes a plurality of spaced metal interconnection layer units, as shown in FIG. 7 Only one metal interconnection layer unit is shown in;
  • the remaining dielectric layer forms the etched dielectric layer 31, and the remaining first barrier layer
  • the etched first barrier layer 21 is formed by the layer, as shown in FIG. 8;
  • a second barrier layer 40 (TaN/Ta) and a conductive metal layer 50 (Cu) are sequentially arranged on the exposed surface of the bottom through hole 32 and the dielectric layer on both sides thereof, and the conductive metal layer 50 covers the two sides of the bottom through hole 32. And the above-mentioned second barrier layer 40 on the surface of the dielectric layer is as shown in FIG. 9;
  • a chemical mechanical polishing method is used to remove part of the conductive metal layer 50 until the second barrier layer 40 on both sides of the bottom through hole 32 is exposed, and the remaining conductive metal layer 50 in the bottom through hole 32 forms a polished conductive metal layer 51. As shown in Figure 10;
  • Bottom electrode metal prefabricated layer 60 (TaN), as shown in FIG. 11;
  • the etching method is used to remove part of the bottom electrode metal prefabricated layer 60 and at least part of the second barrier layer 40 on both sides of the bottom through hole 32, so that part of the dielectric layer is exposed, and the remaining bottom electrode metal forms the MRAM bottom electrode 61.
  • the second barrier layer forms the second barrier layer 41 after etching, as shown in FIG. 13.
  • the conductive metal material on the surface of the second barrier layer is removed by chemical mechanical polishing, and the conductive metal material is stopped on the second barrier layer, that is, the chemical mechanical polishing is performed on the conductive metal layer.
  • the chemical mechanical polishing is performed on the conductive metal layer.
  • only the conductive metal layer is polished without polishing the second barrier layer, which simplifies the process flow, improves the production efficiency and reduces the risk of process stability.
  • the bottom electrode of the MRAM is made by the above-mentioned manufacturing method, and the deposited bottom electrode metal prefabricated layer is chemically and mechanically polished to form a bottom electrode metal prefabricated layer with a flat surface. Engraving and etching can obtain the MRAM bottom electrode with a flat surface, which effectively avoids the problem of depression caused by the polishing of the bottom conductive metal layer, and improves the flatness of the bottom electrode.
  • the bottom electrode of the MRAM has better uniformity and is relatively flat, which can ensure better test accuracy and make the performance of the device better.

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Abstract

本公开提供了一种包括MRAM底电极制作工艺的制作方法及MRAM器件，该制作方法包括：提供一基底，基底包括依次设置的金属互联层、第一阻挡层以及介电层，在第一阻挡层和介电层中形成底部通孔；在底部通孔和底部通孔两侧的介电层的裸露表面上依次覆盖第二阻挡层和导电金属层，导电金属层填充满底部通孔；采用化学机械抛光法去除第二阻挡层表面的导电金属层，保留第二阻挡层，底部通孔中形成凹陷；沉积底电极金属，填充满凹陷，形成底电极金属预制层；通过化学机械抛光去除部分底电极金属预制层，形成表面平整的底电极金属预制层；对底电极金属预制层进行光刻、刻蚀，得到MRAM底电极。该制作方法制作的MRAM底电极的均一性较好。

Description

包括MRAM底电极制作工艺的制作方法及MRAM器件
本公开以2019年10月25日递交的、申请号为201911026209.4且名称为“MRAM底电极制作工艺的制作方法及MRAM器件”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体领域，具体而言，涉及一种包括MRAM底电极制作工艺的制作方法及MRAM器件。
背景技术
磁性随机存储器(Magnetic Random Access Memory，MRAM)是一种新型的非易失性存储器，相比于目前其他类型的存储器，具有读写速度快、可实现无限次擦写、易于与目前的半导体工艺相兼容等优点，此外利用自旋流来实现磁矩翻转的自旋传输扭矩(Spin transfer torque，STT)的MRAM可实现存储单元尺寸的微缩。这些优点使得MRAM成为未来新型存储器的主要发展方向。
在MRAM中的主要功能单元为MTJ单元，其结构主要包括磁性自由层/非磁性氧化层(MgO)/磁性钉扎层。在外加磁场或电流等驱动下，磁性自由层的磁矩方向发生翻转，与磁性钉扎层的磁矩方向呈现平行态或反平行态，使得MRAM出现高低电阻态，可分别定义为存储态“0”和“1”，从而实现信息的存储。
在MRAM的制备过程中，其主要功能单元MTJ单元共有十几至二十几层不同的磁性或非磁性的薄膜组成，其中多层薄膜的厚度要求小于1nm甚至几个埃。为了保证MTJ中超薄薄膜生长的连续性，其底电极的平坦化制程就变得极为重要。
在目前的半导体工艺制程中，底电极的制作过程包括：在前道工艺形成金属互联层1上依次沉积第一阻挡层2和介电层3，形成图1所示的结构；然后，再刻蚀介电层3和第一阻挡层2，在金属互联层1上形成底部通孔4，形成图2所示的结构；之后，在之前形成的结构上依次设置第二阻挡层5和导电金属层6，如图3所示；之后，去除底部通孔之外的导电金属层6以及底部通孔两侧的第二阻挡层5，形成图4所示的结构；之后，在之前形成的结构上设置底电极材料7，形成图5所示的结构；最后，刻蚀去除部分的底电极材料，形成图6所示的底电极7’。
上述的工艺中，去除底部通孔之外的导电金属层6以及底部通孔两侧的第二阻挡层5的过程中，首先，抛光去除部分的导电金属材料；然后，抛光去除导电金属材料和第二阻挡层材料，在这个过程中，涉及到三种不同的材料，具体为介电层的材料、第二阻挡层材料以及导电金属材料，由于多种薄膜材料抛光速率不同的工艺局限性，这三种材料同步平坦化的效果较差，在批量生产MRAM时，形成的导电通孔会出现差异较大的表面凹陷的问题，导致制 作的MRAM底电极的均一性较差，测试准确性较差，更为严重的可能造成开路问题，影响良率。
在背景技术部分中公开的以上信息只是用来加强对本文所描述技术的背景技术的理解，因此，背景技术中可能包含某些信息，这些信息对于本领域技术人员来说并未形成在本国已知的现有技术。
发明内容
本公开的主要目的在于提供一种包括MRAM底电极制作工艺的制作方法及MRAM器件，以解决现有技术中难以形成均一性较好的MRAM底电极及底电极开路的问题。
为了实现上述目的，根据本公开的一种包括MRAM底电极制作工艺的制作方法，所述制作方法包括：步骤S1，提供一基底，所述基底包括依次设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层和所述介电层中形成底部通孔；步骤S2，在所述底部通孔和所述底部通孔两侧的所述介电层的裸露表面上依次覆盖第二阻挡层和导电金属层，所述导电金属层填充满所述底部通孔；步骤S3，采用化学机械抛光法去除所述第二阻挡层表面的所述导电金属层，保留所述第二阻挡层，所述底部通孔中形成凹陷；步骤S4，沉积底电极金属，填充满所述凹陷，形成底电极金属预制层；步骤S5，通过化学机械抛光去除部分所述底电极金属预制层，形成表面平整的所述底电极金属预制层；步骤S6，对所述底电极金属预制层进行光刻、刻蚀，得到MRAM底电极。
可选地，所述步骤S3包括：将抛光终点停止在所述第二阻挡层，依据终点检测方法检测到所述第二阻挡层后进行过抛光。
可选地，沉积的所述底电极金属的厚度大于所述凹陷的深度。
可选地，所述底电极金属的材料选自TaN、Ta、TiN和Ti中的任意一种或者多种。
可选地，所述导电金属层的材料选自Cu、W和Al中的任意一种或者多种。
可选地，所述第二阻挡层的材料选自Ta、TaN、Ti、TiN、Co和Ru中的任意一种或者多种。
可选地，所述介电层的材料选自氧化硅SiO、二氧化硅SiO2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、低K介质及超低K介质中的任意一种或者多种。
可选地，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
可选地，在所述步骤S1之前，所述制作方法还包括：形成包括CMOS传感器的基底，所述金属互联层位于所述基底的表面上。
根据本公开的另一方面，提供了一种MRAM器件，包括MRAM底电极，所述MRAM底电极采用任意一种所述制作方法制作而成。
应用本公开的技术方案，上述包括MRAM底电极制作工艺的制作方法中，采用化学机械抛光法去除第二阻挡层表面的导电金属材料，并停止在第二阻挡层，即在导电金属层的化学机械抛光工艺中只对导电金属层进行抛光，而无需对第二阻挡层进行抛光，简化了工艺流程，提高了生产效率并降低了工艺稳定性风险。此外，对沉积的底电极金属预制层进行化学机械抛光，形成一表面平整的底电极金属层，进一步进行光刻和刻蚀，得到表面平整的MRAM底电极，有效避免了底部导电金属层抛光后产生的凹陷问题，提高了底电极的平整度。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1至图6中示出了根据现有技术中的一种实施例中的MRAM的制作过程的结构示意图；
图7至图13示出了本公开的MRAM的制作过程的结构示意图；
其中，上述附图包括以下附图标记：
1、金属互联层；2、第一阻挡层；3、介电层；4、底部通孔；5、第二阻挡层；6、导电金属层；7、底电极材料；7’、底电极；10、金属互联层；20、第一阻挡层；21、刻蚀后的第一阻挡层；30、介电层；31、刻蚀后的介电层；32、底部通孔；40、第二阻挡层；41、刻蚀后的第二阻挡层；50、导电金属层；51、抛光后的导电金属层；60、底电极金属预制层；61、MRAM底电极。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本公开提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本公开所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本公开的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，现有技术中难以形成均一性较好的MRAM底电极，为了解决如上的技术问题，本公开提出了一种包括MRAM底电极制作工艺的制作方法。
本公开的一种典型的实施方式中，提供了一种包括MRAM底电极制作工艺的制作方法，该制作方法包括：
步骤S1，提供一基底，上述基底包括依次设置的金属互联层10、第一阻挡层20以及介电层30，在上述第一阻挡层和上述介电层中形成底部通孔32，如图8所示；
步骤S2，在上述底部通孔32和上述底部通孔32两侧的上述介电层的裸露表面上依次覆盖第二阻挡层40和导电金属层50，上述导电金属层50填充满上述底部通孔32，如图9所示；
步骤S3，采用化学机械抛光法去除上述第二阻挡层表面的上述导电金属层，保留上述第二阻挡层40，上述底部通孔32中形成凹陷，如图10所示；
步骤S4，沉积底电极金属，填充满上述凹陷，形成底电极金属预制层60，如图11所示；
步骤S5，通过化学机械抛光去除部分上述底电极金属预制层60，形成表面平整的底电极金属预制层60，如图12所示；
步骤S6，对上述底电极金属预制层进行光刻、刻蚀，得到MRAM底电极61，如图13所示。
上述制作方法中，采用化学机械抛光法去除第二阻挡层表面的导电金属材料，并停止在第二阻挡层，即在导电金属层的化学机械抛光工艺中只对导电金属层进行抛光，而无需对第二阻挡层进行抛光，简化了工艺流程，提高了生产效率并降低了工艺稳定性风险。此外，对沉积的底电极金属预制层进行化学机械抛光，形成一表面平整的底电极金属层，进一步进行光刻和刻蚀，得到表面平整的MRAM底电极，有效避免了底部导电金属层抛光后产生的凹陷问题，提高了底电极的平整度。
为了防止导电金属层扩散至介电层中，进一步保证器件的性能较好，本公开的一种实施例中，上述步骤S1之前包括：在上述金属互联层10的裸露表面上设置第一阻挡层20；在上述第一阻挡层20远离上述金属互联层的表面上设置介电层30，如图8所示，上述步骤S1中还包括：刻蚀去除部分上述第一阻挡层20和部分上述介电层，形成底部通孔32，剩余的上述第一阻挡层形成刻蚀后的第一阻挡层21，剩余的上述介电层形成刻蚀后的介电层31，如图9所示。
本公开的一种实施例中，上述步骤S3包括：将抛光终点停止在上述第二阻挡层，依据终点检测方法检测到上述第二阻挡层后进行过抛光。上述方法对导电金属层进行抛光直至暴露出第二阻挡层，然后进一步对第二阻挡层进行过抛光，从而可以完全去除位于底部通孔两侧的上述第二阻挡层表面的导电金属层。
本公开的一种实施例中，沉积的上述底电极金属的厚度大于上述凹陷的深度。上述设置使得底电极金属充满上述凹陷，从而便于对底电极金属进行抛光形成表面平整的MRAM底电极。
本公开中的第一阻挡层的材料为任意可以阻挡金属材料扩散至介电层中的材料，本领域技术人员可以根据实际情况选择合适的材料作为第一阻挡层的材料，比如氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅等材料。
可选地，MRAM可以包括多个MTJ器件，每一个MTJ器件对应一个金属互联层，本公开的一种实施例中，上述金属互联层包括多个间隔的金属互联层，上述底部通孔对应地与上述金属互联层抵接。
本公开的又一种图中未示出的实施例中，上述制作方法还包括：在上述底电极的表面上依次设置自由层、参考层、绝缘势垒层以及顶电极。上述制作方法中，金属导线部上形成的底电极、自由层、参考层、绝缘势垒层和顶电极共同构成MTJ器件，当然，MTJ器件还可以包括其他的结构层，本领域技术人员可以根据实际情况选择其他合适的结构层，例如，钉扎层。
本公开的一种实施例中，上述导电金属层的材料选自Cu、W和Al中的任意一种或者多种。
为了能够选择更高选择比的研磨液，更好地控制底电极金属预制层的抛光过程，进而保证MRAM的均匀性，且同时保证MRAM底电极的导电性能，本公开的一种实施例中，上述底电极材料选自Ta、TaN、Ti、TiN中的任意一种或者多种。
为了进一步降低上述步骤S6的刻蚀难度，使得该制作方法更加高效，本公开中的一种具体的实施例中，上述底电极材料与上述第二阻挡材料相近。上述制作方法可以降低制作底电极的刻蚀难度，从而提高MRAM的制作的效率。具体地，上述第二阻挡层的材料选自Ta、TaN、Ti、TiN、Co和Ru中的任意一种或者多种。
为了保证介电层的绝缘性能，本公开的一种实施例中，上述介电层的材料选自氧化硅、二氧化硅、碳氧化物、氮化硅、氟硅玻璃、磷硅玻璃、硼磷硅玻璃和正硅酸乙酯、超低K介质及超低K介质中的任意一种或者多种。
本公开的又一种实施例中，在上述步骤S1之前，上述制作方法还包括：形成包括CMOS传感器的基底，上述金属导线层位于上述基底的表面上。当然，该基底中还包括一些其他在前道制程中形成的结构。
本公开的又一种实施例中，上述金属互联层的材料为Cu。Cu的电阻较低，可明显降低电阻电容延迟(RC delay)效应。
当然，本公开的金属互联层的材料并不限于Cu，还可以为其他的合适材料，本领域技术人员可以根据实际情况选择合适的金属材料形成金属互联层。
申请中的另一种典型的实施方式中，提供了一种MRAM器件，上述MRAM器件采用上述的任一种的制作方法制作而成。
由于采用上述的制作方法制作而成，该MRAM底电极的均一性较好且较为平坦，可以保证较好的测试准确性，使得器件的性能更好。
为了使得本领域技术人员能够更加清楚地了解本公开的技术方案，以下将结合具体的实施例来说明本公开的技术方案。
实施例
包括MRAM底电极的制作工艺的制作过程包括：
形成包括CMOS传感器的基底，基底包括依次设置的金属互联层10、第一阻挡层20(NBlock)和介电层30(TEOS)，金属互联层10包括多个间隔的金属互联层单元，图7中只示出了一个金属互联层单元；
刻蚀去除部分介电层30和第一阻挡层20，在各金属互联层10的表面上形成底部通孔32，剩余的介电层形成刻蚀后的介电层31，剩余的第一阻挡层形成刻蚀后的第一阻挡层21，如图8所示；
在底部通孔32以及其两侧的介电层的裸露表面上依次设置第二阻挡层40(TaN/Ta)和导电金属层50(Cu)，导电金属层50覆盖底部通孔32两侧的且位于介电层表面上的上述第二阻挡层40，如图9所示；
采用化学机械抛光法去除部分导电金属层50，直至底部通孔32两侧的第二阻挡层40的裸露，剩余的位于底部通孔32中的导电金属层50形成抛光后的导电金属层51，如图10所示；
在抛光后的导电金属层51以及其两侧的第二阻挡层40的裸露表面上沉积底电极金属，形成底电极金属预制层60(TaN)，如图11所示；
采用化学机械抛光法去除部分底电极金属预制层60，直至底电极金属预制层60的远离底部通孔32的表面为平整表面，如图12所示；
采用刻蚀法去除底部通孔32两侧的部分底电极金属预制层60和至少部分第二阻挡层40，使得部分介电层裸露，剩余的底电极金属形成MRAM底电极61，剩余的上述第二阻挡层形成刻蚀后的第二阻挡层41，如图13所示。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
1)、本公开的包括MRAM底电极制作工艺的制作方法中，采用化学机械抛光法去除第二阻挡层表面的导电金属材料，并停止在第二阻挡层，即在导电金属层的化学机械抛光工艺中只对导电金属层进行抛光而无需对第二阻挡层进行抛光，简化了工艺流程，提高了生产效率并降低了工艺稳定性风险。
2)、本公开的MRAM器件中，MRAM底电极由于采用上述的制作方法制作而成，对沉积的底电极金属预制层进行化学机械抛光，形成一表面平整的底电极金属预制层，进一步进行光刻和刻蚀，得到表面平整的MRAM底电极，有效避免了底部导电金属层抛光后产生的凹陷问题，提高了底电极的平整度。该MRAM底电极的均一性较好且较为平坦，可以保证较好的测试准确性，使得器件的性能更好。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种包括MRAM底电极制作工艺的制作方法，其特征在于，所述制作方法包括：
    步骤S1，提供一基底，所述基底包括依次设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层和所述介电层中形成底部通孔；
    步骤S2，在所述底部通孔和所述底部通孔两侧的所述介电层的裸露表面上依次覆盖第二阻挡层和导电金属层，所述导电金属层填充满所述底部通孔；
    步骤S3，采用化学机械抛光法去除所述第二阻挡层表面的所述导电金属层，保留所述第二阻挡层，所述底部通孔中形成凹陷；
    步骤S4，沉积底电极金属，填充满所述凹陷，形成底电极金属预制层；
    步骤S5，通过化学机械抛光去除部分所述底电极金属预制层，形成表面平整的底电极金属预制层；
    步骤S6，对所述底电极金属预制层进行光刻、刻蚀，得到MRAM底电极。
  2. 根据权利要求1所述的制作方法，其特征在于，所述步骤S3包括：将抛光终点停止在所述第二阻挡层，依据终点检测方法检测到所述第二阻挡层后进行过抛光。
  3. 根据权利要求1所述的制作方法，其特征在于，沉积的所述底电极金属的厚度大于所述凹陷的深度。
  4. 根据权利要求1所述的方法，其特征在于，所述底电极金属的材料选自TaN、Ta、TiN和Ti中的任意一种或者多种。
  5. 根据权利要求1所述的方法，其特征在于，所述导电金属层的材料选自Cu、W和Al中的任意一种或者多种。
  6. 根据权利要求1所述的方法，其特征在于，所述第二阻挡层的材料选自Ta、TaN、Ti、TiN、Co和Ru中的任意一种或者多种。
  7. 根据权利要求1所述的方法，其特征在于，所述介电层的材料选自氧化硅、二氧化硅、碳氧化物、氮化硅、氟硅玻璃、磷硅玻璃、硼磷硅玻璃、正硅酸乙酯、低K介质及超低K介质中的任意一种或者多种。
  8. 根据权利要求1所述的方法，其特征在于，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
  9. 根据权利要求1至8中任一项所述的制作方法，其特征在于，在所述步骤S1之前，所述制作方法还包括：
    形成包括CMOS传感器的基底，所述金属互联层位于所述基底的表面上。
  10. 一种MRAM器件，其特征在于，所述MRAM器件采用权利要求1至9中任一项所述的制作方法制作而成。
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