WO2012041085A1 - 一种具有低k介质绝热材料的相变存储器结构及制备方法 - Google Patents

一种具有低k介质绝热材料的相变存储器结构及制备方法 Download PDF

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WO2012041085A1
WO2012041085A1 PCT/CN2011/076309 CN2011076309W WO2012041085A1 WO 2012041085 A1 WO2012041085 A1 WO 2012041085A1 CN 2011076309 W CN2011076309 W CN 2011076309W WO 2012041085 A1 WO2012041085 A1 WO 2012041085A1
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low
phase change
dielectric
change memory
layer
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PCT/CN2011/076309
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French (fr)
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宋志棠
吴良才
封松林
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中国科学院上海微系统与信息技术研究所
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Priority to US13/202,955 priority Critical patent/US8722455B2/en
Publication of WO2012041085A1 publication Critical patent/WO2012041085A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention relates to a phase change memory structure and a method of fabricating the same, and more particularly to a phase change memory using a low-k dielectric material as a heat insulating material.
  • the structure and corresponding preparation methods belong to the field of special devices and processes in microelectronics.
  • phase change memory based on a sulfur-based semiconductor material
  • CMOS Complementary Metal-Oxide-Semiconductor
  • the outstanding advantages of circuit process compatibility have attracted worldwide attention. Reducing current and power consumption, improving data retention and reliability of phase change materials is one of the most important research directions at present.
  • Major companies around the world have successively invested in the research of phase change memory.
  • the main research units are Ovonyx and Inte l. Samsung. IBM. Bayer. ST Mi cron. AMD. Panasonic . Sony. Phi l ips . Br iti sh Areospace . H i tachi and Macronix et al.
  • phase change memory Reducing power consumption, increasing data retention and reliability can be improved in both material and device architecture.
  • the improvement of device structure is also diverse.
  • the structure of phase change memory is roughly divided into classic "mushroom" structure, ⁇ -Trench structure, Pore structure, GST confinement structure, edge contact structure, quantum wire structure, GST. Side wall structure, etc.
  • the key to the structure of the classic T-shape is the preparation method of the bottom heating electrode. The reduction of the operating area of this structure can only be achieved by reducing the bottom electrode, thereby achieving the purpose of reducing the operating voltage and reducing the power consumption.
  • the purpose of various structures is to reduce the contact area between the electrode and the phase change material, thereby achieving a reduction in the reversible phase change region of set and reset, thereby achieving the purpose of reducing current and power consumption.
  • There are two methods for reducing the phase change operation region which are to reduce the size of the phase change material and reduce the size of the heating electrode, and simultaneously pass the electrode.
  • the dielectric transition layer between the phase change material and the heat diffusion that effectively prevents the reversible phase transition process is also an effective way to achieve low voltage and low power consumption.
  • CMOS circuits ⁇ . . , . , , , . , . ⁇ , .
  • low k (low-k) material Use low k (low-k) material.
  • ⁇ interlayer dielectrics can reduce parasitic capacitance and reduce signal crosstalk, thus allowing the distance between interconnects to be closer, further improving chip integration.
  • using low-k dielectric material shortens the signal propagation delay, which is beneficial to increase the chip speed.
  • a phase change memory structure having a low-k dielectric insulating material comprising a substrate and a phase change memory cell array comprising a plurality of phase change memory cells over the substrate;
  • each of the phase change memory units comprises:
  • a heating electrode located above the diode
  • a reversible phase change resistance located above the heating electrode
  • a top electrode located above the reversible phase change resistor
  • a low-k dielectric insulation layer is wrapped around the heating electrode and the reversible phase change resistor
  • the substrate may be a conventional Si substrate, or may be a SOI substrate or other semiconductor material as a substrate.
  • the heating electrode is not limited, and may be a commonly used conductor material such as W or Pt, or other conductive materials such as TiN, TiW, TiAIN, etc., thereby improving the heating effect and reducing the operating current.
  • the low-k dielectric insulation layer uses low-k dielectric materials, including: low-k doped oxides, low-k organic polymers, and low-k porous materials.
  • the low-k dielectric insulating layer is made of fluorine-doped silicon oxide (S iOF ), porous carbon-doped silicon oxide (S iOC ), spin-on organic polymer medium, spin-on silicone-based polymer medium, and porous S iLK or porous silica or the like.
  • the top electrode is not limited, and may be a common conductor material such as Al, W, or Cu, or may be , m ., T
  • the anti-diffusion medium layer can be made of a nitride material such as SiN, SiON or the like or an oxide material such as Ta 2 0 5 , A1 2 0 3 , Zr0 2 , etc., which can effectively prevent the diffusion of the phase change material. Enhance the adhesion of phase change materials and improve the heating effect and reliability of phase change materials.
  • the reversible phase change resistor is made of a phase change material GeSbTe, SiSbTe, or GeSbTe doped with Sn, Ag, N or the like, or SiSbTe doped with Sn, Ag, N or the like.
  • the present invention also provides a method for fabricating a phase change memory structure having the above-described low-k dielectric insulation material, comprising the following steps:
  • the first low-k dielectric insulation layer and the second low-k dielectric insulation layer are prepared, and the low-k dielectric material is used, including: low-k doped oxide, low-k organic polymer, and low-k porous material. . . , , . , , _ . .
  • the first hole and the second hole may be formed by a method such as focused ion beam or electron beam exposure and reactive ion etching.
  • the anti-diffusion dielectric layer is prepared by an ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition) method.
  • ALD Atomic Layer Deposition
  • CVD Chemical Vapor Deposition
  • the CMP process used in the step (7) has a polishing pressure of 0.5 ps i or less, and the second low-k dielectric insulating layer and the phase change material are polished using a colloidal silica polishing solution, and the phase change material and the polishing liquid are used.
  • the high selectivity of low-k dielectrics (“60: 1") and low damage to low-k dielectrics (low corrosion, stable film, constant volume, and no change in thermomechanical properties of the film) enable polishing of phase change materials and retention The second low-k dielectric insulation layer.
  • phase change memory structure and the preparation method for the low-k dielectric insulation material provided by the invention utilize low-k dielectric material as the heat insulation material of the phase change memory in the regions other than the heating electrode and the phase change resistor, and skillfully utilize the low-k dielectric material.
  • the characteristics of the device improve the performance of the phase change memory.
  • Low-k dielectric materials are often used as interlayer dielectrics in CMOS circuits due to their low dielectric constant. They can reduce parasitic capacitance, reduce signal crosstalk, improve chip integration, shorten signal propagation delay, and improve chips. Speed and other effects.
  • low-k dielectric materials generally have a porous structure, a softer texture and a lower thermal conductivity, which are difficult for low-k dielectric materials in CMOS applications.
  • the present invention utilizes these characteristics of the low-k dielectric material, and uses the low-k dielectric material as the thermal insulation material of the phase change memory, thereby avoiding the thermal crosstalk between the phase change memory cells and the mutual influence during operation.
  • the influence of the pressure caused by the volume change of the phase change material on the memory cell can be reduced, the reliability of the device is improved, and the temperature at the amorphous to polycrystalline transition is eliminated. , pressure, etc. on the PCRAM data retention.
  • the soft structure and permeability of the low-k dielectric material in order to prevent the diffusion of elements in the phase change material such as GST into the low-k dielectric material, a non-diffusion is prepared between the low-k dielectric material and the phase change material. Medium layer.
  • the diode switch or peripheral circuit is prepared by a standard CMOS process, reversible phase . . . , , . _ ⁇ ⁇ . . ⁇ . . , ⁇ , Blocking the field ⁇ ⁇ real completion system, does not affect the CMOS standard work.
  • the meta-marking, low-pressure and low-corrosion CMP process avoids damage to the device caused by the polishing process.
  • FIG. 6 are schematic diagrams showing the process flow of preparing a phase change memory structure in the embodiment, and the phase change memory structure finally completed is shown in FIG. 6, wherein each reference numeral is as follows:
  • a phase change memory structure having a low-k dielectric thermal insulation material includes a substrate 1 and a phase change memory cell composed of a plurality of phase change memory cells on the substrate 1.
  • Array Typically, a phase change memory cell consists of a reversible phase change resistor and a diode. The reversible phase change resistor achieves its reversible transition between amorphous (high resistive state) and polycrystalline (low resistive state) by heating the electrode.
  • the phase change memory unit comprises: a diode 2; a heating electrode 4 located above the diode 2; a reversible phase change resistor 7 located above the heating electrode 4; a top electrode 8 located above the reversible phase change resistor 7; A first low-k dielectric insulating layer 3 and a second low-k dielectric insulating layer 5 are wrapped around the heating electrode 4 and the reversible phase change resistor 7, respectively; and a second low-k dielectric insulating layer 5 at and around the reversible phase change resistor 7 An anti-diffusion medium layer 6 is provided between them.
  • the substrate 1 may be a commonly used Si substrate, or may be a SOI substrate or other semiconductor material as a substrate.
  • the heating electrode 4 is not limited, and may be a commonly used conductor material such as W or Pt. , , , . , m ., ⁇ m ., ' ⁇ m . , , ⁇ , , resort _ , . lc ) are the spears of the soldiers, such as TiN, Til TiAIN, so that the force is hot, I3 ⁇ 4H ⁇ operating current.
  • the top electrode 8 is not limited, and may be a commonly used conductor material such as Al, W, Cu, or other conductive materials such as TiN.
  • the first low-k dielectric insulation layer 3 and the second low-k dielectric insulation layer 5 use low-k dielectric materials, including: low-k doped oxide, low-k organic polymer, and low-k porous material.
  • the first low-k dielectric insulating layer 3 and the second low-k dielectric insulating layer 5 are doped with fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), spin-coated organic polymer medium, and spin-coated organic A silicon-based polymer medium, porous SiLK or porous silicon oxide, or the like.
  • low-k dielectric materials have a porous structure, a softer texture and a lower thermal conductivity, and are used as thermal insulation materials for phase change memories to avoid thermal crosstalk between phase change memory cells and interactions during operation.
  • the influence of the pressure caused by the volume change of the phase change material on the memory cell can be reduced, the reliability of the device is improved, and the temperature at the amorphous to polycrystalline transition is eliminated. , pressure, etc. on the PCRAM data retention.
  • the anti-diffusion dielectric layer 6 can be made of a nitride material such as SiN, SiON or the like or an oxide material such as Ta 2 0 5 , A1 2 0 3 , Zr0 2 , etc., which can effectively prevent the phase change material (reversible phase change)
  • the diffusion of the resistor 7) enhances the adhesion of the phase change material and improves the heating effect and reliability of the phase change material.
  • a method for fabricating a phase change memory structure having a low-k dielectric insulation material includes the following steps:
  • a diode array composed of a plurality of diodes 2 is fabricated on a substrate 1 by a standard CMOS process, and is used as a switch of a phase change memory cell array, having a size of 100-1000, wherein the substrate 1 using a Si substrate;
  • a layer of 100-500 thick first low-k dielectric insulating layer 3 is deposited on the diode array by M0CVD (Metal Organic Chemical Vapor Deposition) technique;
  • the heating electrode 4 is as shown in FIG. 3;
  • the nanopore is prepared by electron beam etching on the 50-200 thick second low-k dielectric insulating layer 5, and the bottom of the hole is connected to the upper end of the W electrode, and the diameter of the hole is in the range of 50 nm to 500 nm, as shown in the figure. 4;
  • phase change material GeSbTe magnetron sputtering phase change material GeSbTe, a thickness of about 100 nm, the base pressure is 3X10- 6 Torr, sputtering vacuum to 0.08 Pa, power 100 W, forming a reversible phase change resistor 7;
  • a GeSbTe thin film in a region other than the hole is thrown by CMP, and then a top electrode 8 of A1 is prepared, thereby obtaining a phase change memory device unit of a 1D1R structure on the Si substrate, as shown in Fig. 6.
  • the SiN film of the first step (8) of Example 1 was changed to a SiON film having a thickness of 5 to 20, and the same results as in Example 1 were obtained.
  • the heating electrode W of Example 1 was replaced with TiN or other higher resistivity material, and the same as in Example 1, better results than in Example 1.
  • Embodiment 1 is replaced with a substrate of a SOI substrate or other semiconductor material, and the same as in Embodiment 1, the result similar to that of Embodiment 1 can be obtained, even in some properties such as anti-irradiation, improve.
  • phase change material GeSbTe of the first embodiment is replaced with SiSbTe, or replaced with GeSbTe doped with Sn, Ag, N or the like and SiSbTe doped with Sn, Ag, N or the like.
  • the other steps are the same as those in the first embodiment. This results in better device performance, such as lowering the operating current of the device or increasing the speed of the device.
  • Other process conditions involved in the present invention are conventional process conditions and are well known to those skilled in the art. Any technical solution that does not depart from the spirit and scope of the present invention should be covered by the scope of the patent application of the present invention.

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Description

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一肝具 低 k介质绝热材料的相变存储器结构及制薈万法 技术领域 本发明涉及一种相变存储器结构及制备方法， 特别涉及一种釆用低 k介 质材料作为绝热材料的相变存储器结构及相应的制备方法， 属于微电子学中 特殊器件与工艺领域。
背景技术 在目前的新型存储技术中， 基于硫系半导体材料的相变存储器 （PCRAM ) 具有成本低， 速度快， 存储密度高， 制造简单且与当前的 CMOS (互补金属- 氧化物-半导体）集成电路工艺兼容性好的突出优点， 受到世界范围的广泛关 注。 降低电流和功耗、 提高数据保持力和相变材料的可靠性是目前最主要的 研究方向之一， 全世界各大公司相继投入了相变存储器的研究行列， 主要研 究单位有 Ovonyx、 Inte l . Samsung . IBM. Bayer . ST Mi cron. AMD. Panasonic . Sony. Phi l ips . Br i t i sh Areospace . H i tachi和 Macronix等。
降低功耗、 提高数据保持力和可靠性可以从材料和器件结构两个方面进 行改善。 其中， 器件结构方面的改善方法也是多种多样的， 相变存储器的结 构大致分为经典 "蘑菇型"结构、 μ - Trench结构、 Pore结构、 GST限制结构、 边缘接触结构、 量子线结构、 GST侧墙结构等。 经典 T-shape的结构关键在于 底部加热电极的制备方法， 此种结构的操作区域的减小只能通过缩小底部电 极的方法来实现， 从而达到降低操作电压和降低功耗的目的。 各种结构的目 的都是为了减小电极和相变材料的接触区域， 从而实现 set与 reset的可逆 相变区域的减小， 达到降低电流和功耗的目的。 相变区域的减小与操作电流 的降低呈现明显的线性关系， 减小相变操作区域的方法大致有两种， 分别为 减小相变材料的尺寸和减小加热电极的尺寸， 同时通过电极与相变材料间的 介质过渡层， 有效阻止可逆相变过程的热量扩散也是实现低压、 低功耗的有 效途径。
此外， 随着集成电路技术和 CMOS工艺朝 45nm以及 22讓发展， CMOS电路 . ^ . . , . , , , , . , . ^ , .
吏用低 k( low— k ) 材 。使用 low— k 材f亍 丄 LIU丄 nter Layer Die lectr ics , 层间电介质）， 可以减少寄生电容容量， 降低信号串扰， 这样就允许互连线之间的距离更近， 进一步提高芯片的集成度， 同时使用 low-k介质材料缩短了信号传播延时， 有利于提高芯片速度。 发明内容 本发明的目的在于提供一种具有低 k介质绝热材料的相变存储器结构及 制备方法。
为了达到上述目的及其他目的， 本发明釆用如下技术方案：
一种具有低 k介质绝热材料的相变存储器结构， 包括衬底以及位于所述 衬底之上的由多个相变存储单元组成的相变存储单元阵列；
其中， 每个所述相变存储单元包括：
一个二极管；
位于所述二极管之上的加热电极；
位于所述加热电极之上的可逆相变电阻；
位于所述可逆相变电阻之上的顶电极；
在所述加热电极和可逆相变电阻周围包裹有低 k介质绝热层；
在所述可逆相变电阻与其周围的低 k介质绝热层之间设有防扩散介质层。 较佳的， 所述衬底可以是常用的 S i衬底， 也可以是 S0I衬底或其他半导 体材料作为衬底。
所述加热电极不受限制， 可以是 W、 Pt 等常用的导体材料， 也可以是其 它的导电材料， 如 TiN 、 TiW、 TiAIN等， 从而提高加热效果， 降低操作电流。
所述低 k介质绝热层釆用低 k介质材料， 包括： 低 k的掺杂氧化物、 低 k 的有机聚合物和低 k的多孔材料。 优选的， 所述低 k介质绝热层釆用氟掺杂 氧化硅（S iOF ) 、 多孔碳掺杂氧化硅（S iOC ) 、 旋涂有机聚合物介质、 旋涂 有机硅基聚合物介质、 多孔 S iLK或多孔氧化硅等。
所述顶电极不受限制， 可以是 Al、 W、 Cu等常用的导体材料， 也可以是 , m .、T
的矛¾符 ， p TiN寺。
较佳的， 所述防扩散介质层可釆用氮化物材料如 SiN、 SiON等或氧化物 材料如 Ta205、 A1203、 Zr02等， 可有效地防止相变材料的扩散， 增强相变材料 的附着力， 提高相变材料的加热效果和可靠性。
较佳的， 所述可逆相变电阻釆用相变材料 GeSbTe、 SiSbTe, 或者 Sn、 Ag、 N等掺杂的 GeSbTe, 或者 Sn、 Ag、 N等掺杂的 SiSbTe。
此外， 本发明还提供一种上述具有低 k介质绝热材料的相变存储器结构 的制备方法， 包括如下步骤：
( 1 ) 利用标准的 CMOS工艺制备二极管阵列；
(2) 在二极管阵列上制备 50 nm-1000 讓厚的第一低 k介质绝热层；
( 3) 在第一低 k介质绝热层上分别形成多个直径为 30-300讓的第一 孔洞， 每个第一孔洞的底部与二极管阵列的每个二极管顶端相 连；
( 4 ) 在上述孔洞内填充加热电极材料，接着进行 CMP (化学机械抛光） 工艺， 除去表面多余的加热电极材料， 形成柱状加热电极阵列；
( 5 ) 在柱状加热电极阵列上制备 50 nm-200 nm厚的第二低 k介质绝 热层； 在第二低 k介质绝热层上分别形成多个直径为 50-500 讓 的第二孔洞， 每个第二孔洞的底部与柱状加热电极阵列中的每个 柱状加热电极顶端相连；
(6) 在第二孔洞中制备 1-30 讓厚的防扩散介质层；
(7) 在制备了防扩散介质层的第二孔洞内接着填充相变材料， 然后进 行 CMP工艺， 除去表面多余的相变材料， 形成柱状可逆相变电阻 阵列；
( 8 ) 在柱状可逆相变电阻阵列上形成一层电极材料；
( 9 ) 利用光刻和湿法刻蚀形成相变存储单元阵列的顶电极。
优选地， 制备所述第一低 k介质绝热层和第二低 k介质绝热层， 釆用低 k 介质材料， 包括： 低 k的掺杂氧化物、 低 k的有机聚合物和低 k的多孔材料。 . . , , . , , _ . . . , , >, ^ ,, , 优远的， 还弟一低 k 绝热层和 二低 k 绝热 禾用 爹 轧化硅 ( S iOF ) 、 多孔碳掺杂氧化硅（S iOC ) 、 旋涂有机聚合物介质、 旋涂有机硅 基聚合物介质、 多孔 S iLK或多孔氧化硅等材料。
优选地， 所述第一孔洞和第二孔洞可以用聚焦离子束或电子束曝光和反 应离子刻蚀法等方法形成。
优选地， 所述防扩散介质层利用 ALD (原子层沉积）或 CVD (化学气相沉 积）方法制备。
优选地， 步骤（7 )所用的 CMP工艺， 抛光压力在 0. 5ps i 以下， 使用胶 体氧化硅抛光液对第二低 k介质绝热层和相变材料进行抛光， 利用抛光液对 相变材料和低 k介质的高选择比（》 60: 1)以及对低 k介质的低损伤（低腐蚀， 薄膜稳定、 体积不变以及不改变薄膜热机械性质） ， 可实现相变材料的抛光 以及停留在第二低 k介质绝热层。
本发明提供的具有低 k介质绝热材料的相变存储器结构及制备方法， 在 加热电极和相变电阻以外区域利用了低 k介质材料作为相变存储器的绝热材 料， 巧妙的利用了低 k介质材料的特性， 提高了相变存储器的器件性能。
低 k介质材料由于具有较低的介电常数， 在 CMOS电路中常被用作为层间 电介质， 可以起到减少寄生电容容量， 降低信号串扰， 提高芯片的集成度， 缩短信号传播延时， 提高芯片速度等作用。 然而， 通常低 k介质材料具有多 孔结构， 质地较软密度较低， 热传导性能较差， 这些特点为低 k介质材料在 CMOS中的应用带来一定难度。而本发明正是利用了低 k介质材料的这些特点， 以低 k介质材料作为相变存储器的绝热材料， 避免了相变存储单元之间的热 串扰及操作时的相互影响。 同时由于低 k介质材料的可伸缩性， 可以减小相 变材料相变过程中体积变化所引起的压力对存储单元的影响， 提高了器件的 可靠性， 消除了非晶向多晶转变时温度、 压力等对 PCRAM数据保持力的影响。 此外， 由于低 k介质材料的松软结构和易渗透性， 为了防止 GST等相变材料 中的元素向低 k介质材料的扩散， 在低 k介质材料与相变材料之间制备了一 层防扩散介质层。
在制造工艺上， 二极管开关或外围电路由标准的 CMOS工艺制备， 可逆相 . . . , , . _^ Θ . . ^ . ., ^ , 阻田^ ^实的 疋工 制 ， 不影响 CMOS标 工 。 抛元盯， 禾用低压力 与低腐蚀的 CMP工艺， 避免了抛光工艺对器件造成的损伤。
附图说明
图 1至图 6为实施例中制备相变存储器结构的工艺流程示意图， 最终完 成的相变存储器结构如图 6所示， 其中， 各附图标记说明如下：
1.衬底； 2.二极管； 3. 第一低 k介质绝热层； 4.加热电极； 5. 第二低 k介质绝热层； 6.防扩散介质层； 7.可逆相变电阻； 8. 顶电极
具体实施方式 下面结合图示更完整的描述本发明， 本发明提供优选的实施例， 不应被 认为仅限于在此阐述的实施例中。 在图中， 为了更清楚的反应结构， 适当放 大了层和区域的厚度， 但作为示意图不应该被认为严格反映了几何尺寸的比 例关系， 图中的表示只是示意性质的， 不应该被认为限制本发明的范围。
请参见图 6 ,本发明提供的一种具有低 k介质绝热材料的相变存储器结构， 包括衬底 1 以及位于所述衬底 1之上的由多个相变存储单元组成的相变存储 单元阵列。 通常， 相变存储单元由一个可逆相变电阻和一个二极管构成。 可 逆相变电阻通过加热电极操作实现其在非晶（高阻态）与多晶（低阻态）之间的 可逆转变。 本发明提供的相变存储单元包括： 一个二极管 2 ; 位于二极管 2之 上的加热电极 4 ; 位于加热电极 4之上的可逆相变电阻 7 ; 位于可逆相变电阻 7之上的顶电极 8 ; 在加热电极 4和可逆相变电阻 7周围分别包裹有第一低 k 介质绝热层 3和第二低 k介质绝热层 5 ;在可逆相变电阻 7与其周围的第二低 k介质绝热层 5之间设有防扩散介质层 6。
其中， 衬底 1可以是常用的 S i衬底， 也可以是 S0I衬底或其他半导体材 料作为衬底。 加热电极 4不受限制， 可以是 W、 Pt等常用的导体材料， 也可 , , , . , m .、τ m .，'Γ m . , 、τ , ,„ _ , . lc) 以足兵 的矛 ¾材 ， 如 TiN 、 Til TiAIN , 从而提 ^ 力口热双禾， I¾H氐操 作电流。 顶电极 8不受限制， 可以是 Al、 W、 Cu等常用的导体材料， 也可以 是其它的导电材料， 如 TiN等。
第一低 k介质绝热层 3和第二低 k介质绝热层 5釆用低 k介质材料， 包 括： 低 k的掺杂氧化物、 低 k的有机聚合物和低 k的多孔材料。 优选的， 第 一低 k介质绝热层 3和第二低 k介质绝热层 5釆用氟掺杂氧化硅（ SiOF ) 、 碳掺杂氧化硅（SiOC ) 、 旋涂有机聚合物介质、 旋涂有机硅基聚合物介质、 多孔 SiLK或多孔氧化硅等。 这些低 k介质材料具有多孔结构， 质地较软密度 较低， 热传导性能较差， 作为相变存储器的绝热材料， 避免了相变存储单元 之间的热串扰及操作时的相互影响。 同时由于低 k介质材料的可伸缩性， 可 以减小相变材料相变过程中体积变化所引起的压力对存储单元的影响， 提高 了器件的可靠性， 消除了非晶向多晶转变时温度、 压力等对 PCRAM数据保持 力的影响。
较佳的， 防扩散介质层 6可釆用氮化物材料如 SiN、 SiON等或氧化物材 料如 Ta205、 A1203、 Zr02等， 可有效地防止相变材料（可逆相变电阻 7 )的扩散， 增强相变材料的附着力， 提高相变材料的加热效果和可靠性。
实施例 1:
参见图 1-图 6, 一种上述具有低 k介质绝热材料的相变存储器结构的制 备方法， 包括如下步骤：
( 1 ) 如图 1所示，利用标准的 CMOS工艺在衬底 1上制备由多个二极管 2 构成的二极管阵列， 用作相变存储单元阵列的开关， 尺寸在 100-1000讓， 其 中衬底 1釆用 Si衬底；
( 2 ) 如图 2所示， 利用 M0CVD (金属有机化学气相沉积）技术在二极管 阵列上淀积一层 100 -500 讓厚的第一低 k介质绝热层 3;
( 3 ) 在上述 100 -500讓厚的第一低 k介质绝热层 3上利用电子束刻蚀 技术制备纳米孔洞， 孔洞底部与二极管 1上端相连， 孔洞直径在 100 -300讓 范围；
( 4 ) 利用 CVD技术在上述孔洞里淀积 W薄膜， 直至孔洞填满； 成加热电极 4如图 3所示；
( 6 ) 利用 MOCVD技术在 W电极上淀积一层 50-200 nm厚的第二低 k介质 绝热层 5;
( 7 ) 在上述 50-200讓厚的第二低 k介质绝热层 5上利用电子束刻蚀技 术制备纳米孔洞， 孔洞底部与 W电极上端相连， 孔洞直径在 50 nm-500 nm范 围， 如图 4所示；
( 8 ) 利用 PECVD技术在上述孔洞里淀积 SiN薄膜，厚度 5-20讓，作为防 扩散介质层 6;
(9) 磁控溅射相变材料 GeSbTe, 厚度约 100 nm, 本底真空为 3X10— 6 Torr, 溅射真空为 0.08 Pa, 功率 100 W, 形成可逆相变电阻 7;
( 10) 利用 CMP抛除孔洞以外区域的 GeSbTe薄膜， 接着制备 A1顶电 极 8, 从而得到 Si衬底上的 1D1R结构的相变存储器器件单元， 如图 6所示。
实施例 2:
将实施例 1第 （ 8 )步 SiN薄膜换成厚度 5-20讓左右的 SiON薄膜， 其它 同实施例 1, 也可以得到与实施例 1类似的结果。
实施例 3:
将实施例 1的加热电极 W换成 TiN或其它更高电阻率的材料， 其它同实 施例 1, 可以得到比实施例 1更好的结果。
实施例 4:
将实施例 1的 Si衬底换成 S0I衬底或其它半导体材料的衬底， 其它同实 施例 1, 可以得到类似实施例 1的结果， 甚至在某些性能， 如抗辐照方面， 有 所提高。
实施例 5:
将实施例 1的相变材料 GeSbTe换成 SiSbTe, 或者换成 Sn、 Ag、 N等掺杂 的 GeSbTe和 Sn、 Ag、 N等掺杂的 SiSbTe, 其它步骤同实施例 1。 这样可以得 到更好的器件性能， 如降低器件的操作电流或提高器件速度等。 本发明中涉及的其他工艺条件为常规工艺条件， 属于本领域技术人员熟 案。 任何不脱离本发明精神和范围的技术方案均应涵盖在本发明的专利申请 范围当中。

Claims

权利要求书
1. 一种具有低 k介质绝热材料的相变存储器结构， 包括衬底以及位于所 述衬底之上的由多个相变存储单元组成的相变存储单元阵列， 其特征 在于， 每个所述相变存储单元包括：
一个二极管；
位于所述二极管之上的加热电极；
位于所述加热电极之上的可逆相变电阻；
位于所述可逆相变电阻之上的顶电极；
在所述加热电极和可逆相变电阻周围包裹有低 k介质绝热层； 在所述可逆相变电阻与其周围的低 k介质绝热层之间设有防扩散 介质层。
2. 根据权利要求 1所述一种具有低 k介质绝热材料的相变存储器结构， 其特征在于： 所述低 k介质绝热层釆用低 k介质材料， 所述低 k介质 材料包括： 低 k的掺杂氧化物、低 k的有机聚合物和低 k的多孔材料。
3. 根据权利要求 2所述一种具有低 k介质绝热材料的相变存储器结构， 其特征在于： 所述低 k介质绝热层釆用氟掺杂氧化硅、 多孔碳掺杂氧 化硅、 旋涂有机聚合物介质、 旋涂有机硅基聚合物介质、 多孔 S iLK或 多孔氧化硅材料。
4. 根据权利要求 1所述一种具有低 k介质绝热材料的相变存储器结构， 其特征在于： 所述防扩散介质层釆用 S iN、 S iON、 Ta205、 A1203或 Zr02 材料。
5. 一种具有低 k介质绝热材料的相变存储器结构的制备方法， 其特征在 于， 该方法包括以下步骤：
( 1 ) 利用标准的 CMOS工艺制备二极管阵列； ( 2 ) 在二极管阵列上制备 50 nm-1000讓厚的第一低 k介质绝热层；
( 3 ) 在第一低 k介质绝热层上分别形成多个直径为 30-300 nm的第 一孔洞， 每个第一孔洞的底部与二极管阵列的每个二极管顶端 相连；
( 4 ) 在上述孔洞内填充加热电极材料， 接着进行 CMP 工艺， 除去表 面多余的加热电极材料， 形成柱状加热电极阵列；
( 5 ) 在柱状加热电极阵列上制备 50 nm-200 nm厚的第二低 k介质绝 热层； 在第二低 k介质绝热层上分别形成多个直径为 50-500讓 的第二孔洞， 每个第二孔洞的底部与柱状加热电极阵列中的每 个柱状加热电极顶端相连；
( 6 ) 在第二孔洞中制备 1-30 讓厚的防扩散介质层；
( 7 ) 在制备了防扩散介质层的第二孔洞内接着填充相变材料， 然后 进行 CMP 工艺， 除去表面多余的相变材料， 形成柱状可逆相变 电阻阵列；
( 8 ) 在柱状可逆相变电阻阵列上形成一层电极材料；
( 9 ) 利用光刻和湿法刻蚀形成相变存储单元阵列的顶电极。
6. 根据权利要求 5所述一种具有低 k介质绝热材料的相变存储器结构的 制备方法， 其特征在于： 制备所述第一低 k介质绝热层和第二低 k介 质绝热层釆用低 k介质材料， 所述低 k介质材料包括： 低 k的掺杂氧 化物、 低 k的有机聚合物和低 k的多孔材料。
7. 根据权利要求 6所述一种具有低 k介质绝热材料的相变存储器结构的 制备方法， 其特征在于： 所述第一低 k介质绝热层和第二低 k介质绝 热层釆用氟掺杂氧化硅、 多孔碳掺杂氧化硅、 旋涂有机聚合物介质、 旋涂有机硅基聚合物介质、 多孔 S i LK或多孔氧化硅材料。
8. 根据权利要求 5所述一种具有低 k介质绝热材料的相变存储器结构的 制备方法， 其特征在于： 所述第一孔洞和第二孔洞用聚焦离子束或电 子束曝光和反应离子刻蚀法方法形成。
9. 根据权利要求 5所述一种具有低 k介质绝热材料的相变存储器结构的 制备方法， 其特征在于： 所述防扩散介质层利用 ALD或 CVD方法制备。
10. 根据权利要求 5所述一种具有低 k介质绝热材料的相变存储器结构 的制备方法， 其特征在于： 步骤（7 ) 所用的 CMP 工艺， 抛光压力在 0. 5ps i以下， 使用胶体氧化硅抛光液对第二低 k介质绝热层和相变材 料进行抛光。
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