TW200901458A - Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and methods of forming the same - Google Patents

Abstract

A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e. g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a variable resistance memory device and a method of forming the same. [Prior Art] A non-volatile memory system useful storage device because it has the ability to hold data when no power is supplied. One of the types of variable resistance materials used for non-volatile memory cells is a phase change material, such as a chalcogenide alloy, which is capable of stable transition between an amorphous phase and a crystalline phase. Each phase exhibits a particular resistance state and the resistance states are distinguished from the logic values of a memory component formed from such materials. Specifically, the amorphous state exhibits a relatively high resistance, while a crystalline state exhibits a relatively low resistance. 1A and 1B illustrate a conventional variable resistance memory as a phase change memory element, and the memory often has a layer of material 8 between the first and second electrodes 2, 4. The first electrode 2 is disposed in a dielectric material 6. The phase change material 8 is set to a specific resistance state in accordance with the amount of electric current applied between the first electrode 2 and the second electrode. In order to obtain an amorphous state (Fig. 1B), a relatively high write current pulse ("Twist" pulse) is applied through the phase change memory element for a period of time to melt the cover. At least a portion 9 of the phase change material 8 of an electrode 2. The current is removed and the phase change material 8 is rapidly cooled to less than 2 degrees below the crystallization temperature, which causes the portion 9 of the phase change material 8 covering the first electrode 2 to have the amorphous state. In order to obtain a crystalline state (Fig. 1A), a comparison: the write pulse (-SET (set) pulse) is in a second time period (duration 130554.doc • 6 - 200901458 generally better than the first time period) The crystallization time of the amorphous phase change material is applied to the phase change memory element 丨 to heat the amorphous portion 9 to a temperature lower than its melting point but higher than its crystallization temperature. This causes the amorphous portion 9 of the phase change material 8 to recrystallize to the crystalline state, and once the current is removed, the phase change memory element 1 is cooled to maintain the crystalline state. The phase change memory device process is read by applying a read voltage that does not change the phase state of the phase change material 8.

Due to the low resistivity of the crystalline phase change material, a large reset current density may be required to provide sufficient power to melt the phase change material. A large current relaxation can cause unwanted electromigration in the conductive material and can cause phase separation in the phase change material. In addition, weak bonding between the phase change material and other layers can introduce long term reliability issues in the phase change memory component. SUMMARY OF THE INVENTION In the following detailed description, reference is made to the specific embodiments. The specific embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that it can be used for a variety of structural, logical and electrical changes. The term "substrate" as used in the following description may include any support structure including, but not limited to, a semiconductor substrate having an exposed substrate surface. A semiconductor substrate is understood to be a package (four), an insulator cut (sqi), Asbestos sapphire (SOS), doped and undoped semiconductor, & _ base semiconductor base supported epitaxial layer and other semiconductor structures (including those semiconductor structures made of semiconductors other than germanium). When referring to a semiconductor substrate or wafer in the τ face description, the previous program steps may have been used to form regions or junctions in or on the base or substrate of the base 130554.doc 200901458. The substrate is also not required to be a conductor. The master may be any support structure suitable for use in a support-integrated circuit including, but not limited to, metals, alloys, glass, polymers, ceramics, and any other support material known in the art. As described above, the self-heating of the phase change material made of the variable resistance memory device including the phase change memory device causes a phase between the amorphous and crystalline states. The low resistivity of the crystalline phase change material may require a large RESET current density to provide sufficient work current density to cause unwanted electromigration in the conductive material to cause phase separation in the phase change material. The weak adhesion between the phase change material and the other layers can introduce long-term reliability issues in the phase change memory element. Surface temperature cycling and thermotropic volume changes and stress can exacerbate the problem. A phase change memory device is provided, comprising: an interface bonding heating layer disposed between an electrode and the phase change material. The interface bonding heating layer improves adhesion between a dielectric layer and the phase change material and is also used as The local heating element provides an additional ', ·, to the self-heating of the phase change material. Additional heating from the interface bonding heating layer: reduces the τ current required to cause the phase change by more than thirty times while maintaining The device that is larger than -100 turns on the 'close resistor ratio'. This point meets the need. : The device opening/closing resistance ratio indicates the resistance in the off state (where one of the materials is The ratio of the electrical component in an amorphous state to the electrical resistance in the open state (wherein the phase change material is in a crystalline state). By minimizing the current density of the coffee lamp, it is avoided that it is not required in the conductive material. -migration and phase separation in a variable resistance material. In addition, since the heat dissipation effect can be alleviated by the I30554.doc 200901458. The lower thermal conductivity of the surface bonding heating layer [Embodiment] The specific implementation is now described with reference to the drawings The same reference numerals are used to identify the same features in the example 1J. Figure 2 illustrates a partial cross-sectional squeaking of a phase change memory component 10 constructed in accordance with an embodiment of the present invention. The child C memory component 1 can store at least one bit. Yuan, that is, logic or 〇.

The memory element 10 is supported by a substrate 20. A first dielectric layer 22 is disposed on the substrate 2G, and a first conductive metal layer μ is disposed in the first dielectric layer 22. The conductive metal layer 15 may be formed of any suitable conductive material such as titanium nitride (TiN), nitrided & (TiAiN), bonded (TiW), turned (Pt) or crane (W) and other materials. The thickness of the conductive metal layer can vary. In a specific embodiment, the thickness of the conductive metal layer 15 is about 1 〇〇〇A. A second dielectric layer 24 is disposed on the first dielectric layer 22 and a bottom electrode 12 is disposed in the second dielectric layer 24. The bottom electrode can be formed of any suitable conductive material such as titanium nitride (TiN), titanium nitride (TiAIN), titanium tungsten (TiW), platinum (Pt) or tungsten (W), and other materials. 12 can be scaled down to reduce the required stylized current. The thickness of the variable resistance material layer 18 and the top electrode 14 may also be reduced in size to correspond to the bottom electrode 12 in size. In a specific embodiment, the bottom electrode 12 can be a plug bottom electrode and can have a height of about 700 A and a diameter of about 400 A or less. In other embodiments, the bottom electrode 12 can be a different type of electrode, such as a one-year wheel electrode or a Guan 塾 electrode. 130554.doc 200901458 A third dielectric layer 26 is disposed on the second dielectric layer 24. An interface bonding heating layer 13 is disposed on the bottom electrode 12 and the second dielectric layer 24 in an opening 36 in the third dielectric layer 26. The interface bonding heating layer 13 may be formed of a material that will improve adhesion between a layer of varistor material 18 and the second dielectric layer 24, and/or will provide sufficient resistivity to provide a localized heating effect. , for example, N-rich TaN, N-rich TiAIN,

AlPdRe, HfTe5, TiNiSn, PBTe, Bi2Te3, Al2〇3, A_c,

TiOxNy, TiAlxOy ' SiOxNy or TiOx and other materials. N-rich TaN TaNx, where x is greater than! . Richness can be produced by increasing the flow rate of N2 in proportion to the flow rate of Ar during TaN sputtering. The value of TaNxfx can vary depending on the application requirements. A larger number of N in TaNx results in a higher resistivity. The N-rich TiA1N system is ΤίΑ1Νχ ’ where χ is larger than 】. Rich TiAIN can be produced in a way similar to the richness of Ding. In a particular embodiment, the interface bonding heating layer 13 can have a thickness in the range of between about 5 A and about 5 G A. In another embodiment, the thickness of the interface bonding heating layer 13 may range between about 2 〇 and about 5 。. A variable resistance material layer (10) is disposed at the opening of the third dielectric (4) The interface in 36 is bonded to the heating layer 13. In the illustrated embodiment, the varistor material layer 18 is a chalcogenide material such as a misrecorded hoof compound, Ge2Sb2Te5 (GST), etc. The phase change material (d) may be or include other phase change materials, such as In-Se, Sb2Te3, GaSb, InSb, Αα, 4 Te, GeTe, Te_Ge_As, Te_sn_se, Ge Se Ga,

Bi-Se-Sb > Ga-Se-Te ^ Sn-Sb-Te . in_Sb-Ge ^ Te-Ge-Sb-S ^ Te-Ge-Sn-0 . Te-Ge-Sn-Au > Pd- Te-Ge-Sn ^ In-Se-Ti-C〇. 130554.doc -10- 200901458

Ge-Sb-Te-Pd . Ge-Sb-Te-Co > Sb-Te-Bi Se λ

Ge-Sb-Se_Te, Ge_Sn_Sb_Te, n g'In'Sb'Te '

Ge-Te-Sn-Pt. Fig. 2 shows that - n · M n 丨, 仏 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如The state of the knife 19, while the edge of the variable resistance material layer _ rest: state. In the case of a 杳 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨The dielectric diode 14 is disposed on the material layer 18 in the opening 36 of the third dielectric layer 26. The top electrode 14 can be any suitable electric==20%, such as nitrogen butterfly, nitrided pure (tuin) or crane (W) and other materials. The interface of the varistor material layer 18 and the top electrode (10) are disposed in the ": opening 36 of the dielectric layer 26" but the top electrode 14 can also be configured:

Extending on top of the third dielectric layer 26. In a specific embodiment, the thickness of the top electrode 14 can be about 6 in. A (four) electrical layers 22, 24, 26 U may be formed of an insulating material, such as an emulsion (such as SiO 2 ), nitriding (siN); oxidation; high temperature polymer; low dielectric material; insulating glass; or insulation polymer. The dielectric material used to form the respective dielectric layers 22, 24, 26, 27, 28 may be the same or different between the layers. The interface bonding heating layer 13 improves the adhesion of the second dielectric layer 24 to the variable resistance material layer 18, and thus improves the long-term sin of the memory device 1 , especially in the temperature cycle and heat When the volumetric change is combined with the stress system device processing or operating conditions. Additional advantages have been explained above. 130554.doc 200901458 Figures 3A through 3C illustrate one embodiment of a method of fabricating a phase change memory element as illustrated in Figure 2. Any of the actions described herein do not require a specific order, except where the result of the previous action is logically required. Therefore, although the following actions are performed in a specific order, the order can be changed if necessary. As shown in Figure 3A, the first dielectric layer 22 is formed on the substrate 20 by any suitable technique. Using inertia lithography _, (4), blanket deposition

The first conductive metal layer 15 is formed in the first dielectric layer 22 by a chemical mechanical polishing (CMP) technique. The second dielectric layer 24 is formed on the first dielectric layer 22 and the first conductive metal layer 15 as shown in FIG. 3B. The opening 34 is formed in the second dielectric layer 24 by any suitable technique (e.g., etching) over and aligned with the first conductive metal layer 15. The bottom electrode_ is formed in the opening and is in electrical contact with the first metal layer 15. A flat upper surface may be formed on the top surface of the bottom electrode 12 using chemical mechanical polishing. As shown in FIG. 3C, the interface bonding heating layer 13, the varistor material layer 18 and the top electrode 14 are sequentially deposited on the second dielectric layer 24 and the bottom electrode 12. The interface is then bonded using a conventional lithography technique to engrave the interface bonding heating layer 13, the varistor material layer Μ and the top electrode M to form a stack. The third dielectric layer 26 is formed on the stack. The top electrode 14 can be exposed using a -CMP technique and the top surface of the top electrode 14 and dielectric layer 26 can be planarized. Example 1 targets the SET state by Raytheon. The straw is electrically modeled using a resistance of a memory element of one of the G s phase of a thickness of 1 Å A. The C-GST layer has a resistivity of 7.5 milliohms. The top electrode is 1 GGG Ti thick TiN. The bottom electrode is ΤιΝ with a height of q α and a diameter of 50 nm. The resistance of the memory component in the state of the bribe is about 200 ohms. Example 2/Ten This SET state is modeled by the computer using a 1_A thick GST phase underlying material and having a memory of one of the interface bonding heating layers. The C-GST phase change material has a resistivity of 75 milliohms. centimeter and a resistivity of the interface bonding heating layer of 20 A thickness of 7500 milliohms. The top electrode is TiN of 1000 A thickness. The bottom electrode has a gate of 1 〇〇〇 A and a diameter of 50 nm. The resistance of the memory element in the set state is approximately 4, ohms. The current density of the second layer shows little lateral current spreading on the -Hear bonded heating layer, and the current distribution in the GST phase change material is similar to the example, indicating that the interface bonding heating layer will not affect the stylized volume. The shape will only provide a localized heating on the bottom electrode. The interface bonding heating layer also acts as a thermal barrier to reduce heat loss due to its low thermal conductivity. Example 3 For the RESET state, the computer will use a phase material of a thickness of 1 Å without the resistance modeling of one of the memory elements of the interface bonding heating layer. The resistivity of the c-GST phase change material is 75 milliohms. The resistivity of the phase change material is 7, W milliohms. centimeters. The thickness of the top electrode system 〇A is (ιΝ〇 the height of the bottom electrode system is (10)a and The diameter is 130554.doc 13 200901458 50 nm TiN. The resistance of the memory element in the RESET state is about 2 x 106 ohms. Before the current density distribution is expanded, most of it concentrates on a 300 A a- Within the GST area. Example 4

The RESET state is modeled by a computer using a GST phase change material having a thickness of 1 Å and having a memory element of an interface bonding heating layer. The resistivity of the c-GST phase change material is 75 milliohms.cm. The resistivity of the a-GST phase change material is 7.5 x 1 〇 4 milliohms. cm. The resistivity of the interface bonding heating layer is 75 〇〇 milliohm. centimeters. The top electrode is TiN of 10G0 A thickness. The bottom electrode is a track having a height i just A and a diameter of 50 _. The memory element in the station state has a resistance of approximately 2 x 105 ohms. Similar to the benefit / ^ ^ ^ shell is similar to the dry case 3, the current density distribution is mostly concentrated in a 300 A a-GST area generation j-domain. The lateral current distribution in the interface bonding heating layer is small, so only the channel _μ Λ value results in a small cell resistance change. Example 5

The various systems used in the specific embodiments in which the inventors implement the nanomachines are included in Table 1 below. The four-point bending measurement of the tool determines the joint strength between the materials. The junction 130554.doc 200901458 Table 1 · Bonding energy (Gc) of the tested material (J/m2) SiN/c-GST 0.7 to 0.8 TiN/c-GST 2 to 3 SiN/a-GST 3 to 4 TiN/a- GST 13 to 14 TiN/c-GST (DC sputtering) 3.6±1.1 TiN/c-GST (RF sputtering) 1.1±0.4 SiN/c-GST (severe pre-sputter) ~2.0-3.0 TEOS/c-GST (Severe re-sputtering) ~2.0-3.0 TiN/c-GST (RF Sputtering) ~1.0 TEOS/a-GST (RF Sputtering) 0.2 TEOS/c-GST (Radio Frequency Sputtering) 0.3 SiC/c-GST( RF sputtering) Very weak DARC/c-GST (RF sputtering) Very weak LSO/c-GST (RF sputtering) 1.2 A1203/c-GST > 1.5 TEOS/c-GST <0.5 Figure 2 only describes this article An example of one of the memory elements 10 is illustrated. Other designs incorporating the memory element 10 of the interface bonding heating layer 13 are also possible. For example, the first metal layer 15 can be reconfigured, omitted, or replaced as needed for use in a particular memory device. The specific embodiment may also employ one or more layers of other variable resistance materials as the layer of variable resistance material 18. The thickness of each layer can be modified as needed to take into account the various configurations of the components and the desired resistance. Examples of other variable resistance materials include such materials as metal-doped chalcogenide glasses and those described in various patents and patent applications assigned to Micron Technology, pp. 130554.doc -15-200901458, It includes, but is not limited to, the following: U.S. Patent Application Serial No. 10/765,393; U.S. Patent Application Serial No. 9/853,233; U.S. Patent Application Serial No. 10/022,722; U.S. Patent Application Serial No. 10/ 603,741; U.S. Patent Application Serial No. 9/988,984; U.S. Patent Application Serial No. 10/121,790; U.S. Patent Application Serial No. 09/941,544; U.S. Patent Application Serial No. 1/193,529; Application No. 10/100,450; US Patent Application No. 1/23^779; US Patent

U.S. Patent Application Serial No. 10/230,872; U.S. Patent Application Serial No. 1/865,9, 3; U.S. Patent Application Serial No. 10/230,327; Case No. G9/943, 19(); US Patent Application No. 1G/622, 482; US Patent No. 1 () Ship's nickname; US Patent Application No. 1/819, 315; US Patent The disclosures of U.S. Patent Application Serial No. 1/062, 436, U.S. Patent Application Serial No. Serial No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No. 4 illustrates an exemplary processing system 900 utilizing a resistive variable random access memory device 84, the resistive variable random access memory device 84A comprising the above described with reference to FIGS. 2 and 3-8. An array of one of the constructed memory elements. The processing system 900 includes a local bus controller 902 coupled to a local bus bar 904 and a main bus bar or a plurality of processors 901 903 coupled to the local bus bar 9 4. The processing system 9A can include a plurality of memory controllers 902 and/or a plurality of primary bus bars 903. The memory controller 9〇2 and the main bus bridge can be integrated into a single device 906. 130554.doc -16· 200901458 The (10) body controller 902 is also operatively coupled to one or more memory bus bars 9〇7. The mother-memory busbar accepts a memory component_, which includes at least one memory device 84A as described herein. Alternatively, in a simplified system, the memory control can be omitted and the memory components are directly coupled to one or more processors 9G1. The memory components can be a memory card or a memory module. The memory components 9A8 may include one or more additional devices 909 called Lance, which may be a configuration memory

body. The memory controller 902 can also be coupled to a cache memory 9〇5. The cache memory 905 can be the only cache memory in the processing system. Alternatively, the other device (e.g., processor 9Q1) may also include a cache memory that forms a cache level with the cache memory 〇5. If the processing system 900 includes a peripheral device or controller that is a bus master or supports direct memory access (DMA), the memory controller 〇2 can implement a -cache coherency protocol. If the memory controller is stolen to a plurality of memory bus bars 907, the streams can be operated in parallel, or different address ranges can be mapped to different memories = 907 ° Main bus bar bridge 903 coupling To at least one peripheral busbar 91〇. Various devices, such as peripheral devices or additional busbar bridges, can be coupled to the peripheral busbar 910. Such devices may include a storage controller 911, a miscellaneous I/O device 914, a primary bus bar 915, a multimedia processor 9!8, and an legacy device interface 92A. Main bus bar bridge 903 can also be coupled to one or more dedicated high speed ports 922. For example, in a personal computer, the dedicated device may be an accelerated graphics port (AGp) for coupling a 130554.doc 200901458 and a performance video card to the processing system. The HI storage controller 911 couples one or more storage devices 913 to the peripheral bus bar 91A via a storage busbar 9 i 2 . For example, the storage controller 911 can be a SCSI (Sma11 computer system interface; small, first) controller, and the storage device 913 can be a SCSI disc. This is set to 914 for any type of peripheral device. For example, the I/O device can be a regional network interface (such as an Ethernet card). The secondary bus bridge can be used to interface additional devices to the processing system via another bus. For example, the secondary bus bridge can be a universal serial bus (USB) port controller for translating USB device 917 to the processing system. The multimedia processor 918 can be a sound card, a video capture card, or any other type of media interface, which can also be coupled to an additional device (e.g., speaker 919). The legacy device interface 92 is used to couple legacy devices 1 (e.g., old keyboards and mice) to the processing system. The processing system 900 illustrated in Figure 4 is merely an exemplary processing system that can be used in conjunction with the specific embodiments described herein. Although the Figure 4 illustration is particularly suitable for processing architectures using one of a computer (e.g., a personal computer or a workstation), it should be understood that well-known modifications can be made to configure the processing system 9(10) to be more suitable for various applications. For example, an electronic device to be processed by the present invention can be implemented using a simpler architecture that relies on a "cpu" (Fig. 2) coupled to the memory component 908 and/or the 5 memory component (7). Such electronic devices may include, but are not limited to, audio/video processors and recorders, game instruments, digital televisions, wired or wireless telephones, navigation devices (including global positioning systems, first (GPS) and/or f Shell navigation system, and digital camera and / or record 130554.doc 200901458,. Modifications such as Hi may include, for example, the deletion of unnecessary components, the addition of dedicated devices or circuits, and/or the entirety of a plurality of devices.乂 = (4) and the schema is only considered as a special explanation of the explanation of the real financial statement. Although the specific embodiments described herein provide a good bond between -=== and also reduce the viscosity δ between the S in other variable resistance memory devices, the variable neutrons or Other materials can be used as "兮5", 彳 使用 - 硫 硫 硫 硫 硫 硫 硫 硫 硫 硫 硫 硫. For specific program conditions: , : T to modify and replace. Therefore, it is considered to be limited to the above description and the details of the figure and the physical example (4). Μ ^Only for the scope of patents at any time [Simple description of the diagram]: Explain with the 18 - the usual phase change memory components. : Illustrated in accordance with the present invention - a specific embodiment

Partial sectional view of one of the pieces.邳 隐 隐 隐 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 One of the electronic systems. The form of Α shows the main component symbol description according to the present invention. 1 2 4 6 Phase change memory component No. electrode Second electrode dielectric material 130554.doc 200901458 8 Phase change material 9 Phase change material A portion/amorphous portion 10 phase change memory element 12 bottom electrode 13 interface adhesion heating layer 14 top electrode 15 conductive metal layer/first metal layer 18 variable resistance material layer 19 one portion of variable resistance material layer 20 substrate 22 A dielectric layer 24 a second dielectric layer 26 a third dielectric layer 34 opening 36 opening 840 a resistance variable random access memory device 900 processing system 901 processor / CPU 902 memory controller 903 main bus bar bridge 904 Local Bus 905 Cache Memory 906 Single Device 907 Memory Bus 130554.doc -20- 200901458 908 Memory Component 909 Additional Device 910 Peripheral Bus 911 Storage Control Storage means storing busbar 913 912 914 Miscellaneous I / O device 915 the secondary bus bridge 917 USB multimedia processor 919 speaker 918 920 921 old legacy device interface 922 and device speed sun 130554.doc

Claims (1)

200901458 X. Patent application scope: 1. A resistive memory device comprising: a first electrode; a surface of the M-side bonding heating layer; having a gas/material coupled to the first electrode; a first surface coupled to the second surface of the interface; and a first electrode coupled to the second surface of the one of the variable resistance materials. / The resistive memory device of claim 1, wherein the interface bonding heating layer is free from at least one selected from the group consisting of: N TlA1N, A1PdRe, HfTe5, TiNiSn, PBTe, Bl2Te3, Al203, AC, TiOxNy TiAlx〇y, Si〇xNy, and TiOx 〇3. A resistive memory device such as α, wherein the TaN is an N (n-nCh)-rich TaN' and the TiAIN is an N-rich TiAIN. 4. The resistor memory device of claim 1, wherein the stomach-to-face of the interface bonding heating layer is also bonded to a dielectric layer. 5. The resistor memory device of claim 4, wherein the dielectric layer comprises an oxygen species, an & argon fossil, a oxidized epoxide, a high temperature polymer, an insulating glass, and a sister & π At least one of insulating polymers. 6. A resistive memory device such as a luxury device, wherein the thickness of the interface bonding heating layer is from about 5 angstroms to about 50 angstroms. 7. The resistive memory device of item 1, wherein the resistance change material package 130554.doc 200901458 comprises a G S T material. 8. 9. 10. 11. 12. 13. The resistive memory device of claim 1 , further comprising a first conductive layer coupled to the first electrode and coupled to the second electrode conductive layer. The resistive memory device of claim 1, wherein the first electrode and the second electrode comprise at least one of titanium nitride, titanium aluminum nitride, titanium tungsten, platinum, and goose. A resistive memory device comprising: a first electrode; to > a layer of dielectric material having an opening on the first electrode; an interface bonding heating layer in the opening and contacting the first An electrode; a layer of GST material in the opening and contacting the interface bonding heating layer; and a second electrode contacting the GST material. The resistive memory device of claim 10, wherein the second electrode is disposed within the opening. The resistive memory device of claim 10, wherein the interface bonding heating layer is formed by at least one selected from the group consisting of: TaN, TiAIN, AlPdRe, HfTe5, TiNiSn, pBTe, Bi2Te3, Al2〇3, A_C, Ti〇xNy, TiAlx〇y, 〇 and Ti〇x. The resistive memory device of claim 10, wherein the interface bonding heating layer has a thickness of from about 5 angstroms to about 5 angstroms. The resistor memory device of claim 10, wherein the interface bonding heating layer is also coupled to a dielectric layer. 1 5. A resistive memory device, comprising: a first electrode; an interface bonding heating layer 'having contact with a first surface of the first electrode', the interface bonding heating layer is free of TaN, TiAlN, AlPdRe, HfTe5, TiNiSn, PBTe, Bi2Te3, and a12〇3, A c ' Forming at least one material selected from the group consisting of T1〇xNy, TiAlx〇y, ^(^... and Ding; a material having a first surface having two surfaces; and a second electrode contacting the GST material A second surface. 16. The resistive memory device of claim 15, wherein the first (electrical) layer is surrounded by a dielectric layer and the interface bonding heating layer is also affixed to the electricity: 17. The resistive memory device comprises: - the dielectric layer comprising at least one of - oxide, tantalum nitride, aluminum oxide, a warm polymer, an insulating glass, and an insulating polymer, such as claim 17 The resistive memory device, wherein the dielectric layer "wherein the interface is bonded to the heating layer, the method comprises: 1. 9. The resistive memory device of claim 5, having a thickness of about 5 angstroms to about 50 angstroms. a method of forming a memory device, forming a first electrode; 130554.doc 200901458 forming an interface bonding heating layer having a first surface coupled to one of the first electrodes; forming a layer of variable resistance material having a coupling to the interface bonding plus a first surface of the second surface of the layer; and a second electrode formed to be coupled to the second surface of the one of the layers of the variable resistance material. 1 1 . The method of claim 20, wherein a dielectric layer is formed The method of claim 20, wherein the interface heating layer material, a resistance change material, and a second electrode material are deposited and etched by the interface. And forming the interface bonding heating layer, the resistance change material layer and the second method in a stack, wherein the dielectric layer comprises an oxide, a tantalum nitride, an aluminum oxide. A method of claim 20, wherein the interface bonding heating layer is formed from at least one selected from the group consisting of: τ & ν, TiAIN, AlPdRe, HfTe5, TiNiSn, PBTe, Bi2Te3, A1203, AC, Ti〇xNy, TiAlx〇y, Si〇xNy, and τί〇χ. 25. The method of claim 20, further comprising Forming a dielectric layer around the first electrode, wherein the first surface of the interface bonding heating layer is also coupled to the dielectric layer. 26. The method of claim 2Q, wherein the step comprises: The adhesive heating layer is formed to a thickness of from about 5 angstroms to about 50 angstroms. The method of claim 20, wherein the resistance change material comprises a GST material. r 130554.doc