WO2022143461A1 - 一种相变存储器单元及其制备方法 - Google Patents

一种相变存储器单元及其制备方法 Download PDF

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WO2022143461A1
WO2022143461A1 PCT/CN2021/141209 CN2021141209W WO2022143461A1 WO 2022143461 A1 WO2022143461 A1 WO 2022143461A1 CN 2021141209 W CN2021141209 W CN 2021141209W WO 2022143461 A1 WO2022143461 A1 WO 2022143461A1
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phase change
layer
columnar
electrode
dielectric layer
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PCT/CN2021/141209
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English (en)
French (fr)
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钟旻
李铭
冯高明
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上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司
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Priority to US18/270,243 priority Critical patent/US20240065120A1/en
Publication of WO2022143461A1 publication Critical patent/WO2022143461A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8613—Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a phase-change memory cell and a preparation method thereof.
  • Phase Change Memory is an information storage device that uses the difference in electrical conductivity exhibited by special materials when they transform between crystalline and amorphous states to store data.
  • phase-change memory typically utilizes the huge difference in conductivity between chalcogenides in the crystalline and amorphous states to store data.
  • FIG. 1 is a schematic cross-sectional view of a phase change memory cell implemented based on the prior art.
  • the existing phase change memory cell structure is a vertical stack structure of 1 phase change switch + 1 phase change resistor (1OTS+1R). From bottom to top, the bottom electrode 01, the selection device layer 02, the The barrier layer 03, the phase change material layer 04 and the top electrode 05 are composed.
  • FIG. 2 is a schematic diagram of an effective phase transition operating region realized based on the prior art.
  • the semicircular area near the interface is an effective phase change operation area, and the initial state is a crystalline state. Other regions in the material layer 04 remain crystalline.
  • Vots ⁇ V ⁇ Vset operating voltage V, threshold voltage Vots of the phase change switch, operating voltage Vset of the phase change resistor
  • heat continues to accumulate in the phase change resistance layer 04, and the device is not effective when operating
  • the phase change operating area may change phase, which will change the volume of the effective operating area, make the phase change resistance unstable, and cause device reliability problems.
  • phase change memory cell structure is required to solve the problem of the volume change of the effective operating area in the phase change resistor and improve reliability.
  • the present invention proposes to provide a phase change memory unit and a preparation method thereof, so as to effectively improve the device performance and reliability of the phase change memory unit.
  • a phase-change memory unit which sequentially includes from bottom to top: a bottom electrode, a phase-change unit, a heating electrode and a top electrode located on a substrate; wherein, the phase-change unit is longitudinally connected and arranged on the bottom electrode
  • the cylinder is provided with a cylindrical phase change material layer, an annular cylindrical heat dissipation layer and an annular cylindrical selection device layer in sequence from the inside to the outside; the top electrode, the heating electrode, and the cylindrical phase change layer
  • the change material layers are sequentially connected from top to bottom, and the annular column-shaped selection device layer is connected to the bottom electrode, wherein the column cross-section of the phase change unit includes a circle, an ellipse, a rectangle, a rhombus, and a polygon. one or more combinations.
  • the heating electrode is connected to a contact surface of the columnar phase change material layer, and the annular columnar heat dissipation layer and the annular columnar selection device layer sequentially cover the remaining part of the columnar phase change material core.
  • Contact surface wherein the heating electrode is longitudinally arranged on the top surface of the cylindrical phase change material layer, the bottom shape of the heating electrode is located within the range of the top surface of the cylindrical phase change material layer, and the top of the heating electrode is connected at the lower end of the top electrode.
  • the initial state of the columnar phase change material layer is a crystalline state;
  • the materials of the columnar phase change material layer include GeTe-Sb 2 Te 3 system, GeTe-SnTe system, Sb 2 Te system, In 3 SbTe 2 system, Sb doping system, GeTe-Sb 2 Te 3 system/GeTe-SnTe system/Sb 2 Te system doped with Sc, Ag, In 2 , Al, In, C, S, Se, N, Cu, W elements At least one of /In 3 SbTe 2 system/Sb doping system.
  • cylindrical section of the heating electrode includes one or more combinations of ring, circle, ellipse, rectangle, rhombus and polygon.
  • the thermal conductivity of the material of the annular cylindrical heat dissipation layer is greater than 100W/mK.
  • the selection device formed by the selection of the annular columnar device layer is one of a two-dimensional material transistor, a bidirectional threshold switch and a metal oxide thin film resistance switch.
  • the material of the annular cylindrical heat dissipation layer includes at least one of graphene, carbon-containing compounds, two-dimensional materials, Ti, W, Ta, Cu, tungsten carbonitride, tungsten nitride, and TaN.
  • a method for preparing a phase-change memory cell comprising the following steps: S1: providing a substrate, depositing a first dielectric layer on the substrate, and forming a bottom electrode in the substrate and the first dielectric layer ; S2: depositing a second dielectric layer on the first dielectric layer, and forming a first groove or through-hole structure on the bottom electrode, the first groove or through-hole structure passing through the second dielectric layer; S3: forming a ring-shaped column selection device layer filling the first groove or through-hole structure, a ring-shaped column heat dissipation layer and a column-shaped phase change material layer in sequence on the second dielectric layer; S4: A chemical mechanical polishing process is used to remove the annular columnar selection device layer, the annular columnar heat dissipation layer and the columnar phase change material layer on the second dielectric layer, and the second dielectric layer is formed with the phase change unit; S5: deposit a third dielectric layer on the second dielectric layer, and form a heating electrode connected to
  • the lateral dimension of the first groove or through-hole structure is less than or equal to the lateral dimension of the top surface of the bottom electrode, and in step S5, the lateral dimension of the heating electrode is smaller than the lateral dimension of the columnar phase change material layer. size.
  • the present invention makes the current density and heat distribution more concentrated by covering the phase change resistance layer with the annular cylindrical heat dissipation layer, thereby fixing the effective phase change operation area.
  • the volume of the effective phase-change operation area of the phase-change resistance layer is reduced by the coating of the annular cylindrical heat dissipation layer, thereby reducing the power consumption of the device.
  • the contact area between the annular cylindrical heat dissipation layer and the ineffective phase change operation area of the phase change resistance layer increases, which reduces the heat accumulation in the ineffective phase change operation area and reduces the conversion of the ineffective phase change operation area into an effective phase change. It is possible to operate the area and improve the reliability of the device.
  • FIG. 1 is a schematic cross-sectional view of a phase change memory cell realized based on the prior art
  • FIG. 2 is a schematic diagram of an effective phase transition operating region realized based on the prior art
  • FIG. 3 is a schematic flowchart of a method for preparing a phase change memory cell according to an embodiment of the present invention
  • 4 to 9 are schematic cross-sectional views of products corresponding to the method for fabricating a phase change memory cell according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the simulation results of the current density and heat distribution of the phase change memory cell of the prior art
  • FIG. 11 is a schematic diagram of simulation results of current density and heat distribution of a phase change memory cell according to an embodiment of the present invention.
  • phase change memory cell is provided on the substrate 101 .
  • One or more dielectric layers may be provided on the substrate 101, for example, the first dielectric layer 102, the second dielectric layer 104, the third dielectric layer 110 and the fourth dielectric layer 112; the phase change memory cells may be embedded in the one or more dielectric layers inside the dielectric layer.
  • the phase change memory cell sequentially includes a bottom electrode 103, a phase change unit 109, a heating electrode 111 and a top electrode 113 located on the substrate from bottom to top.
  • the phase change unit 109 is a column vertically connected and arranged on the bottom electrode 103 , and is sequentially provided with a columnar phase change material layer 108 , an annular columnar heat dissipation layer 107 and an annular columnar selection from the inside to the outside.
  • the device layer 106 ; the top electrode 113 , the heating electrode 111 and the columnar phase change material layer 108 are sequentially connected from top to bottom, and the annular columnar selection device layer 106 is connected to the bottom electrode 103 .
  • the cylinder section of the phase change unit 109 may include one or more combinations of circle, ellipse, rectangle, rhombus, and polygon, etc.
  • the annular cylindrical heat dissipation layer 107 and the annular cylindrical shape are selected
  • the cross section of the device layer 106 may include one or more combined rings among circular rings, oval rings, rectangular rings, diamond rings, and polygonal rings.
  • the substrate 101 may comprise a semiconductor material such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon germanium substrate, or a fully depleted silicon-on-insulator (FDSOI) substrate.
  • the substrate 101 may also be an integrated circuit, including an integrated circuit having gate transistors such as triodes, diodes, and the like.
  • the bottom electrode 103 may be located in the substrate 101 and the first dielectric layer 102 at the same time.
  • the lower part of the bottom electrode 103 is located in the substrate 101 , and the upper part is exposed to the surface of the substrate 101 and located in the first dielectric layer 102 .
  • the bottom electrode 103 may be a pillar structure, such as a truncated cone as shown in the figure.
  • the bottom electrode 103 may be a tungsten electrode, but is not limited thereto.
  • the heating electrode 111 is connected to a contact surface of the cylindrical phase change material layer 108 , and the annular cylindrical heat dissipation layer 107 and the annular cylindrical selection device layer 106 are sequentially coated The remaining contact surface of the columnar phase change material layer 108 .
  • the bottom of the heating electrode 111 is located within the range of the top surface of the columnar phase change material layer 108 , and the top of the heating electrode 111 is connected to the lower end of the top electrode 113 .
  • the heating electrode 111 is a columnar or through-hole structure longitudinally disposed on the columnar phase change material layer, and is correspondingly connected to the lower end of the top electrode, and the lateral dimension of the heating electrode is smaller than that of the columnar phase change material.
  • the lateral dimension of the phase change unit 109 is less than or equal to the lateral dimension of the top surface of the bottom electrode 103 .
  • the material of the annular cylindrical heat dissipation layer can be selected from a material with stable chemical properties. For example, the material needs to be annealed at 600° C. for 5 minutes so that the material components of the annular cylindrical heat dissipation layer do not diffuse. Further, the material of the annular cylindrical heat dissipation layer has good thermal conductivity, preferably, the thermal conductivity is greater than 100W/mK.
  • the material of the annular columnar heat dissipation layer 107 may include at least one of graphene, carbon-containing compounds, two-dimensional materials, Ta, tungsten carbonitride, tungsten nitride, and TaN.
  • the selection device formed by the annular column selection device layer may include one of a two-dimensional material transistor, a bidirectional threshold switch (Ovonic Threshold Switch, OTS) and a metal oxide thin film (MOx) resistance switch.
  • OTS bidirectional threshold switch
  • MOx metal oxide thin film
  • the initial state of the columnar phase change material layer 108 may be a crystalline state.
  • the material of the columnar phase change material layer 108 includes GeTe-Sb 2 Te 3 system, GeTe-SnTe system, Sb 2 Te system, In 3 SbTe 2 system, Sb doped system, doped Sc, Ag, In 2 , Al, At least one of a GeTe-Sb 2 Te 3 system/GeTe-SnTe system/Sb 2 Te system/In 3 SbTe 2 system/Sb doped system of In, C, S, Se, N, Cu, and W elements.
  • FIG. 3 is a schematic flowchart of a method for fabricating a phase change memory cell proposed in an embodiment of the present invention. As shown in FIG. 3, a preparation method of a phase change memory cell of the present invention includes:
  • the bottom electrode 103 is a truncated circular electrode (as shown in FIG. 4 ).
  • the lower half of the bottom electrode 103 may be located in the substrate 101 and the upper half may be located in the first dielectric layer 102 .
  • the first groove or through hole 105 can be one of a circle, an ellipse, a rectangle and a polygon.
  • a cylindrical first through hole 105 is formed in the second dielectric layer 104 .
  • the lateral dimension of the first through hole 105 is smaller than the lateral dimension of the top surface of the bottom electrode 103 (adjacent to the first through hole 105 ).
  • a ring-shaped column selection device layer 106 filling the first groove or through-hole structure 105, a ring-shaped column heat dissipation layer 107 and a column-shaped phase change material layer 108 are sequentially formed ;
  • the annular columnar selection device layer 106 is connected to the bottom electrode 103, and the columnar phase change material layer 108 fills the first groove 105 (as shown in FIG. 6).
  • the material of the annular columnar selection device layer 106 is a phase-change material GeSeAs 2 that can form a bidirectional threshold switch, and a GeSeAs 2 film is deposited by chemical vapor deposition.
  • the GeSeAs 2 film is amorphous, During the operation of the columnar phase change material layer 108, the GeSeAs 2 thin film acts as a gate device, and the phase state does not change.
  • the material of the annular columnar heat dissipation layer 107 includes conductive materials and has stable chemical properties, and will not chemically react with the material of the annular columnar selection device layer 106 and the material of the columnar phase change material layer 108 at high temperature (600° C.). Reaction or element diffusion.
  • the annular cylindrical heat dissipation layer coats the cylindrical phase change material layer, so that the current density and heat distribution are more concentrated, thereby fixing the effective phase change operation area.
  • the material of the annular cylindrical heat dissipation layer 107 is TaN.
  • the columnar phase change material layer 108 can be deposited by means of high density plasma chemical vapor deposition (HDP CVD), and the deposition temperature is 200-500° C.
  • the deposited columnar phase change material layer 108 is in a crystalline state.
  • the deposition can be achieved in the same device.
  • a phase change unit 109 is formed in the two dielectric layers 104 (as shown in FIG. 7 ).
  • the above method adopts the method of groove or through hole filling and chemical mechanical polishing to prepare a phase change unit with a three-dimensional columnar nested structure, which can be composed of a selection device and a phase change resistor.
  • FIG. 10 is a schematic diagram of simulation results of current density and heat distribution of a phase change memory cell in the prior art.
  • FIG. 11 is a schematic diagram of simulation results of current density and heat distribution of a phase change memory cell according to an embodiment of the present invention.
  • the heating electrode is connected to one contact surface of the cylindrical phase change material layer, and the annular cylindrical heat dissipation layer covers the other contact surfaces of the cylindrical phase change material layer, so that the effective phase of the cylindrical phase change material layer is Compared with the existing phase change structure (shown in Figure 10), the current density and heat distribution are more concentrated, thus fixing the effective phase change operation area.
  • the volume of the effective phase change operation area of the phase change resistance layer is reduced, and the power consumption of the device is reduced.
  • the contact area between the annular cylindrical heat dissipation layer and the ineffective phase change operation area of the phase change resistance layer increases, which reduces the heat accumulation in the ineffective phase change operation area and reduces the conversion of the ineffective phase change operation area into an effective phase change. It is possible to operate the area and improve the reliability of the device.
  • the annular cylindrical heat dissipation layer adopts stable chemical properties and good thermal conductivity, and will not affect the device performance of the phase change unit.

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Abstract

一种相变存储器单元及其制备方法，其从下到上依次包括位于衬底上的底电极、相变单元、加热电极和顶电极；其中，相变单元为纵向连接设置于底电极上的柱体，设置有同心的柱形相变材料层、环状柱形散热层和环状柱形选择器件层；顶电极与加热电极依次连接柱形相变材料层，环状柱形选择器件层连接底电极。本发明采用环状柱形散热层包覆相变电阻层，电流密度和热量分布更加集中，从而固定相变电阻层的有效相变操作区域，且减小有效相变操作区域体积，降低了器件功耗，提高器件可靠性。

Description

一种相变存储器单元及其制备方法
交叉引用
本申请要求2020年12月30日提交的申请号为202011608134.3的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明属于半导体集成电路制造工艺技术领域，尤其涉及一种相变存储器单元及其制备方法。
技术背景
相变存储器(Phase Change Memory，简称PCM)利用特殊材料在晶态和非晶态之间相互转化时所表现出来的导电性差异来存储数据的一种信息存储装置。具体地，相变存储器通常利用硫族化合物在晶态和非晶态巨大的导电性差异来存储数据。
图1为基于现有技术实现的相变存储器单元截面示意图。如图1所示，现有的相变存储器单元结构为1个相变开关+1个相变电阻(1OTS+1R)的垂直堆叠结构，自下而上由底电极01、选择器件层02、阻挡层03、相变材料层04和顶电极05组成。
图2为基于现有技术实现的有效相变操作区域的示意图。如图2所示，对于相变材料层04，靠近界面的半圆形区域为有效相变操作区域，初始态为晶态，在写操作后，由晶态转为非晶态，而相变材料层04中的其他区域仍为晶态。在反复操作过程中，当Vots<V<Vset(操作电压V，相变开关的阈 值电压Vots，相变电阻的操作电压Vset)，热量在相变电阻层04持续聚集，器件操作时，非有效相变操作区域可能相变，使有效操作区域体积变化，致相变电阻不稳定，产生器件可靠性问题。
因此，需要一种新型的相变存储器单元结构，解决相变电阻中有效操作区域体积变化的问题，提升可靠性。
发明概要
针对现有技术能力的不足，本发明提出了提供一种相变存储器单元及其制备方法，以有效提高相变存储器单元的器件性能和可靠性。
为实现上述目的，本发明的技术方案如下：
一种相变存储器单元，其从下到上依次包括：位于衬底上的底电极、相变单元、加热电极和顶电极；其中，所述相变单元为纵向连接设置于所述底电极上的柱体，其由内而外依次设置有柱形相变材料层、环状柱形散热层和环状柱形选择器件层；所述顶电极、所述加热电极、与所述柱形相变材料层自上而下依次连接，所述环状柱形选择器件层连接所述底电极，其中，所述相变单元的柱体截面包括圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
进一步地，所述加热电极与柱形相变材料层一个接触面相连，所述环状柱形散热层和所述环状柱形选择器件层依次包覆所述柱形相变材料核的剩余接触面，其中，所述加热电极纵向设于柱形相变材料层的顶部表面上，所述加热电极的底部形状位于柱形相变材料层顶部表面的范围内，所述加热电极的顶部连接在所述顶电极的下端。
进一步地，所述柱形相变材料层初始状态为晶态；所述柱形相变材料层的材料包括GeTe-Sb 2Te 3体系、GeTe-SnTe体系、Sb 2Te体系、In 3SbTe 2体系、Sb掺杂体系、掺杂Sc、Ag、In 2、Al、In、C、S、Se、N、Cu、W元素的GeTe-Sb 2Te 3体系/GeTe-SnTe体系/Sb 2Te体系/In 3SbTe 2体系/Sb掺杂体系中的至少一种。
进一步地，所述加热电极的柱体截面包括环形、圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
进一步地，所述环状柱形散热层的材料的导热系数大于100W/mK。
进一步地，所述选择环状柱形器件层形成的选择器件为二维材料晶体管、双向阈值开关和金属氧化物薄膜电阻开关中的一种。
进一步地，所述环状柱形散热层的材料包括石墨烯、含碳化合物、二维材料、Ti、W、Ta、Cu、碳氮化钨、氮化钨、TaN中的至少一种。
为实现上述目的，本发明的技术方案如下：
一种相变存储器单元的制备方法，其特征在于，包括以下步骤：S1：提供衬底，在所述衬底上沉积第一介质层，在所述衬底和第一介质层中形成底电极；S2：在所述第一介质层上沉积第二介质层，并在所述底电极上形成第一凹槽或通孔结构，所述第一凹槽或通孔结构贯通所述第二介质层；S3：在所述第二介质层上依次形成填充所述第一凹槽或通孔结构的环状柱形选择器件层，环状柱形散热层和柱形相变材料层；S4：采用化学机械抛光工艺，去除第二介质层上的所述环状柱形选择器件层、所述环状柱形散热层和所述柱形相变材料层，在第二介质层中形成所述相变单元；S5：在所述第二介质层上沉积第三介质层，在所述第三介质层中形成连接所述环状柱形选择器件 层的加热电极；S6：在所述第三介质层上沉积第四介质层，在所述第四介质层中形成连接所述加热电极的顶电极；其中，所述顶电极、所述加热电极与所述柱形相变材料层自上而下依次连接，所述环状柱形选择器件层连接所述底电极，其中，所述相变单元的柱体截面包括圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
进一步地，步骤S2中，第一凹槽或通孔结构的横向尺寸小于等于底电极的顶面横向尺寸，步骤S5中，所述加热电极的横向尺寸小于所述柱形相变材料层的横向尺寸。
从上述技术方案可以看出，本发明通过采用环状柱形散热层包覆相变电阻层使电流密度和热量分布更加集中，从而固定有效相变操作区域。通过环状柱形散热层的包覆，相变电阻层的有效相变操作区域体积减小，降低了器件功耗。同时，环状柱形散热层与相变电阻层的非有效相变操作区域的接触面积增大，减小非有效相变操作区域的热量聚集，降低非有效相变操作区域转化为有效相变操作区域的可能，提高器件可靠性。
附图说明
图1为基于现有技术实现的相变存储器单元截面示意图；
图2为基于现有技术实现的有效相变操作区域的示意图；
图3为本发明实施例提出的相变存储器单元的制备方法流程示意图；
图4－图9为本发明实施例提出的相变存储器单元的制备方法对应的产品截面示意图；
图10为现有技术的相变存储器单元的电流密度和热量分布仿真结果示 意图；
图11为本发明实施例的相变存储器单元的电流密度和热量分布仿真结果示意图。
发明内容
下面结合附图3-11，对本发明的具体实施方式作进一步的详细说明。
图4－图9为本发明实施例提出的相变存储器单元的制备方法对应的产品截面示意图。如图4-9所示，该相变存储器单元设于衬底101上。衬底101上可设有一至多层介质层，例如，第一介质层102、第二介质层104、第三介质层110和第四介质层112；相变存储器单元可嵌设于所述一至多层介质层内。
具体地，该相变存储器单元从下到上依次包括位于衬底上的底电极103、相变单元109、加热电极111和顶电极113。所述相变单元109为纵向连接设置于所述底电极103上的柱体，其由内而外依次设置有柱形相变材料层108、环状柱形散热层107和环状柱形选择器件层106；所述顶电极113、所述加热电极111与所述柱形相变材料层108自上而下依次连接，所述环状柱形选择器件层106连接所述底电极103。其中，所述相变单元109的柱体截面可以包括圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合等，此外，环状柱形散热层107和环状柱形选择器件层106的截面可以包括圆形环、椭圆形环、矩形环、菱形环及多边形环中的一种或多种组合环等。
衬底101可以包括半导体材料，如硅衬底、砷化镓衬底、锗衬底、锗硅衬底或全耗尽型绝缘层上硅(FDSOI)衬底。衬底101也可以是集成电路， 包括具有选通管如三极管、二极管等的集成电路。
具体地，底电极103可同时位于衬底101及第一介质层102内。例如，底电极103的下部分位于衬底101内，上部分露出衬底101表面，并位于第一介质层102内。底电极103可为柱体结构，例如图示的圆台形。底电极103可以为钨电极，但不限于此。
在本发明的实施例中，所述加热电极111与柱形相变材料层108的一个接触面相连，所述环状柱形散热层107和所述环状柱形选择器件层106依次包覆所述柱形相变材料层108的剩余接触面。较佳地，所述加热电极111的底部位于柱形相变材料层108顶部表面的范围内，所述加热电极111的顶部连接所述顶电极113的下端。
较佳地，加热电极111为纵向设于所述柱形相变材料层上的柱形或通孔结构，并对应连接在所述顶电极的下端，加热电极的横向尺寸小于柱形相变材料层的横向尺寸。相变单元109的横向尺寸小于等于底电极103的顶面横向尺寸。
所述环状柱形散热层的材料可以选择具有稳定化学性质的材料，例如，该材料需要在600℃和5分钟退火后，环状柱形散热层的材料组分不扩散。进一步地，所述环状柱形散热层的材料导热性良好，较佳地，导热系数大于100W/mK。环状柱形散热层107的材料可以包括石墨烯、含碳化合物、二维材料、Ta、碳氮化钨、氮化钨和TaN中的至少一种。
进一步地，所述环状柱形选择器件层形成的选择器件可以包括二维材料晶体管、双向阈值开关(Ovonic Threshold Switch，OTS)和金属氧化物薄膜(MOx)电阻开关中的一种。同时，环状柱形选择器件层的材料不会在相变 存储器操作过程中发生阻变或相变。
在本实施例中，柱形相变材料层108初始状态可以为晶态。柱形相变材料层108的材料包括GeTe-Sb 2Te 3体系、GeTe-SnTe体系、Sb 2Te体系、In 3SbTe 2体系、Sb掺杂体系、掺杂Sc、Ag、In 2、Al、In、C、S、Se、N、Cu、W元素的GeTe-Sb 2Te 3体系/GeTe-SnTe体系/Sb 2Te体系/In 3SbTe 2体系/Sb掺杂体系中的至少一种。
图3为本发明实施例中提出的相变存储器单元的制备方法流程示意图。如图3所示，本发明的一种相变存储器单元的制备方法，包括：
S1：在衬底101上沉积形成第一介质层102，并在衬底101和第一介质层102中形成底电极103。在本实施例中，底电极103为上大下小的圆台形电极(如图4所示)。其中，可使底电极103的下半部分位于衬底101中，上半部分位于第一介质层102中。
S2：在第一介质层102上沉积第二介质层104，并在所述底电极103上形成第一凹槽或通孔结构105，所述第一凹槽或通孔结构105贯通所述第二介质层104(如图5所示)。
从俯视来看，第一凹槽或通孔105可采用圆形、椭圆形、矩形和多边形中的一种。在本实施例中，在第二介质层104中形成圆柱形第一通孔105。其中，第一通孔105的横向尺寸小于底电极103的顶面(相邻所述第一通孔105)横向尺寸。
S3：在所述第二介质层104上依次形成填充所述第一凹槽或通孔结构105的环状柱形选择器件层106，环状柱形散热层107和柱形相变材料层108；环状柱形选择器件层106与底电极103相连，柱形相变材料层108填满第一 凹槽105(如图6所示)。
在本实施例中，环状柱形选择器件层106的材料采用可以形成双向阈值开关的相变材料GeSeAs 2，采用化学气相沉积方式沉积形成GeSeAs 2薄膜，所述GeSeAs 2薄膜为非晶态，在柱形相变材料层108操作过程中，所述GeSeAs 2薄膜作为选通器件，相态不会发生变化。
环状柱形散热层107的材料包括导电材料，并且化学性质稳定，在高温下(600℃)不会和环状柱形选择器件层106的材料、柱形相变材料层108的材料发生化学反应或元素扩散。环状柱形散热层包覆柱形相变材料层，从而使电流密度和热量分布更加集中，由此固定有效相变操作区域。较佳地，环状柱形散热层107的材料采用TaN。
柱形相变材料层108可采用高密度等离子体化学气相淀积(HDP CVD)的方式沉积形成，沉积温度在200-500℃，沉积后的柱形相变材料层108为晶态。
为了得到三种薄膜之间的良好界面，可以在同一设备中实现沉积。
S4：采用化学机械抛光(CMP)工艺，去除所述第二介质层104上的环状柱形选择器件层106、环状柱形散热层107和柱形相变材料层108，在所述第二介质层104中形成相变单元109(如图7所示)。
S5：在所述第二介质层104上沉积第三介质层110，在所述第三介质层110中形成连接所述环状柱形选择器件层的加热电极111(如图8所示)。
S6：在所述第三介质层110上沉积第四介质层112，在所述第四介质层中形成连接所述加热电极的顶电极113(如图9所示)。
上述方法采用凹槽或通孔填充和化学机械抛光的方式，制备出具有立体 柱形嵌套结构的相变单元，可以由1个选择器件和1个相变电阻组成。
图10为现有技术的相变存储器单元的电流密度和热量分布仿真结果示意图。图11为本发明实施例的相变存储器单元的电流密度和热量分布仿真结果示意图。
在本实施例中，加热电极相连柱形相变材料层的一个接触面，环状柱形散热层将柱形相变材料层的其他接触面包覆，使柱形相变材料层的有效相变操作区域相邻于与加热电极相连的接触面(如图11所示)，同现有相变结构(图10所示)相比，电流密度和热量分布更加集中，从而固定有效相变操作区域。通过环状柱形散热层的包覆，相变电阻层有效相变操作区域体积减小，降低了器件功耗。同时，环状柱形散热层与相变电阻层的非有效相变操作区域的接触面积增大，减小非有效相变操作区域的热量聚集，降低非有效相变操作区域转化为有效相变操作区域的可能，提高器件可靠性。
此外，采用填充和抛光工艺制备相变单元，可有效避免随相变单元的横向尺寸减小，及刻蚀引起的侧壁相变材料损伤导致的器件可靠性问题。环状柱形散热层采用具有稳定的化学性质和良好的导热性，不会影响相变单元的器件性能。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (9)

  1. 一种相变存储器单元，其特征在于，从下到上依次包括：位于衬底上的底电极、相变单元、加热电极和顶电极；其中，
    所述相变单元为纵向连接设置于所述底电极上的柱体，并由内而外依次设置有同心的柱形相变材料层、环状柱形散热层和环状柱形选择器件层；所述顶电极、所述加热电极、与所述柱形相变材料层自上而下依次连接，所述环状柱形选择器件层连接所述底电极，其中，所述相变单元的柱体截面包括圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
  2. 根据权利要求1所述的相变存储器单元，其特征在于，所述加热电极相连柱形相变材料层的一个接触面，所述环状柱形散热层和所述环状柱形选择器件层依次包覆所述柱形相变材料层的剩余接触面，其中，所述加热电极纵向设于柱形相变材料层的顶部表面，并底部位于柱形相变材料层顶部表面的范围内，且顶部连接所述顶电极的下端。
  3. 根据权利要求1所述的相变存储器单元，其特征在于，所述柱形相变材料层初始状态为晶态；所述柱形相变材料层的材料包括GeTe-Sb 2Te 3体系、GeTe-SnTe体系、Sb 2Te体系、In 3SbTe 2体系、Sb掺杂体系、掺杂Sc、Ag、In 2、Al、In、C、S、Se、N、Cu、W元素的GeTe-Sb 2Te 3体系/GeTe-SnTe体系/Sb 2Te体系/In 3SbTe 2体系/Sb掺杂体系中的至少一种。
  4. 根据权利要求1所述的相变存储器单元，其特征在于，所述加热电极的柱体截面包括环形、圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
  5. 根据权利要求1所述的相变存储器单元，其特征在于，所述环状柱 形散热层的材料的导热系数大于100W/mK。
  6. 根据权利要求1所述的相变存储器单元，其特征在于，所述环状柱形选择器件层形成的选择器件为二维材料晶体管、双向阈值开关和金属氧化物薄膜电阻开关中的一种。
  7. 根据权利要求1所述的相变存储器单元，其特征在于，所述环状柱形散热层的材料包括石墨烯、含碳化合物，二维材料、Ti、W，Ta、Cu、碳氮化钨、氮化钨、TaN中的至少一种。
  8. 一种相变存储器单元的制备方法，其特征在于，包括以下步骤：
    S1：提供衬底，在所述衬底上沉积第一介质层，在所述衬底和第一介质层中形成底电极；
    S2：在所述第一介质层上沉积第二介质层，并在所述底电极上形成第一凹槽或通孔结构，所述第一凹槽或通孔结构贯通所述第二介质层；
    S3：在所述第二介质层上依次形成填充所述第一凹槽或通孔结构的环状柱形选择器件层，环状柱形散热层和柱形相变材料层；
    S4：采用化学机械抛光工艺，去除第二介质层上的所述环状柱形选择器件层、所述环状柱形散热层和所述柱形相变材料层，在第二介质层中形成所述相变单元；
    S5：在所述第二介质层上沉积第三介质层，在所述第三介质层中形成连接所述环状柱形选择器件层的加热电极；
    S6：在所述第三介质层上沉积第四介质层，在所述第四介质层中形成连接所述加热电极的顶电极；其中，所述顶电极、所述加热电极与所述柱形相变材料层自上而下依次连接，所述环状柱形选择器件层连接所述底电极，其 中，所述相变单元的柱体截面包括圆形、椭圆形、矩形、菱形及多边形中的一种或多种组合。
  9. 根据权利要求8所述的相变存储器单元的制备方法，其特征在于，步骤S2中，第一凹槽或通孔结构的横向尺寸小于等于底电极的顶面横向尺寸，步骤S5中，所述加热电极的横向尺寸小于所述柱形相变材料层的横向尺寸。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113232A1 (en) * 2002-12-13 2004-06-17 Johnson Brian G. Phase change memory
CN1610950A (zh) * 2001-10-11 2005-04-27 英特尔公司 用于相变存储器的含碳分界表面层
CN1992368A (zh) * 2005-12-29 2007-07-04 东部电子股份有限公司 半导体器件以及该半导体器件的制造方法
CN101241966A (zh) * 2006-12-28 2008-08-13 旺宏电子股份有限公司 电阻随机存取存储单元装置
CN101512788A (zh) * 2006-08-15 2009-08-19 美光科技公司 使用能量转换层的相变存储器元件、包含相变存储器元件的存储器阵列及系统以及其制作及使用方法
CN107017276A (zh) * 2015-10-27 2017-08-04 三星电子株式会社 存储器装置及其制造方法
CN112635667A (zh) * 2020-12-30 2021-04-09 上海集成电路装备材料产业创新中心有限公司 一种相变存储器单元及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486306B1 (ko) * 2003-02-24 2005-04-29 삼성전자주식회사 셀프 히터 구조를 가지는 상변화 메모리 소자
CN100423231C (zh) * 2005-12-02 2008-10-01 中国科学院上海微系统与信息技术研究所 一种制备相变存储器纳米加热电极的方法
CN100565955C (zh) * 2008-01-22 2009-12-02 中国科学院上海微系统与信息技术研究所 用于相变存储器的过渡层
JP2010087007A (ja) * 2008-09-29 2010-04-15 Elpida Memory Inc 相変化メモリ装置及びその製造方法
KR101069701B1 (ko) * 2009-09-30 2011-10-04 주식회사 하이닉스반도체 리셋 커런트를 줄일 수 있는 상변화 메모리 장치, 그 제조방법 및 그것의 회로
CN102005466A (zh) * 2010-09-28 2011-04-06 中国科学院上海微系统与信息技术研究所 一种具有低k介质绝热材料的相变存储器结构及制备方法
CN103682089A (zh) * 2012-09-11 2014-03-26 中国科学院上海微系统与信息技术研究所 高速、高密度、低功耗的相变存储器单元及制备方法
CN102832342A (zh) * 2012-09-14 2012-12-19 中国科学院上海微系统与信息技术研究所 含有TiSiN材料层的相变存储单元及其制备方法
CN203812919U (zh) * 2014-04-02 2014-09-03 中国科学院苏州纳米技术与纳米仿生研究所 相变存储结构
CN107978675A (zh) * 2016-10-25 2018-05-01 中芯国际集成电路制造(上海)有限公司 相变随机存储器存储单元及其制作方法、电子装置
CN111146340B (zh) * 2019-12-19 2023-01-31 上海集成电路研发中心有限公司 一种相变存储器单元及其制备方法
CN112133825A (zh) * 2020-09-03 2020-12-25 中国科学院上海微系统与信息技术研究所 一种高稳定性相变存储单元及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1610950A (zh) * 2001-10-11 2005-04-27 英特尔公司 用于相变存储器的含碳分界表面层
US20040113232A1 (en) * 2002-12-13 2004-06-17 Johnson Brian G. Phase change memory
CN1992368A (zh) * 2005-12-29 2007-07-04 东部电子股份有限公司 半导体器件以及该半导体器件的制造方法
CN101512788A (zh) * 2006-08-15 2009-08-19 美光科技公司 使用能量转换层的相变存储器元件、包含相变存储器元件的存储器阵列及系统以及其制作及使用方法
CN101241966A (zh) * 2006-12-28 2008-08-13 旺宏电子股份有限公司 电阻随机存取存储单元装置
CN107017276A (zh) * 2015-10-27 2017-08-04 三星电子株式会社 存储器装置及其制造方法
CN112635667A (zh) * 2020-12-30 2021-04-09 上海集成电路装备材料产业创新中心有限公司 一种相变存储器单元及其制备方法

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