WO2020258800A1 - 新型mram中铜互联上底电极的制备方法 - Google Patents

新型mram中铜互联上底电极的制备方法 Download PDF

Info

Publication number
WO2020258800A1
WO2020258800A1 PCT/CN2019/128703 CN2019128703W WO2020258800A1 WO 2020258800 A1 WO2020258800 A1 WO 2020258800A1 CN 2019128703 W CN2019128703 W CN 2019128703W WO 2020258800 A1 WO2020258800 A1 WO 2020258800A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
bottom electrode
copper
barrier layer
electrode metal
Prior art date
Application number
PCT/CN2019/128703
Other languages
English (en)
French (fr)
Inventor
刘鲁萍
蒋信
王雷
Original Assignee
浙江驰拓科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浙江驰拓科技有限公司 filed Critical 浙江驰拓科技有限公司
Publication of WO2020258800A1 publication Critical patent/WO2020258800A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • the invention relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a copper interconnect upper bottom electrode in a novel MRAM.
  • MRAM Magnetic Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • STT spin transfer torque
  • the main functional unit in MRAM is the MTJ unit, and its structure mainly includes a magnetic free layer/non-magnetic oxide layer (MgO)/magnetic pinned layer. Driven by an external magnetic field or current, the direction of the magnetic moment of the magnetic free layer is reversed, and the direction of the magnetic moment of the magnetic pinned layer is parallel or anti-parallel, making MRAM appear high and low resistance states, which can be defined as storage states. 0" and "1" to realize the storage of information.
  • MgO magnetic free layer/non-magnetic oxide layer
  • the MTJ cell is built on the bottom electrode of the MRAM.
  • the bottom electrode of the MRAM needs to be prepared first.
  • the preparation process of the bottom electrode of MRAM is roughly as follows: provide a substrate, open a through hole on the substrate, deposit a copper barrier layer and a copper layer to form a copper interconnect structure, and then deposit a bottom on the copper interconnect structure An electrode metal layer and patterning the bottom electrode metal layer in a subsequent process to obtain an MRAM bottom electrode.
  • the copper layer needs to be chemically mechanically polished.
  • the current copper chemical mechanical polishing process at least two steps are performed on two grinding discs. First, the bulk of the copper layer needs to be polished, and the polishing end point is stopped on the copper barrier layer. Then, the polishing disc and polishing liquid and other consumables are used for chemical mechanical polishing of the copper barrier layer to remove the copper barrier layer and part of the dielectric. Floor. After the chemical mechanical polishing process of copper is completed, a bottom electrode metal layer is deposited and subsequent related processes are performed.
  • the present invention provides a method for preparing a copper interconnect upper bottom electrode in a novel MRAM. Due to the particularity of the MRAM bottom electrode material and process, there is no need to polish the copper barrier layer, and the process flow is simplified.
  • the invention provides a method for preparing a copper interconnect upper bottom electrode in a novel MRAM, including:
  • a substrate is provided.
  • the substrate includes a metal interconnection layer, a first barrier layer, and a dielectric layer stacked in sequence.
  • a bottom through hole is formed in the first barrier layer and the dielectric layer, and the bottom through hole is connected to the bottom through hole.
  • the metal interconnection layer is connected;
  • the second barrier layer as a polishing end point, chemical mechanical polishing is performed on the copper layer, and polishing is performed after detecting the second barrier layer to completely remove the copper layer on the second barrier layer ;
  • the bottom electrode metal layer is patterned to obtain the MRAM bottom electrode.
  • the patterning the bottom electrode metal layer includes:
  • the etching end point is stopped at the dielectric layer, and the bottom electrode metal layer and the second barrier layer are sequentially etched according to the photolithography pattern.
  • the material of the bottom electrode metal layer is any one or a mixture of TaN, Ta, TiN and Ti.
  • the material of the second barrier layer is any one or a mixture of several of TaN, Ta, TiN, Ti, Co, and Ru.
  • the material of the dielectric layer is silicon oxide SiO, silicon dioxide SiO 2 , carbon oxide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, ortho silicon Ethyl acid TEOS, Low-K dielectric or Ultra-Low-K dielectric.
  • the material of the first barrier layer is silicon oxynitride, silicon nitride, silicon carbonitride or silicon carbide.
  • the polishing end point stops at the second barrier layer below the copper layer, that is, only the bulk is processed in the copper chemical mechanical polishing process.
  • the copper is polished without polishing the copper barrier layer, which simplifies the process flow, improves production efficiency and reduces the risk of process stability.
  • FIG. 1 is a schematic flowchart of a method for preparing a copper interconnect upper bottom electrode in an MRAM according to an embodiment of the present invention
  • Fig. 2 is a schematic diagram of a substrate structure in an embodiment of the present invention.
  • Figure 3 is a schematic diagram of the structure after depositing the second barrier layer and the copper layer;
  • Figure 4 is a schematic diagram of the structure after chemical mechanical polishing
  • Figure 5 is a schematic diagram of the structure after depositing a bottom electrode metal layer
  • FIG. 6 is a schematic diagram of the structure after patterning the bottom electrode metal layer
  • 7-8 are schematic diagrams of another embodiment of patterned bottom electrode metal layer
  • 9-12 are schematic diagrams of another embodiment of the patterned bottom electrode metal layer.
  • the embodiment of the present invention provides a method for preparing a copper interconnect upper bottom electrode in a novel MRAM. As shown in FIG. 1, the method includes:
  • the substrate includes a metal interconnection layer, a first barrier layer, and a dielectric layer stacked in sequence.
  • a bottom through hole is formed in the first barrier layer and the dielectric layer, and the bottom through hole Connected to the metal interconnection layer;
  • a substrate is provided.
  • the substrate includes a metal interconnection layer 201, a first barrier layer 202, and a dielectric layer 203 stacked in sequence, and the first barrier layer 202 and the dielectric layer A bottom through hole is formed in 203, and the bottom through hole is connected to the metal interconnection layer 201.
  • the material of the first barrier layer 202 is silicon oxynitride, silicon nitride, silicon carbonitride, or silicon carbide.
  • the material of the electrical layer 203 is silicon oxide SiO, silicon dioxide SiO 2 , carbon oxide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, tetraethyl orthosilicate TEOS, Low -K dielectric or Ultra-Low-K dielectric.
  • the bottom through hole can use conventional photolithography and etching techniques to define a pattern on the dielectric layer 203, and selectively etch to remove part of the first barrier layer 202 and the dielectric layer 203, and stop on the metal interconnection layer 201 to form Bottom through hole required for metal interconnection.
  • a second barrier layer 204 and a copper layer 205 are sequentially deposited on the surface of the substrate, and the copper layer 205 fills the bottom through hole.
  • the second barrier layer 204 covers the bottom surface and the side surface of the bottom through hole of the substrate, and covers the surface of the substrate outside the bottom through hole.
  • the second barrier layer 204 is formed by physical vapor deposition.
  • the materials used include but not Limited to any one or a mixture of TaN, Ta, TiN, Ti, Co and Ru.
  • a copper layer 205 is formed above the second barrier layer 204, a copper seed layer is formed by physical vapor deposition, and then a copper layer 205 is formed by electroplating.
  • the copper layer 205 is filled with bottom vias, and the thickness of the copper layer 205 is greater than that of the bottom vias. depth.
  • step S103 as shown in FIG. 4, with the second barrier layer 204 as a polishing end point, the copper layer 205 is chemically mechanically polished, and after the second barrier layer 204 is detected, polishing is performed to The copper layer on the second barrier layer 204 is completely removed.
  • a bottom electrode metal layer 206 is deposited on the polished interface.
  • the material of the bottom electrode metal layer 206 includes, but is not limited to, any one or more of TaN, Ta, TiN, and Ti. mixture.
  • step S105 the patterning of the bottom electrode is completed before depositing the MTJ multilayer film, and the bottom electrode metal layer 206 is lithographically and etched to obtain MRAM bottom electrodes 2061 and 2062.
  • the metal layer 206 and the second barrier layer 204 further obtain MRAM bottom electrodes 2061 and 2062.
  • step S105 another embodiment is shown in FIGS. 7-8.
  • the patterning of the bottom electrode can be completed together with the patterning of the subsequently prepared MTJ multilayer film.
  • FIG. 7 after the bottom electrode metal layer 206 is deposited on the polished interface, an MTJ multilayer film 207 is further deposited on the bottom electrode metal layer 206.
  • FIG. 8 the bottom electrode metal layer 206 and the MTJ multilayer film 207 are lithographically and etched simultaneously to form bottom electrodes 2063 and 2064 and MTJ cells 2071 and 2072.
  • step S105 another embodiment is shown in FIGS. 9-12, and the patterning of the bottom electrode can optionally be completed together with the patterning of the top electrode prepared later.
  • an MTJ multilayer film 207 is further deposited on the bottom electrode metal layer 206 (as shown in FIG. 7), and only the MTJ multilayer The film 207 is subjected to photolithography and etching to form MTJ cells 2073 and 2074.
  • a dielectric layer 208 is deposited, the material of which is silicon oxide SiO, silicon dioxide SiO 2 , oxycarbide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicon Glass BPSG, tetraethyl orthosilicate TEOS, Low-K dielectric or Ultra-Low-K dielectric, and polish the dielectric layer 208, stop on the surface of the MTJ unit 2073, 2074.
  • a top electrode metal layer 209 is deposited, the material of which includes but is not limited to any one or a mixture of TaN, Ta, TiN and Ti.
  • top electrodes 2091 and 2092 perform photolithography and etching on the top electrode metal layer 209, and simultaneously etch away the bottom electrode metal layer 206 and the second barrier layer 204, stop at the dielectric layer 203, and form bottom electrodes 2065, 2066 at the same time. And top electrodes 2091 and 2092.
  • the method for preparing the upper bottom electrode of the copper interconnection in the MRAM provided by the embodiment of the present invention, when the copper layer is chemically and mechanically polished, the polishing end point stops at the second barrier layer below the copper layer, that is, in the copper layer.
  • the chemical mechanical polishing process only bulk copper is polished without polishing the copper barrier layer, which simplifies the process flow, improves production efficiency and reduces the risk of process stability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

本发明提供一种新型MRAM中铜互联上底电极的制备方法，包括：提供一基底，所述基底包括依次堆叠设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连；在所述基底表面依次沉积第二阻挡层和铜层，所述铜层充满所述底部通孔；以所述第二阻挡层作为抛光终点，对所述铜层进行化学机械抛光，并在检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层之上的铜层；在抛光后的界面上沉积底电极金属层；图案化所述底电极金属层，得到MRAM底电极。本发明能够简化并彻底颠覆现有大马士革铜的化学机械抛光工艺，提高生产效率并降低工艺稳定性风险。

Description

新型MRAM中铜互联上底电极的制备方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种新型MRAM中铜互联上底电极的制备方法。
背景技术
近年来，采用MTJ(Magnetic Tunnel Junction，磁性隧道结)的磁电阻效应的MRAM(Magnetic Random Access Memory，磁性随机存储器)被认为是未来的固态非易失性记忆体，相比于目前其他类型的存储器，具有读写速度快、可实现无限次擦写、易于与目前的半导体工艺相兼容等优点，此外利用自旋流来实现磁矩翻转的自旋传输扭矩(Spin transfer torque,STT)的MRAM可实现存储单元尺寸的微缩。这些优点使得MRAM成为未来新型存储器的主要发展方向。
在MRAM中的主要功能单元为MTJ单元，其结构主要包括磁性自由层/非磁性氧化层(MgO)/磁性钉扎层。在外加磁场或电流等驱动下，磁性自由层的磁矩方向发生翻转，与磁性钉扎层的磁矩方向呈现平行态或反平行态，使得MRAM出现高低电阻态，可分别定义为存储态“0”和“1”，从而实现信息的存储。
MTJ单元是建立在MRAM底电极上，制备MTJ单元之前，首先需要制备MRAM底电极。按照现有的工艺，MRAM底电极的制备流程大致为：提供一基底，在基底上开设通孔，并沉积铜阻挡层和铜层进而形成铜互连结构，然后在铜互连结构上沉积底电极金属层并在后续工艺中图案化所述底电极金属层得到MRAM底电极。其中，在形成铜互连结构时，需要对铜层进行化学机械抛光。
在目前铜的化学机械抛光工艺中，至少分两步在两个研磨盘上进行。首先需要先对大块铜层进行抛光，将抛光终点停止在铜的阻挡层之上，之后转换研磨盘及研磨液等耗材对铜阻挡层进行化学机械抛光，除去铜的阻挡层及部分介电层。完成铜的化学机械抛光工艺后沉积底电极金属层并进行后续相关工艺。
在上述传统的大马士革铜化学机械抛光工艺中，由于涉及到铜阻挡层和介电层的抛光，因此必须配置铜和铜阻挡层化学机械抛光两步工艺所需的多种不同的耗材以满足工艺要求，两步工艺生产效率低，并且多种材料的引入增加了工艺稳定性的风险，进而影响器件的良率。
发明内容
为解决上述问题，本发明提供一种新型MRAM中铜互联上底电极的制备方法，由于MRAM底电极材料和工艺的特殊性，无需对铜阻挡层进行抛光，简化了工艺流程。
本发明提供一种新型MRAM中铜互联上底电极的制备方法，包括：
提供一基底，所述基底包括依次堆叠设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连；
在所述基底表面依次沉积第二阻挡层和铜层，所述铜层充满所述底部通孔；
以所述第二阻挡层作为抛光终点，对所述铜层进行化学机械抛光，并在检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层之上的铜层；
在抛光后的界面上沉积底电极金属层；
图案化所述底电极金属层，得到MRAM底电极。
可选地，所述图案化所述底电极金属层包括：
通过光刻和刻蚀工艺对所述底电极金属层图案化；
将刻蚀终点停止在所述介电层，按照光刻图形依次刻蚀所述底电极金属层和所述第二阻挡层。
可选地，所述底电极金属层的材料为TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
可选地，所述第二阻挡层的材料为TaN、Ta、TiN、Ti、Co和Ru中的任意一种或者几种的混合物。可选地，所述介电层的材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质。
可选地，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
本发明提供的MRAM中铜互联上底电极的制备方法，对铜层进行化学机械抛光时，抛光终点停止在铜层下方的第二阻挡层，即在铜的化学机械抛光工艺中只对大块铜进行抛光而无需对铜阻挡层进行抛光，简化了工艺流程，提高了生产效率并降低了工艺稳定性风险。
附图说明
图1为本发明一实施例的MRAM中铜互联上底电极的制备方法的流程示意图；
图2为本发明实施例中的基底结构示意图；
图3为沉积第二阻挡层和铜层后的结构示意图；
图4为进行化学机械抛光后的结构示意图；
图5为沉积底电极金属层后的结构示意图；
图6为图案化底电极金属层后的结构示意图；
图7-图8为图案化底电极金属层的另一实施例的示意图；
图9-图12为图案化底电极金属层的又一实施例的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种新型MRAM中铜互联上底电极的制备方法，如图1所示，所述方法包括：
S101、提供一基底，所述基底包括依次堆叠设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连；
S102、在所述基底表面依次沉积第二阻挡层和铜层，所述铜层充满所述底部通孔；
S103、以所述第二阻挡层作为抛光终点，对所述铜层进行化学机械抛光，并在检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层之上的铜层；
S104、在抛光后的界面上沉积底电极金属层；
S105、图案化所述底电极金属层，得到MRAM底电极。
关于步骤S101，如图2所示，提供一基底，所述基底包括依次堆叠设置的金属互联层201、第一阻挡层202以及介电层203，在所述第一阻挡层202及介电层203中形成有底部通孔，所述底部通孔与所述金属互联层201相连， 其中，第一阻挡层202的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅，介电层203的材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质。底部通孔可以采用常规的光刻和刻蚀技术，在介电层203上定义图案，并选择刻蚀去除部分第一阻挡层202和介电层203，停止于金属互联层201上，从而形成金属互联线所需要的底部通孔。
关于步骤S102，如图3所示，在所述基底表面依次沉积第二阻挡层204和铜层205，所述铜层205充满所述底部通孔。
具体地，第二阻挡层204覆盖于基底的底部通孔中的底面和侧面，且覆盖于底部通孔外基底的表面，第二阻挡层204采用物理气相沉积法形成，使用的材料包括但不限于TaN、Ta、TiN、Ti、Co和Ru中的任意一种或者几种的混合物。
在第二阻挡层204上方形成铜层205，利用物理气相沉积形成铜的种子层，之后利用电镀的方法形成铜层205，铜层205充满底部通孔，铜层205的厚度大于底部通孔的深度。
关于步骤S103，如图4所示，以所述第二阻挡层204作为抛光终点，对所述铜层205进行化学机械抛光，并在检测到所述第二阻挡层204后进行过抛光，以完全去除所述第二阻挡层204之上的铜层。
关于步骤S104，如图5所示，在抛光后的界面上沉积底电极金属层206，底电极金属层206的材料包括但不限于TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
关于步骤S105，一种实施例如图6所示，底电极的图案化在沉积MTJ多层膜之前完成，对所述底电极金属层206进行光刻和刻蚀，得到MRAM底电 极2061和2062。在该步骤中，首先在底电极金属层206表面涂光刻胶，图形化所述底电极金属层206，然后以介电层203为刻蚀终点，按照光刻图形依次刻蚀所述底电极金属层206和所述第二阻挡层204，进而得到MRAM底电极2061和2062。
关于步骤S105，另一种实施例如图7-8所示，底电极的图案化可选择同后续制备的MTJ多层膜的图案化一起完成。如图7所示，在抛光后的界面上沉积底电极金属层206之后，在底电极金属层206上进一步沉积MTJ多层膜207。接下来如图8所示，对底电极金属层206和MTJ多层膜207同时进行光刻和刻蚀，形成底电极2063、2064及MTJ单元2071、2072。
关于步骤S105，又一种实施例如图9-12所示，底电极的图案化也可选择同后续制备的顶电极的图案化一起完成。如图9所示，在抛光后的界面上沉积底电极金属层206之后，在底电极金属层206上进一步沉积MTJ多层膜207(如图7所示)，并仅对所述MTJ多层膜207进行光刻和刻蚀，形成MTJ单元2073、2074。接下来如图10所示，沉积介电层208，其材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质，并对介电层208进行抛光，停止于MTJ单元2073、2074的表面。接下来如图11所示，沉积顶电极金属层209，其材料包括但不限于TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。接下来如图12所示，对顶电极金属层209进行光刻和刻蚀，同时刻蚀掉底电极金属层206和第二阻挡层204，停止于介质层203，同时形成底电极2065、2066和顶电极2091、2092。
之后进行后续所需工艺。
通过上述实施例可以看出，本发明实施例提供的MRAM中铜互联上底电 极的制备方法，对铜层进行化学机械抛光时，抛光终点停止在铜层下方的第二阻挡层，即在铜的化学机械抛光工艺中只对大块铜进行抛光而无需对铜阻挡层进行抛光，简化了工艺流程，同时提高了生产效率并降低了工艺稳定性的风险。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (6)

  1. 一种新型MRAM中铜互联上底电极的制备方法，其特征在于，包括：
    提供一基底，所述基底包括依次堆叠设置的金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连；
    在所述基底表面依次沉积第二阻挡层和铜层，所述铜层充满所述底部通孔；
    以所述第二阻挡层作为抛光终点，对所述铜层进行化学机械抛光，并在检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层之上的铜层；
    在抛光后的界面上沉积底电极金属层；
    图案化所述底电极金属层，得到MRAM底电极。
  2. 根据权利要求1所述的方法，其特征在于，所述图案化所述底电极金属层包括：
    通过光刻和刻蚀工艺对所述底电极金属层图案化；
    将刻蚀终点停止在所述介电层，按照光刻图形依次刻蚀所述底电极金属层和所述第二阻挡层。
  3. 根据权利要求1所述的方法，其特征在于，所述底电极金属层的材料为TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
  4. 根据权利要求1所述的方法，其特征在于，所述第二阻挡层的材料为TaN、Ta、TiN、Ti、Co和Ru中的任意一种或者几种的混合物。
  5. 根据权利要求1所述的方法，其特征在于，所述介电层的材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅 玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质。
  6. 根据权利要求1所述的方法，其特征在于，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
PCT/CN2019/128703 2019-06-25 2019-12-26 新型mram中铜互联上底电极的制备方法 WO2020258800A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910552556.4A CN112133821A (zh) 2019-06-25 2019-06-25 新型mram中铜互联上底电极的制备方法
CN201910552556.4 2019-06-25

Publications (1)

Publication Number Publication Date
WO2020258800A1 true WO2020258800A1 (zh) 2020-12-30

Family

ID=73849622

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/128703 WO2020258800A1 (zh) 2019-06-25 2019-12-26 新型mram中铜互联上底电极的制备方法

Country Status (2)

Country Link
CN (1) CN112133821A (zh)
WO (1) WO2020258800A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4730541B2 (ja) * 2006-03-15 2011-07-20 セイコーエプソン株式会社 強誘電体メモリおよびその製造方法
JP4785436B2 (ja) * 2005-06-13 2011-10-05 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリ装置の製造方法
CN109216541A (zh) * 2017-06-30 2019-01-15 中电海康集团有限公司 Mram与其的制作方法
CN109560103A (zh) * 2017-09-27 2019-04-02 中电海康集团有限公司 磁阻式随机存储器及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5243746B2 (ja) * 2007-08-07 2013-07-24 ルネサスエレクトロニクス株式会社 磁気記憶装置の製造方法および磁気記憶装置
US8681536B2 (en) * 2010-01-15 2014-03-25 Qualcomm Incorporated Magnetic tunnel junction (MTJ) on planarized electrode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4785436B2 (ja) * 2005-06-13 2011-10-05 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリ装置の製造方法
JP4730541B2 (ja) * 2006-03-15 2011-07-20 セイコーエプソン株式会社 強誘電体メモリおよびその製造方法
CN109216541A (zh) * 2017-06-30 2019-01-15 中电海康集团有限公司 Mram与其的制作方法
CN109560103A (zh) * 2017-09-27 2019-04-02 中电海康集团有限公司 磁阻式随机存储器及其制备方法

Also Published As

Publication number Publication date
CN112133821A (zh) 2020-12-25

Similar Documents

Publication Publication Date Title
US20210226121A1 (en) Semiconductor device
US10790439B2 (en) Memory cell with top electrode via
US8456883B1 (en) Method of spin torque MRAM process integration
US20190252610A1 (en) Memory device and fabrication method thereof
US7122386B1 (en) Method of fabricating contact pad for magnetic random access memory
US20070012905A1 (en) Novel phase change random access memory
US11217627B2 (en) Magnetic random access memory device and formation method thereof
US11264561B2 (en) Magnetic random access memory device and formation method thereof
TWI694622B (zh) 在互連中之嵌入ｍｒａｍ及其製造方法
EP3772117B1 (en) Method for forming a semiconductor structure
US11551736B2 (en) Semiconductor device and method for fabricating the same
CN109216541B (zh) Mram与其的制作方法
US8524511B1 (en) Method to connect a magnetic device to a CMOS transistor
CN111261773A (zh) 半导体存储器元件及其制作方法
TW202030882A (zh) 磁性儲存裝置
CN107785483B (zh) 一种磁性随机存储器的制作方法
US11594679B2 (en) Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height
WO2021077756A1 (zh) 包括mram底电极制作工艺的制作方法及mram器件
CN102593353B (zh) 一种阻变存储器及其制造方法
WO2020258800A1 (zh) 新型mram中铜互联上底电极的制备方法
WO2020258799A1 (zh) 自对准的mram底电极制备方法
WO2020259220A1 (zh) Mram底电极的制备方法
CN109980081B (zh) 可自停止抛光的mram器件的制作方法与mram器件
US20220359815A1 (en) Memory cell with top electrode via
TWI801885B (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19935430

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19935430

Country of ref document: EP

Kind code of ref document: A1