WO2020259220A1 - Mram底电极的制备方法 - Google Patents

Mram底电极的制备方法 Download PDF

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WO2020259220A1
WO2020259220A1 PCT/CN2020/093755 CN2020093755W WO2020259220A1 WO 2020259220 A1 WO2020259220 A1 WO 2020259220A1 CN 2020093755 W CN2020093755 W CN 2020093755W WO 2020259220 A1 WO2020259220 A1 WO 2020259220A1
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layer
bottom electrode
barrier layer
electrode metal
conductive metal
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王雷
陈桂霖
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浙江驰拓科技有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

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  • the invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a bottom electrode of an MRAM.
  • MRAM magnetic random access memory
  • MTJ magnetic tunnel junction
  • the main structure of MRAM is a transistor and an MTJ cell.
  • the MTJ cell is mainly composed of a reference layer, an insulating barrier layer and a free layer located between the bottom electrode and the top electrode.
  • the direction of the magnetic moment of the reference layer is pinned and it is difficult to change the direction of the magnetic moment, while the direction of the magnetic moment of the free layer is easier to change under the action of an external magnetic field or current.
  • the MTJ unit uses the quantum tunneling effect to make polarized electrons pass through the insulating barrier layer, where the tunneling probability of the polarized electrons is related to the relative magnetization direction between the reference layer and the free layer.
  • the polarization electron tunneling probability is higher, and the MTJ unit shows a low resistance state; when the free layer and the reference layer have the opposite magnetization direction, the polarization electron tunneling probability is lower, and the MTJ
  • MRAM uses the high and low resistance states of the MTJ cell to represent the "1" and "0" of the logic state, thereby realizing data storage.
  • the MTJ unit For the MTJ unit, it is mainly composed of multiple layers of thin films stacked repeatedly. In order to ensure that it has good data reading and writing capabilities, it often has high requirements for the thin film in terms of crystal structure and thickness, and high quality
  • the preparation of the thin film generally has a strong dependence on the flatness and roughness of the bottom electrode. Therefore, in the preparation of MRAM devices, the flatness of the bottom electrode will directly affect the performance of the subsequent MTJ cell, and how to provide a flat MRAM bottom electrode has always been a technical problem to be solved.
  • the present invention provides a method for preparing the bottom electrode of MRAM, which can simplify the method for preparing the bottom electrode of MRAM and improve the flatness of the bottom electrode.
  • the present invention provides a method for preparing a bottom electrode of MRAM, including:
  • a substrate is provided, the substrate includes a metal interconnection layer, a first barrier layer, and a dielectric layer in sequence.
  • a bottom through hole is formed in the first barrier layer and the dielectric layer, and the bottom through hole is interconnected with the metal
  • the layers are connected, and the surface of the substrate is sequentially covered with a second barrier layer and a conductive metal layer, and the conductive metal layer fills the bottom through hole;
  • the bottom electrode metal layer is photoetched and etched to obtain the MRAM bottom electrode.
  • the chemical mechanical polishing of the conductive metal layer includes: stopping the polishing end point at the second barrier layer, and performing polishing after the second barrier layer is detected according to an end point detection method to completely The conductive metal layer above the second barrier layer is removed.
  • the thickness of the bottom electrode metal deposited for the first time is greater than the depth of the dish-shaped recess.
  • the bottom electrode metal deposited for the second time is the same or different from the bottom electrode metal deposited for the first time.
  • the material of the bottom electrode metal is any one or a mixture of TaN, Ta, TiN and Ti.
  • the material of the conductive metal layer is one or a mixture of Cu, W and Al.
  • the material of the second barrier layer is any one or a mixture of Ta, TaN, Ti, TiN, Co, and Ru.
  • the material of the dielectric layer is silicon oxide SiO, silicon dioxide SiO 2 , carbon oxide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, ortho silicon Ethyl acid TEOS, Low-K dielectric or Ultra-Low-K dielectric.
  • the material of the first barrier layer is silicon oxynitride, silicon nitride, silicon carbonitride or silicon carbide.
  • the method for preparing the bottom electrode of MRAM omits the step of polishing the second barrier layer and the dielectric layer when performing CMP on the conductive metal layer, which simplifies the preparation of the bottom electrode of MRAM
  • the bottom electrode of the MRAM with a flat surface can be prepared, which solves the problem of the dish-shaped depression in the bottom through hole after CMP of the conductive metal layer.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a bottom electrode of MRAM according to an embodiment of the present invention
  • 2-9 are schematic cross-sectional views of various steps of a method for preparing a bottom electrode of MRAM according to an embodiment of the present invention.
  • An embodiment of the present invention provides a method for preparing a bottom electrode of MRAM. As shown in FIG. 1, the method includes the following steps:
  • the substrate includes a metal interconnection layer, a first barrier layer, and a dielectric layer in sequence.
  • a bottom through hole is formed in the first barrier layer and the dielectric layer, and the bottom through hole is connected to the The metal interconnection layers are connected, and the surface of the substrate is sequentially covered with a second barrier layer and a conductive metal layer, and the conductive metal layer fills the bottom through hole;
  • S102 Perform chemical mechanical polishing on the conductive metal layer to remove the conductive metal layer above the second barrier layer;
  • S106 Perform photolithography and etching on the bottom electrode metal layer to obtain an MRAM bottom electrode.
  • the method for preparing the bottom electrode of MRAM omits the step of polishing the second barrier layer and the dielectric layer when performing CMP on the conductive metal layer, which simplifies the preparation of the bottom electrode of MRAM
  • the bottom electrode of the MRAM with a flat surface can be prepared, which solves the problem of the dish-shaped depression in the bottom through hole after CMP of the conductive metal layer.
  • the initial structure of the substrate is shown in FIG. 2, and includes a metal interconnection layer 201 from bottom to top (the metal interconnection layer 201 includes a silicon substrate and is on the substrate All the necessary structures and devices, including CMOS and intermediate metal interconnection layers, the first barrier layer 202 and the dielectric layer 203, are prepared by the previous process.
  • bottom through holes are formed in the first barrier layer 202 and the dielectric layer 203, and the bottom through holes are connected to the metal interconnection layer 201, wherein the material of the first barrier layer 202 includes but It is not limited to one of silicon oxynitride compound, silicon nitride, silicon carbonitride compound, and silicon carbide, and is used to prevent ion diffusion of the metal interconnection layer 201.
  • the material of the dielectric layer 203 includes, but is not limited to, silicon oxide SiO, silicon dioxide SiO 2 , carbon oxide CDO, silicon nitride SiN, fluorosilicate glass FSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, and orthosilicate Ester TEOS (chemical formula Si(OC 2 H 5 ) 4 ), one of Low-K dielectric and Ultra-Low-K dielectric.
  • the bottom through hole can use conventional photolithography and etching techniques to define a pattern on the dielectric layer 203, and selectively etch to remove part of the first barrier layer 202 and the dielectric layer 203, and stop on the metal interconnection layer 201 to form Bottom through hole required for metal interconnection.
  • a second barrier layer 204 and a conductive metal layer 205 are further deposited on the surface of the substrate in sequence, and the conductive metal layer 205 fills the bottom through holes to obtain the final substrate structure.
  • the second barrier layer 204 covers the bottom surface and the side surface of the bottom through hole of the substrate, and covers the surface of the substrate outside the bottom through hole.
  • the second barrier layer 204 is formed by physical vapor deposition.
  • the second barrier layer 204 The material is metal or metal nitride, including any one or a mixture of Ta, TaN, Ti, TiN, Co and Ru.
  • the conductive metal layer 205 is formed by a method commonly used in semiconductors, such as physical vapor deposition, chemical vapor deposition, or electroplating.
  • the thickness of the conductive metal layer 205 is equal to or greater than the depth of the bottom through hole.
  • the material of the conductive metal layer 205 is any one or a mixture of several of Cu, W, and Al.
  • step S102 as shown in FIG. 5, the conductive metal layer 205 is chemically mechanically polished, the polishing end point is stopped at the second barrier layer 204, and the second barrier layer 204 is polished after the end point detection method is detected. , To completely remove the conductive metal layer 205 above the second barrier layer 204. Due to the process limitation of the different polishing rates of various thin film materials, a dish-shaped depression 21 is generated in the bottom through hole after polishing. The depth of the dish-shaped recess 21 is denoted as H1, and H1 is generally 0-20 nm.
  • the bottom electrode metal is deposited for the first time to fill the dish-shaped recess 21 formed in the bottom through hole after chemical mechanical polishing of the conductive metal layer to form the bottom electrode metal
  • the thickness of the bottom electrode metal deposited for the first time is denoted as H2, which should satisfy H2>H1.
  • the material of the bottom electrode metal that can be used includes any one or a mixture of TaN, Ta, TiN, and Ti.
  • step S104 chemical mechanical polishing is performed on the bottom electrode metal preform 206, the polishing end point is stopped at the dielectric layer 203, and the dielectric layer 203 is detected according to the end point detection method and then polished , To completely remove the second barrier layer 204 above the dielectric layer 203.
  • the chemical mechanical polishing of the bottom electrode metal preform 206 should ensure that no bottom electrode material remains on the surface of the dielectric layer 203, and a part of the bottom electrode metal will be left in the dish-shaped recess 21 in the bottom through hole at this time.
  • a bottom electrode metal is deposited for the second time to cover the dielectric layer 203 and the bottom electrode metal in the dish-shaped recess 21 to form a bottom electrode metal layer 207. It should be noted that the bottom electrode metal deposited for the second time may be the same or different from the bottom electrode metal deposited for the first time.
  • step S106 photolithography and etching are performed on the bottom electrode metal layer 207 to obtain the bottom electrode 208 of the MRAM device.
  • MRAM bottom electrode 208 It is also supplemented that some subsequent processes are continued on the obtained MRAM bottom electrode 208, such as further depositing a dielectric layer, filling the gaps between the bottom electrodes 208, and then performing chemical mechanical polishing to stop at the bottom electrode 208 interface.
  • the bottom electrode of the MRAM obtained by the above method has a flat surface, which solves the problem of dish-shaped depressions in the bottom through holes after the conductive metal layer (for example, copper) is CMP.
  • the polishing step of the second barrier layer and the dielectric layer is omitted, and the manufacturing process is simpler.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

一种MRAM底电极（208）的制备方法，包括：（S101）提供一基底，所述基底依次包括金属互联层（201）、第一阻挡层（202）以及介电层（203），在所述第一阻挡层（202）及介电层（203）中形成有底部通孔，并在所述基底表面依次覆盖有第二阻挡层（204）和导电金属层（205），所述导电金属层（205）填充满所述底部通孔；（S102）对所述导电金属层（205）进行化学机械抛光，以去除所述第二阻挡层（204）上方的导电金属层（205）；（S103）第一次沉积底电极金属，形成底电极金属预制层（206）；（S104）对所述底电极金属预制层（206）进行化学机械抛光，以去除所述底部通孔外介电层（203）上方多余的第二阻挡层（204）及底电极金属预制层（206）；（S105）第二次沉积底电极金属，形成底电极金属层（207）；（S106）对所述底电极金属层（207）进行光刻和刻蚀。该方法在简化了MRAM底电极（208）制备过程的同时，提高了MRAM底电极（208）的平整性。

Description

MRAM底电极的制备方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种MRAM底电极的制备方法。
背景技术
近年来，基于磁性隧道结(Magnetic Tunnel Junction，MTJ)磁电阻效应的磁性随机存储器(Magnetic Random Access Memory，MRAM)被认为是未来的固态非易失性记忆体，它具有高速读写、大容量以及低能耗等特点。MRAM主要结构为一个晶体管和一个MTJ单元，其中MTJ单元主要由位于底部电极和顶部电极之间的参考层、绝缘势垒层以及自由层构成。其中参考层磁矩方向被钉扎不易改变其磁矩方向，而自由层磁矩方向在外磁场或电流作用下较容易被改变。
MTJ单元利用量子隧穿效应使极化电子通过绝缘势垒层，其中极化电子的隧穿概率与参考层和自由层之间的相对磁化方向有关。当自由层与参考层磁化方向相同时，极化电子隧穿概率较高，MTJ单元表现出低电阻状态；当自由层与参考层磁化方向相反时，极化电子的隧穿概率较低，MTJ单元表现出高电阻状态。MRAM利用MTJ单元的高、低阻态来表示逻辑状态的“1”和“0”，从而实现数据存储。
对MTJ单元而言，其主要由多层薄膜反复堆叠而成，为保证其具有良好的数据读、写能力，往往对薄膜不论是晶体结构还是厚度等方面都有很高的要求，而高质量薄膜的制备通常对底部电极的平坦程度以及粗糙度具有很强的依赖性。因此，在制备MRAM器件时，底电极的平整度会直接影响后续MTJ单元的性能，如何提供平坦的MRAM底电极一直是一个需要解决的技术难题。
发明内容
为解决上述问题，本发明提供一种MRAM底电极的制备方法，能够在简化MRAM底电极制备方法的同时，提高了底电极的平整性。
本发明提供一种MRAM底电极的制备方法，包括：
提供一基底，所述基底依次包括金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连，并在所述基底表面依次覆盖有第二阻挡层和导电金属层，所述导电金属层填充满所述底部通孔；
对所述导电金属层进行化学机械抛光，以去除所述第二阻挡层上方的导电金属层；
第一次沉积底电极金属，以填充满对所述导电金属层进行化学机械抛光后在所述底部通孔内形成的碟形凹陷，形成底电极金属预制层；
对所述底电极金属预制层进行化学机械抛光，以去除所述底部通孔外介电层上方多余的第二阻挡层及底电极金属预制层；
第二次沉积底电极金属，以覆盖所述介电层和所述碟形凹陷内的底电极金属，形成底电极金属层；
对所述底电极金属层进行光刻和刻蚀，得到MRAM底电极。
可选地，所述对所述导电金属层进行化学机械抛光，包括：将抛光终点停止在所述第二阻挡层，依据终点检测方法检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层上方的导电金属层。
可选地，第一次沉积的底电极金属的厚度大于所述碟形凹陷的深度。
可选地，第二次沉积的底电极金属与第一次沉积的底电极金属材料相同或不同。
可选地，所述底电极金属的材料为TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
可选地，所述导电金属层的材料为Cu、W和Al中的一种或几种的混合物。
可选地，所述第二阻挡层的材料为Ta、TaN、Ti、TiN、Co和Ru中的任意一种或几种的混合物。
可选地，所述介电层的材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质。
可选地，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
本发明提供的MRAM底电极的制备方法，与现有技术相比，本发明在对导电金属层进行CMP时，省略了对第二阻挡层和介电层的研磨步骤，简化了MRAM底电极制备过程的同时，还能够制备出表面平整的MRAM底电极，解决了对导电金属层进行CMP之后底部通孔内存在碟形凹陷的问题。
附图说明
图1为本发明一实施例的MRAM底电极的制备方法的流程示意图；
图2～图9为本发明一实施例的MRAM底电极制备方法的各步骤剖面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发 明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明一实施例提供一种MRAM底电极的制备方法，如图1所示，所述方法包括以下步骤：
S101、提供一基底，所述基底依次包括金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连，并在所述基底表面依次覆盖有第二阻挡层和导电金属层，所述导电金属层填充满所述底部通孔；
S102、对所述导电金属层进行化学机械抛光，以去除所述第二阻挡层上方的导电金属层；
S103、第一次沉积底电极金属，以填充满对所述导电金属层进行化学机械抛光后在所述底部通孔内形成的碟形凹陷，形成底电极金属预制层；
S104、对所述底电极金属预制层进行化学机械抛光，以去除所述底部通孔外介电层上方多余的第二阻挡层及底电极金属预制层；
S105、第二次沉积底电极金属，以覆盖所述介电层和所述碟形凹陷内的底电极金属，形成底电极金属层；
S106、对所述底电极金属层进行光刻和刻蚀，得到MRAM底电极。
本发明提供的MRAM底电极的制备方法，与现有技术相比，本发明在对导电金属层进行CMP时，省略了对第二阻挡层和介电层的研磨步骤，简化了MRAM底电极制备过程的同时，还能够制备出表面平整的MRAM底电极，解决了对导电金属层进行CMP之后底部通孔内存在碟形凹陷的问题。
具体地，关于步骤S101，参考图2至图4，所述基底的初始结构如图2所示，从下至上依次包括金属互联层201(金属互联层201为包含硅衬底以及 在衬底上的经前道工艺制备的所有必要的结构以及器件，例如包括CMOS及中间金属互联层)、第一阻挡层202以及介电层203。
如图3所示，在所述第一阻挡层202及介电层203中形成底部通孔，所述底部通孔与所述金属互联层201相连，其中，第一阻挡层202的材料包括但不限于氮氧硅化合物、氮化硅、碳氮硅化合物和碳化硅中的一种，用于防止金属互联层201的离子扩散。介电层203的材料包括但不限于氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS(化学式Si(OC 2H 5) 4)、Low-K介电质及Ultra-Low-K介电质中的一种。底部通孔可以采用常规的光刻和刻蚀技术，在介电层203上定义图案，并选择刻蚀去除部分第一阻挡层202和介电层203，停止于金属互联层201上，从而形成金属互联线所需要的底部通孔。
如图4所示，进一步在基底表面依次沉积第二阻挡层204和导电金属层205，所述导电金属层205充满所述底部通孔，得到最终的基底结构。其中，第二阻挡层204覆盖于基底的底部通孔中的底面和侧面，且覆盖于底部通孔外基底的表面，第二阻挡层204采用物理气相沉积法形成，所述第二阻挡层204的材料为金属或金属氮化物，包括Ta、TaN、Ti、TiN、Co和Ru中的任意一种或几种的混合物。导电金属层205利用半导体通用的方法形成，如物理气相沉积、化学气相沉积或电镀的方法形成，导电金属层205的厚度等于或者大于底部通孔的深度。导电金属层205的材料为Cu、W、Al中的任意一种或者几种的混合物。
关于步骤S102，如图5所示，对导电金属层205进行化学机械抛光，将抛光终点停止在所述第二阻挡层204，依据终点检测方法检测到所述第二阻挡层204后进行过抛光，以完全去除所述第二阻挡层204上方的导电金属层205。 由于多种薄膜材料抛光速率不同的工艺局限性，抛光后在所述底部通孔中产生碟形凹陷21。碟形凹陷21的深度记为H1，一般情况下H1为0～20nm。
关于步骤S103，如图6所示，第一次沉积底电极金属，以填充满对所述导电金属层进行化学机械抛光后在所述底部通孔内形成的碟形凹陷21，形成底电极金属预制层206，第一次沉积的底电极金属的厚度记为H2，应满足H2>H1。
可以使用的底电极金属的材料包括TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
关于步骤S104，如图7所示，对底电极金属预制层206进行化学机械抛光，将抛光终点停止在所述介电层203，依据终点检测方法检测到所述介电层203后进行过抛光，以完全去除所述介电层203上方的第二阻挡层204。底电极金属预制层206的化学机械抛光应保证在介电层203的表面无底电极材料残留，此时会在底部通孔内的碟形凹陷21内留下一部分底电极金属。
关于步骤S105，如图8所示，第二次沉积底电极金属，以覆盖所述介电层203和所述碟形凹陷21内的底电极金属，形成底电极金属层207。需要说明的是，第二次沉积的底电极金属与第一次沉积的底电极金属材料可以相同，也可以不同。
关于步骤S106，如图9所示，对底电极金属层207进行光刻和刻蚀，得到MRAM器件底电极208。
另外补充说明的是，对得到的MRAM底电极208继续执行一些后续工艺，如进一步沉积介电层，填充多个底电极208之间的空隙，然后进行化学机械抛光，停止于底电极208界面。
通过上述方法得到的MRAM底电极，表面平整，解决了导电金属层(例 如，铜)进行CMP之后底部通孔内存在碟形凹陷的问题。另外，与现有技术相比，本发明在对导电金属层(例如，铜)进行CMP时，省略掉了第二阻挡层和介电层的研磨步骤，制程更简单。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (9)

  1. 一种MRAM底电极的制备方法，其特征在于，包括：
    提供一基底，所述基底依次包括金属互联层、第一阻挡层以及介电层，在所述第一阻挡层及介电层中形成有底部通孔，所述底部通孔与所述金属互联层相连，并在所述基底表面依次覆盖有第二阻挡层和导电金属层，所述导电金属层填充满所述底部通孔；
    对所述导电金属层进行化学机械抛光，以去除所述第二阻挡层上方的导电金属层；
    第一次沉积底电极金属，以填充满对所述导电金属层进行化学机械抛光后在所述底部通孔内形成的碟形凹陷，形成底电极金属预制层；
    对所述底电极金属预制层进行化学机械抛光，以去除所述底部通孔外介电层上方多余的第二阻挡层及底电极金属预制层；
    第二次沉积底电极金属，以覆盖所述介电层和所述碟形凹陷内的底电极金属，形成底电极金属层；
    对所述底电极金属层进行光刻和刻蚀，得到MRAM底电极。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述导电金属层进行化学机械抛光，包括：将抛光终点停止在所述第二阻挡层，依据终点检测方法检测到所述第二阻挡层后进行过抛光，以完全去除所述第二阻挡层上方的导电金属层。
  3. 根据权利要求1所述的方法，其特征在于，第一次沉积的底电极金属的厚度大于所述碟形凹陷的深度。
  4. 根据权利要求1所述的方法，其特征在于，第二次沉积的底电极金属 与第一次沉积的底电极金属材料相同或不同。
  5. 根据权利要求1所述的方法，其特征在于，所述底电极金属的材料为TaN、Ta、TiN和Ti中的任意一种或者几种的混合物。
  6. 根据权利要求1所述的方法，其特征在于，所述导电金属层的材料为Cu、W和Al中的一种或几种的混合物。
  7. 根据权利要求1所述的方法，其特征在于，所述第二阻挡层的材料为Ta、TaN、Ti、TiN、Co和Ru中的任意一种或几种的混合物。
  8. 根据权利要求1所述的方法，其特征在于，所述介电层的材料为氧化硅SiO、二氧化硅SiO 2、碳氧化物CDO、氮化硅SiN、氟硅玻璃FSG、磷硅玻璃PSG、硼磷硅玻璃BPSG、正硅酸乙酯TEOS、Low-K介电质或者Ultra-Low-K介电质。
  9. 根据权利要求1所述的方法，其特征在于，所述第一阻挡层的材料为氮氧硅化合物、氮化硅、碳氮硅化合物或者碳化硅。
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