WO2021042266A1 - 异步采样架构及芯片 - Google Patents

异步采样架构及芯片 Download PDF

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Publication number
WO2021042266A1
WO2021042266A1 PCT/CN2019/104220 CN2019104220W WO2021042266A1 WO 2021042266 A1 WO2021042266 A1 WO 2021042266A1 CN 2019104220 W CN2019104220 W CN 2019104220W WO 2021042266 A1 WO2021042266 A1 WO 2021042266A1
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Prior art keywords
asynchronous sampling
clock
frequency
data string
register
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PCT/CN2019/104220
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English (en)
French (fr)
Inventor
王文祺
王欣民
刘如杰
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP19933207.3A priority Critical patent/EP3809597A4/en
Priority to PCT/CN2019/104220 priority patent/WO2021042266A1/zh
Priority to CN201980002046.8A priority patent/CN112771783B/zh
Priority to KR1020217029632A priority patent/KR102500860B1/ko
Priority to US17/134,215 priority patent/US11456850B2/en
Publication of WO2021042266A1 publication Critical patent/WO2021042266A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to an asynchronous sampling architecture and chip, and more particularly to an asynchronous sampling architecture and chip using sigma-delta modulation.
  • One of the objectives of this application is to disclose an asynchronous sampling architecture and chip to solve the above-mentioned problems.
  • An embodiment of the present application discloses an asynchronous sampling architecture for receiving a first input data string from the opposite end.
  • the asynchronous sampling architecture includes: a first register for buffering the first input data string. Input data string, wherein the first input data string is written into the first register according to the opposite end clock of the opposite end; and a gated clock generation unit for generating a gated clock, the frequency of the gated clock The frequency is the same as that of the opposite end clock, and the first input data string is read from the first register as the first output data string according to the gating clock.
  • An embodiment of the present application discloses a chip including the above-mentioned asynchronous sampling architecture.
  • the embodiment of the present application improves the asynchronous sampling architecture, which can reduce cost and power consumption.
  • FIG. 1 is a schematic diagram of the first embodiment of the asynchronous sampling architecture of this application.
  • FIG. 2 is a schematic diagram of an embodiment of the gated clock generation unit of this application.
  • FIG. 3 is a schematic diagram of a second embodiment of the asynchronous sampling architecture of this application.
  • FIG. 4 is a schematic diagram of a third embodiment of the asynchronous sampling architecture of this application.
  • FIG. 5 is a schematic diagram of a fourth embodiment of the asynchronous sampling architecture of this application.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • content of the present invention may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing in the figure
  • the relationship between one component or feature relative to another component or feature is shown.
  • the original meaning of these spatially-relative vocabulary covers a variety of different orientations of the device in use or operation, in addition to the orientation shown in the figure.
  • the device may be placed in other orientations (for example, rotated 90 degrees or in other orientations), and these spatially-relative description vocabulary should be explained accordingly.
  • sampling rate conversion Refers to changing the sampling rate of the signal.
  • the sampling rate conversion can be divided into two types: synchronous sampling rate conversion and asynchronous sampling rate conversion.
  • Synchronous sampling rate conversion means that the rate clocks before and after conversion are synchronous, and the rate ratio is a constant value; asynchronous sampling rate conversion means that the rate clocks before and after conversion are asynchronous and independent, and the rate ratio will be As time changes slowly, this also means that the bit rate ratio may be an irrational number, so it cannot be achieved using a general fixed-rate interpolation filter.
  • Known methods include the use of asynchronous sampling rate converters for complex interpolation algorithms, but they have the disadvantages of high complexity and high power consumption. Therefore, for product applications that emphasize power saving, it is necessary to achieve both power saving and potential at the same time. Accepted performance is a big challenge.
  • FIG. 1 is a schematic diagram of the first embodiment of the asynchronous sampling architecture of this application.
  • the asynchronous sampling architecture 100 in FIG. 1 can be used to receive the first input data string d1 from the opposite end (not shown in the figure) and perform asynchronous data sampling, wherein the opposite end generates a write control signal according to the opposite end clock CLK_P wcrtl1, and write the first input data string d1 into the first register 102 in the asynchronous sampling architecture 100 according to the write control signal wcrtl1.
  • the frequency fp of the opposite end clock CLK_P and the frequency fl of the local clock CLK_L have a first Frequency difference fp-fl.
  • the frequency fp of the opposite end clock CLK_P and the frequency fl of the local clock CLK_L it is not deliberately to make the frequency fp of the opposite end clock CLK_P and the frequency fl of the local clock CLK_L have a first frequency difference, but this problem will inevitably be encountered.
  • the first frequency difference The reason is that, for example, the opposite end clock CLK_P and the local clock CLK_L are directly or indirectly generated by different crystal oscillators, even though the opposite end clock CLK_P and the local clock CLK_L theoretically have the same target frequency, but In fact, because different crystal oscillators must have differences, there are still some differences between the frequency fp of the opposite end clock CLK_P and the frequency f1 of the local clock CLK_L.
  • the asynchronous sampling architecture 100 includes: a first register 102, a gated clock generating unit 106, and a digital signal processing unit 108.
  • the first register 102 is used to buffer the first input data string d1
  • the first register 102 is used to buffer the first input data string d1.
  • the register 102 may be a first-in first-out register.
  • the asynchronous sampling architecture 100 receives the first input data string d1, and writes the first input data string d1 into the first register 102, and the first input data string d1 is read from the first register 102 as the first output data string d1ff It should be noted that because the first input data string d1 received by the asynchronous sampling architecture 100 is transmitted from the opposite end, that is, the first input data string d1 is generated according to the opposite end clock CLK_P instead of the local clock CLK_L, so the first input data string d1 An input data string d1 is written into the first register 102 according to the opposite end clock CLK_P of the opposite end.
  • the asynchronous sampling architecture 100 does not use the local clock CLK_L, but uses the read control signal rctrl1 generated according to the gated clock CLK_G to read the first input data string d1 as the first output data string d1ff. Since the frequency of the gating clock CLK_G generated by the asynchronous sampling architecture 100 should be equal to the frequency of the opposite end clock CLK_P, the first register 102 of this embodiment will not have overflow or underflow problems.
  • the gated clock generation unit 106 of the asynchronous sampling architecture generates the gated clock CLK_G according to the first frequency difference fdelta, the predetermined frequency upside MH, the local clock CLK_L, and the asynchronous sampling rate conversion clock CLK_A, and supplies the gated clock CLK_G to the digital signal processing unit 108.
  • the predetermined frequency headroom MH is a preset value, but this application does not By this limit, the predetermined frequency headroom MH can also be provided externally to the asynchronous sampling architecture 100.
  • the first frequency difference fdelta can also be replaced by any other signal with the same effect.
  • the first frequency difference fdelta can be replaced by the ratio of the frequency fp of the opposite end clock CLK_P to the frequency of the local clock CLK_L, and is based on the ratio. Obtain the first frequency difference fdelta.
  • FIG. 2 is a schematic diagram of an embodiment of the gated clock generating unit of this application, which includes details of the gated clock generating unit 106. As shown in FIG.
  • the gated clock generating unit 106 includes an asynchronous sampling rate conversion ratio generating unit 1062 and a sigma-delta modulator 1066.
  • the frequency fa of the asynchronous sampling rate conversion clock CLK_A is higher than that of the local clock CLK_L. .
  • the asynchronous sampling rate conversion clock CLK_A and the local clock CLK_L can be generated by a phase-locked loop (not shown in the figure).
  • the reason for increasing the frequency of the local clock CLK_L to generate the asynchronous sampling rate conversion clock CLK_A is to generate a finer gating clock CLK_G to adjust the frequency fg of the gating clock CLK_G, and the value of the predetermined frequency up space MH The larger is, the finer the frequency fg of the gating clock CLK_G is adjusted, the better the effect, but the hardware complexity and power consumption will be relatively increased.
  • the predetermined frequency upside MH is greater than 0 and less than 1.
  • the predetermined frequency rise space MH is approximately 0.1-0.2, but this application is not limited to this, and should be determined according to actual applications.
  • the asynchronous sampling rate conversion ratio generating unit 1062 generates the asynchronous sampling rate conversion ratio R according to the first frequency difference fdelta and the predetermined frequency headroom MH.
  • the asynchronous sampling rate conversion ratio R (fp/fl)/(1+MH), that is, (1+fdelta/fl)/(1+MH). Since the first frequency difference fdelta is usually very close to 0, which is a ppm level, (1+fdelta/fl) will approach 1. Therefore, as long as the predetermined frequency rise space MH does not approach 0, the predetermined frequency rise space MH is sufficient. Let the asynchronous sampling rate conversion ratio R be not equal to 1 and have a gap with 1, if the asynchronous sampling rate conversion ratio R is too close to 1, the noise shaping ability of the sigma-delta modulator 1066 will be deteriorated.
  • the sigma-delta modulator 1066 generates the gated clock CLK_G according to the asynchronous sampling rate conversion ratio R and the asynchronous sampling rate conversion clock CLK_A.
  • the gated clock CLK_G is a 1-bit sequence. From a long-term perspective, the frequency of the gated clock CLK_G is asynchronous
  • the degree of jitter of the gated clock CLK_G is related to the value of the predetermined frequency rise space MH.
  • the sigma-delta modulator 1066 Because the sigma-delta modulator 1066 has a noise-shaping property, the sigma-delta modulator 1066 uses a higher super-sampling ratio for sampling rate conversion, so it can easily obtain better performance. Specifically, the sampling rate conversion noise introduced by the sigma-delta modulator 1066 will be at a higher frequency and is basically separated from the baseband signal frequency band, that is, the sampling rate introduced by the sigma-delta modulator 1066 The conversion noise can be suppressed by the subsequent circuit alone, and does not affect the baseband signal. In this embodiment, the sigma-delta modulator 1066 is a one-bit sigma-delta modulator, but the application is not limited to this.
  • the asynchronous sampling architecture of the digital signal processing unit 108 generates the read control signal rctrl1 according to the gating clock CLK_G, and reads the first input data string d1 from the first register 102 according to the read control signal rctrl1, and can Perform any digital signal processing on the first output data string d1ff, and generate an output data string d1dsp after the digital signal processing.
  • FIG. 3 is a schematic diagram of a second embodiment of the asynchronous sampling architecture of this application.
  • the asynchronous sampling architecture 200 of FIG. 3 further includes a frequency difference estimation unit 204, and the digital signal processing unit 108 is more specifically implemented by an interpolation filter 208.
  • the frequency difference estimating unit 204 estimates the first frequency difference fdelta between the opposite end clock CLK_P and the local clock CLK_L according to the storage amount fflv of the first register 102.
  • fdelta the frequency fp of the opposite end clock CLK_P-local end The frequency of the clock CLK_L fl.
  • the frequency difference estimation unit 204 estimates the first frequency difference fdelta according to the storage amount fflv of the first register 102 and the local clock CLK_L. For example, in some embodiments, the frequency difference estimation unit 204 obtains the storage amount change of the first register 102 within a predetermined time according to the local clock CLK_L, and generates the first frequency difference fdelta accordingly. For example, the storage amount fflv of the first register 102 corresponding to a certain time point and after 1000 clock cycles of the local clock CLK_L can be compared to obtain the storage amount change. This application does not implement the frequency difference estimation unit 204 The manner is further limited, and the frequency difference estimation unit 204 may be implemented in the form of hardware, software or firmware.
  • the implementation of the frequency difference estimation unit 204 is not limited to this, as long as the same or similar purpose can be achieved.
  • the interpolation filter 208 performs interpolation filtering processing on the first output data string d1ff read by the first register 102 according to the gated clock CLK_G, and generates an interpolation filter output data string d1if, the main purpose is to keep the signal frequency band clean status.
  • the interpolation filter 208 can be replaced with any baseband digital signal processing circuit.
  • FIG. 4 is a schematic diagram of a third embodiment of the asynchronous sampling architecture of this application.
  • the asynchronous sampling architecture 300 of FIG. 4 further includes a second register 302 and a decimation filter 308.
  • the second register 302 may be a first-in first-out register for buffering the second input data string d2df .
  • the decimation filter 308 generates the write control signal wcrtl2 according to the gating clock CLK_G, and writes the second input data string d2df into the second register 302 according to the write control signal wcrtl2, and the opposite end generates a read according to the opposite end clock CLK_P
  • the signal rcrtl2 is controlled, and the second input data string d2df is read from the second register 302 as the second output data string d2ff according to the read control signal rcrtl2. Similar to the first register 102, since the gated clock CLK_G has the same frequency as the opposite end clock CLK_P, the second register 302 does not have an overflow or underflow problem.
  • the decimation filter 308 performs decimation and filtering processing on the decimation filter input data string d2ad according to the gated clock CLK_G, and generates a second input data string d2df, the main purpose of which is to avoid signal aliasing.
  • the decimation filter 308 can be replaced with any baseband digital signal processing circuit.
  • FIG. 5 is a schematic diagram of a fourth embodiment of the asynchronous sampling architecture of this application.
  • the asynchronous sampling architecture 400 of FIG. 5 further includes a digital-to-analog converter 314, which performs digital-to-analog conversion on the interpolation filter output data string d1if according to the asynchronous sampling rate conversion clock CLK_A, and outputs Analog signal d1da.
  • the asynchronous sampling architecture 400 of FIG. 5 also includes an analog-to-digital converter 316.
  • the analog-to-digital converter 316 performs analog-to-digital conversion on the analog-digital input data string d2 according to the gated clock CLK_G, and generates a decimation filter input data string d2ad.
  • this embodiment can be applied to a Bluetooth headset system.
  • the opposite end transmits the first input data string d1 to the asynchronous sampling architecture 400 through Bluetooth, and the asynchronous sampling architecture 400 outputs the analog signal d1da through the digital-to-analog converter 314. Send to the earphone speaker (not shown in the figure) to play.
  • the asynchronous sampling architecture 400 generates an analog-digital input data string d2 through a microphone (not shown in the figure), and converts the analog-digital input data string d2 into the digital domain through an analog-digital converter 316 and reads it by the opposite end.
  • the second output data string d2ff is output. All data in this embodiment can be a single bit or multiple bits, and the specific bit value can be determined according to the amount of data.
  • This application also provides a chip, which includes an asynchronous sampling architecture 100/200/300/400.
  • the embodiment of the application improves the asynchronous sampling architecture, and uses sigma-delta modulation to generate a gated clock for asynchronous sampling rate conversion, instead of using an asynchronous sampling rate converter to resample the signal with the local clock.
  • the conventional asynchronous Sampling rate converters usually need to perform high-bit multiplication operations. Because the asynchronous sampling architecture of this application uses sigma-delta modulation to generate gated clocks, compared to asynchronous sampling rate converters that resample signals with the local clock The circuit is much simpler in computational complexity, so compared to the conventional asynchronous sampling rate converter, the size and power consumption of the hardware are greatly reduced.

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Abstract

一种异步采样架构(100)及芯片，所述异步采样架构(100)用来从所述对端接收第一输入数据串(dl)，所述异步采样架构(100)包括：第一寄存器(102)，用来缓存所述第一输入数据串(dl)，其中所述第一输入数据串(d1)是依据所述对端的对端时钟(CLK_P)被写入所述第一寄存器(102)；以及门控时钟产生单元(106)，用来产生门控时钟(CLK_G)，所述门控时钟(CLK_G)的频率和所述对端时钟(CLK_P)的频率相同，且所述第一输入数据串(dl)依据所述门控时钟(CLK_G)从所述第一寄存器(102)被读出为第一输出数据串(d1ff)。

Description

异步采样架构及芯片 技术领域
本申请涉及一种异步采样架构及芯片，尤其涉及一种利用∑-δ调制的异步采样架构及芯片。
背景技术
在通讯系统中，常常会面临到系统间的信息传递，系统间存在异步时钟的问题，即系统间的时钟是彼此独立且异步的，造成本端和对端的数据速率产生不可预期的差异，因此异步采样在通讯系统中是一项非常重要的技术。目前的做法，例如使用异步采样率转换器对信号以本端时钟进行重采样，具有较大的硬件复杂度以及严重的系统耗电问题，因此对于强调省电的产品应用来说，要能同时达到省电又能有可接受的性能表现，已成为本领域的一个重要的工作项目。
发明内容
本申请的目的之一在于公开一种异步采样架构及芯片，来解决上述问题。
本申请的一实施例公开了一种异步采样架构，用来从所述对端接收第一输入数据串，其特征在于，所述异步采样架构包括：第一寄存器，用来缓存所述第一输入数据串，其中所述第一输入数据串依据所述对端的对端时钟被写入所述第一寄存器；以及门控时钟产生单元，用来产生门控时钟，所述门控时钟的频率和所述对端时钟的频率相同，且所述第一输入数据串依据所述门控时钟从所述第一寄存器被读出为第一输出数据串。
本申请的一实施例公开了一种芯片，包括上述的异步采样架构。
本申请实施例针对异步采样架构进行改良，可降低成本及功耗。
附图说明
图1为本申请的异步采样架构的第一实施例的示意图。
图2为本申请的门控时钟产生单元的实施例的示意图。
图3为本申请的异步采样架构的第二实施例的示意图。
图4为本申请的异步采样架构的第三实施例的示意图。
图5为本申请的异步采样架构的第四实施例的示意图。
其中，附图标记说明如下：
100、200、300、400        异步采样架构
102                       第一寄存器
106                       门控时钟产生单元
108                       数字信号处理单元
1062                      异步采样率转换比率产生单元
1066                      ∑-δ调制器
204                       频率差估计单元
208                       内插滤波器
308                       抽取滤波器
302                       第二寄存器
314                       数字模拟转换器
316                       模拟数字转换器
d1                        第一输入数据串
d1ff                      第一输出数据串
d1dsp                     输出数据串
d1if                      内插滤波器输出数据串
fflv                      存储量
fdelta                   第一频率差
CLK_P                    对端时钟
CLK_L                    本端时钟
CLK_G                    门控时钟
CLK_A                    异步采样率转换时钟
MH                       预定频率上升空间
R                        异步采样率转换比率
d2ff                     第二输出数据串
d2df                     第二输入数据串
d2ad                     抽取滤波器输入数据串
d2                       模拟数字输入数据串
d1da                     模拟信号
rctrl1、rctrl2           读取控制信号
wcrtl1、wctrl2           写入控制信号
具体实施方式
以下揭示内容提供了多种实施方式或示例，其能用以实现本发明内容的不同特征。下文所述之组件与配置的具体例子系用以简化本发明内容。当可想见，这些叙述仅为例示，其本意并非用于限制本发明内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本发明内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。 这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比率及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
在通讯系统中，常常会面临到两个以上系统间的信息传递，各系统间的频率多少存在差异，称为频率异步，如果没有适当的处理这个频率差异，系统间的信息传递会出现问题。举例来说，音频信号的规格有许多种不同的频率定义，例如32kHz、44.1kHz、48kHz等等，因此在音频信号处理时，信号的采样率转换是一种常用的技术，所谓的采样率转换指的就是改变信号的采样率。采样率的转换可以分为，同步采样率转换与异步采样率转换两种。同步采样率转换是指转换前后的码率时钟是同步的，其码率之比为恒定值；异步采样率转换是指转换前后的码率时钟是异步的且独立的，其码率之比会随着时间缓慢的变化，这也意味着码率之比可能是无理数，因此无法使用一般的固定倍率的内插滤波器来实现。已知的做法包括使用异步采样率转换器进行复杂的内插算法，但具有高复杂度以及 高耗电等缺陷，因此对于强调省电的产品应用来说，要能同时达到省电又有可接受的性能表现是很大的挑战。
图1为本申请的异步采样架构的第一实施例的示意图。图1中的异步采样架构100可用来从对端(未绘示于图中)接收第一输入数据串d1，并进行异步数据采样，其中所述对端依据对端时钟CLK_P产生写入控制信号wcrtl1，并依据写入控制信号wcrtl1来将第一输入数据串d1写入异步采样架构100中的第一寄存器102，对端时钟CLK_P的频率fp和本端时钟CLK_L的频率fl之间具有第一频率差fp-fl。在此实施例中，并非刻意要使对端时钟CLK_P的频率fp和本端时钟CLK_L的频率fl之间具有第一频率差，而是不可避免地会遇到此问题，所述第一频率差形成的原因在于，举例来说，对端时钟CLK_P和本端时钟CLK_L分别由不同的晶体振荡器所直接或间接产生，即使对端时钟CLK_P和本端时钟CLK_L理论上具有相同的目标频率，但实际上由于不同的晶体振荡器必定存在差异，因此对端时钟CLK_P的频率fp和本端时钟CLK_L的频率fl之间多少仍存在差异。
异步采样架构100包括：第一寄存器102、门控时钟产生单元106和数字信号处理单元108，举例来说，在本实施例中，第一寄存器102用来缓存第一输入数据串d1，第一寄存器102可以是先入先出寄存器。异步采样架构100接收第一输入数据串d1，并将第一输入数据串d1写入第一寄存器102，第一输入数据串d1再从第一寄存器102中被读出为第一输出数据串d1ff，应注意的是，因为异步采样架构100接收到的第一输入数据串d1是由对端传送过来，即第一输入数据串d1是依据对端时钟CLK_P产生而非本端时钟CLK_L，因此第一输入数据串d1是依据所述对端的对端时钟CLK_P被写入第一寄存器102。若直接使用本端时钟CLK_L来将第一输入数据串d1读出第一寄存器102，一段时间后，必定会发生第一寄存器102上溢或下溢的问题，在此实施例中，异步采样架构100不使用本端时钟CLK_L，而是使用依据门控时钟CLK_G产生的读取控制信号rctrl1来将第一输入数据串d1读出为第一输出数据串d1ff。由于异 步采样架构100所产生的门控时钟CLK_G的频率应和对端时钟CLK_P的频率相等，因此本实施例的第一寄存器102不会发生上溢或下溢的问题。
异步采样架构100另接收第一频率差fdelta，且fdelta＝对端时钟CLK_P的频率fp-本端时钟CLK_L的频率fl。异步采样架构的门控时钟产生单元106依据第一频率差fdelta、预定频率上升空间MH、本端时钟CLK_L和异步采样率转换时钟CLK_A来产生门控时钟CLK_G，并供应给数字信号处理单元108来产生读取控制信号rctrl1并从第一寄存器102将第一输入数据串d1读出为第一输出数据串d1ff，在此实施例中，预定频率上升空间MH为预设值，但本申请不以此限，预定频率上升空间MH亦可以由外部提供给异步采样架构100。此外，第一频率差fdelta亦可由其他任何具有同样效果的信号代替，例如第一频率差fdelta可由对端时钟CLK_P的频率fp和本端时钟CLK_L的频率的比值来取代，并依据所述比值来得到第一频率差fdelta。图2为本申请的门控时钟产生单元的实施例的示意图，其中包含了门控时钟产生单元106的细节。如图2所示，门控时钟产生单元106包括异步采样率转换比率产生单元1062和∑-δ调制器1066，在本实施例中，异步采样率转换时钟CLK_A的频率fa较本端时钟CLK_L高。具体来说，异步采样率转换时钟CLK_A的频率fa为本端时钟CLK_L的频率fl*(1+预定频率上升空间MH)，即fa-fl＝fl*MH，预定频率上升空间MH大于0。在本实施例中，异步采样率转换时钟CLK_A和本端时钟CLK_L可由锁相环(未绘示于图中)产生。
在本实施例中，提升本端时钟CLK_L的频率来产生异步采样率转换时钟CLK_A的原因在于为了产生较为精细的门控时钟CLK_G以调整门控时钟CLK_G的频率fg，预定频率上升空间MH的值越大，调整门控时钟CLK_G的频率fg的精细度越高，效果越好，但硬件的复杂度以及功耗会相对的提高，在本实施例中，预定频率上升空间MH大于0且小于1，具体来说，预定频率上升空间MH大约为0.1～0.2，但本申请不以此限，应视实际应用而定。
异步采样率转换比率产生单元1062依据第一频率差fdelta和预定频率上升空间MH来产生异步采样率转换比率R。举例来说，异步采样率转换比率R＝(fp/fl)/(1+MH)，即(1+fdelta/fl)/(1+MH)。由于第一频率差fdelta通常非常接近0，是ppm等级，因此(1+fdelta/fl)会趋近于1，因此，只要预定频率上升空间MH不趋近于0，预定频率上升空间MH便可让异步采样率转换比率R不等于1且和1有一段差距，若异步采样率转换比率R太接近1，会让造成∑-δ调制器1066的噪声整形的能力变差。
∑-δ调制器1066依据异步采样率转换比率R和异步采样率转换时钟CLK_A来产生门控时钟CLK_G，门控时钟CLK_G为1位序列，拉长时间来看，门控时钟CLK_G的频率是异步采样率转换时钟CLK_A的频率乘上异步采样率转换比率R，即产生的门控时钟CLK_G的频率fg＝异步采样率转换比率R*异步采样率转换时钟CLK_A，即((fp/fl)/(1+MH))*(fl*(1+MH))＝fp，因此使门控时钟CLK_G的频率fg和对端时钟CLK_P的频率fp相等。门控时钟CLK_G的抖动程度和预定频率上升空间MH的值的大小有关，预定频率上升空间MH的值越大，精细度越高，门控时钟CLK_G的抖动程度越小。
因为∑-δ调制器1066有噪声整形的性质，由于∑-δ调制器1066是利用较高的超取样比率进行采样率转换，因此可以较简单地得到较好的效能。具体来说，由∑-δ调制器1066所引入的采样率转换噪声会在较高频的位置，和基带信号频带基本上是分离的，也就是说，∑-δ调制器1066引入的采样率转换噪声可以单独利用后级电路抑制掉，并不影响基带信号。在本实施例中，∑-δ调制器1066是一位∑-δ调制器，但本申请不以此为限。在本实施例中，数字信号处理单元108异步采样架构依据门控时钟CLK_G产生读取控制信号rctrl1，并依据读取控制信号rctrl1来从第一寄存器102读出第一输入数据串d1，并可对第一输出数据串d1ff进行任何的数字信号处理，并产生经数字信号处理后的输出数据串d1dsp。
图3为本申请的异步采样架构的第二实施例的示意图。相较于图1的异步采样架构100，图3的异步采样架构200另包括频率差估计单元204，且数字信号处理单元108更具体地以内插滤波器208来实现。频率差估计单元204会依据第一寄存器102的存储量fflv来估计对端时钟CLK_P和本端时钟CLK_L的第一频率差fdelta，如前所述，fdelta＝对端时钟CLK_P的频率fp-本端时钟CLK_L的频率fl。具体来说，频率差估计单元204依据第一寄存器102的存储量fflv和本端时钟CLK_L来估计第一频率差fdelta。举例来说，在某些实施例中，频率差估计单元204依据本端时钟CLK_L在预定时间内得到第一寄存器102的存储量变化量，并据以产生第一频率差fdelta。例如可以比较某个时间点和经过1000个本端时钟CLK_L的时钟周期后分别对应的第一寄存器102的存储量fflv来得到所述存储量变化量，本申请并不对频率差估计单元204的实现方式作进一步限定，频率差估计单元204可以以硬件、软件或固件形式实现。所述存储量变化量越大，对端时钟CLK_P和本端时钟CLK_L的第一频率差fdelta越大，反之亦然。在本申请中，频率差估计单元204的实现方式并不以此为限，只要能够达到相同或相似的目的即可。
内插滤波器208依据门控时钟CLK_G来对第一寄存器102读出的第一输出数据串d1ff进行内插滤波处理，并产生内插滤波器输出数据串d1if，主要目的是让信号频带维持干净的状态。在某些实施例中，内插滤波器208可以被置换为任意的基带数字信号处理电路。
图4为本申请的异步采样架构的第三实施例的示意图。相较于图3的异步采样架构200，图4的异步采样架构300另包括第二寄存器302和抽取滤波器308，第二寄存器302可以是先入先出寄存器，用来缓存第二输入数据串d2df。抽取滤波器308依据门控时钟CLK_G产生写入控制信号wcrtl2，并依据写入控制信号wcrtl2来将第二输入数据串d2df写入第二寄存器302，所述对端依据对端时钟CLK_P产生读取控制信号rcrtl2，并依据读取控制信号rcrtl2来将 第二输入数据串d2df从第二寄存器302读出为第二输出数据串d2ff。和第一寄存器102相似，由于门控时钟CLK_G具有和对端时钟CLK_P相等的频率，因此第二寄存器302并不会发生上溢或下溢的问题。在本实施例中，抽取滤波器308依据门控时钟CLK_G来对抽取滤波器输入数据串d2ad进行抽取滤波处理，并产生第二输入数据串d2df，主要目的是避免信号混叠的产生。在某些实施例中，抽取滤波器308可以被置换为任意的基带数字信号处理电路。
图5为本申请的异步采样架构的第四实施例的示意图。相较于图4的异步采样架构300，图5的异步采样架构400另包括数字模拟转换器314，依据异步采样率转换时钟CLK_A来对内插滤波器输出数据串d1if进行数字模拟转换，并输出模拟信号d1da。图5的异步采样架构400还包括模拟数字转换器316，模拟数字转换器316依据门控时钟CLK_G来对模拟数字输入数据串d2进行模拟数字转换，并产生抽取滤波器输入数据串d2ad。举例来说，本实施例可应用于蓝牙耳机系统，所述对端通过蓝牙将第一输入数据串d1传送给异步采样架构400，异步采样架构400则通过数字模拟转换器314将输出模拟信号d1da传送到耳机喇叭(未绘示于图中)播放。相反地，异步采样架构400通过麦克风(未绘示于图中)产生模拟数字输入数据串d2，并通过模拟数字转换器316将模拟数字输入数据串d2转换至数字域并由所述对端读出第二输出数据串d2ff。本实施例中的所有数据都可以为单一比特或多比特，具体的比特值可以根据数据量大小确定。
本申请还提供了一种芯片，其包括异步采样架构100/200/300/400。
本申请实施例针对异步采样架构进行改良，利用∑-δ调制来产生门控时钟以进行异步采样率转换，而非使用异步采样率转换器对信号以本端时钟进行重采样，习知的异步采样率转换器通常需要进行高比特的乘法运算，由于本申请的异步采样架构中利用∑-δ调制来产生门控时钟的电路相较于异步采样率转换器对信号以本端时钟 进行重采样的电路，运算复杂度简单许多，因此相比于习知的异步采样率转换器，大幅地降低了硬件的尺寸和功耗。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本发明内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本发明内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本发明内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本发明内容之精神与范围。

Claims (19)

  1. 一种异步采样架构，用来从所述对端接收第一输入数据串，其特征在于，所述异步采样架构包括：
    第一寄存器，用来缓存所述第一输入数据串，其中所述第一输入数据串依据所述对端的对端时钟被写入所述第一寄存器；以及
    门控时钟产生单元，用来产生门控时钟，所述门控时钟的频率和所述对端时钟的频率相同，且所述第一输入数据串依据所述门控时钟从所述第一寄存器被读出为第一输出数据串。
  2. 如权利要求1所述的异步采样架构，其中所述门控时钟产生单元依据所述对端时钟和所述异步采样架构的本端时钟之间的第一频率差来产生所述门控时钟。
  3. 如权利要求2所述的异步采样架构，其中所述门控时钟产生单元依据所述第一频率差、预定频率上升空间、所述本端时钟和异步采样率转换时钟来产生所述门控时钟，其中所述异步采样率转换时钟的频率大于所述本端时钟的频率，且所述异步采样率转换时钟的频率和所述本端时钟的频率的第二频率差为所述本端时钟的频率乘上所述预定频率上升空间。
  4. 如权利要求3所述的异步采样架构，其中所述门控时钟产生单元包括：
    异步采样率转换比率产生单元，依据所述第一频率差和所述预定频率上升空间来产生异步采样率转换比率；以及
    ∑-δ调制器，依据所述本端时钟、所述异步采样率转换比率和所述异步采样率转换时钟来产生所述门控时钟。
  5. 如权利要求4所述的异步采样架构，其中所述∑-δ调制器是一位∑-δ调制器。
  6. 如权利要求3所述的异步采样架构，其中所述异步采样率转换时钟的频率和所述本端时钟的频率的差值为所述本端时钟的频率 乘上所述预定频率上升空间。
  7. 如权利要求2所述的异步采样架构，另包括频率差估计单元，用来依据所述第一寄存器的存储量来估计所述第一频率差。
  8. 如权利要求7所述的异步采样架构，其中所述频率差估计单元依据所述第一寄存器的所述存储量和所述本端时钟来估计所述第一频率差。
  9. 如权利要求8所述的异步采样架构，其中依据所述本端时钟，所述频率差估计单元在预定时间内得到所述第一寄存器的存储量变化量，并依据所述预定时间和所述存储量变化量估计所述第一频率差。
  10. 如权利要求3所述的异步采样架构，另包括内插滤波器，依据所述门控时钟来产生读取控制信号以将所述第一输入数据串从所述第一寄存器读出以及进行内插滤波处理，并产生内插滤波器输出数据串。
  11. 如权利要求10所述的异步采样架构，另包括数字模拟转换器，依据所述异步采样率转换时钟来对所述内插滤波器输出数据串进行数字模拟转换。
  12. 如权利要求1所述的异步采样架构，另包括第二寄存器，用来缓存第二输入数据串，其中所述第二输入数据串依据所述门控时钟被写入所述第二寄存器，且所述第二输入数据串依据所述对端时钟从所述第二寄存器被读出为第二输出数据串，所述对端从所述异步采样架构接收所述第二输出数据串。
  13. 如权利要求12所述的异步采样架构，另包括抽取滤波器，依据所述门控时钟来对抽取滤波器输入数据串进行抽取滤波处理，并产生所述第二输入数据串，以及依据所述门控时钟来产生写入控制信号，并依据所述写入控制信号将所述第二输入数据串写入所述第二寄存器。
  14. 如权利要求13所述的异步采样架构，另包括模拟数字转换器，
    依据所述门控时钟来对模拟数字输入数据串进行模拟数字转换，并产生所述抽取滤波器输入数据串。
  15. 如权利要求1所述的异步采样架构，其中所述第一寄存器是先入先出寄存器。
  16. 如权利要求12所述的异步采样架构，其中所述第二寄存器是先入先出寄存器。
  17. 如权利要求3所述的异步采样架构，其中所述预定频率上升空间大于0且小于1。
  18. 如权利要求3所述的异步采样架构，其中所述预定频率上升空间大于等于0.1且小于等于0.2。
  19. 一种芯片，其特征在于，包括：
    如权利要求1-18中任一项所述的异步采样架构。
PCT/CN2019/104220 2019-09-03 2019-09-03 异步采样架构及芯片 WO2021042266A1 (zh)

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