WO2021037021A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示面板 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示面板 Download PDF

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Publication number
WO2021037021A1
WO2021037021A1 PCT/CN2020/111042 CN2020111042W WO2021037021A1 WO 2021037021 A1 WO2021037021 A1 WO 2021037021A1 CN 2020111042 W CN2020111042 W CN 2020111042W WO 2021037021 A1 WO2021037021 A1 WO 2021037021A1
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Prior art keywords
pull
control
terminal
node
transistor
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PCT/CN2020/111042
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/424,486 priority Critical patent/US11620934B2/en
Publication of WO2021037021A1 publication Critical patent/WO2021037021A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technology, in particular to a shift register, a driving method thereof, a gate driving circuit, and a display panel.
  • gate drive circuits are generally used to replace gate drive chips to reduce costs.
  • Related technology OLED (Organic Light-Emitting Diode, organic light-emitting diode) gate drive circuit it is very difficult to display and compensate for two waveforms with different cycles and different pulse widths, and the output waveform is complex, and the required circuit structure is usually also very complicated.
  • the embodiment of the present disclosure proposes a shift register, including:
  • a display control circuit the display control circuit is respectively connected to the pull-up node, the first power terminal and the first control terminal, the display control circuit is configured to be in the display mode, under the control of the first control terminal The potential provided by the first power terminal is written into the pull-up node;
  • a sensing control circuit the sensing control circuit is respectively connected to the pull-up node, the second control terminal and the third control terminal, the sensing control circuit is configured to be in the display mode under the control of the second control terminal Storing the potential of the pull-up node, and in the sensing mode, under the control of the third control terminal, writing the stored potential to the pull-up node;
  • a first output circuit the first output circuit is connected to the pull-up node, the first clock terminal and the first output terminal, the first output circuit is configured to control the potential of the pull-up node
  • the first clock signal of the first clock terminal is provided to the first output terminal.
  • the sensing control circuit includes:
  • a sensing input sub-circuit the sensing input sub-circuit is respectively connected to the pull-up node, the holding node and the second control terminal, the sensing input sub-circuit is configured to control the second control terminal Storing the potential of the pull-up node in the holding node;
  • a sensing pull-up sub-circuit the sensing pull-up sub-circuit is respectively connected to the pull-up node, the holding node and the third control terminal, and the sensing pull-up sub-circuit is configured to In the sensing mode, the potential stored in the holding node is written into the pull-up node under the control of the third control terminal.
  • the sensing input sub-circuit includes:
  • the first transistor the first electrode of the first transistor is connected to the pull-up node, the second electrode of the first transistor is connected to the holding node, and the control electrode of the first transistor is connected to the second The control terminal is connected;
  • a first capacitor, one end of the first capacitor is connected to the holding node, and the other end of the first capacitor is connected to a second power terminal.
  • the sensing pull-up sub-circuit includes:
  • a second transistor the first electrode of the second transistor is connected to the holding node, the second electrode of the second transistor is connected to the pull-up node, and the control electrode of the second transistor is connected to the third The control terminal is connected.
  • the first output circuit includes:
  • a third transistor the first electrode of the third transistor is connected to the first clock terminal, the second electrode of the third transistor is connected to the first output terminal, and the control electrode of the third transistor is connected to the first output terminal.
  • the pull-up node is connected;
  • a second capacitor one end of the second capacitor is connected to the control electrode of the third transistor, and the other end of the second capacitor is connected to the second electrode of the third transistor.
  • the shift register further includes:
  • a cascade output circuit the cascade output circuit is connected to a second clock terminal, the pull-up node and a cascade output terminal, the cascade output circuit is configured to control the potential of the pull-up node
  • the second clock signal of the second clock terminal is provided to the cascade output terminal.
  • the cascade output circuit includes:
  • a fourth transistor The first electrode of the fourth transistor is connected to the second clock terminal, the second electrode of the fourth transistor is connected to the cascade output terminal, and the control electrode of the fourth transistor is connected to the second clock terminal.
  • the pull-up nodes are connected.
  • the display control circuit includes:
  • the input sub-circuit is connected to the pull-up node, the first power terminal and the first control terminal, the input sub-circuit is configured to be in the display mode, in the first control Writing the potential provided by the first power terminal into the pull-up node under the control of the terminal;
  • the discharge electronic circuit is respectively connected to the pull-up node, the second power terminal and the discharge control terminal, and the discharge electronic circuit is configured to turn the pull-up node on according to the discharge control signal of the discharge control terminal Discharged to the potential of the second power supply terminal;
  • the pull-down control sub-circuit is connected to the pull-up node, the pull-down node, the first power terminal and the second power terminal, respectively, and the pull-down control sub-circuit is configured to be connected to the upper Under the control of the pull-down node, using the potential of the first power supply terminal and the potential of the second power supply terminal to control the potential of the pull-down node;
  • the first pull-down sub-circuit, the first pull-down sub-circuit is connected to the pull-down node, the pull-up node, the cascade output terminal, and the second power terminal, respectively, and the first pull-down sub-circuit is Configured to pull the pull-up node and the cascade output terminal to the potential of the second power terminal under the control of the pull-down node;
  • a second pull-down sub-circuit is respectively connected to the pull-down node, the first output terminal and the third power terminal, the second pull-down sub-circuit is configured to control the pull-down node Down, pull down the first output terminal to the potential of the third power terminal;
  • a reset sub-circuit the reset sub-circuit is connected to the reset control terminal, the pull-up node and the second power supply terminal, respectively, the reset sub-circuit is configured to under the control of the reset control terminal, The pull-up node is reset to the potential of the second power terminal.
  • the input sub-circuit includes: a fifth transistor, a first pole of the fifth transistor is connected to the first power supply terminal, a second pole of the fifth transistor is connected to the pull-up node, and the The control electrode of the fifth transistor is connected to the first control terminal.
  • the electronic discharge circuit includes: a sixth transistor, a first pole of the sixth transistor is connected to the pull-up node, a second pole of the sixth transistor is connected to the second power terminal, and the The control electrode of the sixth transistor is connected to the discharge control terminal.
  • the pull-down control sub-circuit includes: a seventh transistor and an eighth transistor, the control electrode and the first electrode of the seventh transistor are both connected to the first power supply terminal, and the second electrode of the seventh transistor is connected to the The first electrode of the eighth transistor is connected to the pull-down node, the control electrode of the eighth transistor is connected to the pull-up node, and the second electrode of the eighth transistor is connected to the second power terminal.
  • the first pull-down sub-circuit includes: a ninth transistor and a tenth transistor, a first pole of the ninth transistor is connected to the pull-up node, and a second pole of the ninth transistor is connected to the first pole.
  • the two power terminals are connected, the control electrode of the ninth transistor is connected to the pull-down node, the first electrode of the tenth transistor is connected to the cascade output terminal, and the second electrode of the tenth transistor is connected to the The second power supply terminal is connected, and the control electrode of the tenth transistor is connected to the pull-down node.
  • the second pull-down sub-circuit includes: an eleventh transistor, a first pole of the eleventh transistor is connected to the first output terminal, and a second pole of the eleventh transistor is connected to the third output terminal.
  • the power terminal is connected, and the control electrode of the eleventh transistor is connected to the pull-down node.
  • the reset sub-circuit includes: a twelfth transistor, a first pole of the twelfth transistor M is connected to the pull-up node, and a second pole of the twelfth transistor is connected to the second power supply terminal. Connected, the control electrode of the twelfth transistor is connected to the reset control terminal.
  • the embodiment of the present disclosure also proposes a gate driving circuit, including the above-mentioned shift register in N stages cascaded, where N is an integer greater than one.
  • the first control terminal of the nth stage shift register is connected to the cascade output terminal of the n-2th stage shift register, and the discharge control terminal of the nth stage shift register is connected to the n+3 stage shift register.
  • the embodiment of the present disclosure also provides a display panel including the above-mentioned gate driving circuit.
  • the embodiment of the present disclosure also proposes a driving method of the above-mentioned shift register, including:
  • the display control circuit writes the potential provided by the first power terminal into the pull-up node under the control of the first control terminal, and the sensing control circuit stores the potential of the pull-up node under the control of the second control terminal.
  • the output circuit provides the first clock signal of the first clock terminal to the first output terminal under the control of the potential of the pull-up node;
  • the sensing control circuit writes the stored potential into the pull-up node under the control of the third control terminal
  • the first output circuit writes the stored potential into the pull-up node under the control of the potential of the pull-up node
  • the first clock signal of the first clock terminal is provided to the first output terminal.
  • Fig. 1 is a schematic block diagram of a shift register according to an embodiment of the present invention.
  • Fig. 2 is a block diagram of a shift register according to an embodiment of the present invention.
  • Fig. 3 is a circuit schematic diagram of a shift register according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a signal timing diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a display panel according to an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a driving method of a shift register according to an embodiment of the present invention.
  • Fig. 1 is a block diagram of a shift register according to an embodiment of the present invention.
  • the shift register of the embodiment of the present invention includes: a display control circuit 10, a sensing control circuit 20 and a first output circuit 30.
  • the display control circuit 10 is connected to the pull-up node Q, the first power supply terminal VDD, and the first control terminal G1, respectively.
  • the display control circuit 10 can write the potential provided by the first power terminal VDD to the pull-up node Q under the control of the first control terminal G1 in the display mode.
  • the sensing control circuit 20 is respectively connected to the pull-up node Q, the second control terminal OE and the third control terminal CLKA.
  • the sensing control circuit 20 can store the potential of the pull-up node Q under the control of the second control terminal OE in the display mode.
  • the sensing control circuit 20 can write the potential provided by the first power supply terminal VDD in the display control circuit 10 When the node Q is pulled up, the voltage of the node is controlled and maintained according to the second control signal of the second control terminal OE.
  • the sensing control circuit 20 can write, for example, the stored potential of the holding node into the pull-up node Q under the control of the third control terminal CLKA in the sensing mode.
  • the first output circuit 30 is connected to the pull-up node Q, the first clock terminal CLKE, and the first output terminal OUT ⁇ N>.
  • the first output circuit 30 may provide the first clock signal of the first clock terminal CLKE to the first output terminal OUT ⁇ N> under the control of the potential of the pull-up node Q.
  • the first output circuit 30 may control the first output terminal OUT ⁇ N> to output the gate drive signal according to the potential of the pull-up node Q and the first clock signal of the first clock terminal CLKE in the display mode, and in the sensing mode according to the pull-up The potential of the node Q and the first clock signal of the first clock terminal CLKE control the first output terminal OUT ⁇ N> to output the sensing driving signal.
  • the potential of the first power supply terminal VDD may be a DC high potential.
  • the sensing control circuit 20 includes: a sensing input sub-circuit 21 and a sensing pull-up sub-circuit 22.
  • the sensing input sub-circuit 21 is respectively connected to the pull-up node Q, the holding node H and the second control terminal OE.
  • the sensing input sub-circuit 21 can store the potential of the pull-up node Q under the control of the second control terminal OE in the display mode, for example, when the display control circuit 10 writes the potential provided by the first power terminal VDD to the pull-up node Q According to the second control signal of the second control terminal OE, the potential provided by the first power supply terminal VDD is written into the holding node H.
  • the sensing pull-up sub-circuit 22 is respectively connected to the pull-up node Q, the holding node H and the third control terminal CLKA.
  • the sensing pull-up sub-circuit 22 can write the stored potential of the holding node H into the pull-up node Q in the sensing mode according to the third control signal of the third control terminal CLKA.
  • the second control signal of the second control terminal OE may be a random signal generated by an external circuit such as FPGA (Field-Programmable Gate Array).
  • the shift register further includes: a cascade output circuit 40, the cascade output circuit 40 and the second clock terminal CLKD, the pull-up node Q, and the cascade output terminal CR ⁇ N >Connected.
  • the cascade output circuit 40 can provide the second clock signal of the second clock terminal CLKD to the cascade output terminal CR ⁇ N> under the control of the potential of the pull-up node Q.
  • the cascade output circuit 40 can be in the display mode. , Controlling the cascade output terminal CR ⁇ N> to output the cascade control signal according to the potential of the pull-up node Q and the second clock signal of the second clock terminal CLKD.
  • the display control circuit 10 includes: an input sub-circuit 11, an electronic discharge circuit 12, a pull-down control sub-circuit 13, a first pull-down sub-circuit 14, a second pull-down sub-circuit Sub-circuit 15 and reset sub-circuit 16.
  • the input sub-circuit 11 is respectively connected to the pull-up node Q, the first power terminal VDD and the first control terminal G1.
  • the input sub-circuit 11 is used to write the potential provided by the first power supply terminal VDD to the pull-up node Q under the control of the first control terminal G1 in the display mode.
  • the discharge electronic circuit 12 is respectively connected to the pull-up node Q, the second power supply terminal VGL1 and the discharge control terminal G2.
  • the electronic discharge circuit 12 is used to control the discharge of the pull-up node Q according to the discharge control signal of the discharge control terminal G2, for example, to discharge the pull-up node to the potential of the second power terminal VGL1.
  • the pull-down control sub-circuit 13 is respectively connected to the pull-up node Q, the pull-down node P, the first power supply terminal VDD and the second power supply terminal VGL1.
  • the pull-down control sub-circuit 13 is used to use the potential of the first power terminal VDD and the potential of the second power terminal VGL1 to control the potential of the pull-down node P under the control of the pull-up node Q.
  • the potential of the first power supply terminal VDD or the second power supply terminal VGL1 is written into the pull-down node P.
  • the first pull-down sub-circuit 14 is respectively connected to the pull-down node P, the pull-up node Q, the cascade output terminal CR ⁇ N> and the second power supply terminal VGL1.
  • the first pull-down sub-circuit 14 is used to pull the pull-up node Q and the cascade output terminal CR to the potential of the second power terminal VGL1 under the control of the pull-down node P.
  • the second pull-down sub-circuit 15 is connected to the pull-down node P, the first output terminal OUT ⁇ N>, and the third power supply terminal VGL2, respectively.
  • the second pull-down sub-circuit 15 is used to pull down the first output terminal OUT ⁇ N> to the potential of the third power terminal VGL2 under the control of the pull-down node P.
  • the reset sub-circuit 16 is respectively connected to the reset control terminal TRST, the pull-up node Q and the second power terminal VGL1.
  • the reset sub-circuit 16 is used to pull down the pull-up node Q to the potential of the second power supply VGL1 under the control of the reset control terminal TRST.
  • the potentials of the second power terminal VGL1 and the third power terminal VGL2 are both DC negative potentials, and their values may be the same or different.
  • the potential of the third power terminal VGL2 is higher than the potential of the second power terminal VGL1 .
  • the first control terminal G1 is connected to the cascade output terminal CR ⁇ N> of the first two-stage shift register, and the discharge control terminal G2 is connected to the cascade output terminal CR ⁇ N> of the last three-stage shift register , The following will further describe in detail with reference to FIG. 5.
  • the sensing input sub-circuit 21 includes a first transistor M1 and a first capacitor C1.
  • the first pole of the first transistor M1 is connected to the pull-up node Q, and the second pole of the first transistor M1 is connected to the holding node.
  • H is connected, the control electrode of the first transistor M1 is connected to the second control terminal OE; one end of the first capacitor C1 is connected to the holding node H, and the other end of the first capacitor C1 is connected to the second power terminal VGL1.
  • the sensing pull-up sub-circuit 22 includes: a second transistor M2, the first pole of the second transistor M2 is connected to the holding node H, the second pole of the second transistor M2 is connected to the pull-up node Q, and the first pole of the second transistor M2 is connected to the pull-up node Q.
  • the control electrode of the second transistor M2 is connected to the third control terminal CLKA.
  • the first output circuit 30 includes a third transistor M3 and a second capacitor C2.
  • the first pole of the third transistor M3 is connected to the first clock terminal CLKE, and the second pole of the third transistor M3 is connected to the first clock terminal CLKE.
  • the output terminal OUT ⁇ N> is connected, the control electrode of the third transistor M3 is connected to the pull-up node Q; one end of the second capacitor C2 is connected to the control electrode of the third transistor M3, and the other end of the second capacitor C2 is connected to the third transistor M3
  • the second pole is connected.
  • the cascade output circuit 40 includes a fourth transistor M4, the first pole of the fourth transistor M4 is connected to the second clock terminal CLKD, and the second pole of the fourth transistor M4 is connected to the cascade output terminal CR.
  • the control electrode of the fourth transistor M4 is connected to the pull-up node Q.
  • the input sub-circuit 11 includes: a fifth transistor M5, the first pole of the fifth transistor M5 is connected to the first power supply terminal VDD, the second pole of the fifth transistor M5 is connected to the pull-up node Q, and the fifth transistor M5 is connected to the pull-up node Q.
  • the control electrode of the transistor M5 is connected to the first control terminal G1.
  • the discharge electronic circuit 12 includes: a sixth transistor M6, the first pole of the sixth transistor M6 is connected to the pull-up node Q, the second pole of the sixth transistor M6 is connected to the second power supply terminal VGL1, and the sixth transistor M6 is connected to the second power terminal VGL1.
  • the control electrode of the transistor M6 is connected to the discharge control terminal G2.
  • the pull-down control sub-circuit 13 includes: a seventh transistor M7 and an eighth transistor M8.
  • the control electrode and the first electrode of the seventh transistor M7 are both connected to the first power supply terminal VDD, and the second transistor M7 is connected to the first power supply terminal VDD.
  • the electrode is connected to the first electrode of the eighth transistor M8, the control electrode of the eighth transistor M8 is connected to the pull-up node Q, and the second electrode of the eighth transistor M8 is connected to the second power terminal VGL1.
  • the first pull-down sub-circuit 14 includes a ninth transistor M9 and a tenth transistor M10.
  • the first pole of the ninth transistor M9 is connected to the pull-up node Q, and the second pole of the ninth transistor M9 is connected to the
  • the two power supply terminals VGL1 are connected, the control electrode of the ninth transistor M9 is connected to the pull-down node P; the first electrode of the tenth transistor M10 is connected to the cascade output terminal CR ⁇ N>, and the second electrode of the tenth transistor M10 is connected to the second power supply
  • the terminal VGL1 is connected, and the control electrode of the tenth transistor M10 is connected to the pull-down node P.
  • the second pull-down sub-circuit 15 includes: an eleventh transistor M11, a first pole of the eleventh transistor M11 is connected to the first output terminal OUT ⁇ N>, and a second pole of the eleventh transistor M11 is connected to the first output terminal OUT ⁇ N>.
  • the third power supply terminal VGL2 is connected, and the control electrode of the eleventh transistor M11 is connected to the pull-down node P.
  • the reset sub-circuit 16 includes: a twelfth transistor M12, a first pole of the twelfth transistor M12 is connected to the pull-up node Q, and a second pole of the twelfth transistor M12 is connected to the second power terminal VGL1 ,
  • the control electrode of the twelfth transistor M12 is connected to the reset control terminal TRST.
  • an NPN type MOSFET or an IGBT transistor is taken as an example for description.
  • first capacitor C1 and the second capacitor C2 may be parasitic capacitors of transistors, or may be external capacitors.
  • an embodiment of the present invention also provides a gate driving circuit including multiple stages of the shift register described above.
  • FIG. 4 is a schematic diagram of a gate driving circuit according to an embodiment of the invention.
  • the gate driving circuit includes N stages of cascaded shift registers according to any one of claims 1-14, wherein N is an integer greater than 1.
  • the first control terminal of the nth stage shift register is connected to the cascade output terminal of the n-2th stage shift register, and the discharge control terminal of the nth stage shift register is connected to the n+3 stage The cascade output terminal of the shift register, where n is an integer, 3 ⁇ n ⁇ N-3.
  • the first control terminal G1 of the first stage shift register A1 and the second stage shift register A2 inputs the preset input signal STU, and the discharge control terminal G2 of the first stage shift register A1 is connected to the fourth stage The cascade output terminal CR ⁇ 4> of the shift register A4; the discharge control terminal G2 of the second stage shift register A2 is connected to the cascade output terminal CR ⁇ 5> of the fifth stage shift register A5; the third stage shift register The first control terminal G1 of A3 is connected to the cascade output terminal CR ⁇ 1> of the first stage shift register A1, and the discharge control terminal G2 of the third stage shift register A2 is connected to the cascade output terminal of the sixth stage shift register A6 CR ⁇ 6>; the first control terminal G1 of the fourth-stage shift register A4 is connected to the cascade output terminal CR ⁇ 2> of the second-stage shift register A2, and the discharge control terminal G2 of the fourth-stage shift register A4 is connected to the first The cascade output terminal CR ⁇ 7> of the seven
  • the gate drive circuit is controlled by 8 clock signals CLKD_1, CLKE_1, ... CLKD_4, CLKE_4, among which the shift registers are divided into multiple groups, each group includes four-stage cascaded shift registers, which are respectively connected to receive These 8 clock signals.
  • the first clock terminal and the second clock terminal of the first-stage shift register A1 are respectively connected to receive clock signals CLKD_1 and CLKE_1, the first clock terminal and the second clock terminal of the second-stage shift register A2 They are connected to receive clock signals CLKD_2 and CLKE_2, the first clock terminal and the second clock terminal of the third-stage shift register A3 are connected to receive clock signals CLKD_3 and CLKE_3, respectively, and the first clock terminal of the fourth-stage shift register A4 and The second clock terminal is respectively connected to receive clock signals CLKD_4 and CLKE_4.
  • first clock terminal and the second clock terminal of the fifth stage shift register A5 are respectively connected to receive clock signals CLKD_1 and CLKE_1, and the first clock terminal and the second clock terminal of the sixth stage shift register A6 are respectively connected
  • the connection is to receive the clock signals CLKD_2 and CLKE_2, and so on.
  • the second control terminal OE of each shift register is connected to receive the second control signal (indicated by OE in Figure 4), and the third control terminal is connected to CLKA to receive the third control signal (in Figure 4 by CLKA), the reset control terminal TRST is connected to receive the reset control signal (indicated by TRST in FIG. 4).
  • the gate drive circuit proposed by the embodiment of the present invention by providing a multi-stage shift register, it is possible to output mixed pulses for display and compensation, and to compensate for any row of pixels in any frame of display mode, and
  • the circuit structure is simple.
  • the working principle of the embodiment of FIG. 4 is as follows. The following will take the fourth stage shift register A4 in the embodiment of FIG. 4 as an example to describe the signal timing of the shift register in the embodiment of the present disclosure.
  • H ⁇ 4> is the potential signal of the holding node H of the fourth-stage shift register
  • Q ⁇ 3> is the potential signal of the pull-up node Q of the third-stage shift register
  • Q ⁇ 4> is The potential signal of the pull-up node of the fourth-stage shift register
  • OUT ⁇ 3> is the output signal of the first output terminal of the third-stage shift register
  • OUT ⁇ 4> is the output of the first output terminal of the fourth-stage shift register Signal
  • CR ⁇ 2> is the output signal of the cascade output terminal of the second stage shift register
  • CR ⁇ 7> is the output signal of the cascade output terminal of the seventh stage shift register.
  • the pulse width relationship of the third control signal of the third control terminal CLKA, the second clock signal of the second clock terminal CLKD, the first clock signal of the first clock terminal CLKE, and the output signal of the reset control terminal TRST is adjustable.
  • the output signal CR ⁇ 2> of the cascade output terminal of the second stage shift register is a high level signal, so that the first control terminal G1 of the fourth stage shift register outputs a high level signal .
  • the high level signal of the first control terminal G1 turns on the fifth transistor M5, and the high potential provided by the first power supply terminal VDD is written to the pull-up node through the fifth transistor M5 Q ⁇ 4>, the second capacitor C2 is charged, and the third transistor M3 and the fourth transistor M4 are pre-turned on.
  • the second control signal output by the second control terminal OE is a high-level signal, so that the first transistor M1 is turned on, and the high potential provided by the first power supply terminal VDD is written into the holding node H through the fifth transistor M5 and the first transistor M1. ⁇ 4>, and held by the first capacitor C1.
  • the third control signal output by the third control terminal CLKA is a low-level signal, and the second transistor M2 is turned off.
  • the clock signal CLKE_4 is at a low level, so that the first clock signal output by the first clock terminal CLKE of the fourth-stage shift register is a low-level signal, so that the cascade output terminal CR ⁇ 4> of the fourth-stage shift register outputs a low level.
  • the clock signal CLKD_4 is low level, so that the second clock signal output by the second clock terminal CLKD of the fourth-stage shift register is a low-level signal, so that the first output terminal OUT of the fourth-stage shift register is less than 4 > The output is low.
  • the clock signal CLKE_4 is at a high level, so that the first clock signal output by the first clock terminal CLKE of the fourth-stage shift register is a high-level signal; the clock signal CLKD_4 is at a high level, The second clock signal output by the second clock terminal CLKD of the fourth-stage shift register is a high-level signal.
  • the potential of the pull-up node Q ⁇ 4> of the fourth-stage shift register is acted by the second capacitor C2.
  • the third transistor M3 and the fourth transistor M4 are fully turned on, so that the cascade output terminal CR ⁇ 4> of the fourth stage shift register outputs a high potential, and the first output terminal OUT ⁇ 4 of the fourth stage shift register > The output is high.
  • the third control signal output by the third control terminal CLKA is still a low-level signal
  • the second transistor M2 is still turned off
  • the second control signal output by the second control terminal OE becomes a low-level signal.
  • a transistor M1 is turned off, the output signal of the reset control terminal TRST is a low level signal, and the twelfth transistor M12 is turned off.
  • the clock signal CLKE_4 becomes a low level, so that the first clock signal output by the first clock terminal CLKE of the fourth shift register becomes a low level signal; the clock signal CLKD_4 becomes a low level signal , So that the second clock signal output by the second clock terminal CLKD of the fourth shift register becomes a low level signal, so that the cascade output terminal CR ⁇ 4> of the fourth shift register outputs a low level, and the fourth shift register
  • the first output terminal OUT ⁇ 4> outputs a low potential.
  • the cascade output terminal CR ⁇ 7> of the seventh shift register outputs a high level, so that the discharge control signal output by the discharge control terminal G2 of the fourth stage shift register is a high level signal .
  • the high level signal of the discharge control terminal G2 turns on the sixth transistor M6, the pull-up node Q ⁇ 4> is discharged by the second power terminal VGL1, and the potential of the pull-up node Q ⁇ 4> Pulled low, the reset of the pull-up node Q ⁇ 4> is complete.
  • the holding node H ⁇ 4> of the fourth-stage shift register remains at a high potential until the Blank (blank display) period.
  • the sensing mode is performed during the Blank period.
  • the third control signal output by the third control terminal CLKA of the fourth stage shift register is a high-level signal, and the second transistor M2 is turned on.
  • the cascade output terminal CR ⁇ 2> of the second-stage shift register and the second control signal OE are both high-level signals during the fourth-stage shift register
  • the holding node H ⁇ 4> stores the high level, so at this time, the high potential stored in the holding node H ⁇ 4> in the fourth-stage shift register is written into the pull-up node Q ⁇ 4> through the second transistor M2, and passes The second capacitor C2 is maintained.
  • the third control signal output by the third control terminal CLKA is a low-level signal
  • the second transistor M2 is turned off
  • the first clock terminal CLKE outputs
  • the first clock signal of is a low potential signal.
  • the potential of the pull-up node Q ⁇ 4> is maintained at a high potential
  • the fourth transistor M4 is turned on, so that the first output terminal OUT ⁇ 4> outputs a low potential.
  • the first clock signal output by the first clock terminal CLKE becomes a high-level signal, so that the first output terminal OUT ⁇ 4> becomes an output high-level signal ,
  • the bootstrap effect of the second capacitor C2 causes the potential of the pull-up node Q ⁇ 4> to further increase.
  • the first clock signal output by the first clock terminal CLKE becomes a low level signal, so that the first output terminal OUT ⁇ 4> becomes an output low level signal .
  • the output signal of the reset control terminal TRST is a high level signal
  • the twelfth transistor M12 is turned on, and the pull-up node Q ⁇ 4> is pulled down to the fourth stage.
  • the potential of the second power supply terminal VGL1 is the low potential
  • the second control signal output by the second control terminal OE is a high-level signal. Therefore, the first transistor M1 is turned on, and the low potential of the pull-up node Q ⁇ 4> passes through the first transistor. M1 writes to the holding node H ⁇ 4> to reset the holding node H ⁇ 4>.
  • the second control signal output by the second control terminal OE and the output signal of the reset control terminal TRST are both high-level signals, so that the first transistor M1 and the twelfth transistor M12 Turn on to reset the holding node H and the pull-up node Q of all rows, and then, in the display mode, it can realize compensation for any pixel row.
  • the display control circuit is connected to the pull-up node, the first power terminal and the first control terminal respectively, and the display control circuit is used in the display mode under the control of the first control terminal.
  • the potential provided by the first power terminal is written into the pull-up node, and the sensing control circuit is connected to the pull-up node, the second control terminal, and the third control terminal.
  • the sensing control circuit is used to connect the first power terminal to the display control circuit.
  • the potential of the holding node is controlled according to the second control signal of the second control terminal, and in the sensing mode, under the control of the third control terminal, the stored potential of the holding node is written to the pull-up node ,
  • the first output circuit is connected to the pull-up node, the first clock terminal, and the first output terminal.
  • the first output circuit is used in the display mode or the sensing mode according to the potential of the pull-up node and the first clock terminal.
  • the clock signal controls the first output terminal to output a gate driving signal or a sensing driving signal. Therefore, the shift register of the embodiment of the present invention can realize the output of mixed pulses for display and compensation, and can realize the compensation of any row of pixels in the display mode of any frame, and the circuit structure is simple.
  • an embodiment of the present invention also provides a display panel.
  • FIG. 6 is a schematic diagram of a display panel according to an embodiment of the invention.
  • the display panel 600 includes a gate driving circuit 601, where the gate driving circuit 601 can be implemented by the gate driving circuit of any of the foregoing embodiments.
  • the display panel 600 may include multiple stages of gate driving circuits 601.
  • the gate driving circuit can be provided to output mixed pulses for display and compensation, and can realize compensation for any row of pixels in any frame of display mode, and the circuit structure simple.
  • the embodiment of the present invention also provides a driving method of the shift register.
  • FIG. 7 is a schematic flowchart of a driving method of a shift register according to an embodiment of the present invention. As shown in FIG. 7, the driving method of the shift register in the embodiment of the present invention includes the following steps:
  • the display control circuit writes the potential provided by the first power terminal into the pull-up node under the control of the first control terminal, and the sensing control circuit stores the potential of the pull-up node under the control of the second control terminal Under the control of the potential of the pull-up node, the first output circuit provides the first clock signal of the first clock terminal to the first output terminal for output to be used as a gate drive signal.
  • the sensing control circuit writes the stored potential into the pull-up node under the control of the third control terminal
  • the first output circuit writes the first clock terminal of the first clock terminal under the control of the potential of the pull-up node.
  • the clock signal is provided to the first output terminal to be used as a sensing driving signal.
  • the display control circuit writes the potential provided by the first power terminal to the pull-up node under the control of the first control terminal, and at the same time, the sensing control The circuit controls the potential of the holding node according to the second control signal of the second control terminal, and the first output circuit controls the first output terminal to output the gate drive signal according to the potential of the pull-up node and the first clock signal of the first clock terminal.
  • the sensing control circuit In the sensing mode Under the control of the third control terminal, the sensing control circuit writes the stored potential of the holding node into the pull-up node, and the first output circuit controls the first output terminal to output according to the potential of the pull-up node and the first clock signal of the first clock terminal Sense the drive signal. Therefore, the driving method of the shift register of the embodiment of the present invention can realize the output of mixed pulses for display and compensation, and can realize the compensation of any row of pixels in the display mode of any frame, and the circuit structure is simple.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present invention, “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.
  • a "computer-readable medium” can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, device, or device or in combination with these instruction execution systems, devices, or devices.
  • computer readable media include the following: electrical connections (electronic devices) with one or more wiring, portable computer disk cases (magnetic devices), random access memory (RAM), Read only memory (ROM), erasable and editable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disk read only memory (CDROM).
  • the computer-readable medium can even be paper or other suitable media on which the program can be printed, because it can be done, for example, by optically scanning the paper or other media, and then editing, interpreting, or other suitable media if necessary.
  • the program is processed in a way to obtain the program electronically and then stored in the computer memory.
  • each part of the present invention can be implemented by hardware, software, firmware or a combination thereof.
  • multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.
  • Discrete logic gate circuits with logic functions for data signals Logic circuit, application specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA), etc.
  • a person of ordinary skill in the art can understand that all or part of the steps carried in the method of the foregoing embodiments can be implemented by a program instructing relevant hardware to complete.
  • the program can be stored in a computer-readable storage medium. When executed, it includes one of the steps of the method embodiment or a combination thereof.
  • the aforementioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Abstract

本发明提出一种移位寄存器及其驱动方法、栅极驱动电路、显示面板，其中，移位寄存器包括：显示控制电路，显示控制电路分别与上拉节点、第一电源端和第一控制端相连；感测控制电路，感测控制电路分别与上拉节点、第二控制端和第三控制端相连，所述感测控制电路被配置为在显示模式，在所述第二控制端的控制下存储所述上拉节点的电位，以及在感测模式，在所述第三控制端的控制下，将所存储的电位写入所述上拉节点；第一输出电路，第一输出电路与上拉节点、第一时钟端和第一输出端相连。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示面板
本申请要求于2019年8月30日提交的、申请号为201910816758.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示面板。
背景技术
在显示技术领域，一般采用栅极驱动电路替代栅极驱动芯片以减少成本。相关技术的OLED(Organic Light-Emitting Diode，有机发光二极管)栅极驱动电路，要实现显示和补偿两种不同周期不同脉宽的波形是非常困难的，并且输出波形复杂，需要的电路结构通常也非常复杂。
发明内容
本公开的实施例提出了一种移位寄存器，包括：
显示控制电路，所述显示控制电路分别与上拉节点、第一电源端和第一控制端相连，所述显示控制电路被配置为在显示模式，在所述第一控制端的控制下将所述第一电源端提供的电位写入所述上拉节点；
感测控制电路，所述感测控制电路分别与上拉节点、第二控制端和第三控制端相连，所述感测控制电路被配置为在显示模式，在所述第二控制端的控制下存储所述上拉节点的电位，以及在感测模式，在所述第三控制端的控制下，将所存储的电位写入所述上拉节点；
第一输出电路，所述第一输出电路与所述上拉节点、第一时钟端和第一输出端相连，所述第一输出电路被配置为在所述上拉节点的电位的控制下将所述第一时钟端的第一时钟信号提供至所述第一输出端。
例如，所述感测控制电路包括：
感测输入子电路，所述感测输入子电路分别与所述上拉节点、保持节点和所述第二 控制端相连，所述感测输入子电路被配置为在所述第二控制端的控制下将所述上拉节点的电位存储在所述保持节点；
感测上拉子电路，所述感测上拉子电路分别与所述上拉节点、所述保持节点和所述第三控制端相连，所述感测上拉子电路被配置为在所述感测模式，在所述第三控制端的控制下将所述保持节点存储的电位写入所述上拉节点。
例如，所述感测输入子电路包括：
第一晶体管，所述第一晶体管的第一极与所述上拉节点相连，所述第一晶体管的第二极与所述保持节点相连，所述第一晶体管的控制极与所述第二控制端相连；
第一电容，所述第一电容的一端与所述保持节点相连，所述第一电容的另一端与第二电源端相连。
例如，所述感测上拉子电路包括：
第二晶体管，所述第二晶体管的第一极与所述保持节点相连，所述第二晶体管的第二极与所述上拉节点相连，所述第二晶体管的控制极与所述第三控制端相连。
例如，所述第一输出电路包括：
第三晶体管，所述第三晶体管的第一极与所述第一时钟端相连，所述第三晶体管的第二极与所述第一输出端相连，所述第三晶体管的控制极与所述上拉节点相连；
第二电容，所述第二电容的一端与所述第三晶体管的控制极相连，所述第二电容的另一端与所述第三晶体管的第二极相连。
例如，所述移位寄存器还包括：
级联输出电路，所述级联输出电路与第二时钟端、所述上拉节点和级联输出端相连，所述级联输出电路被配置为在所述上拉节点的电位的控制下将所述第二时钟端的第二时钟信号提供至所述级联输出端。
例如，所述级联输出电路包括：
第四晶体管，所述第四晶体管的第一极与所述第二时钟端相连，所述第四晶体管的第二极与所述级联输出端相连，所述第四晶体管的控制极与所述上拉节点相连。
例如，所述显示控制电路包括：
输入子电路，所述输入子电路分别与所述上拉节点、所述第一电源端和所述第一控制端相连，所述输入子电路被配置为在显示模式，在所述第一控制端的控制下将所述第一电源端提供的电位写入所述上拉节点；
放电子电路，所述放电子电路分别与所述上拉节点、第二电源端和放电控制端相连，所述放电子电路被配置为根据所述放电控制端的放电控制信号将所述上拉节点放电至所述第二电源端的电位；
下拉控制子电路，所述下拉控制子电路分别与所述上拉节点、下拉节点、所述第一电源端和所述第二电源端相连，所述下拉控制子电路被配置为在所述上拉节点的控制下，使用所述第一电源端的电位和所述第二电源端的电位来控制所述下拉节点的电位；
第一下拉子电路，所述第一下拉子电路分别与所述下拉节点、所述上拉节点、所述级联输出端和第二电源端相连，所述第一下拉子电路被配置为在所述下拉节点的控制下，将所述上拉节点和所述级联输出端下拉至所述第二电源端的电位；
第二下拉子电路，所述第二下拉子电路分别与所述下拉节点、所述第一输出端和第三电源端相连，所述第二下拉子电路被配置为在所述下拉节点的控制下，将所述第一输出端下拉至所述第三电源端的电位；
复位子电路，所述复位子电路分别与所述复位控制端、所述上拉节点和所述第二电源端相连，所述复位子电路被配置为在所述复位控制端的控制下，将所述上拉节点复位至所述第二电源端的电位。
例如，所述输入子电路包括：第五晶体管，所述第五晶体管的第一极与所述第一电源端相连，所述第五晶体管的第二极与所述上拉节点相连，所述第五晶体管的控制极与所述第一控制端相连。
例如，所述放电子电路包括：第六晶体管，所述第六晶体管的第一极与所述上拉节点相连，所述第六晶体管的第二极与所述第二电源端相连，所述第六晶体管的控制极与所述放电控制端相连。
例如，所述下拉控制子电路包括：第七晶体管和第八晶体管，所述第七晶体管的控制极和第一极均与第一电源端相连，所述第七晶体管的第二极和所述第八晶体管的第一极与所述下拉节点相连，所述第八晶体管的控制极与所述上拉节点相连，所述第八晶体管的第二极与所述第二电源端相连。
例如，所述第一下拉子电路包括：第九晶体管和第十晶体管，所述第九晶体管的第一极与所述上拉节点相连，所述第九晶体管的第二极与所述第二电源端相连，所述第九晶体管的控制极与所述下拉节点相连，所述第十晶体管的第一极与所述级联输出端相连，所述第十晶体管的第二极与所述第二电源端相连，所述第十晶体管的控制极与所述下拉 节点相连。
例如，所述第二下拉子电路包括：第十一晶体管，所述第十一晶体管的第一极与所述第一输出端相连，所述第十一晶体管的第二极与所述第三电源端相连，所述第十一晶体管的控制极与所述下拉节点相连。
例如，所述复位子电路包括：第十二晶体管，所述第十二晶体管M的第一极与所述上拉节点相连，所述第十二晶体管的第二极与所述第二电源端相连，所述第十二晶体管的控制极与所述复位控制端相连。
本公开的实施例还提出了一种栅极驱动电路，包括N级级联的上述移位寄存器，其中N为大于1的整数。
例如，第n级移位寄存器的第一控制端连接第n-2级移位寄存器的级联输出端，所述第n级移位寄存器的放电控制端连接第n+3级移位寄存器的级联输出端，其中n为整数，3≤n≤N-3。
本公开的实施例还提出了一种显示面板，包括上述栅极驱动电路。
本公开的实施例还提出了一种上述移位寄存器的驱动方法，包括：
在显示模式，显示控制电路在第一控制端的控制下将第一电源端提供的电位写入上拉节点，感测控制电路在第二控制端的控制下存储所述上拉节点的电位，第一输出电路在所述上拉节点的电位的控制下将第一时钟端的第一时钟信号提供至第一输出端；
在感测模式，所述感测控制电路在第三控制端的控制下，将所存储的电位写入所述上拉节点，所述第一输出电路在所述上拉节点的电位的控制下将所述第一时钟端的第一时钟信号提供至所述第一输出端。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为根据本发明实施例的移位寄存器的方框示意图；
图2为根据本发明一个实施例的移位寄存器的方框示意图；
图3为根据本发明一个实施例的移位寄存器的电路原理图；
图4为根据本发明一个实施例的栅极驱动电路的示意图；
图5为根据本发明一个实施例的栅极驱动电路的信号时序图；
图6为根据本发明一个实施例的显示面板的示意图；
图7为根据本发明实施例的移位寄存器的驱动方法流程示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
下面参考附图描述本发明实施例的移位寄存器及其驱动方法、栅极驱动电路、显示面板。
图1为根据本发明实施例的移位寄存器的方框示意图。如图1所示，本发明实施例的移位寄存器包括：显示控制电路10、感测控制电路20和第一输出电路30。
如图1所示，显示控制电路10分别与上拉节点Q、第一电源端VDD和第一控制端G1相连。显示控制电路10可以在显示模式，在第一控制端G1的控制下将第一电源端VDD提供的电位写入上拉节点Q。感测控制电路20分别与上拉节点Q、第二控制端OE和第三控制端CLKA相连。感测控制电路20可以在显示模式在所述第二控制端OE的控制下存储上拉节点Q的电位，例如感测控制电路20可以在显示控制电路10将第一电源端VDD提供的电位写入上拉节点Q时，根据第二控制端OE的第二控制信号控制保持节点的电位。感测控制电路20可以在感测模式，在第三控制端CLKA的控制下，将例如保持节点存储的电位写入上拉节点Q。第一输出电路30与上拉节点Q、第一时钟端CLKE和第一输出端OUT<N>相连。第一输出电路30可以在上拉节点Q的电位的控制下将第一时钟端CLKE的第一时钟信号提供至第一输出端OUT<N>。例如第一输出电路30可以在显示模式根据上拉节点Q的电位和第一时钟端CLKE的第一时钟信号控制第一输出端OUT<N>输出栅极驱动信号，在感测模式根据上拉节点Q的电位和第一时钟端CLKE的第一时钟信号控制第一输出端OUT<N>输出感测驱动信号。
需要说明的是，第一电源端VDD的电位可以为直流高电位。
根据本发明的一个实施例，如图2所示，感测控制电路20包括：感测输入子电路 21和感测上拉子电路22。感测输入子电路21分别与上拉节点Q、保持节点H和第二控制端OE相连。感测输入子电路21可以在显示模式，在第二控制端OE的控制下存储上拉节点Q的电位，例如在显示控制电路10将第一电源端VDD提供的电位写入上拉节点Q时，根据第二控制端OE的第二控制信号，将第一电源端VDD提供的电位写入保持节点H。感测上拉子电路22分别与上拉节点Q、保持节点H和第三控制端CLKA相连。感测上拉子电路22可以在感测模式，根据第三控制端CLKA的第三控制信号，将保持节点H存储的电位写入上拉节点Q。
其中，第二控制端OE的第二控制信号可为外部电路例如FPGA(Field-Programmable Gate Array，现场可编程门阵列)产生的随机信号。
根据本发明的一个实施例，如图2所示，移位寄存器还包括：级联输出电路40，级联输出电路40与第二时钟端CLKD、上拉节点Q和级联输出端CR<N>相连。级联输出电路40可以在上拉节点Q的电位的控制下将第二时钟端CLKD的第二时钟信号提供至所述级联输出端CR<N>，例如级联输出电路40可以在显示模式，根据上拉节点Q的电位和第二时钟端CLKD的第二时钟信号控制级联输出端CR<N>输出级联控制信号。
进一步地，根据本发明的一个实施例，如图2所示，显示控制电路10包括：输入子电路11、放电子电路12、下拉控制子电路13、第一下拉子电路14、第二下拉子电路15和复位子电路16。输入子电路11分别与上拉节点Q、第一电源端VDD和第一控制端G1相连。输入子电路11用于在显示模式，在第一控制端G1的控制下将第一电源端VDD提供的电位写入上拉节点Q。放电子电路12分别与上拉节点Q、第二电源端VGL1和放电控制端G2相连。放电子电路12用于根据放电控制端G2的放电控制信号控制上拉节点Q的放电，例如将所述上拉节点放电至第二电源端VGL1的电位。下拉控制子电路13分别与上拉节点Q、下拉节点P和第一电源端VDD和第二电源端VGL1相连。下拉控制子电路13用于在上拉节点Q的控制下使用第一电源端VDD的电位和第二电源端VGL1的电位来控制下拉节点P的电位，例如在上拉节点Q的控制下，将第一电源端VDD或第二电源端VGL1的电位写入下拉节点P。第一下拉子电路14分别与下拉节点P、上拉节点Q、级联输出端CR<N>和第二电源端VGL1相连。第一下拉子电路14用于在下拉节点P的控制下，将上拉节点Q和级联输出端CR下拉至第二电源端VGL1的电位。第二下拉子电路15分别与下拉节点P、第一输出端OUT<N>和第 三电源端VGL2相连。第二下拉子电路15用于在下拉节点P的控制下，将第一输出端OUT<N>下拉至第三电源端VGL2的电位。复位子电路16分别与复位控制端TRST、上拉节点Q和第二电源端VGL1相连。复位子电路16用于在复位控制端TRST的控制下，将上拉节点Q下拉至第二电源VGL1的电位。
需要说明的是，第二电源端VGL1和第三电源端VGL2的电位均为直流负电位，其值可相同可不相同，优选地，第三电源端VGL2的电位高于第二电源端VGL1的电位。
根据本发明的一个实施例，第一控制端G1连接前两级移位寄存器的级联输出端CR<N>，放电控制端G2连接后三级移位寄存器的级联输出端CR<N>，下文将参考图5来进一步详细说明。
下面结合图3对本发明实施例的移位寄存器的结构进行说明。
如图3所示，感测输入子电路21包括：第一晶体管M1和第一电容C1，第一晶体管M1的第一极与上拉节点Q相连，第一晶体管M1的第二极与保持节点H相连，第一晶体管M1的控制极与第二控制端OE相连；第一电容C1的一端与保持节点H相连，第一电容C1的另一端与第二电源端VGL1相连。
如图3所示，感测上拉子电路22包括：第二晶体管M2，第二晶体管M2的第一极与保持节点H相连，第二晶体管M2的第二极与上拉节点Q相连，第二晶体管M2的控制极与第三控制端CLKA相连。
如图3所示，第一输出电路30包括：第三晶体管M3和第二电容C2，第三晶体管M3的第一极与第一时钟端CLKE相连，第三晶体管M3的第二极与第一输出端OUT<N>相连，第三晶体管M3的控制极与上拉节点Q相连；第二电容C2的一端与第三晶体管M3的控制极相连，第二电容C2的另一端与第三晶体管M3的第二极相连。
如图3所示，级联输出电路40包括：第四晶体管M4，第四晶体管M4的第一极与第二时钟端CLKD相连，第四晶体管M4的第二极与级联输出端CR相连，第四晶体管M4的控制极与上拉节点Q相连。
如图3所示，输入子电路11包括：第五晶体管M5，第五晶体管M5的第一极与第一电源端VDD相连，第五晶体管M5的第二极与上拉节点Q相连，第五晶体管M5的控制极与第一控制端G1相连。
如图3所示，放电子电路12包括：第六晶体管M6，第六晶体管M6的第一极与上拉节点Q相连，第六晶体管M6的第二极与第二电源端VGL1相连，第六晶体管M6的 控制极与放电控制端G2相连。
如图3所示，下拉控制子电路13包括：第七晶体管M7和第八晶体管M8，第七晶体管M7的控制极和第一极均与第一电源端VDD相连，第七晶体管M7的第二极与第八晶体管M8的第一极相连，第八晶体管M8的控制极与上拉节点Q相连，第八晶体管M8的第二极与第二电源端VGL1相连。
如图3所示，第一下拉子电路14包括：第九晶体管M9和第十晶体管M10，第九晶体管M9的第一极与上拉节点Q相连，第九晶体管M9的第二极与第二电源端VGL1相连，第九晶体管M9的控制极与下拉节点P相连；第十晶体管M10的第一极与级联输出端CR<N>相连，第十晶体管M10的第二极与第二电源端VGL1相连，第十晶体管M10的控制极与下拉节点P相连。
如图3所示，第二下拉子电路15包括：第十一晶体管M11，第十一晶体管M11的第一极与第一输出端OUT<N>相连，第十一晶体管M11的第二极与第三电源端VGL2相连，第十一晶体管M11的控制极与下拉节点P相连。
如图3所示，复位子电路16包括：第十二晶体管M12，第十二晶体管M12的第一极与上拉节点Q相连，第十二晶体管M12的第二极与第二电源端VGL1相连，第十二晶体管M12的控制极与复位控制端TRST相连。
需要说明的是，在本发明实施例中，以NPN型MOSFET或IGBT晶体管为例说明。
还需说明的是，第一电容C1和第二电容C2可以为晶体管的寄生电容，也可以为外接电容。
基于上述实施例的移位寄存器，本发明实施例还提出一种栅极驱动电路，包括多级前述的移位寄存器。
图4为根据本发明一个实施例的栅极驱动电路的示意图。
如图4所示，栅极驱动电路包括N级级联的如权利要求1-14中任一项所述的移位寄存器，其中N为大于1的整数。在一些实施例中，第n级移位寄存器的第一控制端连接第n-2级移位寄存器的级联输出端，所述第n级移位寄存器的放电控制端连接第n+3级移位寄存器的级联输出端，其中n为整数，3≤n≤N-3。例如在图4中，第一级移位寄存器A1和第二级移位寄存器A2的第一控制端G1输入预设输入信号STU，第一级移位寄存器A1的放电控制端G2连接第四级移位寄存器A4的级联输出端CR<4>；第二级移位寄存器A2的放电控制端G2连接第五级移位寄存器A5的级联输出端CR<5>； 第三级移位寄存器A3的第一控制端G1连接第一级移位寄存器A1的级联输出端CR<1>，第三级移位寄存器A2的放电控制端G2连接第六级移位寄存器A6的级联输出端CR<6>；第四级移位寄存器A4的第一控制端G1连接第二级移位寄存器A2的级联输出端CR<2>，第四级移位寄存器A4的放电控制端G2连接第七级移位寄存器A7的级联输出端CR<7>，以此类推。
在图4中，栅极驱动电路由8个时钟信号CLKD_1，CLKE_1，…CLKD_4，CLKE_4来控制，其中移位寄存器分为多组，每组包括四级级联的移位寄存器，分别连接为接收这8个时钟信号。如图4所示，第一级移位寄存器A1的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_1和CLKE_1，第二级移位寄存器A2的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_2和CLKE_2，第三级移位寄存器A3的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_3和CLKE_3，第四级移位寄存器A4的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_4和CLKE_4。以类似的方式，第五级移位寄存器A5的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_1和CLKE_1，第六级移位寄存器A6的第一时钟端和第二时钟端分别连接为接收时钟信号CLKD_2和CLKE_2，以此类推。
在图4中，各个移位寄存器的第二控制端OE连接为接收第二控制信号(在图4中由OE表示)，第三控制端连接CLKA为接收第三控制信号(在图4中由CLKA表示)，复位控制端TRST连接为接收复位控制信号(在图4中由TRST表示)。
根据本发明实施例提出的栅极驱动电路，通过设置的多级移位寄存器，可实现输出用于显示和补偿的混合脉冲，并可实现在任意帧的显示模式对任意行像素进行补偿，且该电路结构简单。
结合图5的时序图，图4实施例的工作原理如下。下面将以图4实施例中的第四级移位寄存器A4为例来对本公开实施例的移位寄存器的信号时序进行说明。
如图5所示，H<4>为第四级移位寄存器的保持节点H的电位信号，Q<3>为第三级移位寄存器的上拉节点Q的电位信号，Q<4>为第四级移位寄存器的上拉节点的电位信号，OUT<3>为第三级移位寄存器的第一输出端的输出信号，OUT<4>为第四级移位寄存器的第一输出端的输出信号，CR<2>为第二级移位寄存器的级联输出端的输出信号，CR<7>为第七级移位寄存器的级联输出端的输出信号。其中，第三控制端CLKA的第三控制信号、第二时钟端CLKD的第二时钟信号、第一时钟端CLKE的第一时钟信号以 及复位控制端TRST的输出信号的脉宽关系可调。
在显示模式的第一阶段T1，第二级移位寄存器的级联输出端的输出信号CR<2>为高电平信号，使得第四级移位寄存器的第一控制端G1输出高电平信号。参考图4，在第四级移位寄存器中，第一控制端G1的高电平信号使第五晶体管M5导通，第一电源端VDD提供的高电位通过第五晶体管M5写入上拉节点Q<4>，并对第二电容C2进行充电，第三晶体管M3和第四晶体管M4预开启。第二控制端OE输出的第二控制信号为高电平信号，从而，第一晶体管M1导通，第一电源端VDD提供的高电位通过第五晶体管M5和第一晶体管M1写入保持节点H<4>，并通过第一电容C1保持。此时，第三控制端CLKA的输出的第三控制信号为低电平信号，第二晶体管M2关断。时钟信号CLKE_4为低电平，使得第四级移位寄存器的第一时钟端CLKE输出的第一时钟信号为低电位信号，从而第四级移位寄存器的级联输出端CR<4>输出低电位，时钟信号CLKD_4为低电平，使得第四级移位寄存器的第二时钟端CLKD输出的第二时钟信号为低电位信号，从而第四级移位寄存器的的第一输出端OUT<4>的输出低电位。
在显示模式的第二阶段T2，时钟信号CLKE_4为高电平，使得第四级移位寄存器的第一时钟端CLKE输出到的第一时钟信号为高电位信号；时钟信号CLKD_4为高电平，使得第四级移位寄存器的第二时钟端CLKD输出的第二时钟信号为高电位信号，此时，第四级移位寄存器的上拉节点Q<4>的电位通过第二电容C2的作用自举，第三晶体管M3和第四晶体管M4完全开启，从而，第四级移位寄存器的级联输出端CR<4>输出高电位，第四级移位寄存器的第一输出端OUT<4>的输出高电位。此时，第三控制端CLKA的输出的第三控制信号依然为低电平信号，第二晶体管M2依然保持关断，第二控制端OE输出的第二控制信号变为低电平信号，第一晶体管M1关断，复位控制端TRST的输出信号为低电平信号，第十二晶体管M12关断。
在显示模式的第三阶段T3，时钟信号CLKE_4变为低电平，使得第四移位寄存器的第一时钟端CLKE输出的第一时钟信号变为低电位信号；时钟信号CLKD_4变为低电平，使得第四移位寄存器的第二时钟端CLKD输出的第二时钟信号变为低电位信号，从而第四移位寄存器的级联输出端CR<4>输出低电位，第四移位寄存器的第一输出端OUT<4>输出低电位。完成对第四移位寄存器的级联输出端CR<4>和第一输出端OUT<4>的复位。
在显示模式的第四阶段T4，第七移位寄存器的级联输出端CR<7>输出高电位，从 而使第四级移位寄存器的放电控制端G2输出的放电控制信号为高电平信号。在第四级移位寄存器中，放电控制端G2的高电平信号使第六晶体管M6导通，上拉节点Q<4>被第二电源端VGL1放电，上拉节点Q<4>的电位被拉低，上拉节点Q<4>复位完成。
需要说明的是，在显示模式，第四级移位寄存器的保持节点H<4>一直保持在高电位直至Blank(空白显示)时段。其中，需要说明的是，感测模式在Blank时段进行。
在感测模式的第一阶段T11，第四级移位寄存器的第三控制端CLKA的输出的第三控制信号为高电平信号，第二晶体管M2导通。另外，需要说明的是，由于在第一帧的显示模式，第二级移位寄存器的级联输出端CR<2>和第二控制信号OE同时为高电平信号期间第四级移位寄存器的保持节点H<4>存储了高电平，所以此时第四级移位寄存器中保持节点H<4>存储的高电位通过第二晶体管M2写入上拉节点Q<4>，并通过第二电容C2保持。
在感测模式的第二阶段T22，在第四级移位寄存器中，第三控制端CLKA的输出的第三控制信号为低电平信号，第二晶体管M2关断，第一时钟端CLKE输出的第一时钟信号为低电位信号，此时，上拉节点Q<4>的电位保持在高电位，第四晶体管M4导通，从而第一输出端OUT<4>输出低电位。
在感测模式的第三阶段T33，在第四级移位寄存器中，第一时钟端CLKE输出的第一时钟信号变为高电位信号，从而第一输出端OUT<4>变为输出高电位，第二电容C2的自举作用使得上拉节点Q<4>的电位进一步升高。
在感测模式的第四阶段T44，在第四级移位寄存器中，第一时钟端CLKE输出的第一时钟信号变为低电位信号，从而第一输出端OUT<4>变为输出低电位。
在感测模式的第五阶段T55，在第四级移位寄存器中，复位控制端TRST的输出信号为高电平信号，第十二晶体管M12导通，上拉节点Q<4>下拉至第二电源端VGL1的电位即低电位，第二控制端OE输出的第二控制信号为高电平信号，从而，第一晶体管M1导通，上拉节点Q<4>的低电位通过第一晶体管M1写入保持节点H<4>，以对保持节点H<4>进行复位。
由此，可实现输出用于显示和补偿的混合脉冲，并可实现在任意帧的显示模式对任意行像素进行补偿。
具体而言，在感测模式的第五阶段，第二控制端OE输出的第二控制信号和复位控制端TRST的输出信号均为高电平信号，从而第一晶体管M1和第十二晶体管M12导通， 以对所有行的保持节点H和上拉节点Q进行复位，接着，在显示模式时，可实现对任意像素行进行补偿。
综上，根据本发明实施例提出的移位寄存器，显示控制电路分别与上拉节点、第一电源端和第一控制端相连，显示控制电路用于在显示模式，在第一控制端的控制下将第一电源端提供的电位写入上拉节点，感测控制电路分别与上拉节点、第二控制端和第三控制端相连，感测控制电路用于在显示控制电路将第一电源端提供的电位写入上拉节点时，根据第二控制端的第二控制信号控制保持节点的电位，以及在感测模式，在第三控制端的控制下，将保持节点存储的电位写入上拉节点，第一输出电路与所述上拉节点、第一时钟端和第一输出端相连，第一输出电路用于在显示模式或感测模式，根据上拉节点的电位和第一时钟端的第一时钟信号控制第一输出端输出栅极驱动信号或感测驱动信号。由此，本发明实施例的移位寄存器可实现输出用于显示和补偿的混合脉冲，并可实现在任意帧的显示模式对任意行像素进行补偿，且该电路结构简单。
基于上述实施例的栅极驱动电路，本发明实施例还提出一种显示面板。
图6为根据本发明实施例的显示面板的示意图。如图6所示，显示面板600包括栅极驱动电路601，其中栅极驱动电路601可以由前述任意实施例的栅极驱动电路来实现。在一些实施例中，显示面板600可以包括多级的栅极驱动电路601。
根据本发明实施例提出的显示面板，通过设置的栅极驱动电路，可实现输出用于显示和补偿的混合脉冲，并可实现在任意帧的显示模式对任意行像素进行补偿，且该电路结构简单。
基于上述实施例的移位寄存器，本发明实施例还提出一种移位寄存器的驱动方法。
图7为根据本发明实施例的移位寄存器的驱动方法的流程示意图。如图7所示，本发明实施例的移位寄存器的驱动方法包括以下步骤：
S1，在显示模式，显示控制电路在第一控制端的控制下将第一电源端提供的电位写入上拉节点，感测控制电路在第二控制端的的控制下存储所述上拉节点的电位，第一输出电路在上拉节点的电位的控制下将第一时钟端的第一时钟信号提供至第一输出端输出以用作栅极驱动信号。
S2，在感测模式，感测控制电路在第三控制端的控制下，将所存储的电位写入上拉节点，第一输出电路在上拉节点的电位的控制下将第一时钟端的第一时钟信号提供至第一输出端以用作感测驱动信号。
需要说明的是，前述对移位寄存器实施例的解释说明也适用于本发明实施例的移位寄存器的驱动方法，此处不再赘述。
综上，根据本发明实施例提出的移位寄存器的驱动方法，在显示模式，显示控制电路在第一控制端的控制下将第一电源端提供的电位写入上拉节点，同时，感测控制电路根据第二控制端的第二控制信号控制保持节点的电位，第一输出电路根据上拉节点的电位和第一时钟端的第一时钟信号控制第一输出端输出栅极驱动信号，在感测模式，感测控制电路在第三控制端的控制下，将保持节点存储的电位写入上拉节点，第一输出电路根据上拉节点的电位和第一时钟端的第一时钟信号控制第一输出端输出感测驱动信号。由此，本发明实施例的移位寄存器的驱动方法，可实现输出用于显示和补偿的混合脉冲，并可实现在任意帧的显示模式对任意行像素进行补偿，且该电路结构简单。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现定制逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本发明的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本发明的实施例所属技术领域的技术人员所理解。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从 指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，″计算机可读介质″可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(电子装置)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本发明的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。如，如果用硬件来实现和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (18)

  1. 一种移位寄存器，包括：
    显示控制电路，所述显示控制电路分别与上拉节点、第一电源端和第一控制端相连，所述显示控制电路被配置为在显示模式，在所述第一控制端的控制下将所述第一电源端提供的电位写入所述上拉节点；
    感测控制电路，所述感测控制电路分别与上拉节点、第二控制端和第三控制端相连，所述感测控制电路被配置为在显示模式，在所述第二控制端的控制下存储所述上拉节点的电位，以及在感测模式，在所述第三控制端的控制下，将所存储的电位写入所述上拉节点；
    第一输出电路，所述第一输出电路与所述上拉节点、第一时钟端和第一输出端相连，所述第一输出电路被配置为在所述上拉节点的电位的控制下将所述第一时钟端的第一时钟信号提供至所述第一输出端。
  2. 根据权利要求1所述的移位寄存器，其中，所述感测控制电路包括：
    感测输入子电路，所述感测输入子电路分别与所述上拉节点、保持节点和所述第二控制端相连，所述感测输入子电路被配置为在所述第二控制端的控制下将所述上拉节点的电位存储在所述保持节点；
    感测上拉子电路，所述感测上拉子电路分别与所述上拉节点、所述保持节点和所述第三控制端相连，所述感测上拉子电路被配置为在所述感测模式，在所述第三控制端的控制下将所述保持节点存储的电位写入所述上拉节点。
  3. 根据权利要求2所述的移位寄存器，其中，所述感测输入子电路包括：
    第一晶体管，所述第一晶体管的第一极与所述上拉节点相连，所述第一晶体管的第二极与所述保持节点相连，所述第一晶体管的控制极与所述第二控制端相连；
    第一电容，所述第一电容的一端与所述保持节点相连，所述第一电容的另一端与第二电源端相连。
  4. 根据权利要求2所述的移位寄存器，其中，所述感测上拉子电路包括：
    第二晶体管，所述第二晶体管的第一极与所述保持节点相连，所述第二晶体管 的第二极与所述上拉节点相连，所述第二晶体管的控制极与所述第三控制端相连。
  5. 根据权利要求1所述的移位寄存器，其中，所述第一输出电路包括：
    第三晶体管，所述第三晶体管的第一极与所述第一时钟端相连，所述第三晶体管的第二极与所述第一输出端相连，所述第三晶体管的控制极与所述上拉节点相连；
    第二电容，所述第二电容的一端与所述第三晶体管的控制极相连，所述第二电容的另一端与所述第三晶体管的第二极相连。
  6. 根据权利要求1所述的移位寄存器，其中，还包括：
    级联输出电路，所述级联输出电路与第二时钟端、所述上拉节点和级联输出端相连，所述级联输出电路被配置为在所述上拉节点的电位的控制下将所述第二时钟端的第二时钟信号提供至所述级联输出端。
  7. 根据权利要求6所述的移位寄存器，其中，所述级联输出电路包括：
    第四晶体管，所述第四晶体管的第一极与所述第二时钟端相连，所述第四晶体管的第二极与所述级联输出端相连，所述第四晶体管的控制极与所述上拉节点相连。
  8. 根据权利要求6所述的移位寄存器，其中，所述显示控制电路包括：
    输入子电路，所述输入子电路分别与所述上拉节点、所述第一电源端和所述第一控制端相连，所述输入子电路被配置为在显示模式，在所述第一控制端的控制下将所述第一电源端提供的电位写入所述上拉节点；
    放电子电路，所述放电子电路分别与所述上拉节点、第二电源端和放电控制端相连，所述放电子电路被配置为根据所述放电控制端的放电控制信号将所述上拉节点放电至所述第二电源端的电位；
    下拉控制子电路，所述下拉控制子电路分别与所述上拉节点、下拉节点、所述第一电源端和所述第二电源端相连，所述下拉控制子电路被配置为在所述上拉节点的控制下，使用所述第一电源端的电位和所述第二电源端的电位来控制所述下拉节点的电位；
    第一下拉子电路，所述第一下拉子电路分别与所述下拉节点、所述上拉节点、所述级联输出端和第二电源端相连，所述第一下拉子电路被配置为在所述下拉节点的控制下，将所述上拉节点和所述级联输出端下拉至所述第二电源端的电位；
    第二下拉子电路，所述第二下拉子电路分别与所述下拉节点、所述第一输出端和第三电源端相连，所述第二下拉子电路被配置为在所述下拉节点的控制下，将所述第一输出端下拉至所述第三电源端的电位；
    复位子电路，所述复位子电路分别与所述复位控制端、所述上拉节点和所述第二电源端相连，所述复位子电路被配置为在所述复位控制端的控制下，将所述上拉节点复位至所述第二电源端的电位。
  9. 根据权利要求8所述的移位寄存器，其中，所述输入子电路包括：第五晶体管，所述第五晶体管的第一极与所述第一电源端相连，所述第五晶体管的第二极与所述上拉节点相连，所述第五晶体管的控制极与所述第一控制端相连。
  10. 根据权利要求8所述的移位寄存器，其中，所述放电子电路包括：第六晶体管，所述第六晶体管的第一极与所述上拉节点相连，所述第六晶体管的第二极与所述第二电源端相连，所述第六晶体管的控制极与所述放电控制端相连。
  11. 根据权利要求8所述的移位寄存器，其中，所述下拉控制子电路包括：第七晶体管和第八晶体管，所述第七晶体管的控制极和第一极均与第一电源端相连，所述第七晶体管的第二极和所述第八晶体管的第一极与所述下拉节点相连，所述第八晶体管的控制极与所述上拉节点相连，所述第八晶体管的第二极与所述第二电源端相连。
  12. 根据权利要求8所述的移位寄存器，其中，所述第一下拉子电路包括：第九晶体管和第十晶体管，所述第九晶体管的第一极与所述上拉节点相连，所述第九晶体管的第二极与所述第二电源端相连，所述第九晶体管的控制极与所述下拉节点相连，所述第十晶体管的第一极与所述级联输出端相连，所述第十晶体管的第二极与所述第二电源端相连，所述第十晶体管的控制极与所述下拉节点相连。
  13. 根据权利要求8所述的移位寄存器，其中，所述第二下拉子电路包括：第十一晶体管，所述第十一晶体管的第一极与所述第一输出端相连，所述第十一晶体管的第二极与所述第三电源端相连，所述第十一晶体管的控制极与所述下拉节点相连。
  14. 根据权利要求8所述的移位寄存器，其中，所述复位子电路包括：第十二 晶体管，所述第十二晶体管M的第一极与所述上拉节点相连，所述第十二晶体管的第二极与所述第二电源端相连，所述第十二晶体管的控制极与所述复位控制端相连。
  15. 一种栅极驱动电路，包括N级级联的如权利要求1-14中任一项所述的移位寄存器，其中N为大于1的整数。
  16. 根据权利要求15所述的栅极驱动电路，其中，第n级移位寄存器的第一控制端连接第n-2级移位寄存器的级联输出端，所述第n级移位寄存器的放电控制端连接第n+3级移位寄存器的级联输出端，其中n为整数，3≤n≤N-3。
  17. 一种显示面板，包括如权利要求15或16所述栅极驱动电路。
  18. 一种如权利要求1-14中任一项所述的移位寄存器的驱动方法，包括：
    在显示模式，显示控制电路在第一控制端的控制下将第一电源端提供的电位写入上拉节点，感测控制电路在第二控制端的控制下存储所述上拉节点的电位，第一输出电路在所述上拉节点的电位的控制下将第一时钟端的第一时钟信号提供至第一输出端；
    在感测模式，所述感测控制电路在第三控制端的控制下，将所存储的电位写入所述上拉节点，所述第一输出电路在所述上拉节点的电位的控制下将所述第一时钟端的第一时钟信号提供至所述第一输出端。
PCT/CN2020/111042 2019-08-30 2020-08-25 移位寄存器及其驱动方法、栅极驱动电路、显示面板 WO2021037021A1 (zh)

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