WO2021031266A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

Info

Publication number
WO2021031266A1
WO2021031266A1 PCT/CN2019/106258 CN2019106258W WO2021031266A1 WO 2021031266 A1 WO2021031266 A1 WO 2021031266A1 CN 2019106258 W CN2019106258 W CN 2019106258W WO 2021031266 A1 WO2021031266 A1 WO 2021031266A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
driving circuit
pixel driving
substrate
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/106258
Other languages
English (en)
French (fr)
Inventor
胡凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/623,449 priority Critical patent/US20210327912A1/en
Publication of WO2021031266A1 publication Critical patent/WO2021031266A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the invention relates to the field of displays, in particular to a display panel and a preparation method thereof.
  • Flexible bendable AMOLED screens are favored by many manufacturers due to their large color gamut, strong contrast, wide viewing angle, high resolution, thinness and flexibility.
  • the flexible AMOLED display mainly includes the following parts: flexible substrate, thin film transistor (TFT), OLED and encapsulation layer. Due to the brittleness of the inorganic layer, the TFT device of the AMOLED display screen is prone to TFT failure when it is bent, which may cause the screen to be abnormal or unable to light up.
  • TFT thin film transistor
  • the sub-pixels of the traditional AMOLED display area are closely arranged in a plane.
  • the advantage of this arrangement is that the sub-pixels (sub-pixels) are arranged closely.
  • pixel) can be closely arranged to achieve higher pixel density (PPI) and full high definition (FHD).
  • PPI pixel density
  • FHD full high definition
  • TFT thin-film transistor
  • the purpose of the present invention is to solve the technical problem that the thin film transistors of the prior art display panel are easily damaged during the bending process.
  • the present invention provides a display panel, including: a substrate including a substrate body; and a groove recessed on a surface of one side of the substrate body; and a first pixel driving circuit, a part of which is provided in the Inside the groove.
  • the second pixel driving circuit is provided on the surface of one side of the substrate body.
  • first pixel driving circuit and the second pixel driving circuit are arranged on the same side of the substrate body.
  • the first pixel driving circuit or the second pixel driving circuit includes: a barrier layer attached to the bottom and inner sidewalls of the groove, or attached to the surface of the substrate body; and a buffer layer , Provided on the surface of the barrier layer on the side away from the substrate; the active layer, provided on the surface of the buffer layer on the side away from the barrier layer; the first gate insulating layer, provided on the active layer And the surface of the buffer layer on the side away from the barrier layer; the first gate layer is provided on the surface of the first gate insulating layer on the side away from the buffer layer and opposite to the active layer
  • the second gate insulating layer is provided on the surface of the first gate layer and the first gate insulating layer away from the buffer layer; the second gate layer is provided on the second gate The insulating layer is away from the surface on one side of the first gate insulating layer and is disposed opposite to the first gate layer; the first dielectric layer is disposed on the second gate layer and the second gate An insulating layer is located on a surface away from the first
  • the first pixel driving circuit or the second pixel driving circuit further includes: a source and drain layer, which is provided on the surface of the second dielectric layer on a side away from the first dielectric layer and penetrates Connected to the active layer through the second dielectric layer, the first dielectric layer, the second gate insulating layer and the first gate insulating layer.
  • the display panel further includes: a flat layer provided on the surface of the first pixel driving circuit or the second pixel driving circuit away from the substrate; an anode layer provided on the flat layer away from the substrate
  • the surface on one side of the first pixel drive circuit or the second pixel drive circuit passes through the flat layer and is connected to the source and drain layer; the pixel definition layer is provided on the anode layer and the flat layer Layer away from the first pixel drive circuit or the surface on the side of the second pixel drive circuit; a through hole that penetrates the pixel definition layer and is disposed opposite to the anode layer; and a spacer is disposed on the surface
  • the pixel definition layer is away from the surface of the flat layer.
  • the through hole includes: a first through hole arranged opposite to the first pixel drive circuit; a second through hole arranged opposite to the second pixel drive circuit; the first through hole is opposite to the The second through holes are arranged at intervals.
  • the present invention also provides a method for manufacturing a display panel, including the following steps: a substrate providing step, providing a substrate, including a substrate body; a substrate etching step, etching the substrate body to form a substrate A groove, the groove being recessed on the surface of one side of the substrate body; and the pixel driving circuit preparation step, a pixel driving circuit is prepared in the groove, and a part of the pixel driving circuit is arranged inside the groove.
  • the substrate etching step includes: a photoresist coating step, coating a layer of photoresist on the upper surface of the substrate body; and an exposure step, performing exposure treatment on the upper surface of the photoresist to form A groove; and a photoresist removal step, removing the photoresist.
  • the pixel driving circuit preparation step includes: a barrier layer preparation step, a barrier layer is prepared on the bottom and inner sidewalls of the groove and the upper surface of the substrate body; a buffer layer preparation step, in the barrier layer A buffer layer is prepared on the upper surface of the layer; and the active layer preparation step is to prepare an active layer on the upper surface of the buffer layer in the groove and the buffer layer on the substrate body.
  • the technical effect of the present invention is that a groove is etched on the upper surface of the flexible substrate, and the thickness of the flexible substrate at the groove is small.
  • the stress generated by the substrate at the groove is relatively high.
  • the pixel driving circuit (TFT) is placed in the groove, the stress on the TFT is also relatively small. Therefore, during the bending process of the flexible display panel, the pixel driving circuit is not susceptible to damage due to stress, thereby effectively extending the service life of the display panel.
  • FIG. 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the structure of a substrate according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a substrate etching step according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of the manufacturing steps of the thin film transistor according to the embodiment of the present invention.
  • Substrate body 12. Groove;
  • a first pixel drive circuit 220.
  • a second pixel drive circuit 220.
  • the component can be directly placed on the other component; there may also be an intermediate component on which the component is placed , And the intermediate component is placed on another component.
  • a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is “installed to” or “connected to” through an intermediate component Another component.
  • this embodiment provides a display panel, which includes a substrate 1, a pixel drive circuit 2, a flat layer 3, an anode layer 4, a pixel definition layer 5, and spacers 6.
  • Substrate 1 is a flexible base made of polyimide (PI).
  • Substrate 1 is a yellow transparent film with a relative density of 1.39 to 1.45.
  • the polyimide film has excellent high and low temperature resistance, electrical insulation, and adhesion. It can be used for a long time in the temperature range of -269°C ⁇ 280°C, and can reach a high temperature of 400°C in a short time.
  • the substrate 1 includes a substrate body 11, and a groove 12 is opened downward on the upper surface of the substrate body 11.
  • a groove 12 is added to the existing flexible base, and the thickness of the flexible substrate at the groove 12 is small. When the substrate 1 is bent, the stress generated by the substrate at the groove 12 is small.
  • the groove 12 is arranged in the display area of the display panel, and several grooves 12 can be arranged.
  • the pixel driving circuit 2 is divided into a first pixel driving circuit 210 and a second pixel driving circuit 220.
  • the first pixel driving circuit 210 is arranged in the groove 12 Inside, the second pixel driving circuit is arranged outside the groove 12, that is, on the upper surface of the substrate 1.
  • the first pixel driving circuit 210 and the second pixel driving circuit 220 are spaced apart.
  • the pixel driving circuit 2 can be a single pixel driving circuit or a plurality of pixel driving circuits alternately arranged inside and outside the groove 12.
  • the several grooves 12 are arranged in sequence in the horizontal direction, and may also be arranged in sequence in the vertical direction, so that the subsequent display panel can be bent either horizontally or vertically.
  • the pixel driving circuit 2 includes a barrier layer 21, a buffer layer 22, an active layer 23, a first gate insulating layer 24, a first gate layer 25, a second gate insulating layer 26, a second gate layer 27, and a first gate insulating layer.
  • the barrier layer 21 is attached to the bottom and inner sidewalls of the groove 12 and the upper surface of the substrate body 11, and the barrier layer 21 plays a role of blocking external water and oxygen.
  • the buffer layer 22 is attached to the upper surface of the barrier layer 21 and functions as a buffer to protect the pixel driving circuit 2.
  • the active layer 23 is attached to the upper surface of the buffer layer 22, and the material of the active layer 23 is silicon, which has semiconductor properties.
  • the active layer 23 includes a first active layer and a second active layer. The first active layer is attached to the upper surface of the buffer layer in the groove 12, and the second active layer is attached to the substrate body 11 The upper surface of the buffer layer.
  • the first gate insulating layer (Gate Insulator, GI) 24 is attached to the upper surface of the buffer layer 22 and the active layer 23.
  • the material of the first gate insulating layer 24 is usually silicon nitride (SiNx) or silicon oxide. SiOx, the first gate insulating layer 24 plays an insulating role to prevent short circuits in the pixel driving circuit 2.
  • the first gate layer 25 is attached to the upper surface of the first gate insulating layer 24, is disposed above the active layer 23, and is disposed opposite to the active layer 23.
  • the material of the first gate layer 25 is metal.
  • the second gate insulating layer (Gate Insulator, GI) 26 is attached to the upper surfaces of the first gate insulating layer 24 and the first gate layer 25.
  • the material of the second gate insulating layer 26 is usually silicon nitride ( SiNx) or silicon oxide (SiOx), the second gate insulating layer 26 plays an insulating role to prevent a short circuit in the pixel driving circuit 2.
  • the second gate layer 27 is attached to the upper surface of the second gate insulating layer 26, is arranged above the first gate layer 25, and is opposite to the first gate layer 25.
  • the material of the second gate layer 27 is metal.
  • the first dielectric layer (Inter Layer Dielectric, ILD) 28 is provided on the upper surfaces of the second gate layer 27 and the second gate insulating layer 26.
  • the material of the first dielectric layer 28 is inorganic material, generally oxynitride Silicon (SiON), silica glass doped with boron and phosphorus (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), etc.
  • the second dielectric layer 29 is provided on the upper surface of the first dielectric layer 28.
  • the material of the second dielectric layer 29 is an inorganic material, generally silicon oxynitride (SiON), silicon glass doped with boron and phosphorus (BPSG ), Plasma Enhanced Ethyl Orthosilicate (PETEOS), etc.
  • the second dielectric layer 29 is a dielectric layer that has been planarized, which facilitates the attachment of subsequent film layers.
  • the second dielectric layer 29 is used for isolating the second gate layer 27 and subsequent film layers, preventing short circuits in the pixel driving circuit 2 and protecting the circuit structure.
  • the source-drain layer 20 is disposed on the upper surface of the second dielectric layer 29 and is disposed opposite to the active layer 23.
  • the source-drain layer 20 passes through the second dielectric layer 29 and the first dielectric layer 28 from top to bottom.
  • the second gate insulating layer 26 and the first gate insulating layer 24 are connected to the upper surface of the active layer 23 to realize the circuit connection between the source drain layer 20 and the active layer 23.
  • a planarization layer (PLN) 3 is provided on the upper surfaces of the second dielectric layer 29 and the source and drain layers 20, and the planarization layer 3 is used to level the in-plane steps on the substrate 1 caused by various layer patterns.
  • the planarization layer 3 can reduce the area of the black matrix, increase the aperture ratio of the panel, increase the light transmittance, and reduce the power consumption of the product.
  • the anode layer (Anode Layer) 4 is provided on the upper surface of the flat layer 3 and is connected to the source and drain layer 20 through the flat layer 3 to realize the circuit connection between the anode layer 4 and the pixel driving circuit 2.
  • the Pixel Define Layer (PDL) 5 is provided on the upper surfaces of the anode layer 4 and the flat layer 3, and functions as an insulation to define the size of the light-emitting layer.
  • the pixel defining layer 5 is provided with a through hole 51, the through hole 51 is arranged opposite to the anode layer 4, and a light-emitting layer can be provided in the through hole 51, and the light-emitting layer is connected to the anode layer 4 to obtain electrical signals to make it a light-emitting pixel.
  • the area covered by the pixel definition layer 5 does not emit light.
  • the through hole 51 includes a first through hole 511 and a second through hole 512.
  • the first through hole 511 is disposed opposite to the first pixel driving circuit 210
  • the second through hole 512 is disposed opposite to the second pixel driving circuit 220.
  • 511 and the second through hole 512 are arranged at intervals, so that the light emitting layer in the first through hole 511 and the light emitting layer in the second through hole 512 are arranged at intervals, and the concave and convex directions between adjacent sub-pixels are opposite, that is, the red light emitting layer (R ), the green light-emitting layer (G) and the blue light-emitting layer (B) form a "concave-convex" or "concave-convex” shape.
  • Spacers (Spacer, SP) 6 are provided on the upper surface of the pixel definition layer 5 to prevent the fine metal mask (Fine Metal Mask, referred to as FMM) from directly contacting the pixel definition layer 5 when the OLED material is evaporated, causing the pixel
  • FMM fine metal mask
  • the technical effect of the display panel of this embodiment is that a groove is provided on the upper surface of the flexible substrate, and the thickness of the flexible substrate at the groove is small.
  • the substrate at the groove The stress on the TFT is relatively small, and the pixel driving circuit (TFT) is placed in the groove, and the stress on the TFT is relatively small. Therefore, during the bending process of the flexible display panel, the pixel driving circuit is not susceptible to damage due to stress, thereby effectively extending the service life of the display panel.
  • this embodiment also provides a method for manufacturing the above-mentioned display panel, including the following steps S1 to S3.
  • the substrate providing step is to provide a substrate, the substrate includes a substrate body, and the substrate is a flexible substrate.
  • S2 is a substrate etching step, etching the substrate body to form a groove on the upper surface of the substrate body.
  • the substrate etching step specifically includes steps S21 to S23.
  • a layer of photoresist (Photo Resist, PR) is coated on the upper surface of the substrate body.
  • a mask is set above the photoresist, and the mask is irradiated downward with ultraviolet light (UV) to form a groove.
  • UV ultraviolet light
  • the photoresist removal step is to remove the mask, dissolve the photoresist in a developing solution, and remove the photoresist.
  • a groove is provided on the upper surface of the flexible substrate, and the thickness of the flexible substrate at the groove is small. When the flexible substrate is bent, the stress generated by the substrate at the groove is small.
  • a pixel driving circuit is prepared at the groove and the upper surface of the substrate body, a part of which is arranged in the groove.
  • the pixel driving circuit is arranged in the groove, so the thin film transistor bears less stress and is not easily damaged, which can prolong the service life of the display panel.
  • the steps of preparing the pixel driving circuit include steps S31 to S39.
  • a barrier layer is prepared on the bottom and inner side walls of the groove and the upper surface of the substrate body.
  • a buffer layer is prepared on the upper surface of the barrier layer, which can be prepared by deposition or inkjet printing.
  • S33 is an active layer preparation step, depositing a semiconductor material on the upper surface of the buffer layer, and after patterning, forming a first active layer on the upper surface of the buffer layer in the groove, and on the substrate body
  • the upper surface of the buffer layer forms a second active layer, and the semiconductor material may be silicon.
  • S34 A step of preparing the first gate insulating layer, depositing an inorganic material on the upper surface of the active layer and the buffer layer, the inorganic material including silicon nitride (SiNx) or silicon oxide (SiOx), After the patterning treatment, a first gate insulating layer is formed.
  • S35 The step of preparing the first gate layer, depositing a metal material on the upper surface of the first gate insulating layer, and forming a first gate layer after a patterning treatment.
  • the first gate layer is provided on the Above the source layer, it is arranged opposite to the active layer.
  • the second gate layer preparation step depositing a metal material on the upper surface of the second gate insulating layer, and forming a second gate layer after patterning treatment, the second gate layer being disposed on the Above a gate layer, it is arranged opposite to the first gate layer.
  • the first dielectric layer preparation step depositing an inorganic material on the upper surface of the second gate insulating layer and the second gate layer, the inorganic material includes silicon oxynitride (SiON), doped with boron and phosphorus Silicon glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), etc., are patterned to form the first dielectric layer.
  • SiON silicon oxynitride
  • BPSG boron and phosphorus Silicon glass
  • PETEOS plasma-enhanced tetraethyl orthosilicate
  • the second dielectric layer preparation step depositing an inorganic material on the upper surface of the first dielectric layer, the inorganic material includes silicon oxynitride (SiON), silicon glass doped with boron and phosphorus (BPSG), plasma Reinforce tetraethyl orthosilicate (PETEOS), etc., and form a second dielectric layer after planarization.
  • SiON silicon oxynitride
  • BPSG silicon glass doped with boron and phosphorus
  • PETEOS plasma Reinforce tetraethyl orthosilicate
  • the source-drain layer preparation step is to prepare a source-drain layer on the upper surface of the second dielectric layer, and the source-drain layer sequentially passes through the second dielectric layer and the first dielectric layer , The second gate insulating layer and the first gate insulating layer are connected to the active layer.
  • the technical effect of the method for manufacturing the display panel according to the embodiment of the present invention is that a groove is etched on the substrate by using photoresist, and the thickness of the flexible substrate at the groove is small.
  • the pixel driving circuit is prepared in the groove and the upper surface of the substrate body, and the stress borne by the TFT is relatively small. Therefore, during the bending process of the flexible display panel, the pixel driving circuit is not susceptible to damage due to stress, thereby effectively extending the service life of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板及其制备方法。该显示面板包括：基板（1），包括基板本体（11）及凹槽（12），该凹槽（12）下凹于基板本体（11）一侧的表面；以及像素驱动电路（2），其一部分设于凹槽（12）内部；该显示面板的制备方法包括以下步骤：基板（1）提供步骤、基板（1）刻蚀步骤、以及像素驱动电路（2）制备步骤。

Description

显示面板及其制备方法 技术领域
本发明涉及显示器领域，特别涉及一种显示面板及其制备方法。
 背景技术
人们在使用手机时，无论是办公还是看视频总会遇到屏幕太小，眼睛容易疲劳等问题。柔性折叠屏可以在一定程度上解决这些问题。柔性可弯折AMOLED屏由于其大色域、强对比、广视角、高分辨率、轻薄和柔软等特性而受到很多厂商的青睐。
柔性AMOLED显示屏主要包括以下个部分：柔性基材、薄膜晶体管（TFT），OLED和封装层。AMOLED显示屏的TFT器件由于无机层的脆性，在弯曲的时候容易发生TFT失效从而造成屏幕异常或无法点亮的现象。
传统的AMOLED显示屏在显示区（Active Area）的子像素（sub pixel）是呈平面紧密排布的，这种排布的优点就是子像素（sub pixel）可以紧密排列实现更高像素密度（PPI）和全高清（FHD）。然而，这种平面紧密性排布在弯曲的时候，薄膜晶体管（TFT）器件容易受到大的拉伸或压缩应力，导致薄膜晶体管（TFT）失效，进而造成屏幕无法正常点亮的问题。
 技术问题
本发明的目的在于，解决现有技术的显示面板在弯折过程中薄膜晶体管易损坏的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种显示面板，包括：基板，包括基板本体；及凹槽，下凹于所述基板本体一侧的表面；以及第一像素驱动电路，其一部分设于所述凹槽内部。
进一步地，第二像素驱动电路，设于所述基板本体一侧的表面。
进一步地，所述第一像素驱动电路与所述第二像素驱动电路设于所述基板本体的同一侧。
进一步地，所述第一像素驱动电路或所述第二像素驱动电路包括：阻隔层，贴附于所述凹槽的底部及内侧壁，或者，贴附于所述基板本体的表面；缓冲层，设于所述阻隔层远离所述基板一侧的表面；有源层，设于所述缓冲层远离所述阻隔层一侧的表面；第一栅极绝缘层，设于所述有源层及所述缓冲层远离所述阻隔层一侧的表面；第一栅极层，设于所述第一栅极绝缘层远离所述缓冲层一侧的表面，且与所述有源层相对设置；第二栅极绝缘层，设于所述第一栅极层及所述第一栅极绝缘层远离所述缓冲层一侧的表面；第二栅极层，设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面，且与所述第一栅极层相对设置；第一介电层，设于所述第二栅极层及所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面；以及第二介电层，设于所述第一介电层远离所述第二栅极绝缘层一侧的表面。
进一步地，所述第一像素驱动电路或所述第二像素驱动电路还包括：源漏极层，设于所述第二介电层远离所述第一介电层一侧的表面，且穿过所述第二介电层、所述第一介电层、所述第二栅极绝缘层及所述第一栅极绝缘层，连接至所述有源层。
进一步地，所述显示面板还包括：平坦层，设于所述第一像素驱动电路或所述第二像素驱动电路远离所述基板一侧的表面；阳极层，设于所述平坦层远离所述第一像素驱动电路或所述第二像素驱动电路一侧的表面，且穿过所述平坦层，连接至所述源漏极层；像素定义层，设于所述阳极层及所述平坦层远离所述第一像素驱动电路或所述第二像素驱动电路一侧的表面；通孔，贯穿于所述像素定义层，且与所述阳极层相对设置；以及隔垫物，设于所述像素定义层远离所述平坦层一侧的表面。
进一步地，所述通孔包括：第一通孔，与所述第一像素驱动电路相对设置；第二通孔，与所述第二像素驱动电路相对设置；所述第一通孔与所述第二通孔间隔设置。
为实现上述目的，本发明还提供一种显示面板的制备方法，包括以下步骤：基板提供步骤，提供一基板，包括基板本体；基板刻蚀步骤，对所述基板本体进行刻蚀处理，形成一凹槽，所述凹槽下凹于所述基板本体一侧的表面；以及像素驱动电路制备步骤，在所述凹槽处制备出像素驱动电路，其一部分设于所述凹槽内部。
进一步地，所述基板刻蚀步骤包括：光刻胶涂布步骤，在所述基板本体的上表面涂布一层光刻胶；曝光步骤，在所述光刻胶上表面进行曝光处理，形成一凹槽；以及光刻胶去除步骤，去除所述光刻胶。
进一步地，所述像素驱动电路制备步骤包括：阻隔层制备步骤，在所述凹槽的底部及内侧壁及所述基板本体的上表面制备出一阻隔层；缓冲层制备步骤，在所述阻隔层的上表面制备出一缓冲层；以及有源层制备步骤，在所述凹槽内的缓冲层及所述基板本体上的缓冲层的上表面制备出一有源层。
 有益效果
本发明的技术效果在于，在柔性基板上表面刻蚀出一凹槽，柔性基板在凹槽处的厚度较小，当柔性基板被弯折后，在所述凹槽处的基板产生的应力较小，而像素驱动电路（TFT）被放置于所述凹槽内，所述TFT承受的应力也比较小。因此，在柔性显示面板的弯折过程中，所述像素驱动电路不易受应力影响而被损毁，进而可以有效延长显示面板的使用寿命。
 附图说明
图1为本发明实施例所述显示面板的结构示意图；
图2为本发明实施例所述基板的结构示意图；
图3为本发明实施例所述显示面板的制备方法的流程图；
图4为本发明实施例所述基板刻蚀步骤的流程图；
图5为本发明实施例所述薄膜晶体管制备步骤的流程图。
部分组件标识如下：
1、基板；2、像素驱动电路；3、平坦层；4、阳极层；5、像素定义层；6、隔垫物；
11、基板本体；12、凹槽；
21、阻隔层；22、缓冲层；23、有源层；24、第一栅极绝缘层；25、第一栅极层；26、第二栅极绝缘层；27、第二栅极层；28、第一介电层；29、第二介电层；20、源漏极层；
210、第一像素驱动电路；220、第二像素驱动电路；
51、通孔；511、第一通孔；512、第二通孔。
 本发明的最佳实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
如图1~2所示，本实施例提供一种显示面板，包括基板1、像素驱动电路2、平坦层3、阳极层4、像素定义层5及隔垫物6。
基板1为柔性基底，材质为聚酰亚胺(Polyimide，PI)，基板1呈黄色透明薄膜，相对密度为1.39～1.45，聚酰亚胺薄膜具有优良的耐高低温性、电气绝缘性、粘结性、耐辐射性、耐介质性，能在－269℃～280℃的温度范围内长期使用，短时可达到400℃的高温。基板1包括基板本体11，在基板本体11上表面向下开有凹槽12。
在现有的柔性基底上增加凹槽12，柔性基板在凹槽12处的厚度较小，当基板1被弯折后，在凹槽12处的基板产生的应力较小。
凹槽12设于显示面板的显示区，可设置若干个凹槽12，像素驱动电路2分为第一像素驱动电路210和第二像素驱动电路220，第一像素驱动电路210设于凹槽12内，第二像素驱动电路设于凹槽12外，即设于基板1的上表面。第一像素驱动电路210与第二像素驱动电路220间隔设置。像素驱动电路2可为单个像素驱动电路或是多个像素驱动电路交替设于凹槽12内外。
若干凹槽12在水平方向依次排列，在竖直方向上也可依次排列，使得后续显示面板弯折时既可以水平弯折，也可以竖直弯折。
像素驱动电路2包括阻隔层21、缓冲层22、有源层23、第一栅极绝缘层24、第一栅极层25、第二栅极绝缘层26、第二栅极层27、第一介电层28、第二介电层29及源漏极层20。
阻隔层21贴附于凹槽12的底部及内侧壁以及基板本体11的上表面，阻隔层21起到阻隔外界水氧的作用。
缓冲层22贴附于阻隔层21的上表面，起到缓冲的作用，用以保护像素驱动电路2。
有源层23贴附于缓冲层22的上表面，有源层23的材质为硅，其具有半导体性能。有源层23包括第一有源层以及第二有源层，所述第一有源层贴附于凹槽12内的缓冲层上表面，所述第二有源层贴附于基板本体11上的缓冲层的上表面。
第一栅极绝缘层（Gate Insulator，GI）24贴附于缓冲层22以及有源层23的上表面，第一栅极绝缘层24的材质通常为硅的氮化物（SiNx）或硅的氧化物（SiOx），第一栅极绝缘层24起到绝缘作用，防止像素驱动电路2内发生短路现象。
第一栅极层25贴附于第一栅极绝缘层24的上表面，设于有源层23的上方，与有源层23相对设置，第一栅极层25的材质为金属。
第二栅极绝缘层（Gate Insulator，GI）26贴附于第一栅极绝缘层24及第一栅极层25的上表面，第二栅极绝缘层26的材质通常为硅的氮化物（SiNx）或硅的氧化物（SiOx），第二栅极绝缘层26起到绝缘作用，防止像素驱动电路2内发生短路现象。
第二栅极层27贴附于第二栅极绝缘层26的上表面，设于第一栅极层25的上方，与第一栅极层25相对设置，第二栅极层27的材质为金属。
第一介电层（Inter Layer Dielectric，ILD）28设于第二栅极层27及第二栅极绝缘层26的上表面，第一介电层28的的材质为无机材料，一般为氮氧化硅（SiON），掺有硼、磷的硅玻璃（BPSG），等离子体增强正硅酸乙酯（PETEOS）等。
第二介电层29设于第一介电层28的上表面，第二介电层29的的材质为无机材料，一般为氮氧化硅（SiON），掺有硼、磷的硅玻璃（BPSG），等离子体增强正硅酸乙酯（PETEOS）等。第二介电层29为经过平坦化处理的介电层，便于后续膜层的贴附。第二介电层29用以隔离第二栅极层27与后续膜层，防止像素驱动电路2内发生短路现象，用以保护电路结构。
源漏极层20设于第二介电层29的上表面，与有源层23相对设置，源漏极层20从上往下依次穿过第二介电层29、第一介电层28、第二栅极绝缘层26及第一栅极绝缘层24，连接至有源层23的上表面，实现源漏极层20与有源层23的电路连接。
平坦层（Planarization Layer，PLN）3设于第二介电层29及源漏极层20的上表面，平坦化层3用以平整基板1上因各种不同层图案所造成的面内段差。平坦化层3能够减少黑矩阵（black matrix)的面积、增加面板的开口率、增加光的透过率、降低产品功耗。
阳极层（Anode Layer）4设于平坦层3的上表面，且穿过平坦层3连接至源漏极层20，实现阳极层4与像素驱动电路2的电路连接。
像素定义层（Pixel Define Layer，PDL）5设于阳极层4及平坦层3的上表面，起到绝缘的作用，用以定义发光层的大小。
像素定义层5上设有通孔51，通孔51与阳极层4相对设置，通孔51内可设发光层，所述发光层连接至阳极层4，获得电信号，使其成为发光像素，像素定义层5覆盖的地方不发光。
通孔51包括第一通孔511及第二通孔512，第一通孔511与第一像素驱动电路210相对设置，第二通孔512与第二像素驱动电路220相对设置，第二通孔511与第二通孔512间隔设置，使得第一通孔511内的发光层与第二通孔512内的发光层间隔设置，相邻子像素之间的凹凸方向相反，即红色发光层（R）、绿色发光层（G）及蓝色发光层（B）之间形成“凹凸凹”或是“凸凹凸”的形状。
隔垫物（Spacer，SP）6设于像素定义层5的上表面，用以防止OLED材料蒸镀时，精细金属掩模(Fine Metal Mask，简称FMM)与像素定义层5直接接触，导致像素定义层5刮伤产生缺陷(Defect)。
本实施例所述显示面板的技术效果在于，在柔性基板上表面设一凹槽，柔性基板在凹槽处的厚度较小，当柔性基板被弯折后，在所述凹槽处的基板产生的应力较小，而像素驱动电路（TFT）被放置于所述凹槽内，所述TFT承受的应力也比较小。因此，在柔性显示面板的弯折过程中，所述像素驱动电路不易受应力影响而被损毁，进而可以有效延长显示面板的使用寿命。
如图3所示，本实施例还提供一种上述显示面板的制备方法，包括以下步骤S1~S3。
S1 基板提供步骤，提供一基板，所述基板包括基板本体，所述基板为柔性基板。
S2 基板刻蚀步骤，刻蚀处理所述基板本体，在所述基板本体的上表面形成凹槽。如图4所示，所述基板刻蚀步骤具体包括步骤S21~S23。S21 光刻胶涂布步骤，在所述基板本体的上表面涂布一层光刻胶（Photo Resist，PR）。S22 曝光步骤，在所述光刻胶上方设置一掩膜板，利用紫外光（UV）向下照射所述掩膜板，形成凹槽。S23 光刻胶去除步骤，移除所述掩膜版，将所述光刻胶溶解于显影液中，去除所述光刻胶。在柔性基板的上表面开设凹槽，柔性基板在所述凹槽处的厚度较小，当柔性基板被弯折后，在所述凹槽处的基板产生的应力较小。
S3 像素驱动电路制备步骤，在所述凹槽处及所述基板本体的上表面制备出像素驱动电路，其一部分设于所述凹槽内部。所述像素驱动电路设于所述凹槽内，故所述薄膜晶体管所承受的应力较小，进而不易被损毁，可延长显示面板的使用寿命。
如图5所示，所述像素驱动电路制备步骤包括步骤S31~S39。
S31 阻隔层制备步骤，在所述凹槽的底部及内侧壁以及所述基板本体的上表面制备出阻隔层。
S32 缓冲层制备步骤，在所述阻隔层的上表面制备出一缓冲层，可利用沉积的方式或喷墨打印的方式制备所得。
S33 有源层制备步骤，在所述缓冲层的上表面沉积半导体材料，经过图案化处理后，在所述凹槽内的缓冲层的上表面形成第一有源层，在所述基板本体上的缓冲层的上表面形成第二有源层，所述半导体材料可为硅。
S34 第一栅极绝缘层制备步骤，在所述有源层及所述缓冲层的上表面沉积无机材料，所述无机材料包括硅的氮化物（SiNx）或硅的氧化物（SiOx），经过图案化处理后，形成第一栅极绝缘层。
S35 第一栅极层制备步骤，在所述第一栅极绝缘层的上表面沉积金属材料，经图案化处理后，形成第一栅极层，所述第一栅极层设于所述有源层的上方，与所述有源层相对设置。
S36 第二栅极绝缘层制备步骤，在所述第一栅极绝缘层及所述第一栅极层的上表面沉积无机材料，所述无机材料包括硅的氮化物（SiNx）或硅的氧化物（SiOx），经过图案化处理后，形成第二栅极绝缘层。
S37 第二栅极层制备步骤，在所述第二栅极绝缘层的上表面沉积金属材料，经图案化处理后，形成第二栅极层，所述第二栅极层设于所述第一栅极层的上方，与所述第一栅极层相对设置。
S38 第一介电层制备步骤，在所述第二栅极绝缘层及所述第二栅极层的上表面沉积无机材料，所述无机材料包括氮氧化硅（SiON），掺有硼、磷的硅玻璃（BPSG），等离子体增强正硅酸乙酯（PETEOS）等，经图案化处理后形成第一介电层。
S39 第二介电层制备步骤，在所述第一介电层的上表面沉积无机材料，所述无机材料包括氮氧化硅（SiON），掺有硼、磷的硅玻璃（BPSG），等离子体增强正硅酸乙酯（PETEOS）等，经平坦化处理后形成第二介电层。
S30源漏极层制备步骤，在所述第二介电层的上表面制备出源漏极层，所述源漏极层依次穿过所述第二介电层、所述第一介电层、所述第二栅极绝缘层及所述第一栅极绝缘层，连接至所述有源层。
本发明实施例所述显示面板的制备方法的技术效果在于，利用光刻胶，在基板上刻蚀出一凹槽，柔性基板在凹槽处的厚度较小，当柔性基板被弯折后，在所述凹槽处的基板产生的应力较小，在所述凹槽内及基板本体的上表面制备出像素驱动电路，所述TFT承受的应力也比较小。因此，在柔性显示面板的弯折过程中，所述像素驱动电路不易受应力影响而被损毁，进而可以有效延长显示面板的使用寿命。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种显示面板，其包括：
    基板，包括
    基板本体；及
    凹槽，下凹于所述基板本体一侧的表面；以及
    第一像素驱动电路，设于所述凹槽内部。
  2. 如权利要求1所述的显示面板，其中，
    第二像素驱动电路，设于所述基板本体一侧的表面。
  3. 如权利要求2所述的显示面板，其中，
    所述第一像素驱动电路与所述第二像素驱动电路设于所述基板本体的同一侧。
  4. 如权利要求2所述的显示面板，其中，
    所述第一像素驱动电路或所述第二像素驱动电路包括：
    阻隔层，贴附于所述凹槽的底部及内侧壁，或者，贴附于所述基板本体的表面；
    缓冲层，设于所述阻隔层远离所述基板一侧的表面；
    有源层，设于所述缓冲层远离所述阻隔层一侧的表面；
    第一栅极绝缘层，设于所述有源层及所述缓冲层远离所述阻隔层一侧的表面；
    第一栅极层，设于所述第一栅极绝缘层远离所述缓冲层一侧的表面，且与所述有源层相对设置；
    第二栅极绝缘层，设于所述第一栅极层及所述第一栅极绝缘层远离所述缓冲层一侧的表面；
    第二栅极层，设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面，且与所述第一栅极层相对设置；
    第一介电层，设于所述第二栅极层及所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面；以及
    第二介电层，设于所述第一介电层远离所述第二栅极绝缘层一侧的表面。
  5. 如权利要求4所述的显示面板，其中，
    所述第一像素驱动电路或所述第二像素驱动电路还包括：
    源漏极层，设于所述第二介电层远离所述第一介电层一侧的表面，且穿过所述第二介电层、所述第一介电层、所述第二栅极绝缘层及所述第一栅极绝缘层，连接至所述有源层。
  6. 如权利要求5所述的显示面板，其还包括
    平坦层，设于所述第一像素驱动电路或所述第二像素驱动电路远离所述基板一侧的表面；
    阳极层，设于所述平坦层远离所述第一像素驱动电路或所述第二像素驱动电路一侧的表面，且穿过所述平坦层，连接至所述源漏极层；
    像素定义层，设于所述阳极层及所述平坦层远离所述第一像素驱动电路或所述第二像素驱动电路一侧的表面；
    通孔，贯穿于所述像素定义层，且与所述阳极层相对设置；以及
    隔垫物，设于所述像素定义层远离所述平坦层一侧的表面。
  7. 如权利要求6所述的显示面板，其中，
    所述通孔包括：
    第一通孔，与所述第一像素驱动电路相对设置；
    第二通孔，与所述第二像素驱动电路相对设置；
    所述第一通孔与所述第二通孔间隔设置。
  8. 一种显示面板的制备方法，其包括以下步骤：
    基板提供步骤，提供一基板，包括基板本体；
    基板刻蚀步骤，对所述基板本体进行刻蚀处理，形成一凹槽，所述凹槽下凹于所述基板本体一侧的表面；以及
    像素驱动电路制备步骤，在所述凹槽处制备出像素驱动电路，其一部分设于所述凹槽内部。
  9. 如权利要求8所述的显示面板的制备方法，其中，
    所述基板刻蚀步骤包括：
    光刻胶涂布步骤，在所述基板本体的上表面涂布一层光刻胶；
    曝光步骤，在所述光刻胶上表面进行曝光处理，形成一凹槽；以及
    光刻胶去除步骤，去除所述光刻胶。
  10. 如权利要求8所述的显示面板的制备方法，其中，
    所述像素驱动电路制备步骤包括：
    阻隔层制备步骤，在所述凹槽的底部及内侧壁及所述基板本体的上表面制备出一阻隔层；
    缓冲层制备步骤，在所述阻隔层的上表面制备出一缓冲层；以及
    有源层制备步骤，在所述凹槽内的缓冲层及所述基板本体上的缓冲层的上表面制备出一有源层。
PCT/CN2019/106258 2019-08-21 2019-09-17 显示面板及其制备方法 Ceased WO2021031266A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/623,449 US20210327912A1 (en) 2019-08-21 2019-09-17 Display panel and method for fabricating same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910773342.X 2019-08-21
CN201910773342.XA CN110634886A (zh) 2019-08-21 2019-08-21 显示面板及其制备方法

Publications (1)

Publication Number Publication Date
WO2021031266A1 true WO2021031266A1 (zh) 2021-02-25

Family

ID=68970657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/106258 Ceased WO2021031266A1 (zh) 2019-08-21 2019-09-17 显示面板及其制备方法

Country Status (3)

Country Link
US (1) US20210327912A1 (zh)
CN (1) CN110634886A (zh)
WO (1) WO2021031266A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312722A (zh) * 2019-11-13 2020-06-19 武汉华星光电半导体显示技术有限公司 显示面板及其制造方法
KR102811541B1 (ko) * 2020-02-03 2025-05-23 삼성디스플레이 주식회사 표시 장치
CN113451411A (zh) * 2020-03-26 2021-09-28 深圳市柔宇科技有限公司 薄膜晶体管及其制作方法、显示面板及电子设备
CN113745272B (zh) 2020-05-29 2024-08-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111834430B (zh) * 2020-07-09 2022-03-08 昆山国显光电有限公司 显示面板及显示装置
CN119730520A (zh) * 2023-09-25 2025-03-28 群创光电股份有限公司 可卷曲电子装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018860B1 (en) * 2002-05-30 2006-03-28 Au Optronics Corporation Method of preventing cathode of active matrix organic light emitting diode from breaking
CN103779202A (zh) * 2014-01-27 2014-05-07 深圳市华星光电技术有限公司 像素结构及其制作方法和显示面板
CN105489611A (zh) * 2015-11-26 2016-04-13 Tcl集团股份有限公司 一种印刷型发光显示器及其制作方法
CN106356380A (zh) * 2016-11-11 2017-01-25 深圳市华星光电技术有限公司 柔性tft基板及其制作方法
CN106449657A (zh) * 2016-10-27 2017-02-22 上海天马微电子有限公司 Oled显示面板、显示装置、阵列基板及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472507B2 (en) * 2013-06-17 2016-10-18 Samsung Display Co., Ltd. Array substrate and organic light-emitting display including the same
CN104659285A (zh) * 2015-01-20 2015-05-27 深圳市华星光电技术有限公司 适用于amoled的tft背板制作方法及结构
CN105182652A (zh) * 2015-09-25 2015-12-23 京东方科技集团股份有限公司 像素隔离墙、显示基板及其制作方法和显示装置
CN106876412A (zh) * 2017-03-15 2017-06-20 厦门天马微电子有限公司 一种阵列基板以及制作方法
CN108538898A (zh) * 2018-04-28 2018-09-14 武汉华星光电半导体显示技术有限公司 柔性显示面板及其制作方法
CN109037278B (zh) * 2018-07-23 2022-06-17 云谷（固安）科技有限公司 显示面板及显示装置
CN109326633B (zh) * 2018-09-30 2022-01-28 厦门天马微电子有限公司 一种显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018860B1 (en) * 2002-05-30 2006-03-28 Au Optronics Corporation Method of preventing cathode of active matrix organic light emitting diode from breaking
CN103779202A (zh) * 2014-01-27 2014-05-07 深圳市华星光电技术有限公司 像素结构及其制作方法和显示面板
CN105489611A (zh) * 2015-11-26 2016-04-13 Tcl集团股份有限公司 一种印刷型发光显示器及其制作方法
CN106449657A (zh) * 2016-10-27 2017-02-22 上海天马微电子有限公司 Oled显示面板、显示装置、阵列基板及其制作方法
CN106356380A (zh) * 2016-11-11 2017-01-25 深圳市华星光电技术有限公司 柔性tft基板及其制作方法

Also Published As

Publication number Publication date
US20210327912A1 (en) 2021-10-21
CN110634886A (zh) 2019-12-31

Similar Documents

Publication Publication Date Title
WO2021031266A1 (zh) 显示面板及其制备方法
US11476309B2 (en) Display panel and method of manufacturing the same, display device
US9722005B2 (en) Light-emitting device, array substrate, display device and manufacturing method of light-emitting device
US9614018B2 (en) COA WOLED structure and manufacturing method thereof
TWI611613B (zh) 有機發光裝置及該裝置的製造方法
CN104282729B (zh) 一种有机发光显示面板及其制备方法、显示装置
CN103035848B (zh) 有机发光显示装置及其制造方法
CN110112146B (zh) 一种阵列基板、其制备方法及显示面板
WO2014205998A1 (zh) Coa基板及其制造方法、显示装置
KR20150135624A (ko) 낮은 반사율을 갖는 블랙 매트릭스를 구비한 평판 표시장치 및 그 제조 방법
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2018120691A1 (zh) 阵列基板及其制造方法、显示装置
CN109768180A (zh) Oled基板、oled基板的制作方法及柔性显示装置
WO2021012529A1 (zh) 显示面板的制备方法、显示面板及显示装置
WO2020191888A1 (zh) 显示面板、显示模组及制作方法
WO2020211259A1 (zh) 显示背板及其制作方法
WO2020062410A1 (zh) 有机发光二极管显示器及其制作方法
CN109037277B (zh) 一种oled显示面板的制备方法及oled显示面板、显示装置
CN106158739B (zh) 显示器的阵列基板及其制造方法
KR20200012914A (ko) Toc형 oled 디스플레이의 제조방법 및 toc형 oled 디스플레이
WO2020216225A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
CN105629598B (zh) Ffs模式的阵列基板及制作方法
KR102234318B1 (ko) 표시 장치의 제조 방법
CN110416274B (zh) 一种基板及其制备方法和oled显示面板
WO2016119306A1 (zh) Oled像素结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19941872

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19941872

Country of ref document: EP

Kind code of ref document: A1