WO2020211259A1 - 显示背板及其制作方法 - Google Patents

显示背板及其制作方法 Download PDF

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Publication number
WO2020211259A1
WO2020211259A1 PCT/CN2019/103927 CN2019103927W WO2020211259A1 WO 2020211259 A1 WO2020211259 A1 WO 2020211259A1 CN 2019103927 W CN2019103927 W CN 2019103927W WO 2020211259 A1 WO2020211259 A1 WO 2020211259A1
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Prior art keywords
layer
transparent
storage capacitor
metal layer
oxide semiconductor
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PCT/CN2019/103927
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English (en)
French (fr)
Inventor
余明爵
任章淳
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020211259A1 publication Critical patent/WO2020211259A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display backplane and a manufacturing method thereof.
  • the light-shielding metal layer of the display backplane can block part of the incident light, but the internal reflected light still affects the display backplane.
  • the electrode of the storage capacitor is made of metal, the light-emitting area and aperture ratio of the pixel of the display backplane are reduced.
  • the light-shielding metal layer of the display backplane can block part of the incident light, but the internal reflected light still affects the display backplane.
  • the electrode of the storage capacitor is made of metal, the light-emitting area and aperture ratio of the pixel of the display backplane are reduced.
  • an object of the present disclosure is to provide a display backplane and a manufacturing method thereof, which can avoid internal light reflection of the display backplane and increase the aperture ratio.
  • the present disclosure provides a method for manufacturing a display backplane, including providing a substrate, forming a transparent metal layer on the substrate, forming a black matrix photoresist layer on the transparent metal layer, and patterning the black matrix A photoresist layer partially covers the transparent metal layer, a buffer layer is formed on the substrate, the transparent metal layer and the black matrix photoresist layer, and a transparent oxide semiconductor layer is formed on the buffer layer.
  • the area where the transparent metal layer is covered by the black matrix photoresist layer is defined as a driving thin film transistor area, and the area where the transparent metal layer is not covered by the black matrix photoresist layer is defined as a storage capacitor area.
  • the transparent metal layer in the storage capacitor region is the bottom electrode of the storage capacitor, and the transparent oxide semiconductor layer in the storage capacitor region is the storage capacitor The upper electrode.
  • the transparent metal layer, the buffer layer and the transparent oxide semiconductor layer in the storage capacitor region constitute a storage capacitor.
  • the method further includes sequentially forming a gate insulating layer and a first metal layer on the transparent oxide semiconductor layer.
  • the method further includes forming an interlayer dielectric insulating layer on the buffer layer, the transparent oxide semiconductor layer, the gate insulating layer, and the first metal layer And patterning the interlayer dielectric insulating layer to form a plurality of via holes, the via holes penetrating the interlayer dielectric insulating layer.
  • the method further includes forming a source electrode and a drain electrode on the transparent oxide semiconductor layer, and the source electrode and the drain electrode communicate with the transparent oxide through corresponding via holes. The edge contact of the semiconductor layer.
  • the method further includes sequentially forming a protective layer, a flat layer, a transparent electrode layer, and a pixel definition layer on the interlayer dielectric insulating layer, the source electrode, and the drain electrode And patterning the protection layer and the flat layer to form a contact hole, and the transparent electrode layer contacts the source electrode or the drain electrode through the contact hole.
  • the present disclosure also provides a display backplane, including a substrate, a transparent metal layer, a black matrix photoresist layer, a buffer layer, and a transparent oxide semiconductor layer.
  • the transparent metal layer is disposed on the substrate.
  • the black matrix photoresist layer is disposed on the transparent metal layer.
  • the buffer layer is disposed on the substrate, the transparent metal layer and the black matrix photoresist layer.
  • the transparent oxide semiconductor layer is disposed on the buffer layer.
  • the black matrix photoresist layer partially covers the transparent metal layer, and the area where the transparent metal layer is covered by the black matrix photoresist layer is defined as a driving thin film transistor area, and is not covered by the black matrix photoresist layer
  • the area where the transparent metal layer is located is defined as the storage capacitor area.
  • the transparent metal layer in the storage capacitor region is the bottom electrode of the storage capacitor, and the transparent oxide semiconductor layer in the storage capacitor region is the storage capacitor
  • the upper electrode, the transparent metal layer, the buffer layer and the transparent oxide semiconductor layer in the storage capacitor region constitute the storage capacitor.
  • the display backplane further includes a gate insulating layer, a first metal layer, an interlayer dielectric insulating layer, a source electrode, and a leakage current which are sequentially disposed on the transparent oxide semiconductor layer.
  • the edge of the semiconductor layer is in contact with each other, the protective layer and the flat layer include a contact hole, and the transparent electrode layer is in contact with the source electrode or the drain electrode through the contact hole.
  • the present disclosure also provides a display backplane, including a substrate, a transparent metal layer, a black matrix photoresist layer, a buffer layer, and a transparent oxide semiconductor layer.
  • the transparent metal layer is disposed on the substrate.
  • the black matrix photoresist layer is disposed on the transparent metal layer.
  • the buffer layer is disposed on the substrate, the transparent metal layer and the black matrix photoresist layer.
  • the transparent oxide semiconductor layer is disposed on the buffer layer.
  • the black matrix photoresist layer partially covers the transparent metal layer, and the area where the transparent metal layer is covered by the black matrix photoresist layer is defined as a driving thin film transistor area, and is not covered by the black matrix photoresist layer
  • the area where the transparent metal layer is located is defined as the storage capacitor area.
  • the transparent oxide semiconductor layer in the storage capacitor region is the upper electrode of the storage capacitor.
  • the transparent metal layer in the storage capacitor region is the bottom electrode of the storage capacitor.
  • the transparent metal layer, the buffer layer, and the transparent oxide semiconductor layer in the storage capacitor region constitute the storage capacitor.
  • the display backplane further includes a gate insulating layer, a first metal layer, an interlayer dielectric insulating layer, a source electrode, and a leakage current which are sequentially disposed on the transparent oxide semiconductor layer. Electrode, protective layer, flat layer, transparent electrode layer and pixel definition layer.
  • the interlayer dielectric insulating layer includes a plurality of via holes, and the source electrode and the drain electrode are in contact with the edge of the transparent oxide semiconductor layer through corresponding via holes.
  • the protection layer and the flat layer include contact holes, and the transparent electrode layer contacts the source electrode or the drain electrode through the contact holes.
  • the black matrix photoresist layer partially covers the transparent metal layer and is exposed to light by the black matrix.
  • the area where the transparent metal layer is covered by the resist layer is defined as a driving thin film transistor area, and the area where the transparent metal layer is not covered by the black matrix photoresist layer is defined as a storage capacitor area.
  • the black matrix photoresist layer is used as a light-shielding layer, which can prevent the internal light reflection of the display backplane and reduce the parasitic capacitive coupling phenomenon caused by the conventional light-shielding metal layer.
  • Both the upper electrode and the lower electrode of the storage capacitor use transparent materials to increase the pixel light-emitting area and aperture ratio of the display backplane.
  • FIG. 1 shows a flowchart of a manufacturing method of a display backplane according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a display backplane according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a manufacturing method 100 of a display backplane, which includes the following steps.
  • step 1 provide a substrate 110.
  • the substrate 110 is, for example, a glass substrate.
  • the method of providing the glass substrate further includes cleaning and baking the glass substrate.
  • Step 2 A transparent metal layer 120 is formed on the substrate 110.
  • the material of the transparent metal layer 120 includes, for example, indium tin oxide (indium tin oxide). oxide, ITO) or indium zinc oxide (IZO).
  • indium tin oxide indium tin oxide
  • oxide ITO
  • IZO indium zinc oxide
  • Step 3 A black matrix (BM) photoresist layer 130 is formed on the transparent metal layer 120.
  • Step 4 Pattern the black matrix photoresist layer 130 to partially cover the transparent metal layer 120.
  • the area where the transparent metal layer 120 is covered by the black matrix photoresist layer 130 is defined as the driving thin film transistor area 10, and the area where the transparent metal layer 120 is not covered by the black matrix photoresist layer 130 is defined For the storage capacitor area 20.
  • the black matrix photoresist layer 130 is exposed using a black matrix halftone mask (halftone mask) to define the driving thin film transistor area 10 and the The storage capacitor area 20.
  • a black matrix halftone mask halftone mask
  • the black matrix photoresist layer 130 of the driving thin film transistor region 10 is thick, and the black matrix photoresist layer 130 of the storage capacitor region 20 is thin.
  • the driving thin film transistor region 10 has the black matrix photoresist layer 130, and the storage capacitor region 20 does not have the black matrix photoresist layer 130.
  • etching the transparent metal layer 120 and performing an ashing process of the black matrix photoresist layer 130 to form the black matrix photoresist layer 130 and the black matrix photoresist layer 130 in the driving thin film transistor area 105 A transparent metal layer 120, and the transparent metal layer 120 is formed in the storage capacitor region 20.
  • the transparent metal layer 120 in the storage capacitor region 20 is the bottom electrode of the storage capacitor.
  • Step 5 forming a buffer layer 140 on the substrate 110, the transparent metal layer 120 and the black matrix photoresist layer 130.
  • the material of the buffer layer 140 may be silicon dioxide (SiO2) or other materials.
  • Step 6 forming a transparent oxide semiconductor layer 150 on the buffer layer 140.
  • the material of the transparent oxide semiconductor layer 150 may be indium gallium zinc oxide (indium gallium zinc oxide). zinc oxide, IGZO) or indium tin zinc oxide (indium tin zinc oxide) oxide, ITZO).
  • the transparent oxide semiconductor layer 150 defines the active area and the upper electrode of the storage capacitor.
  • the transparent oxide semiconductor layer 150 in the storage capacitor region 20 is the upper electrode of the storage capacitor.
  • the transparent metal layer 120, the buffer layer 140 and the transparent oxide semiconductor layer 150 in the storage capacitor region 20 constitute a storage capacitor.
  • step 7 a gate insulating layer 160 and a first metal layer 170 are sequentially formed on the transparent oxide semiconductor layer 150.
  • the gate insulating layer 160 may be a single-layer SiNx film, a single-layer SiO2 film, or a double-layer film.
  • the material of the double-layer film may include at least one of SiNx and SiO2.
  • the material of the first metal layer 170 may include Mo, Al or Cu, and the first metal layer 170 defines an oxide thin film transistor (thin film transistor). transistor, TFT).
  • the oxide thin film transistor (thin film transistor transistor, TFT) includes driving thin film transistors and switching thin film transistors.
  • the driving thin film transistor is located in the driving thin film transistor region 10.
  • the switching thin film transistor is located in the switching thin film transistor area 30.
  • the driving thin film transistor region 10 is located between the storage capacitor region 20 and the switching thin film transistor region 30.
  • the first metal layer 170 defines the gate of the driving thin film crystal.
  • the first metal layer 170 defines the gate of the switching thin film transistor.
  • Step 8 Form an interlayer dielectric insulating layer 180 on the buffer layer 140, the transparent oxide semiconductor layer 150, the gate insulating layer 160 and the first metal layer 170 and pattern the interlayer
  • the dielectric insulating layer 180 forms a plurality of via holes 182 passing through the interlayer dielectric insulating layer 180.
  • Step 9 A source electrode 192 and a drain electrode 194 are formed on the transparent oxide semiconductor layer 150, and the source electrode 192 and the drain electrode 194 pass through the corresponding via hole 182 and the edge of the transparent oxide semiconductor layer 150. contact.
  • Step 10 On the interlayer dielectric insulating layer 180, the source electrode 192 and the drain electrode 194, a protective layer 210, a flat layer 220, a transparent electrode layer 230, and a pixel definition layer 240 are sequentially formed and patterned.
  • the protection layer 210 and the planarization layer 220 form a contact hole 212, and the transparent electrode layer 230 contacts the source electrode 192 or the drain electrode 194 through the contact hole 212.
  • the interlayer dielectric insulating layer 180 may be a single layer of SiNx or a single layer of SiO2.
  • the material of the source electrode 192 and the drain electrode 194 may include Mo, Al, or Cu.
  • the source electrode 192 and the drain electrode 194 define the source electrode and the drain electrode of the driving thin film crystal.
  • the source electrode 192 and the drain electrode 194 define the source electrode and the drain electrode of the switching thin film transistor.
  • the material of the transparent electrode layer 230 may include ITO.
  • the display backplane may be an organic light emitting diode (OLED) backplane.
  • the display backplane may be a liquid crystal display (LCD) backplane.
  • the display backplane includes a substrate 110, a transparent metal layer 120, a black matrix photoresist layer 130, a buffer layer 140, and a transparent oxide semiconductor layer 150.
  • the transparent metal layer 120 is disposed on the substrate 110.
  • the black matrix photoresist layer 130 is disposed on the transparent metal layer 120.
  • the buffer layer 140 is disposed on the substrate 110, the transparent metal layer 120 and the black matrix photoresist layer 130.
  • the transparent oxide semiconductor layer 150 is disposed on the buffer layer 140.
  • the black matrix photoresist layer 130 partially covers the transparent metal layer 120, and the area where the transparent metal layer 120 is covered by the black matrix photoresist layer 130 is defined as the driving thin film transistor area 10, which is not covered by the black
  • the area where the transparent metal layer 120 covered by the matrix photoresist layer 130 is located is defined as the storage capacitor area 20.
  • the transparent metal layer 120 in the storage capacitor region 20 is the bottom electrode of the storage capacitor, and the transparent oxide semiconductor layer 120 in the storage capacitor region 20 is The upper electrode of the storage capacitor, the transparent metal layer 120, the buffer layer 140 and the transparent oxide semiconductor layer 120 in the storage capacitor region 20 constitute the storage capacitor.
  • the display backplane further includes a gate insulating layer 160, a first metal layer 170, an interlayer dielectric insulating layer 180, and a gate insulating layer 160 sequentially disposed on the transparent oxide semiconductor layer 120.
  • the interlayer dielectric insulating layer 180 includes a plurality of via holes 182, the source electrode 192 and the drain electrode 194 are in contact with the edge of the transparent oxide semiconductor layer 120 through the corresponding via holes 182, and the protection layer 210 and the flat layer 220 include a contact hole 212, and the transparent electrode layer 230 contacts the source electrode 192 or the drain electrode 194 through the contact hole 212.
  • the black matrix photoresist layer partially covers the transparent metal layer, and the area where the transparent metal layer covered by the black matrix photoresist layer is located defines To drive the thin film transistor area, the area where the transparent metal layer is not covered by the black matrix photoresist layer is defined as a storage capacitor area.
  • the black matrix photoresist layer is used as a light-shielding layer, which can prevent the internal light reflection of the display backplane and reduce the parasitic capacitive coupling phenomenon caused by the conventional light-shielding metal layer.
  • Both the upper electrode and the lower electrode of the storage capacitor use transparent materials to increase the pixel light-emitting area and aperture ratio of the display backplane.

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Abstract

显示背板及其制作方法。所述显示背板的制作方法包括提供基板（1）；在所述基板上形成透明金属层（2）；在所述透明金属层上形成黑色矩阵光阻层（3）；图案化所述黑色矩阵光阻层，以部分覆盖所述透明金属层（4）；在所述基板、所述透明金属层和所述黑色矩阵光阻层上形成缓冲层（5）以及在所述缓冲层上形成透明氧化物半导体层（6）。

Description

显示背板及其制作方法 技术领域
本揭示涉及显示技术领域，特别涉及一种显示背板及其制作方法。
 背景技术
目前显示背板的遮光金属层能阻挡部分入射光，但还是有内部反射光线影响到显示背板。另外，因储存电容的电极是金属, 减少了显示背板的像素发光面积及开口率。
故，有需要提供一种显示背板及其制作方法，以解决现有技术存在的问题。
 技术问题
目前显示背板的遮光金属层能阻挡部分入射光，但还是有内部反射光线影响到显示背板。另外，因储存电容的电极是金属, 减少了显示背板的像素发光面积及开口率。
 技术解决方案
为解决上述技术问题，本揭示的一目的在于提供显示背板及其制作方法，其可避免所述显示背板的内部光线反射与提升开口率。
为达成上述目的，本揭示提供一显示背板的制作方法，包括提供基板，在所述基板上形成透明金属层，在所述透明金属层上形成黑色矩阵光阻层，图案化所述黑色矩阵光阻层,以部分覆盖所述透明金属层,在所述基板、所述透明金属层和所述黑色矩阵光阻层上形成缓冲层以及在所述缓冲层上形成透明氧化物半导体层。被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。
于本揭示其中的一实施例中，在所述储存电容区域中的所述透明金属层为储存电容的下电极，在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极。
于本揭示其中的一实施例中，在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成储存电容。
于本揭示其中的一实施例中，所述方法还包括在所述透明氧化物半导体层上依次形成栅极绝缘层和第一金属层。
于本揭示其中的一实施例中，所述方法还包括在所述缓冲层、所述透明氧化物半导体层、所述栅极绝缘层和所述第一金属层上形成层间介电绝缘层以及图案化所述层间介电绝缘层以形成多个过孔，所述过孔贯穿所述层间介电绝缘层。
于本揭示其中的一实施例中，所述方法还包括在所述透明氧化物半导体层上形成源电极和漏电极，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触。
于本揭示其中的一实施例中，所述方法还包括在所述层间介电绝缘层、所述源电极和所述漏电极上依次形成保护层、平坦层、透明电极层和像素定义层以及图案化所述保护层和所述平坦层以形成接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
本揭示还提供一显示背板，包括基板、透明金属层、黑色矩阵光阻层、缓冲层以及透明氧化物半导体层。所述透明金属层设置在所述基板上。所述黑色矩阵光阻层设置在所述透明金属层上。所述缓冲层设置在所述基板、所述透明金属层和所述黑色矩阵光阻层上。所述透明氧化物半导体层设置在所述缓冲层上。所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。
于本揭示其中的一实施例中，在所述储存电容区域中的所述透明金属层为储存电容的下电极，在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极，在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成所述储存电容。
于本揭示其中的一实施例中，所述显示背板还包括依次设置在所述透明氧化物半导体层上的栅极绝缘层、第一金属层、层间介电绝缘层、源电极和漏电极、保护层、平坦层、透明电极层和像素定义层，其中所述层间介电绝缘层包括多个过孔，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触，所述保护层和所述平坦层包括接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
本揭示还提供一显示背板，包括基板、透明金属层、黑色矩阵光阻层、缓冲层以及透明氧化物半导体层。所述透明金属层设置在所述基板上。所述黑色矩阵光阻层设置在所述透明金属层上。所述缓冲层设置在所述基板、所述透明金属层和所述黑色矩阵光阻层上。所述透明氧化物半导体层设置在所述缓冲层上。所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极。
于本揭示其中的一实施例中，在所述储存电容区域中的所述透明金属层为储存电容的下电极。
于本揭示其中的一实施例中，在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成所述储存电容。
于本揭示其中的一实施例中，所述显示背板还包括依次设置在所述透明氧化物半导体层上的栅极绝缘层、第一金属层、层间介电绝缘层、源电极和漏电极、保护层、平坦层、透明电极层和像素定义层。
于本揭示其中的一实施例中，所述层间介电绝缘层包括多个过孔，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触。
于本揭示其中的一实施例中，所述保护层和所述平坦层包括接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
 有益效果
相较于现有技术，为解决上述技术问题，由于本揭示的实施例中的显示背板及其制作方法，所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。所述黑色矩阵光阻层作为遮光层, 可避免所述显示背板的内部光线反射,减少习知因遮光金属层造成的寄生电容耦合现象。储存电容的上电极和下电极都使用透明材料，增加显示背板的像素发光面积及开口率。
 附图说明
图1显示根据本揭示的一实施例的显示背板的制作方法的流程图；以及
图2显示根据本揭示的一实施例的显示背板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1，本揭示的一实施例提供显示背板的制作方法100，包括如下步骤。
参照图1及图2，步骤1、提供基板110。
具体地，所述基板110例如是玻璃基板。提供所述玻璃基板的方法还包括清洗与烘烤所述玻璃基板。
步骤2、在所述基板110上形成透明金属层120。
具体地，所述透明金属层120的材料例如包括氧化铟锡(indium tin oxide, ITO)或氧化铟锌(indium zinc oxide, IZO)。
步骤3、在所述透明金属层120上形成黑色矩阵(black matrix, BM)光阻层130。
步骤4、图案化所述黑色矩阵光阻层130,以部分覆盖所述透明金属层120。被所述黑色矩阵光阻层130覆盖的所述透明金属层120所在的区域定义为驱动薄膜晶体管区域10,没有被所述黑色矩阵光阻层130覆盖的所述透明金属层120所在的区域定义为储存电容区域20。
具体地，涂层整层的所述黑色矩阵光阻层130后, 使用黑色矩阵半色调掩模(halftone mask)曝光所述黑色矩阵光阻层130, 定义出所述驱动薄膜晶体管区域10和所述储存电容区域20。在一实施例中，所述驱动薄膜晶体管区域10的所述黑色矩阵光阻层130较厚, 所述储存电容区域20的所述黑色矩阵光阻层130较薄。在另一实施例中，所述驱动薄膜晶体管区域10具有所述黑色矩阵光阻层130, 所述储存电容区域20没有所述黑色矩阵光阻层130。
具体地，蚀刻所述透明金属层120与进行所述黑色矩阵光阻层130灰化制程(ashing process), 以在所述驱动薄膜晶体管区域105中形成所述黑色矩阵光阻层130和所述透明金属层120, 并在所述储存电容区域20形成所述透明金属层120。
具体地，在所述储存电容区域20中的所述透明金属层120为储存电容的下电极。
步骤5、在所述基板110、所述透明金属层120和所述黑色矩阵光阻层130上形成缓冲层140。
具体地，所述缓冲层140的材料可以是二氧化硅(SiO2)或其他材料。
步骤6、在所述缓冲层140上形成透明氧化物半导体层150。
具体地，所述透明氧化物半导体层150的材料可以是铟镓锌氧化物(indium gallium zinc oxide, IGZO)或氧化铟锡锌(indium tin zinc oxide, ITZO)。所述透明氧化物半导体层150定义出主动区与储存电容的上电极。具体地，在所述储存电容区域20中的所述透明氧化物半导体层150为所述储存电容的上电极。在所述储存电容区域20中的所述透明金属层120、所述缓冲层140和所述透明氧化物半导体层150构成储存电容。
参照图2，步骤7、在所述透明氧化物半导体层150上依次形成栅极绝缘层160和第一金属层170。
具体地，所述栅极绝缘层160可以是单层SiNx膜、单层SiO2膜或是双层膜。所述双层膜的材料可以包括SiNx和SiO2的至少其中之一。
具体地，所述第一金属层170的材料可以包括Mo、Al或Cu，所述第一金属层170定义出氧化物薄膜晶体管(thin film transistor, TFT)的栅极。所述氧化物薄膜晶体管(thin film transistor, TFT)包括驱动薄膜晶体管和开关薄膜晶体管。所述驱动薄膜晶体管位于所述驱动薄膜晶体管区域10。所述开关薄膜晶体管位于开关薄膜晶体管区域30。在一实施例中，所述驱动薄膜晶体管区域10位于所述储存电容区域20和所述开关薄膜晶体管区域30之间。所述第一金属层170定义出所述驱动薄膜晶体的栅极。所述第一金属层170定义出所述开关薄膜晶体管的栅极。
步骤8、在所述缓冲层140、所述透明氧化物半导体层150、所述栅极绝缘层160和所述第一金属层170上形成层间介电绝缘层180以及图案化所述层间介电绝缘层180以形成多个过孔182，所述过孔182贯穿所述层间介电绝缘层180。
步骤9、在所述透明氧化物半导体层150上形成源电极192和漏电极194，所述源电极192和所述漏电极194通过对应的过孔182与所述透明氧化物半导体层150的边缘接触。
步骤10、在所述层间介电绝缘层180、所述源电极192和所述漏电极194上依次形成保护层210、平坦层220、透明电极层230和像素定义层240以及图案化所述保护层210和所述平坦层220以形成接触孔212，所述透明电极层230通过所述接触孔212与所述源电极192或所述漏电极194接触。
具体地，所述层间介电绝缘层180可以是单层SiNx或单层SiO2。所述源电极192和所述漏电极194的材料可以包括Mo、Al或Cu。所述源电极192和所述漏电极194定义出所述驱动薄膜晶体的源电极和漏电极。所述源电极192和所述漏电极194定义出所述开关薄膜晶体管的源电极和漏电极。所述透明电极层230的材料可以包括ITO。
具体地，所述显示背板可以是有机发光二极管(organic light emitting diode, OLED）背板。所述显示背板可以是液晶显示器(liquid crystal display, LCD)背板。
所述显示背板包括基板110、透明金属层120、黑色矩阵光阻层130、缓冲层140以及透明氧化物半导体层150。所述透明金属层120设置在所述基板110上。所述黑色矩阵光阻层130设置在所述透明金属层120上。所述缓冲层140设置在所述基板110、所述透明金属层120和所述黑色矩阵光阻层130上。所述透明氧化物半导体层150设置在所述缓冲层140上。所述黑色矩阵光阻层130部分覆盖所述透明金属层120,被所述黑色矩阵光阻层130覆盖的所述透明金属层120所在的区域定义为驱动薄膜晶体管区域10,没有被所述黑色矩阵光阻层130覆盖的所述透明金属层120所在的区域定义为储存电容区域20。
于本揭示其中的一实施例中，在所述储存电容区域20中的所述透明金属层120为储存电容的下电极，在所述储存电容区域20中的所述透明氧化物半导体层120为所述储存电容的上电极，在所述储存电容区域20中的所述透明金属层120、所述缓冲层140和所述透明氧化物半导体层120构成所述储存电容。
于本揭示其中的一实施例中，所述显示背板还包括依次设置在所述透明氧化物半导体层120上的栅极绝缘层160、第一金属层170、层间介电绝缘层180、源电极192和漏电极194、保护层210、平坦层220、透明电极层230和像素定义层240。所述层间介电绝缘层180包括多个过孔182，所述源电极192和所述漏电极194通过对应的过孔182与所述透明氧化物半导体层120的边缘接触，所述保护层210和所述平坦层220包括接触孔212，所述透明电极层230通过所述接触孔212与所述源电极192或所述漏电极194接触。
由于本揭示的实施例中的显示背板及其制作方法，所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。所述黑色矩阵光阻层作为遮光层, 可避免所述显示背板的内部光线反射,减少习知因遮光金属层造成的寄生电容耦合现象。储存电容的上电极和下电极都使用透明材料，增加显示背板的像素发光面积及开口率。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (16)

  1. 一种显示背板的制作方法，包括:
    提供基板；
    在所述基板上形成透明金属层；
    在所述透明金属层上形成黑色矩阵光阻层；
    图案化所述黑色矩阵光阻层,以部分覆盖所述透明金属层,其中被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域；
    在所述基板、所述透明金属层和所述黑色矩阵光阻层上形成缓冲层；以及
    在所述缓冲层上形成透明氧化物半导体层。
  2. 如权利要求1所述的显示背板的制作方法，其中在所述储存电容区域中的所述透明金属层为储存电容的下电极，在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极。
  3. 如权利要求1所述的显示背板的制作方法，其中在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成储存电容。
  4. 如权利要求1所述的显示背板的制作方法，还包括在所述透明氧化物半导体层上依次形成栅极绝缘层和第一金属层。
  5. 如权利要求4所述的显示背板的制作方法，还包括在所述缓冲层、所述透明氧化物半导体层、所述栅极绝缘层和所述第一金属层上形成层间介电绝缘层以及图案化所述层间介电绝缘层以形成多个过孔，所述过孔贯穿所述层间介电绝缘层。
  6. 如权利要求5所述的显示背板的制作方法，还包括在所述透明氧化物半导体层上形成源电极和漏电极，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触。
  7. 如权利要求6所述的显示背板的制作方法，还包括在所述层间介电绝缘层、所述源电极和所述漏电极上依次形成保护层、平坦层、透明电极层和像素定义层以及图案化所述保护层和所述平坦层以形成接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
  8. 一种显示背板，包括:
    基板；
    透明金属层，设置在所述基板上；
    黑色矩阵光阻层，设置在所述透明金属层上；
    缓冲层，设置在所述基板、所述透明金属层和所述黑色矩阵光阻层上；以及
    透明氧化物半导体层，设置在所述缓冲层上；
    其中所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域。
  9. 如权利要求8所述的显示背板，其中在所述储存电容区域中的所述透明金属层为储存电容的下电极，在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极，在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成所述储存电容。
  10.     如权利要求8所述的显示背板，还包括依次设置在所述透明氧化物半导体层上的栅极绝缘层、第一金属层、层间介电绝缘层、源电极和漏电极、保护层、平坦层、透明电极层和像素定义层，其中所述层间介电绝缘层包括多个过孔，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触，所述保护层和所述平坦层包括接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
  11.      一种显示背板，包括:
    基板；
    透明金属层，设置在所述基板上；
    黑色矩阵光阻层，设置在所述透明金属层上；
    缓冲层，设置在所述基板、所述透明金属层和所述黑色矩阵光阻层上；以及
    透明氧化物半导体层，设置在所述缓冲层上；
    其中所述黑色矩阵光阻层部分覆盖所述透明金属层,被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为驱动薄膜晶体管区域,没有被所述黑色矩阵光阻层覆盖的所述透明金属层所在的区域定义为储存电容区域；
    其中在所述储存电容区域中的所述透明氧化物半导体层为所述储存电容的上电极。
  12.     如权利要求11所述的显示背板，其中在所述储存电容区域中的所述透明金属层为储存电容的下电极。
  13.     如权利要求12所述的显示背板，在所述储存电容区域中的所述透明金属层、所述缓冲层和所述透明氧化物半导体层构成所述储存电容。
  14.     如权利要求11所述的显示背板，还包括依次设置在所述透明氧化物半导体层上的栅极绝缘层、第一金属层、层间介电绝缘层、源电极和漏电极、保护层、平坦层、透明电极层和像素定义层。
  15.     如权利要求14所述的显示背板，其中所述层间介电绝缘层包括多个过孔，所述源电极和所述漏电极通过对应的过孔与所述透明氧化物半导体层的边缘接触。
  16.     如权利要求15所述的显示背板，其中所述保护层和所述平坦层包括接触孔，所述透明电极层通过所述接触孔与所述源电极或所述漏电极接触。
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