WO2020259337A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2020259337A1
WO2020259337A1 PCT/CN2020/096106 CN2020096106W WO2020259337A1 WO 2020259337 A1 WO2020259337 A1 WO 2020259337A1 CN 2020096106 W CN2020096106 W CN 2020096106W WO 2020259337 A1 WO2020259337 A1 WO 2020259337A1
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Prior art keywords
layer
rigid substrate
driving circuit
binding
flexible base
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PCT/CN2020/096106
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English (en)
French (fr)
Inventor
孟柯
崔强伟
刘超
王莉莉
汪楚航
初宇天
龚林辉
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/264,036 priority Critical patent/US20210296394A1/en
Publication of WO2020259337A1 publication Critical patent/WO2020259337A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the embodiments of the present disclosure relate to an array substrate and a preparation method thereof, a display panel and a display device.
  • Micro LED Micro Light Emitting Diode
  • Micro LED is due to its self-luminous, high luminous efficiency, high contrast, wide operating temperature range, long life, low power consumption, excellent resistance to water and oxygen, and fast response. , It is more and more widely used in the field of large-size splicing.
  • At least one embodiment of the present disclosure provides an array substrate, including a binding area and a non-binding area, wherein the array substrate further includes:
  • the rigid substrate is arranged in the non-binding area
  • the driving circuit layer is provided on one side of the rigid substrate and located in the non-binding area;
  • the light emitting diode layer is arranged on a side of the driving circuit layer away from the rigid substrate and electrically connected to the driving circuit layer;
  • the flexible base layer is provided in the binding area and is located on the same side of the rigid substrate as the driving circuit layer;
  • a binding lead layer is provided on a side of the flexible base layer away from the rigid substrate, and the binding lead layer is electrically connected to the driving circuit layer;
  • the binding lead layer and the flexible base layer can be bent along the edge of the rigid substrate to a side of the rigid substrate away from the driving circuit layer.
  • the flexible base layer extends to the non-binding area and is located between the rigid substrate and the driving circuit layer.
  • the array substrate further includes:
  • the planarization layer is arranged between the driving circuit layer and the light emitting diode layer, wherein the planarization layer extends to a side of the bonding lead layer away from the rigid substrate.
  • the flexible base layer extends to the non-binding area and is located between the driving circuit layer and the light emitting diode layer.
  • the flexible base layer is provided with conductive vias electrically connected to the bonding lead layer;
  • the array substrate further includes:
  • the conductive adhesive layer is arranged between the driving circuit layer and the flexible base layer, wherein the binding lead layer is electrically connected to the driving circuit layer through the conductive via and the conductive adhesive layer.
  • the flexible base layer further includes:
  • the connecting electrode is arranged on a side of the flexible base layer away from the light emitting diode layer, and is electrically connected to the binding lead layer through the conductive via.
  • the array substrate further includes:
  • the buffer layer is located between the rigid substrate and the drive circuit layer.
  • the buffer layer is a flexible layer.
  • the light emitting diode layer includes a pixel electrode layer and one or more light emitting diodes on the pixel electrode layer in the arrangement.
  • the plurality of light emitting diodes include micro light emitting diodes arranged in an array.
  • the bonding lead layer includes a plurality of bonding leads and a plurality of bonding ends
  • the plurality of binding leads are electrically connected to the driving circuit layer, and the plurality of binding ends are electrically connected to the ends of the plurality of binding leads away from the driving circuit layer in a one-to-one correspondence.
  • the array substrate further includes:
  • the circuit element is bound, and the circuit element is arranged in the binding area and electrically connected to the plurality of binding ends.
  • At least another embodiment of the present disclosure provides a method for manufacturing an array substrate, including:
  • the rigid substrate material layer includes a binding area and a non-binding area
  • binding lead layer Forming a binding lead layer, wherein the binding lead layer is provided on a side of the flexible base layer away from the rigid substrate material layer, and is electrically connected to the driving circuit layer;
  • the part of the rigid substrate material layer located in the binding area is removed, so that the remaining part of the rigid substrate material layer forms a rigid substrate, and enables the binding lead layer and the flexible base layer to follow the rigid substrate Bend the edge of the rigid substrate to the side of the rigid substrate away from the driving circuit layer;
  • a light emitting diode is arranged on the surface of the pixel electrode layer away from the rigid substrate, so that the pixel electrode layer and the light emitting diode form a light emitting diode layer.
  • the flexible base layer is located in the non-binding area and the binding area, and between the rigid substrate material layer and the driving circuit layer,
  • Removing the part of the rigid substrate material layer located in the binding zone includes:
  • a peeling method is used to separate the portion of the rigid substrate material layer located in the binding area from the flexible base layer, and then the portion of the rigid substrate material layer located in the binding area is removed by a cutting method.
  • the flexible substrate layer is located in the non-binding area and the binding area, and the flexible substrate layer extends to the non-binding area and is located in the non-binding area.
  • the preparation method further includes:
  • a buffer layer is formed on the rigid substrate material layer, wherein the drive circuit layer is formed on the side of the buffer layer away from the rigid substrate material layer, and the rigid substrate material layer located in the binding area is removed. After the part, the part of the buffer layer located in the binding area is removed.
  • forming the flexible base layer provided in the binding area includes:
  • a conductive via electrically connected to the bonding lead layer is formed on the flexible base layer.
  • forming the flexible base layer provided in the binding zone further includes:
  • a connecting electrode is formed on a side of the flexible base layer away from the pixel electrode layer, wherein the connecting electrode is electrically connected to the bonding lead layer through the conductive via.
  • At least another embodiment of the present disclosure provides a method for manufacturing an array substrate, including:
  • a first substrate is provided, wherein the first substrate includes a flexible base layer, a binding lead layer and a pixel electrode layer, the flexible base layer includes a binding area and a non-binding area; the pixel electrode layer is connected to the binding
  • the fixed lead layer is arranged on the same side of the flexible base layer, and the binding lead layer is located in the binding area, the pixel electrode layer is located in the non-binding area; the non-binding of the flexible base layer
  • the area is provided with a conductive via electrically connected to the bonding lead layer;
  • a second substrate is provided, wherein the second substrate includes a rigid substrate and a driving circuit layer that are stacked; and when the second substrate is paired with the first substrate, the second substrate is positioned on the first substrate.
  • the orthographic projection on a substrate can coincide with the non-binding area;
  • a light emitting diode is arranged on the surface of the pixel electrode layer away from the rigid substrate, so that the pixel electrode layer and the light emitting diode form a light emitting diode layer.
  • At least another embodiment of the present disclosure provides a display panel including the array substrate described in any of the above embodiments.
  • At least another embodiment of the present disclosure provides a display device including the display panel described in any of the above embodiments.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a structure of forming a flexible base layer according to an embodiment of the present disclosure.
  • Fig. 4 is a schematic diagram of a structure of forming a driving circuit layer and a bonding lead layer according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of forming a planarization layer according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a structure of forming a pixel electrode layer according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a structure for forming a rigid substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a structure of forming a buffer layer according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a structure of forming a driving circuit layer according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a structure of forming a flexible base layer according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the structure of forming a pixel electrode layer and a bonding lead layer according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a structure for forming a rigid substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic top view of the structure of a bonding lead layer according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a first substrate according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a structure of forming a pixel electrode layer and a bonding lead layer according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a structure for removing a base substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of a second substrate according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of a structure of a first substrate and a second substrate paired with a box according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic structural diagram of a display device provided by still another embodiment of the present disclosure.
  • a glass substrate provided with a driving circuit can be used to drive the Micro LED to emit light, so as to realize the high resolution of the Micro LED screen.
  • At least one embodiment of the present disclosure provides an array substrate, which is used for preparing a display panel.
  • the array substrate includes a binding area A and a non-binding area B, and also includes a rigid substrate 100, a driving circuit layer 200, a light emitting diode layer 300, a flexible base layer 400 and a binding area.
  • Lead layer 500 is provided.
  • the rigid substrate 100 is provided in the non-binding area B; the driving circuit layer 200 is provided on one side of the rigid substrate 100, for example, including a plurality of driving circuits; the light emitting diode layer 300 is provided on the side of the driving circuit layer 200 away from the rigid substrate 100; flexible
  • the base layer 400 is provided in the bonding area A and is located on the same side of the rigid substrate 100 as the drive circuit layer 200; the bonding lead layer 500 is provided on the side of the flexible base layer 400 away from the rigid substrate 100, and the lead layer 500 is bound to the drive At least one driving circuit in the circuit layer 200 is electrically connected.
  • the bonding lead layer 500 and the flexible base layer 400 can be bent along the edge of the rigid substrate 100 to the side of the rigid substrate 100 away from the driving circuit layer 200, and on this side, for example, at least The part extends in a plane parallel to the board surface of the rigid substrate 100 and thus overlaps with the non-binding area B in a direction perpendicular to the board surface of the rigid substrate 100.
  • This side is the non-display side of the display panel.
  • the rigid substrate 100 is not provided in the bonding area A, so the bonding lead layer 500 can be bent to the side of the rigid substrate 100 away from the driving circuit layer 200 (the backlight surface of the array substrate), and
  • the circuit board 900 is connected (that is, the circuit board 900 is bound in the bonding area A), which avoids connecting the circuit board 900 to the side of the rigid substrate 100 close to the driving circuit layer 200 (the light-emitting surface of the array substrate), which can effectively reduce
  • the frame of the display panel of the array substrate is small, and the seam of the display device spliced by the display panel can be reduced, and the display effect can be improved.
  • the rigid substrate 100 is disposed in the non-binding area B and used to support structures such as the driving circuit layer 200.
  • the material of the rigid substrate 100 may be glass, acrylic or other materials, which is not limited in the present disclosure.
  • the driving circuit layer 200 is provided on one side of the rigid substrate 100.
  • the driving circuit layer 200 is provided with a driving circuit for driving the light emitting diode 320 to emit light.
  • the driving circuit includes at least one electronic component 220.
  • the electronic component 220 includes but is not limited to transistors, capacitors, resistors, coils, and the like. It can be understood that the driving circuit layer 200 is also provided with a signal lead 230 connected to the electronic component 220 and a transfer electrode 210. In one embodiment, a thin film transistor is provided in the driving circuit.
  • the non-binding area B includes a pixel array, for example, the non-binding area B includes a display area, and the display area includes the pixel array.
  • the pixel array includes a plurality of pixel units arranged in multiple rows and multiple columns, and each pixel unit includes a pixel circuit and a light-emitting element.
  • the non-binding area B may further include multiple gate lines, multiple data lines, and other signal leads, which are respectively connected to corresponding pixel units in the pixel array to provide scanning signals and data for multiple pixel units in the pixel array. Signal etc.
  • the pixel circuit is configured to drive the light-emitting element in the corresponding pixel unit to emit light according to the received scan signal and data signal.
  • the single pixel channel may include multiple switching elements (such as thin film transistors) and capacitors, which are located in the drive circuit layer 200, that is, the drive circuit layer 200 includes the pixel circuits of the multiple pixel units; in addition, the drive circuit layer 200 also includes the aforementioned various signal leads.
  • the drive circuit layer 200 includes the pixel circuits of the multiple pixel units; in addition, the drive circuit layer 200 also includes the aforementioned various signal leads.
  • the pixel circuit may be a 2T1C pixel circuit, which includes two TFTs (Thin-film Transistor, thin film transistors) and a storage capacitor Cs to drive the light-emitting element to emit light.
  • TFTs Thin-film Transistor, thin film transistors
  • storage capacitor Cs to drive the light-emitting element to emit light.
  • One of the two TFTs is a driving transistor, and the other One is a data write transistor.
  • the pixel circuit may also have a compensation function.
  • the compensation function may be realized by voltage compensation, current compensation or hybrid compensation.
  • the pixel circuit with compensation function may be, for example, 4T1C or 4T2C. No more details here.
  • the driving circuit layer is a multi-layered structure, for example, including one or more conductive layers, one or more insulating layers, one or more semiconductor layers, between adjacent conductive layers and conductive layers or between adjacent conductive layers and The semiconductor layers may be electrically connected to each other through via holes formed in the intermediate insulating layer.
  • the one or more conductive layers are used to form the gate and source and drain of the thin film transistor, to form the electrode of the storage capacitor, and to form various signal leads.
  • the gate line can be arranged on the same layer as the gate of the thin film transistor , The data line and the source and drain of the thin film transistor are arranged in the same layer.
  • the switching electrode is electrically connected with the corresponding pixel circuit, so as to realize the electrical connection between the pixel circuit and the light emitting diode, for example.
  • the one or more insulating layers may be inorganic insulating layers or organic insulating layers, and may be located only in the unbound area, or may be located in both the bound area and the unbound area.
  • the light-emitting element may be a light-emitting diode.
  • the light emitting diode layer 300 is provided on the side of the driving circuit layer 200 away from the rigid substrate 100, and it may include an electrical connection with the driving circuit layer 200 (the pixel circuit of the corresponding pixel unit).
  • the pixel electrode layer 310 and the light emitting diode 320 connected to the pixel electrode layer 310. It can be understood that the pixel electrode layer 310 may be provided with a pixel electrode and the pixel electrode is electrically connected to the driving circuit.
  • each pixel unit includes a corresponding pixel electrode, and the pixel electrode is electrically connected to the pixel circuit of the pixel unit and electrically connected to the light emitting diode of the pixel unit, so that the pixel circuit can drive the light emitting diode.
  • the array substrate further includes a pixel definition layer, and the pixel definition layer includes pixel openings corresponding to a plurality of pixel units, for example, at least partially covering the plurality of pixel electrodes, and the plurality of pixel openings at least partially expose the plurality of pixel electrodes, respectively,
  • the plurality of light emitting diodes are respectively electrically connected to the plurality of pixel electrodes through the plurality of pixel openings.
  • the light emitting diode 320 may be a micro LED, a nano LED, or other types of light emitting diodes, such as organic light emitting diodes (OLED) or quantum dot light emitting diodes (QLED), etc. Not limited.
  • the light emitting diode layer 300 includes micro light emitting diodes 320 arranged in an array, corresponding to a plurality of pixel units in the pixel array.
  • the bonding wire layer 500 may include a plurality of bonding wires 510 (bonding lines) and a plurality of bonding pads 520 (bonding pads).
  • the multiple bonding leads 510 are connected to the multiple signal leads 230 in the driving circuit layer 200 in one-to-one correspondence, and the multiple bonding ends 520 are connected to the ends of the multiple bonding leads 510 away from the driving circuit in a one-to-one correspondence.
  • the bonding wire layer 500 needs to have a certain width. If the bonding lead layer 500 cannot be bent toward the back of the rigid substrate 100 (the side far from the driving circuit layer 200), the bonding lead layer 500 will completely appear on the light-emitting surface of the display panel using the array substrate, resulting in The display panel has a large border.
  • the bonding lead layer 500 can be bent toward the back of the rigid substrate 100, which reduces the area of the bonding lead layer 500 exposed to the light emitting surface of the display panel, thereby reducing the frame of the display panel. .
  • the binding terminal 520 is used to electrically connect with a binding circuit element, and the binding circuit element is bound in the binding area by, for example, a conductive adhesive.
  • the binding circuit element is a circuit board 900. If the bonding lead layer 500 cannot be bent toward the backlight surface of the rigid substrate 100, the circuit board 900 needs to be connected to the light-emitting surface of the display panel to increase the frame of the display panel; even if the circuit board 900 is a flexible circuit board 900, the flexible circuit board 900 will still increase the border of the display panel.
  • the binding lead layer 500 can be bent toward the back of the rigid substrate 100, so that the array substrate is bound to the circuit board 900 on the backlight surface, avoiding the need for the circuit board 900 to be arranged on the side of the rigid substrate 100 Increase the border of the display panel.
  • the bonding circuit element may also be an integrated circuit chip (for example, a driver chip), etc., which is not limited in the present disclosure.
  • the flexible base layer 400 may be a flexible material such as resin, for example, a polyimide (PI) material may be used.
  • the flexible base layer 400 is used to carry and fix the bonding lead layer 500 to prevent the bonding lead layer 500 from being damaged when bent.
  • the flexible base layer 400 may extend to the non-binding area B and is located between the rigid substrate 100 and the driving circuit layer 200. In this way, the flexible base layer 400 can serve as a buffer layer between the driving circuit layer 200 and the rigid substrate 100.
  • the driving circuit layer 200 and the bonding wire layer 500 are disposed on the same side of the flexible base layer 400, and the driving circuit layer 200 and the bonding wire layer 500 are electrically connected.
  • the bonding lead 510 and the signal lead 230 connected to each other are different parts of the same lead.
  • a plurality of signal leads may be provided on the side of the flexible base layer 400 away from the rigid substrate 100, wherein the part of the signal lead located in the bonding area A is the bonding lead 510, and the signal lead is located in the part of the non-bonding area B For the signal lead 230.
  • the array substrate may further include a planarization layer 610, the planarization layer 610 is provided between the driving circuit layer 200 and the light emitting diode layer 300, and the planarization layer 610 extends to the bonding lead layer 500 The side away from the rigid substrate 100.
  • the bonding wire layer 500 and the driving circuit layer 200 are provided on the same side of the planarization layer 610.
  • a first conductive via 710 may be provided on the planarization layer 610, and the light emitting diode layer 300 may be electrically connected to the driving circuit layer 200 through the first conductive via 710, for example, for each In the pixel unit, the light-emitting diode located in the light-emitting diode layer 300 may be electrically connected to the pixel circuit located in the driving circuit layer 200 through the first conductive via 710 and the switching electrode 210.
  • an insulating material layer may be further provided between the bonding lead layer 500 and the flexible base layer 400, and the material of the insulating material layer may include one of the insulating materials used in the driving circuit layer 200.
  • the insulating material deposited on the bonding area A does not need to be completely removed when preparing the driving circuit layer 200, which simplifies the preparation of the array substrate.
  • the flexible base layer 400 may extend to the non-binding area B and is located between the driving circuit layer 200 and the light emitting diode layer 300.
  • the bonding wire layer 500 and the light emitting diode layer 300 may be disposed on the same side of the flexible base layer 400.
  • the flexible base layer 400 can also play a role in planarizing the surface of the driving circuit layer 200 away from the rigid substrate 100, so as to further form the light emitting diode layer 300. Since the driving circuit layer 200 is disposed on the side of the flexible base layer 400 away from the bonding lead layer 500, there will be no residual material of the driving circuit layer 200 between the flexible base layer 400 and the bonding lead layer 500.
  • the bonding lead layer 500 has a smaller thickness and is easier to bend, which can further reduce the frame of the display panel and reduce the bending stress of the flexible base layer 400 and the bonding lead layer 500.
  • the bonding wire 510 in the bonding wire layer 500 and the pixel electrode in the light-emitting diode layer 300 can be made of the same conductive material and have the same thickness, so that the same conductive material film layer can be simultaneously prepared
  • the wire 510 and the pixel electrode are bound.
  • the material of the bonding wire 510 and the pixel electrode is copper to increase the driving current of the light emitting diode.
  • a first conductive via 710 and a second conductive via 720 may be provided on the flexible base layer 400, and the light emitting diode layer 300 is electrically connected to the driving circuit layer 200 through the first conductive via 710
  • the light emitting diode located in the light emitting diode layer 300 may be electrically connected to the pixel circuit located in the driving circuit layer 200 through the first conductive via 710; the binding lead layer 500 is through the second conductive via 720 It is electrically connected to the driving circuit layer 200.
  • the bonding wire 510 in the bonding wire layer 500 may be electrically connected to the corresponding signal wire in the driving circuit layer 200 through the second conductive via 720.
  • the flexible base layer 400 may extend to the non-binding area B and is located between the driving circuit layer 200 and the light emitting diode layer 300.
  • the array substrate further includes a conductive adhesive layer 630, and the conductive adhesive layer 630 is disposed between the driving circuit layer 200 and the flexible base layer 400.
  • the bonding lead layer 500 and the light emitting diode layer 300 are disposed on the same side of the flexible base layer 400, and the bonding lead layer 500, the light emitting diode layer 300, and the flexible base layer 400 can be used as covering the bonding area A And the first substrate 810 of the non-binding area B.
  • the driving circuit layer 200 and the rigid substrate 100 can be used as the second substrate 820 located in the non-binding area B; the first substrate 810 and the second substrate 820 can be bonded by the conductive adhesive layer 630 in a box-matching manner. Then, the array substrate of the embodiment of the present disclosure is formed.
  • the flexible base layer 400 is provided with a first conductive via 710 and a second conductive via 720, and the light emitting diode layer 300 passes through the first conductive via 710 and the conductive adhesive layer 630 and the driving circuit
  • the layer 200 is electrically connected, and the bonding lead layer 500 is electrically connected to the driving circuit layer 200 through the second conductive via 720 and the conductive adhesive layer 630.
  • the first conductive via 710 and the second conductive via 720 are located in the non-binding region B.
  • the side of the flexible base layer 400 close to the driving circuit layer 200 may further include a A connection electrode 711 and a second connection electrode 721; wherein the first connection electrode 711 is electrically connected to the first conductive via 710, and the second connection electrode 721 is electrically connected to the second conductive via 720.
  • the conductive adhesive layer 630 can be an anisotropic conductive film (ACF) to ensure that the signals between the bonding lead layer 500 and the light-emitting diode layer 300 will not crosstalk with each other and simplify the conductive adhesive layer 630 setting method.
  • the conductive adhesive layer 630 may include a viscous base material and a plurality of conductive particles dispersed in the viscous base material. When the conductive adhesive layer is pressed, a conductive path may be formed at the pressed position.
  • the adhesive matrix material is a thermoplastic resin or a thermosetting resin
  • the conductive particles may be metal particles or graphite particles.
  • At least one embodiment of the present disclosure also provides a method for preparing an array substrate. As shown in FIG. 23, the method for preparing an array substrate may include the following steps S110-S170:
  • Step S110 providing a rigid substrate material layer 101, the rigid substrate material layer 101 includes a binding area A and a non-binding area B;
  • Step S120 as shown in FIG. 4 and FIG. 11, a driving circuit layer 200 is formed.
  • the driving circuit layer 200 is provided on one side of the rigid substrate material layer 101 and located in the non-binding area B;
  • Step S130 as shown in FIGS. 6 and 13, a pixel electrode layer 310 is formed, and the pixel electrode layer 310 is disposed on the side of the driving circuit layer 200 away from the rigid substrate material layer 101;
  • Step S140 as shown in FIG. 3 and FIG. 12, forming a flexible base layer 400 disposed in the binding area A, the flexible base layer 400 and the driving circuit layer 200 are disposed on the same side of the rigid substrate material layer 101;
  • Step S150 as shown in FIGS. 4 and 13, a bonding lead layer 500 is formed.
  • the bonding lead layer 500 is provided on the side of the flexible base layer 400 away from the rigid substrate material layer 101 and is electrically connected to the driving circuit layer 200;
  • Step S160 remove the part of the rigid substrate material layer 101 located in the binding area A, so that the remaining part of the rigid substrate material layer 101 forms the rigid substrate 100, and binds the lead layer 500 and the flexible substrate.
  • the bottom layer 400 can be bent along the edge of the rigid substrate 100 to the side of the rigid substrate 100 away from the driving circuit layer 200;
  • Step S170 as shown in FIGS. 1 and 8, a light emitting diode 320 is provided on the surface of the pixel electrode layer 310 away from the rigid substrate 100, so that the pixel electrode layer 310 forms the light emitting diode layer 300.
  • the array substrate prepared by the method of manufacturing the array substrate of the embodiment of the present disclosure, as shown in FIG. 1 and FIG. 8, is not provided with the rigid substrate 100 in the bonding area A, so the bonding lead layer 500 can be bent to the rigid substrate 100
  • the frame of the display panel to which the array substrate is applied is effectively reduced, and the seam of the display device spliced by the display panel can be reduced, and the display effect can be improved.
  • the material of the rigid substrate material layer 101 may be glass, acrylic or other materials.
  • a driving circuit for driving the light-emitting diode 320 to emit light is provided in the driving circuit layer 200.
  • the driving circuit includes at least one electronic component 220.
  • the electronic component 220 includes but is not limited to transistors, capacitors, resistors, coils, and the like. It can be understood that the driving circuit layer 200 is also provided with a signal lead 230 connected to the electronic component 220 and a transfer electrode 210. In one embodiment, a thin film transistor is provided in the driving circuit.
  • the driving circuit layer 200 includes pixel circuits of a plurality of pixel units, and in addition, the driving circuit layer 200 also includes a variety of signal leads which are respectively electrically connected to the corresponding pixel circuits to provide scan signals, data signals, and power supply voltages. Wait.
  • the driving circuit layer 200 is located in the non-binding area B, indicating that the orthographic projection of the driving circuit layer 200 on the rigid substrate material layer 101 coincides with the non-binding area B.
  • the pixel electrode layer 310 is electrically connected to the driving circuit layer 200.
  • the pixel electrode layer 310 may be provided with a pixel electrode, and the pixel electrode is electrically connected to a corresponding pixel circuit in the driving circuit layer through the switching electrode 210.
  • the light emitting diode 320 when the light emitting diode 320 is provided in step S170, the light emitting diode 320 can be connected to the pixel electrode in a one-to-one correspondence, so that the pixel electrode layer 310 and the light emitting diode 320 together form the light emitting diode layer 300.
  • the flexible base layer 400 may be a flexible material such as resin, for example, a polyimide material may be used.
  • the flexible base layer 400 is used to carry and fix the bonding lead layer 500 to prevent the bonding lead layer 500 from being damaged when bent.
  • the bonding wire layer 500 may include a plurality of bonding wires 510 (bonding lines) and a plurality of bonding pads 520 (bonding pads).
  • the plurality of bonding leads 510 are connected to the plurality of signal leads 230 in the driving circuit layer 200 in one-to-one correspondence, and the plurality of bonding ends 520 are connected to the ends of the plurality of bonding leads 510 away from the driving circuit in a one-to-one correspondence, and are connected to the plurality of
  • the signal lead 230 electrically connected to the bonding lead 510 includes but is not limited to a gate line, a data line, a power line, etc., which is not limited in the present disclosure.
  • the bonding wire layer 500 needs to have a certain width. If the bonding lead layer 500 cannot be bent to the back of the rigid substrate 100 (the side far from the driving circuit layer 200), the bonding lead layer 500 will be completely present on the light-emitting surface of the display panel, which will cause the display panel to have a relatively narrow frame. Big problem.
  • the bonding lead layer 500 can be bent toward the back of the rigid substrate 100, which reduces the area of the bonding lead layer 500 exposed to the light emitting surface of the display panel, thereby reducing The border of the display panel is displayed.
  • the bonding terminal 520 is used to connect to the circuit board 900. If the bonding lead layer 500 cannot be bent toward the backlight surface of the rigid substrate 100, the circuit board 900 needs to be connected to the light-emitting surface of the display panel to increase the display panel Frame; even if the circuit board 900 is a flexible circuit board 900, the flexible circuit board 900 will still increase the frame of the display panel.
  • the bonding lead layer 500 can be bent toward the back of the rigid substrate 100, so that the array substrate is bound to the circuit board 900 on the backlight surface, which prevents the circuit board 900 from adding a display panel Border.
  • step S160 laser lift off technology (LLO; Laser Lift Off) may be used to separate the part of the rigid substrate material layer 101 located in the binding area A from other film structures including the flexible base layer; and then through cutting The method of removing the part of the rigid substrate material layer 101 located in the binding area A.
  • LLO Laser Lift Off
  • the light emitting diode 320 may be a micro light emitting diode, a nano light emitting diode or other types of light emitting diodes, which are not particularly limited in the present disclosure.
  • the circuit board 900 can also be connected to the bonding end 520, and then the circuit board 900 can be bent by bonding the lead layer 500 and the flexible base layer 400 And it is fixed to the back of the rigid substrate 100 (the side away from the driving circuit layer 200) to obtain a display panel based on the array substrate.
  • the circuit board 900 can be a flexible circuit board 900 or a rigid circuit board 900, which is not particularly limited in the present disclosure.
  • a driver chip is provided on the circuit board 900, and the driver chip includes but is not limited to a data driver, a gate driver, a timing controller, etc., which is not limited in the present disclosure.
  • the display panel has the characteristics of a narrow frame. For example, based on the display panel with a narrow frame, a display device with a smaller seam can be spliced together.
  • step S140 may be performed before step S120.
  • a flexible base layer 400 covering the binding area A and the non-binding area B may be formed on one side of the rigid substrate material layer 101; as shown in FIG. 4
  • the driving circuit layer 200 may be formed on the side of the flexible base layer 400 away from the rigid substrate material layer 101.
  • the flexible base layer 400 can extend to the non-binding area B and is located between the rigid substrate 100 and the driving circuit layer 200.
  • the flexible base layer 400 can serve as a buffer layer between the driving circuit layer 200 and the rigid substrate 100.
  • step S150 may be performed before step S130.
  • step S120 while step S120 is performed, step S150 is performed, that is, the bonding lead layer 500 and the driving circuit layer 200 are formed at the same time.
  • signal leads can be formed in both the bonding area A and the non-bonding area B.
  • the part of the signal lead located in the bonding area A is the bonding lead 510, and the signal lead
  • the part of the lead located in the non-bonding area B is the signal lead 230.
  • the bonding leads 510 and the corresponding signal leads 230 can be formed in the same process, which simplifies the manufacturing method of the array substrate.
  • step S120 and step S150 are performed at the same time, the insulating material used to form the drive circuit layer 200 may remain in the bonding area A, and then the prepared array substrate is bound to the leads There may be insulating materials in the layer 500.
  • step S180 may be performed: forming a planarization layer 610 on the side of the driving circuit layer 200 away from the rigid substrate material layer 101, so as to provide flatness for forming the pixel electrode layer 310. surface.
  • a first via 712 may be provided on the planarization layer 610, the first via 712 is used for metallization in step S130 to become the first conductive via 710, and the first via 712 exposes the transfer electrode 210, so as to electrically connect corresponding pixel circuits and pixel electrodes in the driving circuit layer 200 and the pixel electrode layer 310 through the transfer electrode 210.
  • the planarization layer 610 may also be disposed on the side of the bonding lead layer 500 away from the rigid substrate material layer 101 to protect the bonding lead layer 500. Further, the planarization layer 610 may expose the bonding end 520 of the bonding lead layer 500 so that the bonding end 520 is connected to the circuit board 900.
  • step S120 when the driving circuit layer 200 is formed, the insulating material deposited on the part A of the binding area of the rigid substrate material layer 101 may be partially or completely retained as Supporting layer 201; In this way, in step S120, the part of the binding area A of the rigid substrate material layer 101 can form the supporting layer 201.
  • step S140 can be performed between step S120 and step S130.
  • a flexible layer covering the binding area A and the non-binding area B may be formed on the side of the supporting layer 201 and the driving circuit layer 200 away from the rigid substrate material layer 101.
  • the pixel electrode layer 310 may be formed on the side of the flexible base layer 400 away from the rigid substrate material layer 101; as shown in FIG. 13, in step S150, a bonding lead layer 500 may be formed On the side of the flexible base layer 400 away from the rigid substrate material layer 101.
  • the flexible base layer 400 can extend to the non-binding area B and is located between the pixel electrode layer 310 and the driving circuit layer 200. In this way, the flexible base layer 400 can be used as a planarization layer between the driving circuit layer 200 and the pixel electrode layer 310.
  • the flexible base layer 400 may be provided with a first via 712 and a second via 722.
  • the first via 712 is used for metallization in step S130 to become the first conductive via 710 so as to electrically connect the driving circuit layer 200 and the pixel electrode layer 310.
  • the second via 722 is used for metallization in step S150 to become a second conductive via 720, and the second conductive via 720 exposes the corresponding signal lead 230 so as to be electrically connected to the driving circuit layer through the second conductive via 720
  • the signal wire 230 and the bonding wire 510 corresponding to each other in the 200 and bonding wire layer 500.
  • step S150 may be executed first, and then step S130 may be executed.
  • step S150 is performed while step S130 is performed, that is, the bonding wire layer 500 and the pixel electrode layer 310 are formed at the same time.
  • a conductive material film layer that is simultaneously disposed in the bonding area A and the non-binding area B can be formed, and the conductive material film layer makes the first via 712 and the second via 722 is respectively transformed into a first conductive via 710 and a second conductive via 720; then the conductive material film layer is patterned to obtain the bonding wire 510 located in the bonding area A and the pixel electrode located in the non-binding area B .
  • the material of the conductive material film layer can be copper or copper alloy to increase the driving current of the light emitting diode.
  • step S190 may be performed: forming a buffer layer 620 on one side of the rigid substrate material layer 101.
  • the buffer layer 620 may be a flexible layer, such as another flexible substrate, for example, may be made of polyimide material or the like.
  • the buffer layer 620 may cover the binding area A and the non-binding area B, so as to avoid an increase in the process of patterning the buffer layer 620 and simplify the preparation method of the array substrate of the embodiment of the present disclosure.
  • the driving circuit layer 200 may be formed on the side of the buffer layer 620 away from the rigid substrate material layer 101.
  • the buffer layer 620 may only cover the unbound area B.
  • step S160 the part of the buffer layer 620 located in the binding area A and the support layer 201 can also be removed, so that the thickness of the array substrate in the binding area A can be reduced, and the binding area can be reduced. A stress when bending. Further, the part of the buffer layer 620 located in the binding area A and the support layer 201 can be removed by a laser cladding method.
  • the embodiment of the present disclosure also provides another method for preparing the array substrate.
  • the method for preparing the array substrate may include:
  • a first substrate 810 is provided.
  • the first substrate 810 includes a flexible base layer 400, a bonding lead layer 500 and a pixel electrode layer 310; wherein the flexible base layer 400 includes a bonding area A and a non-binding area.
  • Fixed area B; the pixel electrode layer 310 and the bonding lead layer 500 are provided on the same side of the flexible base layer 400, and the bonding lead layer 500 is located in the bonding area A, and the pixel electrode layer 310 is located in the non-binding area B; the flexible base layer
  • the non-bonding area B of 400 is provided with a second conductive via 720 electrically connected to the bonding lead layer 500;
  • a second substrate 820 is provided.
  • the second substrate 820 includes a rigid substrate 100 and a driving circuit layer 200 that are stacked; and when the second substrate 820 and the first substrate 810 are boxed together, the second substrate The orthographic projection of the substrate 820 on the first substrate 810 can coincide with the non-binding area B;
  • step S230 as shown in FIG. 22, the first substrate 810 and the second substrate 820 are paired so that the driving circuit layer 200 is away from the surface of the rigid substrate 100 and the unbound area B of the flexible base layer 400 is away from the surface of the pixel electrode layer 310 Connect through the conductive adhesive layer 630;
  • step S240 as shown in FIG. 16, a light emitting diode 320 is disposed on the surface of the pixel electrode layer 310 away from the rigid substrate 100, so that the pixel electrode layer 310 forms the light emitting diode layer 300.
  • the array substrate prepared by the method of manufacturing the array substrate of the embodiment of the present disclosure, as shown in FIG. 16 and FIG. 17, is not provided with the rigid substrate 100 in the bonding area A, so the bonding lead layer 500 can be bent to the rigid substrate 100
  • the frame of the display panel to which the array substrate is applied is effectively reduced, and the seam of the display device spliced by the display panel can be reduced, and the display effect can be improved.
  • the first substrate 810 may be provided by the following method:
  • Step 310 provide a base substrate 811
  • Step 320 forming a flexible base layer 400 on one side of the base substrate 811, the flexible base layer 400 including a binding area A and a non-binding area B;
  • Step 330 as shown in FIG. 19, a bonding lead layer 500 is formed, and the bonding lead layer 500 is disposed on the side of the flexible base layer 400 away from the base substrate 811 and located in the bonding area A;
  • Step 340 as shown in FIG. 19, a pixel electrode layer 310 is formed.
  • the pixel electrode layer 310 is disposed on the side of the flexible base layer 400 away from the base substrate 811 and located in the non-binding area B;
  • Step 350 as shown in FIG. 20, remove the base substrate 811;
  • a second conductive via 720 is formed in the unbonded area B of the flexible base layer 400, and the second conductive via 720 is electrically connected to the bonding lead layer 500.
  • a second conductive via 720 may be formed in the non-binding area B of the flexible base layer 400, and the second conductive via 720 is electrically connected to the pixel electrode layer 310.
  • the first connection electrode 711 and the second connection electrode 721 may also be formed on the side of the flexible base layer 400 away from the pixel electrode layer 310.
  • the first connection electrode 711 is connected to the first conductive via 710 to ensure that the first conductive via 710 can be fully electrically connected to the conductive adhesive layer 630;
  • the second connection electrode 721 is connected to the second conductive via 720 for This ensures that the second conductive via 720 can be fully electrically connected to the conductive adhesive layer 630.
  • step 330 and step 340 may be performed simultaneously, that is, the bonding lead layer 500 and the pixel electrode layer 310 are formed at the same time.
  • the flexible base layer 400 extends into the non-binding area B and is located between the driving circuit layer 200 and the light emitting diode layer 300, As the planarization layer 610 of the array substrate.
  • the provided second substrate 820 should meet the following requirements, that is, when the second substrate 820 and the first substrate 810 are aligned, the orthographic projection of the second substrate 820 on the first substrate 810 can be unbound Area B coincides. In other words, when the second substrate 820 is paired with the first substrate 810, the second substrate 820 can expose the binding area A of the first substrate 810.
  • the second substrate 820 may further include a buffer layer 620, and the buffer layer 620 is disposed between the rigid substrate 100 and the driving circuit layer 200.
  • a conductive adhesive layer 630 may be provided on the unbound area B of the second substrate 820 or the first substrate 810 first, and then the second substrate 820 and the unbound area B of the first substrate 810 may be aligned and combined. Bonding. It can be understood that, as shown in FIG. 22, the second substrate 820 is aligned with the unbound area B of the first substrate 810, which means that the orthographic projection of the second substrate 820 on the first substrate 810 can be Area B overlaps.
  • the surface of the driving circuit layer 200 away from the rigid substrate 100 faces the unbound area B of the flexible base layer 400 away from the surface of the pixel electrode layer 310, and is conductive
  • the glue layer 630 is disposed on one of these two surfaces.
  • the conductive adhesive layer 630 can be an anisotropic conductive adhesive film.
  • the embodiments of the present disclosure also provide a display panel, which includes any one of the array substrates described in the above-mentioned array substrate embodiment.
  • the display panel further includes a circuit board 900, and the circuit board 900 is provided with a driving chip.
  • the bonding area A of the array substrate is bent along the edge of the rigid substrate 100 to the side of the rigid substrate 100 away from the driving circuit layer 200, and the circuit board 900 is electrically connected to the bonding lead layer 500 and located on the rigid substrate 100 away from the driving circuit layer 200 Side.
  • the array substrate used in the display panel of the embodiment of the present disclosure is the same as the array substrate in the above-mentioned embodiment of the array substrate, and therefore, has the same beneficial effects, which will not be repeated here.
  • the display panel or the array substrate of the embodiments of the present disclosure may also include other necessary packaging elements and functional circuits, for example, touch circuits or fingerprint recognition. Circuits, etc. further include touch and fingerprint recognition functions.
  • the present disclosure also provides a display device including the display panel described in the above display panel embodiment. As shown in FIG. 25, the display device 1 includes the display panel 10 described above.
  • the display device may be an electronic advertising screen, a stage background screen, a TV set or other types of display devices, which are not particularly limited in the present disclosure.
  • the display panel adopted by the display device in the embodiment of the present disclosure is the same as the display panel in the above-mentioned display panel embodiment, and therefore, has the same beneficial effects, which will not be repeated here.

Abstract

一种阵列基板及其制备方法、显示面板和显示装置。该阵列基板包括绑定区和非绑定区，所述阵列基板还包括刚性基板、驱动电路层、发光二极管层、柔性基底层和绑定引线层；刚性基板设于所述非绑定区；柔性基底层设于所述绑定区且与所述驱动电路层位于所述刚性基板的同一侧；绑定引线层设于所述柔性基底层远离所述刚性基板的一侧，且所述绑定引线层与所述驱动电路层电连接；所述绑定引线层和所述柔性基底层能够沿所述刚性基板的边缘弯折至所述刚性基板远离所述驱动电路层的一侧。该阵列基板能够降低显示面板的边框。

Description

阵列基板及其制备方法、显示面板和显示装置
本申请要求于2019年6月25日递交且名为“阵列基板及其制备方法、显示面板和显示装置”的中国专利申请第201910554975.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
Micro LED(Micro Light Emitting Diode，微型发光二极管)由于其自发光、发光效率高、对比度高、工作温度范围宽、寿命长、功耗低、对水和氧的阻绝性优良、响应快等优良特性，在大尺寸拼接领域的应用越来越广泛。
发明内容
本公开的至少一实施例提供一种阵列基板，包括绑定区和非绑定区，其中，所述阵列基板还包括：
刚性基板，设于所述非绑定区；
驱动电路层，设于所述刚性基板的一侧且位于所述非绑定区；
发光二极管层，设于所述驱动电路层远离所述刚性基板的一侧，且与所述驱动电路层电连接；
柔性基底层，设于所述绑定区且与所述驱动电路层位于所述刚性基板的同一侧；
绑定引线层，设于所述柔性基底层远离所述刚性基板的一侧，且所述绑定引线层与所述驱动电路层电连接；
其中，所述绑定引线层和所述柔性基底层能够沿所述刚性基板的边缘弯折至所述刚性基板远离所述驱动电路层的一侧。
在所述的阵列基板的至少一个示例中，例如，所述柔性基底层延伸至所述非绑定区，且位于所述刚性基板与所述驱动电路层之间。
在所述的阵列基板的至少一个示例中，例如，所述阵列基板还包括：
平坦化层，设于所述驱动电路层与所述发光二极管层之间，其中，所述平坦化层延伸至所述绑定引线层远离所述刚性基板的一侧。
在所述的阵列基板的至少一个示例中，例如，所述柔性基底层延伸至所述非绑定区，且位于所述驱动电路层与所述发光二极管层之间。
在所述的阵列基板的至少一个示例中，例如，所述柔性基底层设置有与所述绑定引线层电连接的导电过孔；
所述阵列基板还包括：
导电胶层，设于所述驱动电路层与所述柔性基底层之间，其中，所述绑定引线层通过所述导电过孔和所述导电胶层与所述驱动电路层电连接。
在所述的阵列基板的至少一个示例中，例如，所述柔性基底层还包括：
连接电极，设于所述柔性基底层远离所述发光二极管层的一侧，且通过所述导电过孔与所述绑定引线层电连接。
在所述的阵列基板的至少一个示例中，例如，所述阵列基板还包括：
缓冲层，位于所述刚性基板与所述驱动电路层之间。
在所述的阵列基板的至少一个示例中，例如，所述缓冲层为柔性层。
在所述的阵列基板的至少一个示例中，例如，所述发光二极管层包括像素电极层以及设置中所述像素电极层上的一个或多个发光二极管。
在所述的阵列基板的至少一个示例中，例如，所述多个发光二极管包括阵列设置的微型发光二极管。
在所述的阵列基板的至少一个示例中，例如，所述绑定引线层包括多个绑定引线以及多个绑定端，
所述多个绑定引线与所述驱动电路层电连接，所述多个绑定端一一对应地电连接于所述多个绑定引线远离所述驱动电路层的一端。
在所述的阵列基板的至少一个示例中，例如，所述阵列基板还包括：
绑定电路元件，所述电路元件设置于所述绑定区，并且与所述多个绑定端电连接。
本公开至少另一实施例提供一种阵列基板的制备方法，包括：
提供一刚性基板材料层，其中，所述刚性基板材料层包括绑定区和非绑定区；
形成驱动电路层，其中，所述驱动电路层设于所述刚性基板材料层的一侧且位于所述非绑定区；
形成像素电极层，其中，所述像素电极层设于所述驱动电路层远离所述刚性基板材料层的一侧；
形成设于所述绑定区的柔性基底层，其中，所述柔性基底层与所述驱动电路层设于所述刚性基板材料层的同一侧；
形成绑定引线层，其中，所述绑定引线层设于所述柔性基底层远离所述刚性基板材料层的一侧，且与所述驱动电路层电连接；
去除所述刚性基板材料层位于所述绑定区的部分，使得所述刚性基板材料层的剩余部分形成刚性基板，且使得所述绑定引线层和所述柔性基底层能够沿所述刚性基板的边缘弯折至所述刚性基板远离所述驱动电路层的一侧；
在所述像素电极层远离所述刚性基板的表面设置发光二极管，使得所述像素电极层和所述发光二极管形成发光二极管层。
在所述的制备方法的至少一个示例中，例如，所述柔性基底层位于所述非绑定区和所述绑定区，且位于所述刚性基板材料层与所述驱动电路层之间，
去除所述刚性基板材料层位于所述绑定区的部分包括：
采用剥离方法使得刚性基板材料层位于所述绑定区的部分与所述柔性基底层分离，然后再通过切割方法去除所述刚性基板材料层位于所述绑定区的部分。
在所述的制备方法的至少一个示例中，例如，所述柔性基底层位于所述非绑定区和所述绑定区，所述柔性基底层延伸至所述非绑定区，且位于所述驱动电路层与所述发光二极管层之间，
所述制备方法还包括：
在所述刚性基板材料层形成缓冲层，其中，所述驱动电路层形成于所述缓冲层远离所述刚性基板材料层一侧，并且，去除所述刚性基板材料层位于所述绑定区的部分之后，将所述缓冲层位于所述绑定区内的部分去除。
在所述的制备方法的至少一个示例中，例如，形成设于所述绑定区的柔性基底层包括：
在所述柔性基底层形成与所述绑定引线层电连接的导电过孔。
在所述的制备方法的至少一个示例中，例如，形成设于所述绑定区的柔 性基底层还包括：
在所述柔性基底层远离所述像素电极层的一侧形成连接电极，其中，所述连接电极通过所述导电过孔与所述绑定引线层电连接。
本公开至少另一实施例提供一种阵列基板的制备方法，包括：
提供第一基板，其中，所述第一基板包括柔性基底层、绑定引线层和像素电极层，所述柔性基底层包括绑定区和非绑定区；所述像素电极层与所述绑定引线层设于所述柔性基底层的同一侧，且所述绑定引线层位于所述绑定区，所述像素电极层位于所述非绑定区；所述柔性基底层的非绑定区设置有与所述绑定引线层电连接的导电过孔；
提供第二基板，其中，所述第二基板包括层叠设置的刚性基板和驱动电路层；且使得当所述第二基板与所述第一基板对盒时，所述第二基板在所述第一基板上的正投影能够与所述非绑定区重合；
将所述第一基板和所述第二基板对盒，使得所述驱动电路层远离所述刚性基板的表面与所述柔性基底层的非绑定区远离所述像素电极层的表面连接；
在所述像素电极层远离所述刚性基板的表面设置发光二极管，使得所述像素电极层和所述发光二极管形成发光二极管层。
本公开至少另一实施例提供一种显示面板，包括上述任一实施例所述的阵列基板。
本公开至少另一实施例提供一种显示装置，包括上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一种实施方式的阵列基板的结构示意图。
图2是本公开一种实施方式的显示面板的结构示意图。
图3是本公开一种实施方式的形成柔性基底层的结构示意图。
图4是本公开一种实施方式的形成驱动电路层和绑定引线层的结构示意 图。
图5是本公开一种实施方式的形成平坦化层的结构示意图。
图6是本公开一种实施方式的形成像素电极层的结构示意图。
图7是本公开一种实施方式的形成刚性基板的结构示意图。
图8是本公开一种实施方式的阵列基板的结构示意图。
图9是本公开一种实施方式的显示面板的结构示意图。
图10是本公开一种实施方式的形成缓冲层的结构示意图。
图11是本公开一种实施方式的形成驱动电路层的结构示意图。
图12是本公开一种实施方式的形成柔性基底层的结构示意图。
图13是本公开一种实施方式的形成像素电极层和绑定引线层的结构示意图。
图14是本公开一种实施方式的形成刚性基板的结构示意图。
图15是本公开一种实施方式的绑定引线层的俯视结构示意图。
图16是本公开一种实施方式的阵列基板的结构示意图。
图17是本公开一种实施方式的显示面板的结构示意图。
图18是本公开一种实施方式的第一基板的结构示意图。
图19是本公开一种实施方式的形成像素电极层和绑定引线层的结构示意图。
图20是本公开一种实施方式的去除衬底基板的结构示意图。
图21是本公开一种实施方式的第二基板的结构示意图。
图22是本公开一种实施方式的第一基板和第二基板对盒的结构示意图。
图23是本公开一种实施方式的阵列基板的制备方法的流程示意图。
图24是本公开一种实施方式的阵列基板的制备方法的流程示意图。
图25是本公开再一实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以采用设置有驱动电路的玻璃基板来驱动Micro LED发光，以实现Micro LED屏幕的高分辨率。然而，玻璃基板设置有驱动电路后难以开设玻璃通孔，导致玻璃基板无法通过弯折降低其边框。这导致Micro LED屏幕拼接的大尺寸显示屏幕中的拼缝大，降低了显示效果。
本公开至少一实施方式中提供一种阵列基板，该阵列基板用于制备显示面板。如图1、图8和图16所示，该阵列基板包括绑定区A和非绑定区B，还包括刚性基板100、驱动电路层200、发光二极管层300、柔性基底层400和绑定引线层500。
刚性基板100设于非绑定区B；驱动电路层200设于刚性基板100的一侧，例如包括多个驱动电路；发光二极管层300设于驱动电路层200远离刚性基板100的一侧；柔性基底层400设于绑定区A且与驱动电路层200位于刚性基板100的同一侧；绑定引线层500设于柔性基底层400远离刚性基板100的一侧，且绑定引线层500与驱动电路层200中的至少一个驱动电路电连接。
如图2、图9和图17所示，绑定引线层500和柔性基底层400能够沿刚性基板100的边缘弯折至刚性基板100远离驱动电路层200的一侧，且在该侧例如至少部分在平行于刚性基板100的板面的平面内延伸，由此与非绑定区B在垂直于刚性基板100的板面的方向上彼此重叠。该侧为显示面板的非显示侧。
本公开实施例的阵列基板中，在绑定区A没有设置刚性基板100，因此 绑定引线层500可以弯折至刚性基板100远离驱动电路层200的一侧(阵列基板的背光面)，与电路板900连接(即电路板900绑定在绑定区A中)，避免了将电路板900连接于刚性基板100靠近驱动电路层200的一侧(阵列基板的出光面)，可以有效地减小应用该阵列基板的显示面板的边框，且可以减小由显示面板拼接的显示装置的拼缝，提高显示效果。
下面结合附图对本公开多个实施方式提供的阵列基板的各部件进行详细说明。
刚性基板100设于非绑定区B，用于支撑驱动电路层200等结构。在一实施方式中，刚性基板100的材料可以为玻璃、亚克力或者其他材料，本公开的对此不作限制。
如图1、图8和图16所示，驱动电路层200设于刚性基板100的一侧。驱动电路层200中设置有用于驱动发光二极管320发光的驱动电路。例如，驱动电路包括至少一种电子元件220。该电子元件220包括但不限于晶体管、电容、电阻、线圈等。可以理解的是，驱动电路层200中还设置有连接电子元件220的信号引线230以及转接电极210。在一实施方式中，驱动电路中设置有薄膜晶体管。
在至少一个实施例中，非绑定区B包括像素阵列，例如，该非绑定区B包括显示区，该显示区包括该像素阵列。该像素阵列包括排列为多行多列的多个像素单元，每个像素单元包括像素电路和发光元件。该非绑定区B还可以进一步包括多条栅线、多条数据线等多种信号引线，分别与像素阵列中对应的像素单元连接，以为像素阵列中的多个像素单元提供扫描信号和数据信号等。该像素电路配置为根据接收的扫描信号和数据信号等，以驱动对应像素单元中的发光元件发光。根据需要，该像素单路可以包括多个开关元件(例如薄膜晶体管)和电容，位于驱动电路层200中，也即，驱动电路层200包括该多个像素单元的像素电路；此外，驱动电路层200还包括前述多种信号引线。
例如，该像素电路可以为2T1C像素电路，即包括两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动发光元件发光，该两个TFT中的一个为驱动晶体管，而另一个为数据写入晶体管。又例如，在上述2T1C的像素电路的基础上，像素电路还可以具有补偿功能，补偿功能可 以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等，这里不再详述。
该驱动电路层为多层叠层结构，例如包括一个或多个导电层、一个或多个绝缘层、一个或多个半导体层，相邻的导电层与导电层之间或者相邻的导电层与半导体层之间可以通过形成于中间绝缘层中的过孔彼此电连接。该一个或多个导电层用于形成薄膜晶体管中栅极和源漏极，形成存储电容的电极，以及用于形成各种信号引线等，例如，栅线可以与薄膜晶体管的栅极同层设置，数据线与薄膜晶体管的源漏极同层设置。转接电极与对应的像素电路电连接，以便于实现像素电路例如与发光二极管的电连接。该一个或多个绝缘层可以为无机绝缘层或有机绝缘层，可以仅位于非绑定区中，也可以同时位于绑定区和非绑定区。例如，该发光元件可以为发光二极管。
如图1、图8和图16所示，发光二极管层300设于驱动电路层200远离刚性基板100的一侧，其可以包括与驱动电路层200(对应的像素单元的像素电路)电连接的像素电极层310和与像素电极层310连接的发光二极管320。可以理解的是，像素电极层310中可以设置有像素电极且像素电极与驱动电路电连接。例如，每个像素单元包括对应的像素电极，该像素电极与该像素单元的像素电路电连接且与该像素单元的发光二极管电连接，由此使得该像素电路可以驱动该发光二极管。例如，该阵列基板还包括像素定义层，该像素定义层包括对应于多个像素单元的像素开口，例如至少部分覆盖多个像素电极，且使得多个像素开口分别至少部分暴露多个像素电极，多个发光二极管分别通过该多个像素开口分别电连接到多个像素电极。
例如，发光二极管320可以为微型发光二极管(Micro LED)、纳米发光二极管(Nano LED)或者其他类型的发光二极管，例如有机发光二极管(OLED)或量子点发光二极管(QLED)等，本公开对此不做限定。在一实施方式中，发光二极管层300包括阵列设置的微型发光二极管320，对应于像素阵列中的多个像素单元。
如图15所示，绑定引线层500可以包括多个绑定引线510(bonding line)以及多个绑定端520(bonding pad)。多个绑定引线510与驱动电路层200中的多个信号引线230一一对应连接，多个绑定端520一一对应地连接于多个绑定引线510远离驱动电路的一端。
一方面，为了将各个绑定引线510连接至各自对应的绑定端520，因此绑定引线层500需要具有一定的宽度。若绑定引线层500不能向刚性基板100的背面(远离驱动电路层200的一侧)弯折，则该绑定引线层500将完全呈现在应用该阵列基板的显示面板的出光面，会导致显示面板出现边框较大的问题。
本公开实施例的阵列基板中，绑定引线层500可以向刚性基板100的背面弯折，减小了绑定引线层500暴露于显示面板的发光面的面积，进而减小了显示面板的边框。
另一方面，绑定端520用于与绑定电路元件电连接，该绑定电路元件例如通过导电胶的方式绑定于该绑定区中，例如该绑定电路元件为电路板900。若绑定引线层500不能向刚性基板100的背光面弯折，则电路板900需要连接于显示面板的出光面而增加显示面板的边框；即便电路板900为柔性电路板900，该柔性电路板900依然会增加显示面板的边框。本公开实施例的阵列基板中，绑定引线层500可以向刚性基板100的背面弯折，如此阵列基板在背光面与电路板900绑定，避免了在刚性基板100的侧面设置电路板900而增加显示面板的边框。在本公开的实施例中，绑定电路元件还可以为集成电路芯片(例如驱动芯片)等，本公开对此不作限制。
柔性基底层400可以采用树脂等柔性材料，例如可以采用聚酰亚胺(PI)材料。柔性基底层400用于承载和固定绑定引线层500，避免绑定引线层500在弯折时受到损伤。
在一实施方式中，如图1所示，柔性基底层400可以延伸至非绑定区B，且位于刚性基板100与驱动电路层200之间。如此，该柔性基底层400可以作为驱动电路层200与刚性基板100之间的缓冲层。
如此，驱动电路层200和绑定引线层500设于柔性基底层400的同一侧，且驱动电路层200和绑定引线层500电连接。可选的，相互连接的绑定引线510和信号引线230为同一引线的不同部分。可选的，可以在柔性基底层400远离刚性基板100的一侧设置多个信号引线，其中，信号引线位于绑定区A的部分为绑定引线510，信号引线位于非绑定区B的部分为信号引线230。
可选的，如图1所示，阵列基板还可以包括平坦化层610，平坦化层610设于驱动电路层200与发光二极管层300之间，且平坦化层610延伸至绑定 引线层500远离刚性基板100的一侧。绑定引线层500和驱动电路层200设于平坦化层610的同一侧。
可选的，如图1所示，平坦化层610上可以设置有第一导电过孔710，发光二极管层300可以通过第一导电过孔710与驱动电路层200电连接，例如，对于每个像素单元，位于发光二极管层300的发光二极管可以通过第一导电过孔710、转接电极210与位于驱动电路层200中的像素电路电连接。
可选的，在绑定区A，绑定引线层500与柔性基底层400之间还可以设置有绝缘材料层，绝缘材料层的材料可以包括驱动电路层200中所使用的绝缘材料中的一种或者多种。如此，在制备驱动电路层200时沉积于绑定区A的绝缘材料无需完全清除，简化了阵列基板的制备。
在另一实施方式中，如图8所示，柔性基底层400可以延伸至非绑定区B，且位于驱动电路层200与发光二极管层300之间。如此，绑定引线层500和发光二极管层300可以设置于柔性基底层400的同一侧。该柔性基底层400还可以发挥对驱动电路层200远离刚性基板100的表面进行平坦化的作用，以便进一步形成发光二极管层300。由于驱动电路层200设置于柔性基底层400远离绑定引线层500的一侧，因此柔性基底层400和绑定引线层500之间不会夹杂有驱动电路层200的残留材料，柔性基底层400和绑定引线层500的厚度更小，更容易进行弯折，可以进一步降低显示面板的边框，且降低柔性基底层400和绑定引线层500的弯折应力。
可选的，绑定引线层500中的绑定引线510和发光二极管层300中(位于像素单元内)的像素电极可以采用同一导电材料且具有同一厚度，以便通过同一导电材料膜层同时制备出绑定引线510和像素电极。在一实施方式中，绑定引线510和像素电极的材料为铜，用以提高发光二极管的驱动电流。
可选的，如图8所示，柔性基底层400上可以设置有第一导电过孔710和第二导电过孔720，发光二极管层300通过第一导电过孔710与驱动电路层200电连接，例如，对于每个像素单元，位于发光二极管层300的发光二极管可以通过第一导电过孔710与位于驱动电路层200中的像素电路电连接；绑定引线层500通过第二导电过孔720与驱动电路层200电连接，例如，对于每个像素单元，位于绑定引线层500的绑定引线510可以通过第二导电过孔720与位于驱动电路层200中对应的信号引线电连接。
在另一实施方式中，如图16所示，柔性基底层400可以延伸至非绑定区B，且位于驱动电路层200与发光二极管层300之间。阵列基板还包括导电胶层630，导电胶层630设于驱动电路层200与柔性基底层400之间。
如此，如图18所示，绑定引线层500和发光二极管层300设置于柔性基底层400的同一侧，绑定引线层500、发光二极管层300和柔性基底层400可以作为覆盖绑定区A和非绑定区B的第一基板810。如图21所示，驱动电路层200和刚性基板100可以作为位于非绑定区B的第二基板820；第一基板810和第二基板820可以通过对盒的方式，通过导电胶层630粘接而形成本公开实施例的阵列基板。
可选的，如图16所示，柔性基底层400上设置有第一导电过孔710和第二导电过孔720，发光二极管层300通过第一导电过孔710及导电胶层630与驱动电路层200电连接，绑定引线层500通过第二导电过孔720及导电胶层630与驱动电路层200电连接。可以理解的是，如图16所示，第一导电过孔710和第二导电过孔720位于非绑定区B。
可选的，如图18所示，为了保证第一导电过孔710和第二导电过孔720与导电胶层630有效电连接，柔性基底层400靠近驱动电路层200的一侧还可以包括第一连接电极711和第二连接电极721；其中，第一连接电极711与第一导电过孔710电连接，第二连接电极721与第二导电过孔720电连接。
可选的，导电胶层630可以选用异方性导电胶膜(Anisotropic Conductive Film，ACF)，以保证绑定引线层500和发光二极管层300之间的信号不会相互串扰，并简化导电胶层630的设置方法。例如，该导电胶层630可以包括粘性基体材料以及分散在该粘性基体材料中的多个导电颗粒，当该导电胶层被按压时，可以在被按压的位置形成导电路径。例如，该粘性基体材料为热塑性树脂或热固性树脂，导电颗粒可以为金属颗粒或石墨颗粒。
本公开至少一实施例还提供一种阵列基板的制备方法，如图23所示，该阵列基板的制备方法可以包括如下步骤S110-S170：
步骤S110，提供一刚性基板材料层101，刚性基板材料层101包括绑定区A和非绑定区B；
步骤S120，如图4和图11所示，形成驱动电路层200，驱动电路层200设于刚性基板材料层101的一侧且位于非绑定区B；
步骤S130，如图6和图13所示，形成像素电极层310，像素电极层310设于驱动电路层200远离刚性基板材料层101的一侧；
步骤S140，如图3和图12所示，形成设于绑定区A的柔性基底层400，柔性基底层400与驱动电路层200设于刚性基板材料层101的同一侧；
步骤S150，如图4和图13所示，形成绑定引线层500，绑定引线层500设于柔性基底层400远离刚性基板材料层101的一侧，且与驱动电路层200电连接；
步骤S160，如图7和图14所示，去除刚性基板材料层101位于绑定区A的部分，使得刚性基板材料层101的剩余部分形成刚性基板100，且使得绑定引线层500和柔性基底层400能够沿刚性基板100的边缘弯折至刚性基板100远离驱动电路层200的一侧；
步骤S170，如图1和图8所示，在像素电极层310远离刚性基板100的表面设置发光二极管320，使得像素电极层310形成发光二极管层300。
通过本公开实施例的阵列基板的制备方法所制备的阵列基板，如图1和图8所示，在绑定区A没有设置刚性基板100，因此绑定引线层500可以弯折至刚性基板100远离驱动电路层200的一侧(阵列基板的背光面)以便与电路板900连接，避免了将电路板900连接于刚性基板100靠近驱动电路层200的一侧(阵列基板的出光面)，可以有效地减小应用该阵列基板的显示面板的边框，且可以减小由显示面板拼接的显示装置的拼缝，提高显示效果。
下面结合附图对本公开实施方式提供的阵列基板的制备方法的各步骤的示例进行详细说明：
在步骤S110中，刚性基板材料层101的材料可以为玻璃、亚克力或者其他材料。
在步骤S120中，如图4和图11所示，驱动电路层200中设置有用于驱动发光二极管320发光的驱动电路，例如，驱动电路包括至少一种电子元件220。该电子元件220包括但不限于晶体管、电容、电阻、线圈等。可以理解的是，驱动电路层200中还设置有连接电子元件220的信号引线230以及转接电极210。在一实施方式中，驱动电路中设置有薄膜晶体管。例如，驱动电路层200包括多个像素单元的像素电路，此外驱动电路层200还包括多种信号引线，该多种信号引线分别与对应的像素电路电连接以提供扫描信号、 数据信号、电源电压等。
驱动电路层200位于非绑定区B，表明驱动电路层200在刚性基板材料层101上的正投影与非绑定区B重合。
在步骤S130中，如图6和图13所示，像素电极层310与驱动电路层200电连接。像素电极层310中可以设置有像素电极且像素电极通过转接电极210与驱动电路层中对应的像素电路电连接。如图1和图8所示，当在步骤S170中设置发光二极管320时，发光二极管320可以与像素电极一一对应连接，使得像素电极层310和发光二极管320共同形成发光二极管层300。
在步骤S140中，柔性基底层400可以采用树脂等柔性材料，例如可以采用聚酰亚胺材料。柔性基底层400用于承载和固定绑定引线层500，避免绑定引线层500在弯折时受到损伤。
在步骤S150中，绑定引线层500可以包括多个绑定引线510(bonding line)以及多个绑定端520(bonding pad)。多个绑定引线510与驱动电路层200中的多个信号引线230一一对应连接，多个绑定端520一一对应地连接于多个绑定引线510远离驱动电路的一端，与多个绑定引线510电连接的信号引线230包括但不限于栅线、数据线、电源线等，本公开对此不作限制。一方面，为了将各个绑定引线510连接至各自对应的绑定端520，因此绑定引线层500需要具有一定的宽度。若绑定引线层500不能向刚性基板100的背面(远离驱动电路层200的一侧)弯折，则该绑定引线层500将完全呈现在显示面板的出光面，会导致显示面板出现边框较大的问题。
本公开实施例的制备方法所制备的阵列基板中，绑定引线层500可以向刚性基板100的背面弯折，减小了绑定引线层500暴露于显示面板的发光面的面积，进而减小了显示面板的边框。
另一方面，绑定端520用于与电路板900连接，若绑定引线层500不能向刚性基板100的背光面弯折，则电路板900需要连接于显示面板的出光面而增加显示面板的边框；即便电路板900为柔性电路板900，该柔性电路板900依然会增加显示面板的边框。
本公开实施例的制备方法所制备的阵列基板中，绑定引线层500可以向刚性基板100的背面弯折，如此阵列基板在背光面与电路板900绑定，避免了电路板900增加显示面板的边框。
在步骤S160中，可以先通过激光剥离技术(LLO；Laser Lift Off)使得刚性基板材料层101位于绑定区A的部分与包括柔性基底层在内的其他的膜层结构分离；然后再通过切割的方法去除刚性基板材料层101位于绑定区A的部分。
在步骤S170中，发光二极管320可以为微型发光二极管、纳米发光二极管或者其他类型的发光二极管，本公开对此不做特殊的限定。
可以理解的是，在制备阵列基板后，如图2和图9所示，还可以在绑定端520连接电路板900，然后通过绑定引线层500和柔性基底层400将电路板900弯折并固定至刚性基板100的背面(远离驱动电路层200的一侧)，进而获得基于该阵列基板的显示面板。该电路板900可以为柔性电路板900或者刚性电路板900，本公开对此不做特殊的限制。
例如，电路板900上设置有驱动芯片，该驱动芯片包括但不限于数据驱动器、栅极驱动器、时序控制器等，本公开对此不作限制。该显示面板具有窄边框的特性。例如，基于该窄边框的显示面板，可以拼接出具有较小拼接缝的显示装置。
在一实施方式中，如图3和图4所示，步骤S140可以在步骤S120之前执行。可选的，如图3所示，在执行步骤S140时，可以在刚性基板材料层101的一侧形成一覆盖绑定区A和非绑定区B的柔性基底层400；如图4所示，在步骤S120中，驱动电路层200可以形成于柔性基底层400远离刚性基板材料层101的一侧。如此，所制备的阵列基板中，柔性基底层400可以延伸至非绑定区B，且位于刚性基板100与驱动电路层200之间。如此，该柔性基底层400可以作为驱动电路层200与刚性基板100之间的缓冲层。
如图4和图6所示，步骤S150可以在步骤S130之前执行。可选的，如图4所示，在执行步骤S120的同时，执行步骤S150，即同时形成绑定引线层500和驱动电路层200。可选的，在执行步骤S120和步骤S150时，可以形成同时设置于绑定区A和非绑定区B的信号引线，其中，信号引线位于绑定区A的部分为绑定引线510，信号引线位于非绑定区B的部分为信号引线230。例如，绑定引线510和对应的信号引线230可以在同一工序中形成，简化了阵列基板的制备方法。
可选的，如图4所示，在同时执行步骤S120和步骤S150时，用于形成 驱动电路层200的绝缘材料等可以残留在绑定区A，则所制备的阵列基板中，绑定引线层500中可以有绝缘材料。
可选的，如图5所示，在执行步骤S130之前还可以执行步骤S180：在驱动电路层200远离刚性基板材料层101的一侧形成平坦化层610，以便为形成像素电极层310提供平坦表面。可以理解的是，平坦化层610上可以设置有第一过孔712，第一过孔712用于在步骤S130中金属化而成为第一导电过孔710，第一过孔712暴露转接电极210，以便通过转接电极210电连接驱动电路层200和像素电极层310中对应的像素电路与像素电极。
可选的，如图5所示，在步骤S180中，平坦化层610还可以设置于绑定引线层500远离刚性基板材料层101的一侧，以保护绑定引线层500。进一步地，平坦化层610可以暴露绑定引线层500的绑定端520，以便绑定端520与电路板900连接。
在另一实施方式中，如图11所示，在步骤S120中，在形成驱动电路层200时，沉积于刚性基板材料层101的绑定区A部分的绝缘材料等可以部分或者全部保留，作为支撑层201；如此，在步骤S120中，刚性基板材料层101的绑定区A部分可以形成支撑层201。
如图12和图13所示，步骤S140可以在步骤S120和步骤S130之间执行。可选的，如图12所示，在执行步骤S140时，可以在支撑层201和驱动电路层200远离刚性基板材料层101的一侧形成一覆盖绑定区A和非绑定区B的柔性基底层400。如图13所示，在步骤S130中，像素电极层310可以形成于柔性基底层400远离刚性基板材料层101的一侧；如图13所示，在步骤S150中，绑定引线层500可以形成于柔性基底层400远离刚性基板材料层101的一侧。如此，所制备的阵列基板中，柔性基底层400可以延伸至非绑定区B，且位于像素电极层310与驱动电路层200之间。如此，该柔性基底层400可以作为驱动电路层200与像素电极层310之间的平坦化层。
可以理解的是，如图12所示，柔性基底层400上可以设置有第一过孔712和第二过孔722。第一过孔712用于在步骤S130中金属化而成为第一导电过孔710，以便电连接驱动电路层200和像素电极层310。第二过孔722用于在步骤S150中金属化而成为第二导电过孔720，该第二导电过孔720暴露对应的信号引线230，以便通过该第二导电过孔720电连接驱动电路层200 和绑定引线层500中彼此对应的信号引线230和绑定引线510。
本实施方式对步骤S150和步骤S130的执行步骤不做特殊的限定，举例而言，可以先执行步骤S150，再执行步骤S130。可选的，在执行步骤S130的同时，执行步骤S150，即同时形成绑定引线层500和像素电极层310。
可选的，在执行步骤S130和步骤S150时，可以形成同时设置于绑定区A和非绑定区B的导电材料膜层，且导电材料膜层使得第一过孔712和第二过孔722分别转变为第一导电过孔710和第二导电过孔720；然后对导电材料膜层进行图案化，进而获得位于绑定区A的绑定引线510和位于非绑定区B的像素电极。可选的，导电材料膜层的材料可以为铜或铜合金，用以提高发光二极管的驱动电流。
可选的，如图10所示，在执行步骤S120之前还可以执行步骤S190：在刚性基板材料层101的一侧形成缓冲层620。例如，该缓冲层620例如可以为柔性层，例如为另一柔性基底，例如可以采用聚酰亚胺材料等制备。缓冲层620可以覆盖绑定区A和非绑定区B，以避免增加对缓冲层620进行图感化的工序，简化本公开实施例的阵列基板的制备方法。在步骤S120中，如图11所示，驱动电路层200可以形成于缓冲层620远离刚性基板材料层101的一侧。当然地，在其他实施方式中，缓冲层620也可以仅覆盖非绑定区B。
可选的，在步骤S160中，如图14所示，还可以去除缓冲层620位于绑定区A的部分和支撑层201，如此可以降低阵列基板在绑定区A的厚度，降低绑定区A弯折时的应力。进一步地，可以通过激光熔覆的方法去除缓冲层620位于绑定区A的部分和支撑层201。
本公开的实施例还提供另一种阵列基板的制备方法，如图24所示，阵列基板的制备方法可以包括：
步骤S210，如图18所示，提供第一基板810，第一基板810包括柔性基底层400、绑定引线层500和像素电极层310；其中，柔性基底层400包括绑定区A和非绑定区B；像素电极层310与绑定引线层500设于柔性基底层400的同一侧，且绑定引线层500位于绑定区A，像素电极层310位于非绑定区B；柔性基底层400的非绑定区B设置有与绑定引线层500电连接的第二导电过孔720；
步骤S220，如图21所示，提供第二基板820，第二基板820包括层叠 设置的刚性基板100和驱动电路层200；且使得当第二基板820与第一基板810对盒时，第二基板820在第一基板810上的正投影能够与非绑定区B重合；
步骤S230，如图22所示，第一基板810和第二基板820对盒，使得驱动电路层200远离刚性基板100的表面与柔性基底层400的非绑定区B远离像素电极层310的表面通过导电胶层630连接；
步骤S240，如图16所示，在像素电极层310远离刚性基板100的表面设置发光二极管320，使得像素电极层310形成发光二极管层300。
通过本公开实施例的阵列基板的制备方法所制备的阵列基板，如图16和图17所示，在绑定区A没有设置刚性基板100，因此绑定引线层500可以弯折至刚性基板100远离驱动电路层200的一侧(阵列基板的背光面)以便与电路板900连接，避免了将电路板900连接于刚性基板100靠近驱动电路层200的一侧(阵列基板的出光面)，可以有效地减小应用该阵列基板的显示面板的边框，且可以减小由显示面板拼接的显示装置的拼缝，提高显示效果。
下面结合附图对本公开实施方式提供的阵列基板的制备方法的各步骤进行详细说明：
在一实施方式中，在步骤S210中，可以通过如下方法提供第一基板810：
步骤310，提供一衬底基板811；
步骤320，在衬底基板811的一侧形成柔性基底层400，柔性基底层400包括绑定区A和非绑定区B；
步骤330，如图19所示，形成绑定引线层500，绑定引线层500设于柔性基底层400远离衬底基板811的一侧，且位于绑定区A；
步骤340，如图19所示，形成像素电极层310，像素电极层310设于柔性基底层400远离衬底基板811的一侧，且位于非绑定区B；
步骤350，如图20所示，去除衬底基板811；
步骤360，如图18所示，在柔性基底层400的非绑定区B形成第二导电过孔720，第二导电过孔720电连接绑定引线层500。
可选的，在步骤360中，如图18所示，还可以在柔性基底层400的非绑定区B形成第二导电过孔720，第二导电过孔720电连接像素电极层310。
可选的，在步骤360中，如图18所示，还可以在柔性基底层400远离像素电极层310的一侧形成第一连接电极711和第二连接电极721。其中，第一连接电极711与第一导电过孔710连接，用于保证第一导电过孔710能够与导电胶层630充分电连接；第二连接电极721与第二导电过孔720连接，用于保证第二导电过孔720能够与导电胶层630充分电连接。
可选的，如图19所示，可以同时执行步骤330和步骤340，即同时形成绑定引线层500和像素电极层310。
可以理解的是，按照本公开实施例的阵列基板的制备方法所制备的阵列基板中，柔性基底层400延伸至非绑定区B中且位于驱动电路层200和发光二极管层300之间，可以作为阵列基板的平坦化层610。
在步骤S220中，所提供的第二基板820应当满足如下要求，即当第二基板820与第一基板810对盒时，第二基板820在第一基板810上的正投影能够与非绑定区B重合。换言之，当第二基板820与第一基板810对盒时，第二基板820能够暴露第一基板810的绑定区A。
可选的，如图21所示，第二基板820还可以包括缓冲层620，缓冲层620设置于刚性基板100和驱动电路层200之间。
在步骤S230中，可以先在第二基板820或者第一基板810的非绑定区B上设置导电胶层630，然后将第二基板820与第一基板810的非绑定区B对准并粘接。可以理解的是，如图22所示，第二基板820与第一基板810的非绑定区B对准，指的是使得第二基板820在第一基板810上的正投影能够与非绑定区B重合。当第二基板820与第一基板810的非绑定区B对准时，驱动电路层200远离刚性基板100的表面朝向柔性基底层400的非绑定区B远离像素电极层310的表面，且导电胶层630设置于这两个表面之一。
可选的，导电胶层630可以选用异方性导电胶膜。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
本公开实施方式还提供一种显示面板，该显示面板包括上述阵列基板实 施方式所描述的任意一种阵列基板。
可选的，参见图2、图9和图17，该显示面板还包括电路板900，且电路板900上设置有驱动芯片。阵列基板的绑定区A沿刚性基板100的边缘弯折至刚性基板100远离驱动电路层200的一侧，且电路板900与绑定引线层500电连接且位于刚性基板100远离驱动电路层200的一侧。
本公开实施方式的显示面板采用的阵列基板与上述阵列基板的实施方式中的阵列基板相同，因此，具有相同的有益效果，在此不再赘述。如本领域技术人员所理解的，除了上述阵列基板的结构之外，本公开实施例的显示面板或阵列基板还可以包括其他必要的封装元件和功能电路，例如还可以包括触控电路或指纹识别电路等以进一步包括触控、指纹识别功能。
本公开还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的显示面板。如图25所示，该显示装置1包括上述任意一项所述的显示面板10。
例如，该显示装置可以为电子广告屏、舞台背景屏幕、电视机或者其他类型的显示装置，本公开对此不做特殊的限定。
本公开实施方式的显示装置采用的显示面板与上述显示面板的实施方式中的显示面板相同，因此，具有相同的有益效果，在此不再赘述。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种阵列基板，包括绑定区和非绑定区，其中，所述阵列基板还包括：
    刚性基板，设于所述非绑定区；
    驱动电路层，设于所述刚性基板的一侧且位于所述非绑定区；
    发光二极管层，设于所述驱动电路层远离所述刚性基板的一侧，且与所述驱动电路层电连接；
    柔性基底层，设于所述绑定区且与所述驱动电路层位于所述刚性基板的同一侧；
    绑定引线层，设于所述柔性基底层远离所述刚性基板的一侧，且所述绑定引线层与所述驱动电路层电连接；
    其中，所述绑定引线层和所述柔性基底层能够沿所述刚性基板的边缘弯折至所述刚性基板远离所述驱动电路层的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述柔性基底层延伸至所述非绑定区，且位于所述刚性基板与所述驱动电路层之间。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    平坦化层，设于所述驱动电路层与所述发光二极管层之间，其中，所述平坦化层延伸至所述绑定引线层远离所述刚性基板的一侧。
  4. 根据权利要求1所述的阵列基板，其中，所述柔性基底层延伸至所述非绑定区，且位于所述驱动电路层与所述发光二极管层之间。
  5. 根据权利要求4所述的阵列基板，其中，所述柔性基底层设置有与所述绑定引线层电连接的导电过孔；
    所述阵列基板还包括：
    导电胶层，设于所述驱动电路层与所述柔性基底层之间，其中，所述绑定引线层通过所述导电过孔和所述导电胶层与所述驱动电路层电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述柔性基底层还包括：
    连接电极，设于所述柔性基底层远离所述发光二极管层的一侧，且通过所述导电过孔与所述绑定引线层电连接。
  7. 根据权利要求4所述的阵列基板，还包括：
    缓冲层，位于所述刚性基板与所述驱动电路层之间。
  8. 根据权利要求7所述的阵列基板，其中，所述缓冲层为柔性层。
  9. 根据权利要求1-8任一所述的阵列基板，其中，所述发光二极管层包括像素电极层以及设置中所述像素电极层上的一个或多个发光二极管。
  10. 根据权利要求9所述的阵列基板，其中，所述多个发光二极管包括阵列设置的微型发光二极管。
  11. 根据权利要求1-10任一所述的阵列基板，其中，所述绑定引线层包括多个绑定引线以及多个绑定端，
    所述多个绑定引线与所述驱动电路层电连接，所述多个绑定端一一对应地电连接于所述多个绑定引线远离所述驱动电路层的一端。
  12. 根据权利要求11所述的阵列基板，还包括：
    绑定电路元件，所述电路元件设置于所述绑定区，并且与所述多个绑定端电连接。
  13. 一种阵列基板的制备方法，包括：
    提供一刚性基板材料层，其中，所述刚性基板材料层包括绑定区和非绑定区；
    形成驱动电路层，其中，所述驱动电路层设于所述刚性基板材料层的一侧且位于所述非绑定区；
    形成像素电极层，其中，所述像素电极层设于所述驱动电路层远离所述刚性基板材料层的一侧；
    形成设于所述绑定区的柔性基底层，其中，所述柔性基底层与所述驱动电路层设于所述刚性基板材料层的同一侧；
    形成绑定引线层，其中，所述绑定引线层设于所述柔性基底层远离所述刚性基板材料层的一侧，且与所述驱动电路层电连接；
    去除所述刚性基板材料层位于所述绑定区的部分，使得所述刚性基板材料层的剩余部分形成刚性基板，且使得所述绑定引线层和所述柔性基底层能够沿所述刚性基板的边缘弯折至所述刚性基板远离所述驱动电路层的一侧；
    在所述像素电极层远离所述刚性基板的表面设置发光二极管，使得所述像素电极层和所述发光二极管形成发光二极管层。
  14. 根据权利要求13所述的制备方法，其中，所述柔性基底层位于所述非绑定区和所述绑定区，且位于所述刚性基板材料层与所述驱动电路层之间，
    去除所述刚性基板材料层位于所述绑定区的部分包括：
    采用剥离方法使得刚性基板材料层位于所述绑定区的部分与所述柔性基底层分离，然后再通过切割方法去除所述刚性基板材料层位于所述绑定区的部分。
  15. 根据权利要求13所述的制备方法，其中，所述柔性基底层位于所述非绑定区和所述绑定区，所述柔性基底层延伸至所述非绑定区，且位于所述驱动电路层与所述发光二极管层之间，
    所述制备方法还包括：
    在所述刚性基板材料层形成缓冲层，其中，所述驱动电路层形成于所述缓冲层远离所述刚性基板材料层一侧，并且，去除所述刚性基板材料层位于所述绑定区的部分之后，将所述缓冲层位于所述绑定区内的部分去除。
  16. 根据权利要求15所述的制备方法，其中，形成设于所述绑定区的柔性基底层包括：
    在所述柔性基底层形成与所述绑定引线层电连接的导电过孔。
  17. 根据权利要求16所述的制备方法，其中，形成设于所述绑定区的柔性基底层还包括：
    在所述柔性基底层远离所述像素电极层的一侧形成连接电极，其中，所述连接电极通过所述导电过孔与所述绑定引线层电连接。
  18. 一种阵列基板的制备方法，包括：
    提供第一基板，其中，所述第一基板包括柔性基底层、绑定引线层和像素电极层，所述柔性基底层包括绑定区和非绑定区；所述像素电极层与所述绑定引线层设于所述柔性基底层的同一侧，且所述绑定引线层位于所述绑定区，所述像素电极层位于所述非绑定区；所述柔性基底层的非绑定区设置有与所述绑定引线层电连接的导电过孔；
    提供第二基板，其中，所述第二基板包括层叠设置的刚性基板和驱动电路层；且使得当所述第二基板与所述第一基板对盒时，所述第二基板在所述第一基板上的正投影能够与所述非绑定区重合；
    将所述第一基板和所述第二基板对盒，使得所述驱动电路层远离所述刚性基板的表面与所述柔性基底层的非绑定区远离所述像素电极层的表面连接；
    在所述像素电极层远离所述刚性基板的表面设置发光二极管，使得所述像素电极层和所述发光二极管形成发光二极管层。
  19. 一种显示面板，包括权利要求1～12任一项所述的阵列基板。
  20. 一种显示装置，包括根据权利要求19所述的显示面板。
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