Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/3244—Gas supply means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
  • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
  • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
  • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
  • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
  • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
  • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
  • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

• Embodiments of the present disclosure generally relate to methods and, more specifically, to methods of forming thin film transistors.
• a thin-film transistor is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) made by depositing thin films of an active semiconductor layer, as well as the dielectric layer and metallic contacts, over a supporting substrate.
• MOSFET metal-oxide-semiconductor field-effect transistor
• a common substrate is glass, because one application of TFTs is in liquid-crystal displays (LCDs).
• TFTs have gained significant interest in display applications due to their high resolution, low power consumption, and high speed operation for LCDs and organic light- emitting diode (OLED) displays.
• TFTs are embedded within the panel of the display.
• Data line and gate line voltage signals from display modules in the display system are delivered to TFTs in pixel circuits and/or gate driver circuits in peripheral display panel areas to control display images by turning on and off the TFTs.
• Image distortion is decreased by improving the response of TFT with higher mobility and/or by reducing crosstalk between pixels.
• Most display products including LCD televisions (TVs) and monitors include TFTs in the panel.
• Many modern high-resolution and high-quality electronic visual display devices use active matrix based displays with a large amount of TFTs.
• TFT technology is its use of a separate TFT for each pixel on the display.
• Each TFT works as a switch or a source of current in pixel circuit or gate driver circuit by controlling voltage and current through data and gate signal lines for increased control of display images.
• Higher on current from high mobility TFT allows fast refresh of the display images and better image qualities by minimizing the distortion of data and gate signal voltages.
• TFTs in the art can have unacceptably low mobilities in the conducting channels.
• methods of forming TFTs may not allow for good control of channel mobilities.
• it can be difficult to modify the mobilities of channels after the channel is already deposited.
• Embodiments disclosed herein generally relate to methods of forming TFTs.
• the methods include depositing layers that modify the mobilities of the underlying channel.
• One exemplary method of forming a thin film transistor device includes forming a metal oxide layer over a first portion of a substrate, forming a gate insulating (Gl) layer over the first portion of the substrate, forming a gate electrode over the Gl layer, and etching one or more residual portions of the Gl layer.
• Forming the Gl layer includes depositing a silicon-containing layer with a high density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP).
• the HDP- CVD process has an ICP power density of about 2.3 W/cm 2 to about 5.3 W/cm 2 and an ICP frequency of about 2 MHz to about 13.56 MHz.
• Another exemplary method of forming a thin film transistor device includes forming a first metal oxide layer over a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT), forming an interfacial gate insulator (Gl) layer of the first TFT in contact with the first metal oxide layer over the first portion of the substrate, forming an underside layer over a second portion of the substrate, the second portion of the substrate corresponding to a second TFT, and the underside layer contacting a bottom surface of a second metal oxide layer of the second TFT, the forming the interfacial Gl layer and the underside layer including depositing a first silicon-containing layer over the first portion and the second portion, the first silicon- containing layer deposited with a high density plasma chemical vapor deposition (HDP- CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having, an ICP power density of about 2.3 W/cm 2 to about 5.3 W/cm 2 and an ICP power density
• Yet another exemplary method of forming a thin film transistor device includes forming a poly-silicon layer over a first portion of a substrate, the first portion of a substrate corresponding to a poly-silicon thin film transistor (TFT), depositing a first gate insulator (Gl) layer over the poly-silicon layer of the first portion and over a second portion of the substrate, the second portion of the substrate corresponding to a metal oxide (MOx) TFT, forming a first gate electrode of the poly-silicon TFT over the first Gl layer and forming a shield metal of the MOx TFT, forming a first interlayer dielectric (ILD) layer over the first Gl layer, the first gate electrode, and the shield metal, forming a metal oxide layer of the MOx TFT over the first ILD layer of the second portion of the substrate, forming a second Gl layer on the metal oxide layer, the forming the second Gl layer including depositing a silicon-containing layer with a high density plasma chemical vapor deposition (HDP-
• FIG. 1 illustrates a schematic cross-sectional view of a chamber, according to one embodiment.
• FIGs. 2A-2H illustrate schematic cross-sectional views of a TFT, according to one embodiment.
• FIG. 3 is a flow diagram of a method of forming a TFT, according to one embodiment.
• FIGs. 4A-4J illustrate schematic cross-sectional views of a two transistor structure, according to one embodiment.
• FIG. 5 is a flow diagram of a method of forming a two transistor structure, according to one embodiment.
• FIG. 6 illustrates a schematic cross-sectional view of a two transistor structure, according to one embodiment.
• FIG. 7 illustrates a schematic cross-sectional view of a two transistor structure, according to one embodiment.
• FIG. 8 illustrates a schematic cross-sectional view of a two transistor structure, according to one embodiment.
• FIGs. 9A-9N illustrate schematic cross-sectional views of a two transistor structure, according to one embodiment.
• FIG. 10 is a flow diagram of a method of forming a two transistor structure, according to one embodiment.
• FIG. 1 1 illustrates a schematic cross-sectional view of a two transistor structure, according to one embodiment.
• Embodiments disclosed herein generally relate to methods of forming TFTs.
• the methods include depositing one or more metal oxide layers and/or poly-silicon layers.
• a Gl layer is deposited over the one or more metal oxide layers and/or poly silicon layers.
• Depositing the Gl layer using HDP-CVD results in an unexpected increase in mobility of the metal oxide layer and/or poly-silicon layer deposited thereon.
• Selective placement of the Gl layer leads to control of mobility of the underlying layer, depending on whether the Gl layer is deposited by HDP-CVD or a CVD process using a CCP.
• Depositing the Gl layer allows for control of mobility of the underlying layer after the layer deposition; that is, the mobility can be enhanced after deposition, in addition to during deposition.
• Embodiments disclosed herein can be useful for, but are not limited to, forming TFTs including channels with enhanced mobility.
• the term“about” refers to a +/- 10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.
• layers or other materials are referred to as being etched. It is understood that the etching of these materials can be performed using any conventional methods used in semiconductor manufacturing, such as, but not limited to, reactive ion etching (RIE), dry etching, wet etching, plasma etching, microloading, the selective etching of any of the above, combinations of the above, and any other suitable method. It is to be understood that when a method operation is described herein as etching two or more types of materials, or two or more portions of the same material, the etching can occur simultaneously with the same etching process, or the etching can be performed in separate suboperations using different etching processes.
• RIE reactive ion etching
• an operation describing etching a metal and a dielectric includes a first etching suboperation using a first etching process that etches the metal, and the operation further includes a second etching suboperation using a second etching process that etches the dielectric.
• FIG. 1 illustrates a schematic cross-sectional view of a chamber 100, according to one embodiment.
• Suitable chambers may be obtained from Applied Materials, Inc. located in Santa Clara, Calif. It is to be understood that the system described below is an exemplary chamber and other chambers, including chambers from other manufacturers, may be used with or modified to accomplish aspects of the present disclosure.
• the chamber 100 is configured to generate an HDP.
• the chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108.
• the lid assembly 106 is disposed at an upper end of the chamber body 104.
• the substrate support assembly 108 is at least partially disposed within an interior volume of the chamber body 104.
• the substrate support assembly 108 includes a substrate support 1 10 and a shaft 1 12.
• the substrate support 1 10 has a support surface 1 14 for supporting at least one substrate 102.
• the substrate 102 is a large area substrate, such as a substrate having a surface area of typically about 1 m 2 or greater.
• the substrate 102 is not limited to any particular size or shape.
• the term“substrate” refers to any polygonal, squared, rectangular, curved or otherwise non-circular workpiece, such as a glass or polymer substrate used in the fabrication of flat panel displays.
• the substrate 102 can include any suitable material, such as silicon based substrates, semiconductor based substrates, insulating based substrates, germanium based substrates, and, in general, one or more generic layers that would be present in a complementary metal- oxide-semiconductor (CMOS) device structure.
• CMOS complementary metal- oxide-semiconductor
• the substrate 102 can include a transparent material, such as rigid glass or flexible polyimides (PI), which can be useful if the substrate is used in LCD or OLED display applications, such as TVs, tablets, laptops, mobile phones or other displays.
• the substrate 102 can have any number of metal, semiconducting, or insulating layers thereon.
• the lid assembly 106 includes a diffuser 1 16 at the upper end of the chamber body 104.
• the diffuser 1 16 includes one or more diffuser inlets 1 18 coupleable to at least one gas source 120.
• the diffuser 1 16 provides one or more gases from the gas source 120 to a processing region 124 between the diffuser 1 16 and the substrate support 1 10.
• the one or more gases are provided to the processing region 124 through a plurality of holes (not shown) of the diffuser 1 16.
• Flow controllers 122 such as mass flow control (MFC) devices, are disposed between each of the diffuser inlets 1 18 and the gas source 120 to control flow rates of gases from the gas source 120 to the diffuser 1 16.
• a pump 126 is in fluid communication with the processing region 124. The pump 126 is operable to control the pressure within the processing region 124 and to exhaust gases and byproducts from the processing region 124.
• MFC mass flow control
• the lid assembly 106 includes at least one cavity 128 having one or more inductively coupled plasma generating components (alternatively referred to as coils) 130 formed therein.
• the coils 130 are supported by at least one dielectric plate 132.
• Each dielectric plate 132 provides a physical barrier having the structural strength to withstand structural loads created the presence of atmospheric pressure the in cavity 128 and the presence of vacuum pressure within the interior volume of the chamber body 104.
• Each coil 130 is connected to a power source 134 and to a ground 138.
• each coil 130 is connected to the power source 134 through a match box 136 having a match circuit for adjusting electrical characteristics, such as impedance, of the coil 130.
• a first capacitor 137 is electrically connected between the coils 130 and the match box 136.
• a terminal capacitor 139 is electrically connected between the coils 130 and the ground 138.
• Each of the coils 130 is configured to create an electromagnetic field that energizes the gases in the processing region 124 to create a high-density plasma (HDP).
• the electron density created in the chamber is greater than about 1 E1 1/cm 3 .
• the ion plasma density created in the chamber is greater than about 1 E1 1/cm 3 .
• an ICP power density used to create the HDP is about 5.3 W/cm 2 .
• an ICP frequency used to create the HDP is about 2 MHz to about 13.56 MHz.
• a controller 190 is coupled to the chamber 100 and configured to control aspects of the chamber 100 during processing.
• the controller 190 includes a central processing unit (CPU) 191 , memory 192, and support circuits (alternatively referred to as I/O) 193.
• the CPU 191 is one of any form of computer processors that are used in industrial settings for controlling various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor the processes (e.g., processing time and substrate position or location).
• the memory 192 is connected to the CPU 191 , and is one or more of a readily available memory, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote.
• RAM random access memory
• ROM read only memory
• floppy disk hard disk, or any other form of digital storage, local or remote.
• Software instructions and data can be coded and stored within the memory 192 for instructing the CPU 191.
• the support circuits 193 are also connected to the CPU 191 for supporting the CPU in a conventional *manner.
• the support circuits 193 include conventional cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like.
• a program (or computer instructions) readable by the controller 190 determines which tasks are performable on the substrate 102.
• the program can be software readable by the controller 190 and can include code to monitor and control, for example, the processing parameters (e.g., pressure, temperature, gas flow rate) in the chamber 100.
• FIGs. 2A-2H illustrate schematic cross-sectional views illustrating methods of forming a TFT 200, according to one embodiment.
• FIG. 3 is a flow diagram of a method 300 of forming the TFT 200, according to the same embodiment.
• FIGs. 2A-2H, 3, 8, and 1 1 will be described with reference to the chamber 100 of FIG. 1.
• ICP-CVD chambers other than the chamber 100 may be utilized in conjunction with method 300.
• the method 300 can be stored or accessible to the controller 190 as computer readable media containing instructions, that when executed by the CPU 191 , cause the chamber 100 to perform the method 300.
• the TFT 200 is formed over the substrate 102 (FIG. 2A).
• the method 300 begins at operation 310, where a metal oxide layer 204 is formed, as shown in FIG. 2B.
• the metal oxide layer 204 is formed by any conventional method used in the art. In some embodiments, the metal oxide layer 204 is deposited over the substrate 102. In one embodiment, which can be combined with other embodiments described herein, the metal oxide layer 204 includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf).
• Examples of the metal oxide layer 204 include, but are not limited to, In- Ga-Zn-O, In-Zn-O, In-Ga-Sn-O, ln-Zn-Sn-0 In-Ga-Zn-Sn-O, In-Sn-O, Hf-ln-Zn-O, Ga-Zn- O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, and Al-Sn- Zn-ln-O.
• Operation 310 can include doping the metal oxide layer 204 with n-type or p- type dopants, such as boron (B) or nitrogen (N).
• the metal oxide layer 204 can have a thickness of about 30 nm to about 50 nm.
• a metal oxide layer film can be formed in a first suboperation and etched in a second suboperation to create the metal oxide layer 204. In other embodiments, the metal oxide layer 204 is deposited using selective deposition to create the metal oxide layer 204 with a desired shape.
• a Gl layer 206 is deposited, as shown in FIG. 2C.
• the Gl layer 206 is deposited over at least a portion of the metal oxide layer 204.
• the Gl layer 206 is in direct contact with the metal oxide layer 204.
• the Gl layer 206 includes insulating materials such as silicon, silicon oxide (SixOy), silicon nitride (SiN x ), other insulating materials, or combinations thereof.
• the Gl layer 206 can have a thickness from about 200 A to about 8000 A.
• Operation 340 is performed using high density plasma-chemical vapor deposition (HDP-CVD).
• Operation 340 includes flowing a gas including nitrous oxide (N2O) at a flow rate of about 0.40 sccm/cm 2 to about 0.60 sccm/cm 2 and silane (SiFU) at a flow rate of about 0.01 sccm/cm 2 to about 0.01 sccm/cm 2 , the ratio of N2O to SiFU of about 5 to about 40, the chamber pressure at a pressure of about 75 mTorr to about 150 mTorr, at a chamber temperature of about 70 °C to about 350 °C, at a substrate temperature of about 80° C to about 160 °C, for a period of about 20 s to about 900 s.
• N2O nitrous oxide
• SiFU silane
• Operation 340 is performed using HDP-CVD, with an ICP power density of about 2 W/cm 2 to about 6 W/cm 2 , such as about 2.3 W/cm 2 to about 5.3 W/cm 2 , with an ICP frequency of about 1 MHz to about 15 MHz, such as about 2 MHz to about 13.56 MHz, with an applied bias power of about 0 W to about 200 W, with an ICP power of about 4000 W to about 10000 W.
• silicon tetraflouride (S1F4), dislane (S12H6), oxygen gas (O2), ozone (O3), Ar, nitrogen gas (N2), ammonia (NH3), He, or a mixture of the above are coflowed. Spacing between the substrate and the gas source can be from about 7000 mm to about 8000 mm.
• the Gl layer 206 can be deposited at a rate of about 700 A/min to about 1500 A/min.
• the refractive index of the Gl layer can be from about 1.8 to about 2.0.
• the percentage of silicon-hydrogen (Si-H) bonds can be from about 0.1 % to about 12%.
• the percentage of silicon-nitrogen (Si-N) bonds can be from about 10% to about 25%.
• the peak position of silicon-oxygen bonds (Si-O) measured in spectroscopy can be from about 1050 1/cm to about 1 100 1/cm.
• the stress of the Gl layer 206 is from about -450 MPa to about 700 MPa.
• Exemplary process variables for operation 340, where the Gl layer 206 includes SixN y are given in Table 1.
• Exemplary process variables for operation 340, where the Gl layer 206 includes SixOy are given in Table 2.
• Table 1 Exemplary process variables for operation 340 for a Gl layer including SixNy. A blank cell indicates that the variable is not applicable.
• Table 2 Exemplary process variables for operation 340 for a Gl layer including SixOy. A blank cell indicates that the variable is not applicable.
• a capacitively-coupled plasma chemical vapor deposition (CCP-CVD) process opposed electrodes, such as parallel plate electrodes, are provided, and one of the electrodes is coupled to ground while the other is coupled to a power source, and a gas is introduced therebetween to form in effect a capacitor.
• a power source By powering the powered electrode, electrically, electrical energy is capacitively coupled into the gas to form a plasma thereof.
• the ion density of the plasma is a function of the power transferred into the gas.
• a coil surrounds or is over the gas region in which the plasma is to be formed, and electrical energy flowing through the coil is electromagnetically coupled into the gas, to ionize or otherwise energize the gas atoms or molecules.
• the plasma ion density is a function of the energy coupled into the gas.
• one of the electrodes is also typically the substrate support, so the power that can be coupled into the gas is limited by the potential negative effects of that power on the substrate.
• the power to ionize the gas atoms and molecules is decoupled from the circuit components holding the substrate, and higher power can be used to impart higher energy into the plasma, and thus achieve a higher ion density in the plasma without detrimentally effecting the substrate.
• an HDP can be created from the ICP source (i.e. , an HDP-CVD process).
• the mobility of the metal oxide layer 204 can be increased from under 15 cm 2 /V s to greater than about 150 cm 2 /V s, such as up to about 450 cm 2 /V s or even greater.
• the mobility of the metal oxide layer 204 at saturation can be greater than about 3000 cm 2 /V s. There is no such increase in mobility or mobility at saturation when using a CVD process using a CCP to deposit SiOx on the same metal oxide layer 204.
• the deposition of the Gl layer 206 using HDP-CVD leads to a chemical transformation of the underlying metal oxide layer 204, which results in the increased mobility.
• the interface between the metal oxide layer 204 and the Gl layer 206 may have an increased carrier density, which increases the mobility of the metal oxide layer.
• metal oxide layers 204 including indium (In) diffusion of In atoms from the metal oxide layer to the Gl layer 206 may result in increased carrier generation, and hence mobility.
• the metal oxide layer 204 may undergo a structural change that further increases the mobility, such as diffusion of atoms to heal atomic defects.
• a gate electrode 208 is formed, as shown in Fig. 2D.
• the gate electrode 208 is formed over the Gl layer 206.
• the gate electrode 208 includes molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any electrically conductive materials, such as including conductive metal oxides, such as indium tin oxide (InSnO) (ITO) and indium zinc oxide (InZnO) (IZO), or any combination thereof.
• the gate electrode 208 is deposited in a single operation. In other embodiments, material of the gate electrode 208 is deposited in a first suboperation to form a metal layer, and one or more residual portions of the metal layer are etched to make the gate electrode 208.
• the gate electrode 208 is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across layers of the TFT 200.
• one or more residual portions 206* of the Gl layer 206 are etched, as shown in FIG. 2E.
• the gate electrode 208 acts as a mask to etch the Gl layer 206 to a desired size and shape.
• the wet etch rate (WER) of the Gl layer 206 is from about 200 A/min to about 7000 A/min.
• Operation 360 can include a dry etch.
• an interlayer dielectric (ILD) layer 210 is formed, as shown in FIG. 2F.
• the ILD layer 210 is formed over the gate electrode 208 and the metal oxide layer 204.
• the ILD layer 210 includes insulating materials such as single silicon dioxide (SiOx), silicon nitride (SiN x ), multi-layer silicon nitride/silicon oxide (SiNx/SiOy), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• the ILD layer 210 is deposited using same process parameters as operation 330.
• the ILD layer 210 can be planarized, such as by chemical mechanical polishing (CMP).
• CMP chemical mechanical polishing
• the ILD layer 210 can be deposited using HDP-CVD or a CVD process using a CCP.
• sequence 380 As a result of sequence 380, a source electrode 212, a drain electrode 214, a source electrode via 216, and a drain electrode via 218 are formed in the ILD layer 210, as shown in FIG. 2G.
• the sequence 380 can include any conventional methods of forming gate and drain electrode structures used in the art.
• portions of the ILD layer 210 are etched such that a portion of the metal oxide layer 204 are exposed.
• portions of the ILD that expose the portion of the metal oxide layer 204 are filled with a conducting material to form the source electrode 212, the drain electrode 214, the source electrode via 216, and the drain electrode via 218.
• the conducting material includes Mo, Cr, Cu, Ti, Ta, W, alloy metals including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any electrically conductive materials, such as including conductive metal oxides, such as ITO or IZO, or any combination thereof.
• a passivation layer 220 is formed, as shown in FIG. 2H.
• the passivation layer 220 is formed over the ILD layer 210, the source electrode 212, and the drain electrode 214.
• the passivation layer 220 can include any material used in the ILD layer 210 or the buffer layer 202.
• the passivation layer 220 can be deposited using HDP-CVD or a CVD process using a CCP. In some embodiments, the passivation layer 220 is deposited using same process parameters as operation 330.
• the passivation layer 220 can be planarized, such as by chemical mechanical polishing (CMP).
• a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204.
• the buffer layer includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiN x ), multi-layer silicon nitride/silicon oxide (SiNx/SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• the TFT 200 further includes a secondary buffer layer (not shown) disposed over the buffer layer and under the metal oxide layer 204.
• a shield metal (not shown) is disposed over the buffer layer, within the secondary buffer layer, and under the metal oxide layer 204.
• the secondary buffer layer can include any of the materials of the buffer layer described above.
• the shield metal can include any of the materials of the gate electrode 208 described above. The shield metal reduces exposure of the TFT 200 to undesired electromagnetic radiation.
• FIGs. 4A-4J illustrate schematic cross-sectional views of a two transistor structure 400, according to one embodiment.
• FIG. 5 is a flow diagram of the method 500 of forming the two transistor structure 400, according to the same embodiment.
• FIGs. 4A-4J, 5, 6, and 7 will be described with reference to the chamber 100 of FIG. 1.
• ICP-CVD chambers other than the chamber 100 may be utilized in conjunction with method 500.
• the method 500 can be stored or accessible to the controller 190 as computer readable media containing instructions, that when executed by the CPU 191 , cause the chamber 100 to perform the method 500.
• the two transistor structure 400 includes the substrate 102 (FIG. 4A).
• the method 500 begins at operation 510, where the first metal oxide layer 204A is formed, as shown in FIG. 4B.
• the first metal oxide layer 204A is formed over a first portion 491 of the substrate 102 (or over the buffer layer 202 if present).
• Operation 510 can be carried out similarly to operation 310.
• the Gl layer 206 (alternatively referred to as an interfacial Gl layer) is deposited, as shown in FIG. 4C.
• the Gl layer is deposited over at least a portion of the first metal oxide layer 204A.
• the Gl layer 206 is in direct contact with the metal oxide layer 204A.
• Operation 540 can be carried out similarly to operation 340.
• a second metal oxide layer 204B is formed, as shown in FIG. 4D.
• the second metal oxide layer 204B is formed over the Gl layer 206, over a second portion 492 of the substrate 102. Operation 550 can be carried out similarly to operation 510.
• a secondary Gl layer (alternatively referred to as a bulk layer) 406 is deposited, as shown in FIG. 4E.
• the secondary Gl layer 406 is deposited over the Gl layer 206 and the second metal oxide layer 204B.
• the secondary Gl layer 406 is in direct contact with the second metal oxide layer 204B.
• the secondary Gl layer 406 can include any material included in the Gl layer 206.
• the deposition of the secondary Gl layer includes a CVD process using a CCP. Operation 555 can be carried out similarly to operation 340.
• the first gate electrode 208A and the second gate electrode 208B are formed, as shown in FIG. 4F.
• the first and second gate electrodes 208A, 208B are formed over the secondary Gl layer 406.
• the first gate electrode 208A is formed over the first metal oxide layer 204A
• the second gate electrode 208B is formed over the second metal oxide layer 204B.
• Operation 560 can be carried out similarly to operation 350.
• one or more residual portions 206* of the Gl layer 206 and one or more residual portions 406* of the secondary Gl layer 406 are etched, as shown in FIG. 4G.
• the first gate electrode 208A and the second gate electrode 208B act as masks to etch the Gl layer 206 to a desired size and shape, forming a first Gl layer portion (alternatively referred to as an interfacial Gl layer) 206A, a first secondary Gl portion (alternatively referred to as a bulk Gl layer) 406A, an underside layer 206B, and a Gl layer 406B.
• the first gate electrode 208A and the second gate electrode 208B act as masks to etch the secondary Gl layer 406 to a desired size and shape, forming the first Gl layer portion 206A, the first secondary Gl portion 406A, the underside layer 206B, and the Gl layer 406B.
• Forming the underside layer 206B and the first Gl layer portion 206A in a single operation 570 reduces the total number of masking and etch operations.
• throughput is increased, reducing cost of ownership (CoO) for the operator.
• the operation 570 reduces the size of the two transistor structure 400, and thus space in a display that incudes the two transistor structure 400. Operation 570 can be carried out similarly to operation 360.
• the ILD layer 210 is formed, as shown in FIG. 4H.
• the ILD layer is formed over the first and second gate electrodes 208A, 208B. Operation 580 can be carried out similarly to operation 370.
• a first source electrode 212A, a second source electrode 212B, a first drain electrode 214A, a second drain electrode 214B, a first source electrode via 216A, a second source electrode via 216B, a first drain electrode via 218A, and a second drain electrode via 218B are formed in the ILD layer 210, as shown in FIG. 4I.
• the sequence 590 can include any conventional methods of forming gate and drain electrode structures used in the art.
• portions of the ILD layer 210 are etched in a first operation such that a portion of the first metal oxide layer 204A is exposed and a portion of the second metal oxide layer 204B is exposed,.
• Sequence 590 can be carried out similarly to sequence 380.
• the passivation layer 220 is formed, as shown in FIG. 4J.
• the passivation layer 220 is formed over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B.
• Operation 595 can be carried out similarly to operation 390.
• two TFTs 401 A, 401 B are formed in the two transistor structure 400.
• the two TFTs 401 A, 401 B can be connected in series or in parallel.
• the two TFTs 401 A, 401 B can receive the same input voltage signal or different voltage signals.
• a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A.
• the buffer layer includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiN x ), multi-layer silicon nitride/silicon oxide (SiNx/SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• the two transistor structure 400 further includes a secondary buffer layer (not shown) disposed over the buffer layer and under the metal oxide layer 204A and the underside layer 206B.
• One or more shield metals are disposed over the buffer layer, within the secondary buffer layer, and under one, or both, of the metal oxide layers 204A, 204B.
• FIG. 6 illustrates a two transistor structure 600, according to one embodiment.
• the method 500 can also be used to form the two transistor structure 600, as will be described in more detail below.
• the two transistor structure 600 includes a first TFT 601 A and a second TFT 601 B.
• the first TFT 601 A can be similar to the first TFT 401 A (FIG. 4J). However, the first TFT 601 A does not include the secondary Gl layer, and thus operation 555 can be omitted.
• the second TFT 601 B can be similar to the second TFT 401 B (FIG. 4J). However, the second metal oxide layer 204B is disposed over the ILD layer 210, and thus operation 550 is performed after operation 560. In addition, the second source electrode 212B and the second drain electrode 214B are in direct contact with the second metal oxide layer 204B, and a source electrode via or a drain electrode via are not included.
• the two transistor structure 600 further includes a secondary buffer layer (not shown) disposed over the buffer layer.
• One or more shield metals are disposed over the buffer layer, within the secondary buffer layer, and under one, or both, of the metal oxide layers 204A, 204B.
• the two TFTs 601 A, 601 B can be connected in series or in parallel.
• the two TFTs 601 A, 601 B can receive the same input voltage signal or different voltage signals.
• a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A.
• the buffer layer includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiNx), multi-layer silicon nitride/silicon oxide (SiNx/SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• FIG. 7 illustrates a two transistor structure 700, according to one embodiment.
• the method 500 can also be used to form the two transistor structure 700, as will be described in more detail below.
• the two transistor structure 700 includes a first TFT 701 A and a second TFT 701 B.
• the first TFT 701 A is similar to the first TFT 401 A (FIG. 4J). However, the first TFT 701A does not include the secondary Gl layer, and thus operation 555 can be omitted.
• the two transistor structure 700 also includes an etch stop layer (ESL) 710 disposed over the ILD layer 210 and under the passivation layer 220.
• the ESL 710 can be formed in an operation following operation 550. The formation of the ESL 710 can be carried out similarly to operation 370.
• the ESL 710 can include any materials included in the ILD layer 210.
• the first source electrode 212A and the first drain electrode 214A are disposed over the ESL 710.
• the first source electrode via 216A and the first drain electrode via 218A are disposed in the ESL 710 and the ILD layer 210.
• the second TFT 701 B is similar to the second TFT 401 B (FIG. 4J). However, the second metal oxide layer 204B is disposed over the ESL 710, and thus operation 550 is performed after operation 560.
• the second source electrode 212B and the second drain electrode 214B are disposed over the ESL 710. The second source electrode via 216B and the second drain electrode via 218B are disposed in the ESL 710.
• a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A.
• the buffer layer includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiN x ), multi-layer silicon nitride/silicon oxide (SiNx/SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• the two transistor structure 700 further includes a secondary buffer layer (not shown) disposed over the buffer layer.
• One or more shield metals are disposed over the buffer layer, within the secondary buffer layer, and under one, or both, of the second metal oxide layers 204A, 204B.
• the two TFTs 701 A, 701 B can be connected in series or in parallel.
• the two TFTs 701 A, 701 B can receive the same input voltage signal or different voltage signals.
• FIG. 8 illustrates a two transistor structure 800, according to one embodiment.
• the method 300 can also be used to form the two transistor structure 800, as will be described in more detail below.
• the two transistor structure 800 includes a first TFT 801 A and a second TFT 801 B.
• the first TFT 801 A can be similar to the TFT 200 (FIG. 2H).
• the second TFT 801 B can be similar to the TFT 200 (FIG. 2H).
• a Gl layer and gate electrode are not included.
• the two transistor structure 800 can be formed using the method 300, where operation 310 further includes depositing the second metal oxide layer 204B.
• a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A.
• the buffer layer includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiNx), multi-layer silicon nitride/silicon oxide (SiNx/SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• the two transistor structure 800 further includes a buffer layer 202 disposed over the substrate 102.
• the buffer layer 202 includes insulating materials such as silicon dioxide (SiOx), silicon nitride (SiN x ), multi-layer silicon nitride/silicon oxide (SiNx/SiOy), silicon oxynitride (SiON), other insulating materials, or combinations thereof.
• a secondary buffer layer 203 is disposed over the buffer layer 202.
• the secondary buffer layer 203 includes any of the material included in the buffer layer 202.
• a shield metal 808B is disposed over the buffer layer 202, within the secondary buffer layer 203, and under the metal oxide layer 204B.
• the shield metal 908B is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across layers of the TFT 801 B.
• the two transistor structure 800 further includes an additional shield metal disposed over the buffer layer 202, within the secondary buffer layer 203, and under the first metal oxide layer 204A.
• the two TFTs 801 A, 801 B can be connected in series or in parallel.
• the two TFTs 801 A, 801 B can receive the same input voltage signal or different voltage signals.
• FIGs. 9A-9N illustrate schematic cross-sectional views of a two transistor structure 900, according to one embodiment.
• FIG. 10 is a flow diagram of the method 1000 of forming the two transistor structure 900, according to the same embodiment.
• FIGs. 9A-9N, and 10 will be described with reference to the chamber 100 of FIG. 1.
• ICP-CVD chambers other than the chamber 100 may be utilized in conjunction with method 1000.
• the method 1000 can be stored or accessible to the controller 190 as computer readable media containing instructions, that when executed by the CPU 191 , cause the chamber 100 to perform the method 1000.
• the two transistor structure 900 includes the substrate 102 (FIG. 9A).
• the method 1000 begins at operation 1005, where a poly-silicon layer 904A is deposited, as shown in FIG. 9B.
• the poly-silicon layer 904A is deposited over the substrate 102 (or over the buffer layer 202 if present).
• the poly-silicon layer 904A can be deposited using any desired method.
• Operation 1005 includes doping the poly-silicon layer 904A with n-type or p-type dopants (e.g., B or N), such as by ion implantation.
• the first Gl layer 206 is deposited, as shown in FIG. 9C.
• the first Gl layer is deposited over at least a portion of the poly silicon layer 904A. Operation 1010 can be carried out similarly to operation 340.
• a first gate electrode 208A and a shield metal 908B are formed, as shown in FIG. 9D.
• the first gate electrode 208A and the shield metal 908B are formed over the first Gl layer 206.
• the first gate electrode 208A is formed over the poly-silicon layer 904A.
• a metal layer is deposited in a first suboperation, and one or more residual portions of the metal layer are removed to form the first gate electrode 208A and the shield metal 908B in a second suboperation. Operation 1020 can be carried out similarly to operation 350.
• a secondary ILD layer 910 is formed, as shown in FIG. 9E.
• the secondary ILD layer 910 is formed over the first gate electrode 208A and the shield metal 908B.
• the secondary ILD layer 910 includes any of the materials of the ILD layer 210. Operation 1025 can be carried out similarly to operation 370.
• a secondary source electrode 912A, a secondary drain electrode 914A, a secondary source electrode via 916A, and a secondary drain electrode via 918A are formed in the secondary ILD layer 910, as shown in FIG. 9F.
• the sequence 1030 can include any conventional methods of forming gate and drain electrode structures used in the art.
• portions of the secondary ILD layer 910 are etched such that a portion of the poly-silicon layer 904A are exposed in a first operation.
• the portions of the secondary ILD layer 910 are filled with a conducting material in a second operation to form the secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A.
• the secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A include any of the materials included in the first source electrode 212A, the first drain electrode 214A, the first source electrode via 216A, and the first drain electrode via 218A. Sequence 1030 can be carried out similarly to sequence 380.
• the secondary buffer layer 203 is formed, as shown in FIG. 9G.
• the secondary buffer layer 203 is deposited over the secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A.
• the secondary buffer layer 203 can be deposited using HDP-CVD or a CVD process using a CCP.
• the second metal oxide layer 204B is formed, as shown in FIG. 9H. In some embodiments, the second metal oxide layer 204B is formed over the secondary buffer layer 203. Operation 1040 can be carried out similarly to operation 510.
• the secondary Gl layer 406 is deposited, as shown in FIG. 9I.
• the secondary Gl layer 406 is deposited over the second metal oxide layer 204B.
• the secondary Gl layer 406 is in direct contact with the second metal oxide layer 204B.
• Operation 1050 can be carried out similarly to operation 555.
• the second gate electrode 208B is formed, as shown in FIG. 9J. In some embodiments, the second gate electrode 208B is formed over the secondary Gl layer 406. The second gate electrode 208B is formed over the second metal oxide layer 204B. Operation 1060 can be carried out similarly to operation 350.
• the one or more residual portions 406* of the secondary Gl layer 406 are etched, as shown in FIG. 9K.
• the second gate electrode 208B acts as a mask to etch the secondary Gl layer 406 to a desired size and shape. Operation 1065 can be carried out similarly to operation 360.
• the ILD layer 210 is formed, as shown in FIG. 9L. In some embodiments, the ILD layer 210 is formed over the second gate electrode 208B and the metal oxide layer 206B. Operation 1070 can be carried out similarly to operation 370.
• sequence 1075 As a result of sequence 1075, the source electrodes 212A, 212B, the drain electrodes 214A, 214B, the source electrode vias 216A, 216B, and the drain electrode vias 218A, 218B are formed in the ILD layer 210, as shown in FIG. 9M.
• the sequence 1075 can include any conventional methods of forming gate and drain electrode structures used in the art.
• the first source electrode via 216A and the first drain electrode via 218A are in electrical contact with the secondary source electrode 912A and the secondary drain electrode 914A, respectively.
• Sequence 1075 can be carried out similarly to sequence 380.
• the passivation layer 220 is formed, as shown in FIG. 9N.
• the passivation layer 220 is deposited over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B.
• Operation 1080 can be carried out similarly to operation 390.
• a first TFTs (alternatively referred to as a poly-silicon TFT) 901 A and a second TFT (alternatively referred to as a metal oxide (MOx) TFT) 901 B are formed in the two transistor structure 400.
• a first TFTs alternatively referred to as a poly-silicon TFT
• MOx metal oxide
• the shield metal 908B is formed over the secondary ILD layer 910.
• operation 1020 is separated into two suboperations, and the suboperation where the shield metal 908B is formed is performed after operation 1025.
• sequence 1030 is not performed, and thus the secondary source electrode, secondary source electrode via, secondary drain electrode, and secondary drain electrode via are not formed.
• the first source electrode via 216A and the first drain electrode via 216A are further disposed in the secondary ILD layer 910 and the secondary buffer layer 203.
• the first source electrode via 216A and the first drain electrode via 218A are in direct electrical contact with the poly-silicon layer 904A.
• the poly-silicon layer 904 is p-doped (e.g., with B) and the metal oxide layer 204B is n-doped (e.g., with N).
• the two TFTs 901 A, 901 B can be connected in series or in parallel.
• the two TFTs 901 A, 901 B can receive the same input voltage signal or different voltage signals.
• FIG. 1 1 illustrates a two transistor structure 1 100, according to one embodiment.
• the method 300 can also be used to form the two transistor structure 1 100, as will be described in more detail below.
• the two transistor structure 1 100 includes a first TFT 1 101 A and a second TFT 1 101 B.
• the first TFT 1 101 A can be similar to the TFT 200 (FIG. 2I).
• a poly-silicon layer 904A is included instead.
• operation 310 only forms the second metal oxide layer 904B.
• Operation 1005 is also included.
• the second TFT 1 101 B is similar to the TFT 200 (FIG. 2I).
• the two transistor structure 1 100 further includes the buffer layer 202 disposed over the substrate 102 and under the ILD layer 210.
• the two transistor structure 1 100 further includes the shield metal 908B.
• the shield metal 908B is disposed over the substrate 102, within the buffer layer 202, and under the metal oxide layer 904B.
• the Gl layer 206A does not increase the mobility of the poly-silicon layer 904A below the Gl layer 206A.
• the Gl layer 206 is etched in operation 360 such that the Gl layer is present both over an entire surface 904S of the poly-silicon layer 904A and over the metal oxide layer 204B.
• the Gl layer 206 is not etched, and thus the Gl layer 206 is disposed as one layer over both the poly-silicon layer 904A and the metal oxide layer 204B.
• the two TFTs 1 101 A, 1 101 B can be connected in series or in parallel.
• the two TFTs 1 101 A, 1 101 B can receive the same input voltage signal or different voltage signals.
• the two TFTs in each of the two transistor structures described above e.g., the two transistor structures 400, 600, 700, 800, 900, 1 100
• LCD liquid crystal display
• OLED organic light-emitting diode
• GIP gate driver in panel
• Each two transistor structure includes a TFT with a first TFT (e.g., TFT 401A, 601A, 701A, 801A, 901 B, 1 101 B) with a higher mobility than a second TFT (e.g., TFT 401 B, 601 B, 701 B, 801 B, 901 A, 1 101 A).
• the first TFT has a higher mobility than the second TFT due to the Gl layer deposited over the metal oxide layer in the first TFT, with the Gl layer deposited by HDP-CVD.
• the Gl layer in direct contact with the metal oxide layer, the Gl layer deposited by HDP-CVD, increases the mobility of the underlying metal oxide layer, which is described in detail above in the discussion of method 300.
• the first TFT has a mobility of greater than about 30 cm2/V s and the second TFT has a mobility of less than about 30 cm2/V s, according to one embodiment.
• any of the metal oxide layers disclosed can be pre-treated.
• the pre-treatment includes flowing a gas, the gas including nitrous oxide (N20) at a flow rate of about 0.40 sccm/cm2 to about 0.60 sccm/cm2, the gas including argon gas (Ar) at a flow rate of about 0 sccm/cm2 (i.e.
• the chamber pressure at a pressure of about 1 mTorr to about 300 mTorr, at a temperature of about 25 °C to about 400 °C, for a period of about 1 s to about 600 s.
• the pre-treatment includes flowing a gas including nitrous oxide (N20) at a flow rate of about 0.40 sccm/cm2 to about 0.60 sccm/cm2 and argon gas (Ar) at a flow rate of about 0 sccm/cm2 (i.e., no Ar coflow) to about 0.60 sccm/cm2, the chamber pressure at a pressure of about 10 mTorr to about 150 mTorr, at a temperature of about 50 °C to about 300 °C, for a period of about 1 s to about 45 s, in one example.
• nitrous oxide N20
• Ar argon gas
• nitrogen dioxide (N02), neon gas (Ne), helium gas (He), or a mixture of the above can also be coflowed.
• the pre-treatment can increase the mobility of the pre-treated metal oxide layer.
• the pre-treatment can be performed in a static chamber, or by a linear source in a dynamic chamber, such as the chamber 100 described above.
• a seed layer can be deposited over any of the metal oxide layers disclosed herein.
• the seed layer is deposited over at least a portion of the metal oxide layer.
• the seed layer improves adhesion of a layer deposited thereon (e.g., the Gl layer).
• the seed layer can have a thickness of about 1 nm to about 100 nm.
• the deposition of the seed layer can include a CVD process using a CCP.
• the deposition of the seed layer can be include a CVD process using a CCP, followed by Gl layer deposited over the interfacial seed layer, and the Gl layer is deposited by an HDP-CVD process. Due to the thin seed layer, the metal oxide layer below the seed layer is still affected by the HDP-CVD process, and the mobility of the metal oxide layer is advantageously increased. In any of the above embodiments, one or more residual portions of the seed Gl layer can also be removed.
• MO/GI operations Formation of metal oxide layers, optional pre-treatment of metal oxide layers, optional deposition of seed layers, and deposition of Gl layers (hereafter collectively referred to as MO/GI operations) can be performed in a single chamber (e.g., chamber 100) without a vacuum break.
• the MO/GI operations can be performed in an integrated system with multiple chambers without vacuum breaks, and each of the MO/GI operations can be performed in any of the chambers.
• any of the MO/GI operations can performed in any number of chambers, where vacuum breaks can be included between the MO/GI operations.
• the formation of the metal oxide layer is performed in a first chamber, the substrate is transferred under vacuum to a second chamber, and the Gl layer is deposited in the second chamber.
• the formation of the metal oxide layer is performed in a first chamber, the substrate is transferred with a vacuum break to a second chamber, and the Gl layer is deposited in the second chamber.
• the methods include depositing one or more metal oxide layers and/or poly-silicon layers.
• a Gl layer is deposited using an HDP-CVD process over the one or more metal oxide layers.
• Depositing the Gl layer using HDP-CVD results in an unexpected increase in mobility of the metal oxide layer and/or poly-silicon layer deposited thereon.
• Selective placement of the Gl layer leads to control of mobility of the underlying layer, depending on whether the Gl layer is deposited by HDP-CVD or a CVD process using a CCP.
• Depositing the Gl layer allows for control of mobility of the underlying layer after the layer deposition; that is, the mobility can be enhanced after deposition, in addition to during deposition.

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Ceramic Engineering (AREA)
• Plasma & Fusion (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Crystallography & Structural Chemistry (AREA)
• Analytical Chemistry (AREA)
• Thin Film Transistor (AREA)
• Formation Of Insulating Films (AREA)
• Electrodes Of Semiconductors (AREA)

Priority Applications (5)

Applications Claiming Priority (4)

Publications (1)

Family

ID=74040899

Family Applications (2)

Family Applications Before (1)

Country Status (4)

Families Citing this family (1)

Citations (5)

Family Cites Families (11)

• 2020
  • 2020-06-17 CN CN202080044698.0A patent/CN114008743A/zh active Pending
  • 2020-06-17 WO PCT/US2020/038182 patent/WO2020257314A1/en active Application Filing
  • 2020-06-17 KR KR1020227001377A patent/KR102624643B1/ko active IP Right Grant
  • 2020-06-17 KR KR1020237038590A patent/KR20230169244A/ko not_active Application Discontinuation
  • 2020-06-17 CN CN202080044751.7A patent/CN113994458A/zh active Pending
  • 2020-06-17 WO PCT/US2020/038202 patent/WO2020257324A1/en active Application Filing
  • 2020-06-17 KR KR1020227001378A patent/KR102601596B1/ko active IP Right Grant
  • 2020-06-17 JP JP2021574256A patent/JP7394887B2/ja active Active
• 2023
  • 2023-11-28 JP JP2023200496A patent/JP2024028772A/ja active Pending

Patent Citations (5)

Also Published As

Similar Documents

Legal Events