WO2020257314A1 - Method of forming inductively coupled high density plasma films for thin film transistor structures - Google Patents

Method of forming inductively coupled high density plasma films for thin film transistor structures Download PDF

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Publication number
WO2020257314A1
WO2020257314A1 PCT/US2020/038182 US2020038182W WO2020257314A1 WO 2020257314 A1 WO2020257314 A1 WO 2020257314A1 US 2020038182 W US2020038182 W US 2020038182W WO 2020257314 A1 WO2020257314 A1 WO 2020257314A1
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Prior art keywords
layer
depositing
gas
forming
tft
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PCT/US2020/038182
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French (fr)
Inventor
Tae Kyung Won
Soo Young Choi
Dong Kil Yim
Zongkai WU
Young Dong Lee
Sanjay D. Yadav
Jung Bae Kim
Zhiyuan Wang
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Applied Materials, Inc.
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Priority to KR1020227001377A priority Critical patent/KR102624643B1/en
Priority to CN202080044751.7A priority patent/CN113994458A/en
Publication of WO2020257314A1 publication Critical patent/WO2020257314A1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present disclosure generally relate to methods of making thin-film transistors (TFT). More specifically, embodiments described herein relate to a method of depositing layers in thin-film transistors having high electron mobility.
  • TFTs Thin-film transistors
  • LCD and OLED displays have gained significant interest in display applications due to their high resolution, low power consumption, and high speed operation for LCD and OLED displays.
  • Current materials used in the layers making up TFTs often have limited electron mobility due to the method of depositing the layers relative to one another and relative to a metal oxide layer of the TFT.
  • a method of forming a thin-film transistor including depositing a buffer layer over a substrate and forming a gate layer over the buffer layer. A portion of the gate layer is etched to form a gate electrode and a gate insulating (Gl) layer is deposited over the buffer layer and the gate electrode. A metal oxide layer is deposited over the Gl layer. A passivation layer is deposited over the metal oxide layer using high density plasma chemical vapor deposition (HDP CVD) using inductively coupled plasma (ICP).
  • the high density plasma includes an electron or ion plasma density greater than 1.0E1 1/cm 3 .
  • a method of fabricating a thin-film transistor including depositing a buffer layer over a substrate and forming a gate layer at least partially over the buffer layer.
  • a gate insulating (Gl) layer is deposited over the buffer layer and the gate layer and a metal oxide layer is deposited over the Gl layer.
  • An etch stop layer is deposited using high density plasma chemical vapor deposition (HDP CVD) using an inductively coupled plasma (ICP) and forming a source electrode and a drain electrode in the etch stop layer.
  • a passivation layer is deposited thereon using an inductively coupled plasma (ICP) based or capacitively coupled (CCP) based chemical vapor deposition process such as HDP CVD.
  • a method including forming a low temperature polysilicon thin-film transistor (LTPS TFT) on a substrate and forming a metal oxide thin-film transistor (MO TFT) on the substrate.
  • the MO TFT includes a metal oxide channel layer.
  • a silicon oxide layer is deposited over the metal oxide channel layer of the MO TFT and over a layer of the LTPS TFT by HDP CVD using ICP.
  • the HDP includes an electron or ion plasma density greater than 1.0E1 1/cm 3 .
  • FIG. 1 is a schematic cross-sectional view of a chamber according to an embodiment.
  • FIGS. 2A-2H are schematic cross-sectional views of a metal oxide TFT at various stages of fabrication according to an embodiment.
  • FIG. 2I is a schematic cross-sectional view of a metal oxide TFT having a passivation layer according to an embodiment.
  • FIG. 3 is a schematic cross-sectional view of a metal oxide TFT with two passivation layers according to an embodiment.
  • FIG. 4 is a schematic cross-sectional view of a metal oxide TFT with an etch stop layer (ESL) and a passivation layer according to an embodiment.
  • ESL etch stop layer
  • FIG. 5 is a schematic cross-sectional view of a metal oxide TFT with two etch stop layers and a passivation layer according to an embodiment.
  • FIG. 6 is a flow diagram of an example method of fabricating an MO TFT structure according to an embodiment.
  • FIGS. 7A-7G are schematic cross-sectional views of a metal oxide TFT and a low temperature polysilicon (LTPS) TFT at various stages of fabrication according to an embodiment.
  • LTPS low temperature polysilicon
  • FIG. 7G is a schematic cross-sectional view of an MO TFT and an LTPS TFT with passivation layer according to an embodiment.
  • FIG. 8 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with a passivation layer, and an etch stop layer according to an embodiment.
  • FIG. 9 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with a passivation layer according to an embodiment.
  • FIG. 10 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with an etch stop layer, and a passivation layer according to an embodiment.
  • FIG. 1 1 is a flow diagram of an example inductively coupled plasma (ICP) high density plasma (HDP) process according to an embodiment.
  • ICP inductively coupled plasma
  • HDP high density plasma
  • the present disclosure generally relates to a method of manufacturing a TFT.
  • the TFT has an active channel that comprises a metal oxide such as indium-gallium-zinc oxide (IGZO) and/or zinc oxide.
  • IGZO indium-gallium-zinc oxide
  • ESL etch stop layer
  • the interface between the metal oxide and the layers disposed over the metal oxide provide predetermined TFT properties useful in some applications of the TFTs.
  • the method of treating and depositing the layers over the metal oxide affect the TFT properties.
  • Methods of making thin-film transistors are provided herein including depositing a layer using inductively coupled plasma high density plasma processes over a metal oxide channel layer to improve electron mobility of the metal oxide channel layer and/or an interface of the MO channel layer and the layer deposited by high density plasma chemical vapor deposition using inductively coupled plasma.
  • high density plasma refers to an electron or ion plasma having a density greater than wherein high density plasma comprises an electron or ion plasma density greater than 1.0E1 1/cm 3 .
  • the deposition process includes pretreating the metal oxide layer with N2O gas or N2O gas with argon gas, energizing the gas to form an inductively coupled plasma, and then introducing SiFU gas to deposit the interface layer including silicon oxide.
  • the interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.
  • FIG. 1 is a schematic cross-sectional view of a chamber 100 useful for practicing embodiments described herein. Suitable chambers may be obtained from Applied Materials, Inc. located in Santa Clara, Calif. It is to be understood that the chamber described below is an exemplary chamber and other chambers, including chambers from other manufacturers, may be used with, or modified to accomplish, aspects of the present disclosure.
  • the chamber 100 is configured to generate an inductively coupled high density plasma.
  • the chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108.
  • the lid assembly 106 is disposed at an upper end of the chamber body 104.
  • the substrate support assembly 108 is at least partially disposed within the interior volume of the chamber body 104.
  • the substrate support assembly 108 includes a substrate support 1 10 and a shaft 1 12 extending therefrom.
  • the substrate support 1 10 has a support surface 1 14 for supporting at least one substrate 102.
  • the substrate 102 is a large area substrate, such as a substrate having a surface area of typically about 1 square meter or greater.
  • the substrate 102 is not limited to any particular size or shape.
  • the term“substrate” refers to any polygonal, squared, rectangular, curved or otherwise non-circular workpiece.
  • the lid assembly 106 includes a diffuser 1 16 extending across at least a portion of the upper end of the chamber body 104.
  • One or more gas inlets 1 18 are coupled through the lid assembly to communicate process gases from at least one gas source 120 to the diffuser 1 16.
  • the one or more gases from the gas source 120 flow through the diffuser 1 16 and into a processing region 124 located between the diffuser 1 16 and the substrate support 1 10.
  • the one or more gases are provided to the processing region 124 through a plurality of holes or openings (not shown) in the processing region 124 facing side of the diffuser 1 16.
  • Flow controllers 122 such as a mass flow control (MFC) devices, are disposed between each of the diffuser inlets 1 18 and the gas source 120 to control the flow rates of gases from the gas source 120 to the diffuser 1 16.
  • the diffuser 1 16 is composed of a ceramic material, such as AI2O3.
  • a pump 126 is in fluid communication with the interior volume of the chamber and thus with the processing region 124. The pump 126 is operable, in conjunction with the mass flow controllers 122, to control the pressure within the processing region 124 and to exhaust gases and byproducts from the processing region 124.
  • the lid assembly 106 includes at least one recess 128 extending inwardly of the upper outer surface thereof having one or more inductively coupled plasma generating components, coils 130, located therein and supported over at least one dielectric plate 132.
  • Each dielectric plate 132 provides a physical barrier between the processing region 124 and the exterior of the chamber 100, and has the structural strength required to withstand structural loads created the presence of atmospheric pressure in the recess 128 and the presence of vacuum pressure within the interior volume of the chamber body 104.
  • Each coil 130 is connected to a power source 134 and to a ground 138.
  • each coil 130 is connected to the power source 134 through a match box 136 having a match circuit for adjusting electrical characteristics, such as impedance, of the coil 130 to“match” the electrical characteristics of the plasma formed in the processing region 124.
  • Each of the coils 130 is configured to create an electromagnetic field within the processing region that energizes the gases in the processing region 124 into an inductively coupled high density plasma.
  • a controller 158 is coupled to the chamber 100 and configured to control aspects of the chamber 100 during processing.
  • FIGS. 2A-2I are schematic illustrations of a metal oxide (MO) TFT 200 at various stages of fabrication according to an embodiment.
  • the TFT 200 is fabricated by first depositing a buffer layer 202 over the substrate 102.
  • the substrate 102 may include any suitable material such as a glass, soda lime glass, polymer(s), and semiconductors used in the fabrication of flat panel displays.
  • Suitable substrates 102 include silicon based substrates, insulating based substrates, germanium based substrates, and, in general, one or more generic layers that would be present in a CMOS structure. It is to be understood that other materials are contemplated as well.
  • the buffer layer 202 is formed by physical vapor deposition or other suitable deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD).
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer 202 is conformally formed using capacitively coupled plasma (CCP) or by high density plasma (HDP), such as an inductively coupled high density plasma in a chamber 100, as described with reference to FIG. 1.
  • CCP capacitively coupled plasma
  • HDP high density plasma
  • the buffer layer 202 is composed of a material comprising a p-type silicon (e.g., boron-doped silicon), metal nitride (e.g., aluminum nitride or tungsten nitride), metal oxide (e.g., vanadium oxide), or combination(s) thereof.
  • the buffer layer 202 includes at least one of silicon oxide (SiOx), silicon nitride (SixNy), and combinations thereof. Unless otherwise specified, any of the layers of the TFT can be deposited using any suitable deposition method known in the industry and/or described herein.
  • a gate layer 203 is deposited over the buffer layer 202.
  • Suitable materials used for the gate layer 203 include chromium, molybdenum, copper, aluminum, tungsten, titanium, and combinations thereof.
  • the gate layer 203 can be formed by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating or chemical vapor deposition (CVD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the gate layer 203 is patterned to form a gate electrode 204.
  • the patterning includes forming either a photolithographic mask or a hard mask (not shown) over the gate layer 203 and exposing the gate layer 203 to an etchant which is referred to herein as“etching.”
  • etching an etchant which is referred to herein as“etching.”
  • the gate layer 203 is patterned by exposing portions thereof not covered by a mask to a wet etchant, or by exposing portions of the gate layer 203 not covered by the mask to an etching plasma.
  • the gate layer 203 is patterned by etching portions of the gate layer 203 not covered by the mask to an etching plasma, which plasma includes sulfur hexafluoride gas, oxygen gas, chlorine gas, or combination(s) thereof.
  • etching plasma and the etching process described can be used in any of the patterning and etching of any layer described herein.
  • the gate insulating (Gl) layer 206 is deposited over the gate electrode 204.
  • the Gl layer 206 is formed using any of the methods of depositing described herein and known in the industry. In some embodiments, which can be combined with other embodiments described herein, the Gl layer 206 is formed using HDP CVD or CCP CVD.
  • CCP opposed electrodes, such as parallel plate electrodes, are provided, and one of the electrodes is coupled to ground while the other is coupled to a power source, and a gas is introduced therebetween to form in effect a capacitor. By powering the powered electrode, electrically, electrical energy is capacitively coupled into the gas to form a plasma thereof.
  • the ion density of the plasma is a function of the power transferred into the gas.
  • a coil surrounds or is over the gas region in which the plasma is to be formed, and electrical energy flowing through the coil is electromagnetically coupled into the gas, to ionize or otherwise energize the gas atoms or molecules.
  • the plasma ion density is a function of the energy coupled into the gas.
  • one of the electrodes is also typically the substrate support, so the power that can be coupled into the gas is limited by the potential negative effects of that power on the substrate.
  • the power to ionize the gas atoms and molecules is decoupled from the circuit components holding the substrate, and higher power can be used to impart higher energy into the plasma, and thus achieve a higher ion density in the plasma without detrimentally effecting the substrate.
  • an active layer such as a metal oxide (MO) layer 207
  • MO layer 207 is disposed over the Gl layer 206.
  • the MO layer 207 is deposited by suitable deposition methods such as physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • the MO layer 207 is patterned using any method of patterning described herein, such as by a wet etch process.
  • the MO channel layer 208 includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (0), tin (Sn), aluminum (Al), and hafnium (Hf).
  • MO channel layer 208 examples include, but are not limited to, InGaZnO, InZnO, InGaSnO, InZnSnO InGaZnSnO, InSnO, HflnZnO, GaZnO, InO, AlSnZnO, ZnO, ZnSnO, AIZnO, AIZnSnO, HfZnO, SnO, and AlSnZnlnO.
  • Suitable materials used for the MO layer 207 include IGZO and/or zinc oxide. As shown in FIG. 2F, the MO layer 207 is patterned by etching to form a MO channel layer 208. Any MO layer and/or MO channel layer can be a 1 1 14 mol% InGaZnO layer.
  • a metal layer 210 is formed over the MO channel layer 208 and exposed Gl layer 206 by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating or chemical vapor deposition (CVD). Any of the processes of PVD, electroplating, electroless plating, or CVD can be used for any of the metal layers described herein, unless otherwise provided.
  • the metal layer 210 is then patterned to form a source electrode 21 OA and a drain electrode 21 OB, and an opening 21 1 formed therebetween.
  • the metal layer 210 is patterned using any suitable method described herein, such as a back channel etch (BCE) process.
  • BCE back channel etch
  • each of the source electrodes, drain electrodes, and gate electrodes described herein can include a conductive material such as copper, titanium, tantalum, or any electrically conductive metal. It is to be understood that other materials are contemplated as well.
  • the opening 21 1 over the MO channel layer 208 exposes a portion of the MO channel layer 208 at the base thereof.
  • a passivation layer 212 is formed over the MO channel layer 208, and the exposed Gl layer 206 and the source and drain electrodes 210A, 210B by an HDP CVD process using an inductively coupled plasma.
  • the processes shown and described in FIGS. 2A to 2I disclose the fabrication of an embodiment of a gate covered by a passivation layer. After the source and drain electrodes are formed, but before the passivation or etch stop layers are deposited thereover, the MO channel layer 208 within the opening 21 1 is pretreated prior to the HDP CVD process using ICP. A top surface of the MO channel layer 208 and/or an interface between the MO channel layer 208 and the layer to be deposited thereover (e.g., ESL or passivation layer) is believed to be chemically modified to have high electron mobility.
  • the passivation layer (e.g., 212) is typically the top most layer of TFT devices which protects the devices from environmental damage, including chemically or mechanically induced damage.
  • the passivation layer also provides stable and reliable TFT performance against prolonged thermal and electrical bias stress. Due to the sensitivity of metal oxide layers with respect to hydrogen and other environmental chemicals, high quality, low hydrogen containing, oxides such as silicon oxides described herein are provided as the passivation layer 212.
  • the passivation layer is disposed directly over and contacts the metal oxide layer of the gate
  • using the HDP CVD process using an inductively coupled plasma provides a silicon oxide composition having a low hydrogen content compared to silicon oxides produced from other forms of deposition.
  • the passivation layer 212 is depicted as a single layer in FIG. 2I, multiple passivation layers are contemplated, and one such example is provided in reference to FIG. 3 described herein.
  • FIG. 3 depicts a first passivation layer 302 formed over the source and drain electrodes 210A, 210B, and a portion of the MO channel layer 208 using a CCP CVD process, followed by a second passivation layer 304 deposited using an HDP CVD process using an inductively coupled plasma to form bottom gate TFT 300.
  • the second passivation layer 304 formed on the outermost or uppermost layer of the TFT is formed using an HDP CVD process using an inductively coupled plasma, it has a high quality, stable, and low hydrogen content composition capable of protecting the MO channel layer from environmental damage and enhancing electron mobility in the MO channel.
  • the MO channel layer 208 is pretreated using a capacitively coupled plasma before depositing the first passivation layer 302 using CCP CVD.
  • the first passivation layer 302 has a thickness of less than 100 nm.
  • the second passivation layer 304 has a thickness of about 10 nm to about 300 nm. Without being bound by theory, it is believed that depositing a second passivation layer 304 over a first passivation layer 302 is capable of increasing the electron mobility of the MO channel layer 208 disposed below the first passivation layer 302.
  • FIG. 4 depicts an embodiment of a bottom gate TFT 400 with an etch stop layer 402 deposited over the gate insulation layer 206 and gate electrode 204.
  • the etch stop layer 402 is deposited by an HDP CVD process using an inductively coupled plasma and is then patterned to formed source electrode 410A and drain electrode 410B using any method of forming source and drain electrodes described herein.
  • a passivation layer 404 is deposited over the source and drain electrodes 410A, 410B, and over the etch stop layer 402.
  • the passivation layer 404 is deposited using any method of deposition disclosed herein, such as CCP CVD, or HDP CVD.
  • FIG. 5 depicts an embodiment of a bottom gate TFT 500 with a first etch stop layer 502 deposited by using CCP CVD deposition process, followed by a second etch stop layer 504 deposited by an HDPCVD process using an inductively coupled plasma.
  • Source and drain electrodes 510A, 51 OB are formed in the first and second etch stop layers 502, 504.
  • a passivation layer 506 is deposited thereon using any method disclosed herein, such as by CCP CVD, or by HDPCVD process using an inductively coupled plasma.
  • FIG. 6 is a flow diagram of an exemplary method of fabricating an MO TFT structure according to an embodiment.
  • a buffer layer e.g., 202
  • a gate layer e.g., 203
  • a gate electrode e.g., 204
  • a Gl layer e.g., 206
  • a patterned metal oxide layer e.g., 208 is formed over the Gl layer.
  • a passivation layer or an etch stop layer is deposited over the patterned metal oxide layer using HDP CVD using an inductively coupled plasma.
  • FIGS. 7A-7G are schematic cross-sectional views of an MO TFT 730 and an LTPS TFT 720 (collectively TFT 700) at various stages of fabrication according to an embodiment.
  • a first buffer layer 702 is formed over the substrate 102 in a similar manner as described with reference in FIG. 2A.
  • a silicon layer is deposited over the buffer layer 702 and then etched using any of the methods described herein to form a low temperature polycrystalline silicon (LTPS) layer 704.
  • LTPS low temperature polycrystalline silicon
  • a Gl layer 706 is deposited thereon and a gate 708 is formed using methods of patterning described herein.
  • An interlayer dielectric (ILD) layer 710 is deposited over the Gl layer 706 and the gate 708.
  • ILD interlayer dielectric
  • Suitable materials used for the ILD layer include silicon nitride, silicon oxide, and silicon oxynitride. Additionally, while shown as a single layer, it is contemplated that the ILD layer 710 may comprise multiple layers, each of which may comprise a different chemical composition.
  • the ILD layer is deposited using any method described herein, such as using HDP CVD or CCP CVD. A portion of the ILD layer 710 and a portion of the Gl layer 706 is etched down to the LTPS layer 704 to form a first lower opening 71 1A and a second lower opening 71 1 B. A first metal layer 713 is formed (as shown in FIG. 7B). As shown in FIG.
  • the first metal layer 713 is patterned to form a lower source via 712A, an intermediate source electrode pad 712C, an intermediate drain electrode pad 712D, and a lower drain via 712B of the LTPS TFT 720. Additionally, the first metal layer 713 is patterned to form a gate electrode 714 of the MO TFT 730.
  • the lower source via 712A extends up to an intermediate source electrode pad 712C and the lower drain via 712B extends up to an intermediate drain electrode pad 712D.
  • a second buffer layer 716 is then formed thereon as depicted in FIG. 7D.
  • a metal oxide layer 717 is deposited over the second buffer layer 716 as shown in FIG. 7E, and in FIG. 7F, a portion of the metal oxide layer
  • the second buffer layer 716 is patterned to form a first upper opening 721A extending down to the intermediate source electrode pad 712C, and a second upper opening 721 B extending down to the intermediate drain electrode pad 712D of the LTPS TFT 720.
  • a second metal layer (not shown) is deposited and patterned to form an upper source via 722A extending from the intermediate source electrode pad 712C to an upper source electrode pad 722C and an upper drain electrode via 722B extending from the intermediate drain electrode pad 712D to an upper drain electrode pad 722D of the LTPS TFT 720 as shown in FIG. 7G.
  • the lower source via 712A, intermediate source electrode pad 712C, upper source via 722A, and upper source electrode pad 722C together form the source electrode 742A.
  • the lower drain via 712B, intermediate drain electrode pad 712D, upper drain electrode via 722B, and upper drain electrode pad 722D together form the drain electrode 742B of the LTPS TFT 720.
  • An MO TFT source electrode 732A and an MO TFT drain electrode 732B is formed over the MO channel layer 718 of the MO TFT 730.
  • a passivation layer 724 is deposited by an HDP CVD process using an inductively coupled plasma to form the MO TFT 730 and the LTPS TFT 720 of the structure 700.
  • FIG. 8 is a schematic cross-sectional view of a TFT structure 800 including an MO TFT 830 and an LTPS TFT 820 with a passivation layer 804, and an etch stop layer 802 according to an embodiment.
  • the layers of the TFT structure 800 are deposited in a similar manner as illustrated in FIGS. 7A-7E.
  • the etch stop layer 802 is deposited by an HDP CVD process using an inductively coupled plasma over the MO channel layer
  • the etch stop layer 802 is patterned and an MO TFT source electrode via 832A is formed extending from the MO channel layer 718 to the MO TFT source electrode pad 832C.
  • An MO TFT drain electrode 832B is formed extending from the MO channel layer 718 to the MO TFT drain pad 832D in the MO TFT 830.
  • the passivation layer 804 is deposited either by CCP CVD or by HDP CVD.
  • an upper source electrode via 822A is formed extending from the intermediate source electrode pad 712C to an upper source electrode pad 822C and an upper drain electrode via 822B is formed extending from the intermediate drain electrode pad 712D to an upper drain electrode pad 822D of the LTPS TFT 820.
  • the lower source via 712A, intermediate source electrode pad 712C, upper source via 822A, and upper source electrode pad 822C together form the source electrode 842A.
  • the lower drain via 712B, intermediate drain electrode pad 712D, upper drain electrode via 822B, and upper drain electrode pad 822D together form the drain electrode 842B of the LTPS TFT 820.
  • FIG. 9 is a schematic cross-sectional view of a TFT structure 900 including an MO TFT 930 and an LTPS TFT 920 with a passivation layer 906 according to an embodiment.
  • Layers 702, 706, 708, and 710 of the TFT structure 900 are formed in a manner described with reference to FIG. 7A.
  • an MO TFT gate 908 is formed in the MO TFT 930.
  • the ILD layer 710 is formed thereon and a second buffer layer 902 is formed over the ILD layer 710.
  • a source electrode 922A and a drain electrode 922B are formed in the second buffer layer 902, the ILD layer 710, and the Gl layer 706 extending to the LTPS layer 704 of the LTPS TFT 920.
  • a source electrode 932A and a drain electrode 932B is formed around a metal oxide layer 904 in the MO TFT 930.
  • the passivation layer 906 is formed thereon by HDP CVD using inductively coupled plasma. It has been discovered that a complementary structure including a p-type LTPS TFT and an n-type MO TFT can be formed suitable for use in applications such as a semiconductor based circuit.
  • MO TFT structures include MO channel layers having electron mobility of less than 30 cm 2 /Vsec, such as about 10 cm 2 /Vsec.
  • conventional p-type LTPS TFT structures include layers with electron mobility of about 80 cm 2 /Vsec to about 100 cm 2 /Vsec.
  • the electron mobility of the MO channel layer of the present disclosure is greater than 30 cm 2 /Vsec, such as greater than 50 cm 2 /Vsec, such as about 80 cm 2 /Vsec to about 100 cm 2 /Vsec, or about 100 cm 2 /Vsec to about 400 100 cm 2 /Vsec.
  • the methods described herein use less masks as the conventional methods of forming structures that include an LTPS TFT and MO TFT.
  • FIG. 10 is a schematic cross-sectional view of an MO TFT 1030 and an LTPS TFT 1020 (collectively TFT structure 1000) with an etch stop layer (ESL) 1006, and a passivation layer 1008 according to an embodiment.
  • a second buffer layer 1002 is formed over the ILD layer 710.
  • the MO channel layer 1004 is formed in the ESL 1006, and the ESL 1006 is formed using an HDP CVD process using an inductively coupled plasma.
  • a source electrode 1022A and a drain electrode 1022B is formed in the LTPS TFT 1020 and a source electrode 1032A and a drain electrode 1032B is formed in the MO TFT 1030.
  • the passivation layer 1008 is formed by CCP CVD or HDP CVD.
  • MO channel layer of the MO TFT is disposed in the same plane as the gate of the LTPS TFT.
  • the MO channel layer of the MO TFT is disposed in a different plane as the gate electrode of the LTPS TFT.
  • an MO channel layer may undergo a pretreatment process prior to depositing a layer over the MO channel layer by HDP CVD using ICP. An example pretreatment and deposition process is shown in method 1 100 of FIG. 1 1 and summarized in Table 1 below.
  • Plasma e.g., (e.g., 1 102) Plasma (e.g., (e.g., Deposition), and
  • Operation 1 102 of FIG. 1 1 includes a pretreatment process using a pretreatment gas to pretreat a film layer hereof.
  • the pretreatment gas includes nitrous oxide gas, argon gas, or a combination of an oxygen containing gas and argon gas to the processing region 124 of the process chamber in operation 1 102 of FIG. 1 1.
  • the oxygen containing gas is one or more of N2O gas, NO gas, 02 gas, and O3 gas, such as N2O gas.
  • the substrate 102 Prior to operation 1 102, the substrate 102 is positioned within the processing region 124 to provide a spacing between the diffuser 1 16 and the substrate 102 of about 100 mm to about 300 mm.
  • Introducing the pretreatment gas includes introducing the N2O gas at about 0.3 sccm/cm 2 to about 0.7 sccm/cm 2 and an argon gas at about 0 sccm/cm 2 to about 0.7 sccm/cm 2 .
  • the unit“sccm/cm 2 ” refers to standard cubic centimeter of volumetric gas flow per square centimeter of substrate surface area.
  • the pretreatment gas introduced to the process volume includes a N2O gas to argon gas ratio of about 1 :0 to about 1 :2 by volume, such as about 3:1 to about 1 :1.
  • argon gas is not used with N2O gas.
  • a pretreatment process pressure of the process volume is about 10 mT to about 150 mT, such as about 12 mT to about 120 mT.
  • the pretreatment process temperature of the substrate is about 70 °C to about 350 °C, such as about 70 °C to about 250 °C and the pretreatment process time is about 5 seconds to about 60 seconds, such as about 10 seconds to about 40 seconds.
  • the pretreatment gas is introduced into the process volume prior to be energized into a plasma.
  • a plasma pretreatment which includes energizing the pretreatment gas within the process volume at an ICP coil energy supplied at a frequency of about 1 MHz to about 30 MHz, such as about 2 MHz to about 15 MHz.
  • the plasma treatment conditions described in Table 1 and in operation 1 104 is used to pretreat an MO channel layer after operation 1 102.
  • the MO channel layer can be pretreated using the conditions provided in operation 1 104 without pretreating using the conditions provided with reference to operation 1 102. It has been found that a low ICP coil frequency reduces damage associated with energized plasma, increases uniformity, and reduces energy consumption.
  • High plasma energy frequency uses power having frequencies over 100 MHz, such as 100 GHz in its processes.
  • High frequency can be used in the HDP process described herein, however, the ICP coil frequency of about 1 MHz to about 30 MHz, such as about 2 MHz to about 15 MHz energizes the pretreatment gas to produce plasma.
  • Energizing the pretreatment gas includes providing electrical power at a power density of about 2.3 W/cm 2 to about 5.3 W/cm 2 .
  • the term“power density” refers to an amount of electrical power provided per square centimeter of an exposed substrate surface area.
  • the temperature of the substrate is maintained at about 70 °C to about 350 °C, such as about 70 °C to about 250 °C.
  • the plasma pretreatment time is about 2 seconds to about 32 seconds.
  • the pretreatment gas is converted to a plasma formed in situ prior to depositing a silicon oxide layer as described herein.
  • the plasma is formed ex situ and introduced to the process volume. It is believed that the plasma pretreatment process enhances the metal oxide TFT characteristics and performance under thermal bias stress.
  • the plasma pretreatment is performed prior to forming the etch stop layer(s) and/or the passivation layer(s).
  • the combination of the stated range of gas flow rates, power densities and frequencies produce a low plasma density, which is adequate for preparation of the exposed film surface for subsequent deposition of the silicon oxide layer, and provides low ion bombardment and low potential to damage the partially fabricated TFT structure.
  • silane (SihU) gas is introduced at about 0.02 sccm/cm 2 to about 0.09 sccm/cm 2 to form a silicon oxide interface (e.g., ESL or passivation layer interfacing the MO channel layer).
  • the plasma conditions in operation 1 104 are maintained during and after the addition of SihU gas at a ratio of N2O gas flow to SihU gas flow of about 5: 1 to about 40:1 by volume.
  • the MO channel layer is not exposed to the pretreatment process described in operations 1 102 and 1 104.
  • the process conditions of operation 1 106 as described in the“deposition” column of Table 1 are applied to the MO channel layer without pretreatment.
  • the processing region 124 volume pressure is maintained at about 80 mT to about 12 mT.
  • the SihU gas is introduced for about 26 seconds to about 260 seconds.
  • a silicon oxide interface layer (e.g., passivation layer or ESL) is formed with a thickness of about 200 angstroms to about 2000 angstroms, such as about 500 angstroms to about 2000 angstroms.
  • the silicon oxide interface layer produced by HDP CVD using an inductively coupled plasma has a hydrogen content at 250°C of about 1.9% and the interface layer produced by CCP has a hydrogen content at 250°C of about 3.5%, based on atomic percentages.
  • An additional operation (e.g., post deposition column depicted in Table 1 ) includes annealing for about 5 to about 15 seconds maintaining a temperature of about 70 °C to about 250 °C.
  • the top surface of the exposed MO channel layer and/or the interface between the MO channel layer and the layer deposited thereon by HDP CVD using ICP is chemically and/or physically modified by one or more of operation 1 102, operation 1 104, operation 1 106, and the post deposition operation. It is believed that the high electron mobility is achieved by increasing electron carrier densities in the MO channel layer and/or at the interface between the MO channel layer and the layer deposited thereover.
  • the MO channel layer has a mobility of greater than 30 cm/Vsec, such as greater than 60 cm/Vsec.
  • the film density of the example film deposited using HDP CVD using an inductively coupled plasma had a film density at about 2.3 g/cm 3 at about 250 °C, as measured by x-ray reflectivity, which is higher than a typical film density of a silicon oxide film deposited by other depositions. These films have a film density of 2.2 g/cm 3 or lower at about 250 °C.
  • CMOS complementary metal oxide semiconductor
  • the TFT structures described herein using a p-type LTPS TFT, and a n-type MO TFT, reduces the numbers of masks needed to form a TFT structure having improved performance, stability, and electron mobility.
  • methods of making thin-film transistors including depositing an interface layer using inductively coupled plasma high density plasma processes over a metal oxide layer to improve electron mobility.
  • the deposition process includes pretreating the metal oxide layer with N2O gas or N2O gas with argon gas, energizing the gas to form an inductively coupled plasma, and then introducing SiFU gas to deposit the interface layer including silicon oxide.
  • the interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.

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Abstract

Embodiments of the present disclosure generally relate to methods of making thin-film transistors (TFT). More specifically, embodiments described herein relate to a method of depositing an insulating layer using inductively coupled plasma high density plasma processes over a metal oxide layer to improve electron mobility. The high density plasma includes an electron or ion plasma density greater than 1.0E11/cm3. The metal oxide layer is pretreated with an inductively coupled plasma formed from N2O gas or N2O gas with argon gas. Inductively coupled plasma formed from SiH4 gas and N2O gas is used to deposit the insulating layer, such as a silicon oxide layer. The silicon oxide layer is an etch stop layer, or the silicon oxide layer is a passivation layer of the TFT structure. The present disclosure is used for MO TFT structures and complementary MO TFT and LTPS TFT structures.

Description

METHOD OF FORMING INDUCTIVELY COUPLED HIGH DENSITY PLASMA FILMS FOR THIN FILM TRANSISTOR STRUCTURES
BACKGROUND
Field
[0001] Embodiments of the present disclosure generally relate to methods of making thin-film transistors (TFT). More specifically, embodiments described herein relate to a method of depositing layers in thin-film transistors having high electron mobility.
Description of the Related Art
[0002] Thin-film transistors (TFTs) are metal oxide layered semiconductor devices used in integrated circuits and in displays to control pixel operation. TFTs have gained significant interest in display applications due to their high resolution, low power consumption, and high speed operation for LCD and OLED displays. Current materials used in the layers making up TFTs often have limited electron mobility due to the method of depositing the layers relative to one another and relative to a metal oxide layer of the TFT.
[0003] Accordingly, what is needed in the art are improved TFTs and methods of fabricating TFTs. In particular, there is a need for insulating layers, such as passivation and etch stop layers for TFTs having a lower hydrogen content, a higher density, a lower wet etch rate, and a lower plasma damage.
SUMMARY
[0004] In one embodiment, a method of forming a thin-film transistor is provided including depositing a buffer layer over a substrate and forming a gate layer over the buffer layer. A portion of the gate layer is etched to form a gate electrode and a gate insulating (Gl) layer is deposited over the buffer layer and the gate electrode. A metal oxide layer is deposited over the Gl layer. A passivation layer is deposited over the metal oxide layer using high density plasma chemical vapor deposition (HDP CVD) using inductively coupled plasma (ICP). The high density plasma includes an electron or ion plasma density greater than 1.0E1 1/cm3.
[0005] In another embodiment, a method of fabricating a thin-film transistor is provided including depositing a buffer layer over a substrate and forming a gate layer at least partially over the buffer layer. A gate insulating (Gl) layer is deposited over the buffer layer and the gate layer and a metal oxide layer is deposited over the Gl layer. An etch stop layer is deposited using high density plasma chemical vapor deposition (HDP CVD) using an inductively coupled plasma (ICP) and forming a source electrode and a drain electrode in the etch stop layer. A passivation layer is deposited thereon using an inductively coupled plasma (ICP) based or capacitively coupled (CCP) based chemical vapor deposition process such as HDP CVD.
[0006] In another embodiment, a method is provided including forming a low temperature polysilicon thin-film transistor (LTPS TFT) on a substrate and forming a metal oxide thin-film transistor (MO TFT) on the substrate. The MO TFT includes a metal oxide channel layer. A silicon oxide layer is deposited over the metal oxide channel layer of the MO TFT and over a layer of the LTPS TFT by HDP CVD using ICP. The HDP includes an electron or ion plasma density greater than 1.0E1 1/cm3.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.
[0008] FIG. 1 is a schematic cross-sectional view of a chamber according to an embodiment.
[0009] FIGS. 2A-2H are schematic cross-sectional views of a metal oxide TFT at various stages of fabrication according to an embodiment. [0010] FIG. 2I is a schematic cross-sectional view of a metal oxide TFT having a passivation layer according to an embodiment.
[0011] FIG. 3 is a schematic cross-sectional view of a metal oxide TFT with two passivation layers according to an embodiment.
[0012] FIG. 4 is a schematic cross-sectional view of a metal oxide TFT with an etch stop layer (ESL) and a passivation layer according to an embodiment.
[0013] FIG. 5 is a schematic cross-sectional view of a metal oxide TFT with two etch stop layers and a passivation layer according to an embodiment.
[0014] FIG. 6 is a flow diagram of an example method of fabricating an MO TFT structure according to an embodiment.
[0015] FIGS. 7A-7G are schematic cross-sectional views of a metal oxide TFT and a low temperature polysilicon (LTPS) TFT at various stages of fabrication according to an embodiment.
[0016] FIG. 7G is a schematic cross-sectional view of an MO TFT and an LTPS TFT with passivation layer according to an embodiment.
[0017] FIG. 8 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with a passivation layer, and an etch stop layer according to an embodiment.
[0018] FIG. 9 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with a passivation layer according to an embodiment.
[0019] FIG. 10 is a schematic cross-sectional view of an MO TFT and an LTPS TFT with an etch stop layer, and a passivation layer according to an embodiment.
[0020] FIG. 1 1 is a flow diagram of an example inductively coupled plasma (ICP) high density plasma (HDP) process according to an embodiment.
[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
DETAILED DESCRIPTION
[0022] The present disclosure generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises a metal oxide such as indium-gallium-zinc oxide (IGZO) and/or zinc oxide. One or more passivation layers and/or one or more etch stop layer (ESL) is disposed over the metal oxide. The interface between the metal oxide and the layers disposed over the metal oxide provide predetermined TFT properties useful in some applications of the TFTs. In particular, the method of treating and depositing the layers over the metal oxide affect the TFT properties.
[0023] Methods of making thin-film transistors (TFT) are provided herein including depositing a layer using inductively coupled plasma high density plasma processes over a metal oxide channel layer to improve electron mobility of the metal oxide channel layer and/or an interface of the MO channel layer and the layer deposited by high density plasma chemical vapor deposition using inductively coupled plasma. As used herein, the term“high density plasma,” refers to an electron or ion plasma having a density greater than wherein high density plasma comprises an electron or ion plasma density greater than 1.0E1 1/cm3. The deposition process includes pretreating the metal oxide layer with N2O gas or N2O gas with argon gas, energizing the gas to form an inductively coupled plasma, and then introducing SiFU gas to deposit the interface layer including silicon oxide. The interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.
[0024] FIG. 1 is a schematic cross-sectional view of a chamber 100 useful for practicing embodiments described herein. Suitable chambers may be obtained from Applied Materials, Inc. located in Santa Clara, Calif. It is to be understood that the chamber described below is an exemplary chamber and other chambers, including chambers from other manufacturers, may be used with, or modified to accomplish, aspects of the present disclosure. The chamber 100 is configured to generate an inductively coupled high density plasma. [0025] The chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. The lid assembly 106 is disposed at an upper end of the chamber body 104. The substrate support assembly 108 is at least partially disposed within the interior volume of the chamber body 104. The substrate support assembly 108 includes a substrate support 1 10 and a shaft 1 12 extending therefrom. The substrate support 1 10 has a support surface 1 14 for supporting at least one substrate 102. In one embodiment, which can be combined with other embodiments described herein, the substrate 102 is a large area substrate, such as a substrate having a surface area of typically about 1 square meter or greater. However, the substrate 102 is not limited to any particular size or shape. In one aspect, the term“substrate” refers to any polygonal, squared, rectangular, curved or otherwise non-circular workpiece.
[0026] The lid assembly 106 includes a diffuser 1 16 extending across at least a portion of the upper end of the chamber body 104. One or more gas inlets 1 18 are coupled through the lid assembly to communicate process gases from at least one gas source 120 to the diffuser 1 16. The one or more gases from the gas source 120 flow through the diffuser 1 16 and into a processing region 124 located between the diffuser 1 16 and the substrate support 1 10. The one or more gases are provided to the processing region 124 through a plurality of holes or openings (not shown) in the processing region 124 facing side of the diffuser 1 16. Flow controllers 122, such as a mass flow control (MFC) devices, are disposed between each of the diffuser inlets 1 18 and the gas source 120 to control the flow rates of gases from the gas source 120 to the diffuser 1 16. In some embodiments, which can be combined with other embodiments described herein, the diffuser 1 16 is composed of a ceramic material, such as AI2O3. A pump 126 is in fluid communication with the interior volume of the chamber and thus with the processing region 124. The pump 126 is operable, in conjunction with the mass flow controllers 122, to control the pressure within the processing region 124 and to exhaust gases and byproducts from the processing region 124.
[0027] Here, the lid assembly 106 includes at least one recess 128 extending inwardly of the upper outer surface thereof having one or more inductively coupled plasma generating components, coils 130, located therein and supported over at least one dielectric plate 132. Each dielectric plate 132 provides a physical barrier between the processing region 124 and the exterior of the chamber 100, and has the structural strength required to withstand structural loads created the presence of atmospheric pressure in the recess 128 and the presence of vacuum pressure within the interior volume of the chamber body 104. Each coil 130 is connected to a power source 134 and to a ground 138. In one embodiment, which can be combined with other embodiments described herein, each coil 130 is connected to the power source 134 through a match box 136 having a match circuit for adjusting electrical characteristics, such as impedance, of the coil 130 to“match” the electrical characteristics of the plasma formed in the processing region 124. Each of the coils 130 is configured to create an electromagnetic field within the processing region that energizes the gases in the processing region 124 into an inductively coupled high density plasma. A controller 158 is coupled to the chamber 100 and configured to control aspects of the chamber 100 during processing.
[0028] FIGS. 2A-2I are schematic illustrations of a metal oxide (MO) TFT 200 at various stages of fabrication according to an embodiment. As shown in FIG. 2A, the TFT 200 is fabricated by first depositing a buffer layer 202 over the substrate 102. The substrate 102 may include any suitable material such as a glass, soda lime glass, polymer(s), and semiconductors used in the fabrication of flat panel displays. Suitable substrates 102 include silicon based substrates, insulating based substrates, germanium based substrates, and, in general, one or more generic layers that would be present in a CMOS structure. It is to be understood that other materials are contemplated as well. The buffer layer 202 is formed by physical vapor deposition or other suitable deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, which can be combined with other embodiments described herein, the buffer layer 202 is conformally formed using capacitively coupled plasma (CCP) or by high density plasma (HDP), such as an inductively coupled high density plasma in a chamber 100, as described with reference to FIG. 1. The buffer layer 202 is composed of a material comprising a p-type silicon (e.g., boron-doped silicon), metal nitride (e.g., aluminum nitride or tungsten nitride), metal oxide (e.g., vanadium oxide), or combination(s) thereof. In some embodiments, which can be combined with other embodiments described herein, the buffer layer 202 includes at least one of silicon oxide (SiOx), silicon nitride (SixNy), and combinations thereof. Unless otherwise specified, any of the layers of the TFT can be deposited using any suitable deposition method known in the industry and/or described herein.
[0029] As shown in FIG. 2B, a gate layer 203 is deposited over the buffer layer 202. Suitable materials used for the gate layer 203 include chromium, molybdenum, copper, aluminum, tungsten, titanium, and combinations thereof. The gate layer 203 can be formed by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating or chemical vapor deposition (CVD). As depicted in FIG. 2C, the gate layer 203 is patterned to form a gate electrode 204. The patterning includes forming either a photolithographic mask or a hard mask (not shown) over the gate layer 203 and exposing the gate layer 203 to an etchant which is referred to herein as“etching.” Depending on the material used in the gate layer 203, the gate layer 203 is patterned by exposing portions thereof not covered by a mask to a wet etchant, or by exposing portions of the gate layer 203 not covered by the mask to an etching plasma. In some embodiments, which can be combined with other embodiments described herein, the gate layer 203 is patterned by etching portions of the gate layer 203 not covered by the mask to an etching plasma, which plasma includes sulfur hexafluoride gas, oxygen gas, chlorine gas, or combination(s) thereof. The etching plasma and the etching process described can be used in any of the patterning and etching of any layer described herein.
[0030] As shown in FIG. 2D, the gate insulating (Gl) layer 206 is deposited over the gate electrode 204. The Gl layer 206 is formed using any of the methods of depositing described herein and known in the industry. In some embodiments, which can be combined with other embodiments described herein, the Gl layer 206 is formed using HDP CVD or CCP CVD. In CCP, opposed electrodes, such as parallel plate electrodes, are provided, and one of the electrodes is coupled to ground while the other is coupled to a power source, and a gas is introduced therebetween to form in effect a capacitor. By powering the powered electrode, electrically, electrical energy is capacitively coupled into the gas to form a plasma thereof. The ion density of the plasma is a function of the power transferred into the gas. In contrast, in an ICP plasma, a coil surrounds or is over the gas region in which the plasma is to be formed, and electrical energy flowing through the coil is electromagnetically coupled into the gas, to ionize or otherwise energize the gas atoms or molecules. Again the plasma ion density is a function of the energy coupled into the gas. In a CCP system, one of the electrodes is also typically the substrate support, so the power that can be coupled into the gas is limited by the potential negative effects of that power on the substrate. In contrast, using an ICP arrangement, the power to ionize the gas atoms and molecules is decoupled from the circuit components holding the substrate, and higher power can be used to impart higher energy into the plasma, and thus achieve a higher ion density in the plasma without detrimentally effecting the substrate.
[0031] As shown in FIG. 2E, an active layer, such as a metal oxide (MO) layer 207, is disposed over the Gl layer 206. The MO layer 207 is deposited by suitable deposition methods such as physical vapor deposition (PVD). The MO layer 207 is patterned using any method of patterning described herein, such as by a wet etch process. In one embodiment, which can be combined with other embodiments described herein, the MO channel layer 208 includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (0), tin (Sn), aluminum (Al), and hafnium (Hf). Examples of the MO channel layer 208 include, but are not limited to, InGaZnO, InZnO, InGaSnO, InZnSnO InGaZnSnO, InSnO, HflnZnO, GaZnO, InO, AlSnZnO, ZnO, ZnSnO, AIZnO, AIZnSnO, HfZnO, SnO, and AlSnZnlnO. Suitable materials used for the MO layer 207 include IGZO and/or zinc oxide. As shown in FIG. 2F, the MO layer 207 is patterned by etching to form a MO channel layer 208. Any MO layer and/or MO channel layer can be a 1 1 14 mol% InGaZnO layer.
[0032] As shown in FIG. 2G, a metal layer 210 is formed over the MO channel layer 208 and exposed Gl layer 206 by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating or chemical vapor deposition (CVD). Any of the processes of PVD, electroplating, electroless plating, or CVD can be used for any of the metal layers described herein, unless otherwise provided. The metal layer 210 is then patterned to form a source electrode 21 OA and a drain electrode 21 OB, and an opening 21 1 formed therebetween. The metal layer 210 is patterned using any suitable method described herein, such as a back channel etch (BCE) process. Unless otherwise specified, each of the source electrodes, drain electrodes, and gate electrodes described herein can include a conductive material such as copper, titanium, tantalum, or any electrically conductive metal. It is to be understood that other materials are contemplated as well.
[0033] The opening 21 1 over the MO channel layer 208 exposes a portion of the MO channel layer 208 at the base thereof. As shown in FIG. 2I, a passivation layer 212 is formed over the MO channel layer 208, and the exposed Gl layer 206 and the source and drain electrodes 210A, 210B by an HDP CVD process using an inductively coupled plasma. The processes shown and described in FIGS. 2A to 2I disclose the fabrication of an embodiment of a gate covered by a passivation layer. After the source and drain electrodes are formed, but before the passivation or etch stop layers are deposited thereover, the MO channel layer 208 within the opening 21 1 is pretreated prior to the HDP CVD process using ICP. A top surface of the MO channel layer 208 and/or an interface between the MO channel layer 208 and the layer to be deposited thereover (e.g., ESL or passivation layer) is believed to be chemically modified to have high electron mobility.
[0034] The sequence of operation of the HDP CVD process using an inductively coupled plasma is described herein with reference to FIG. 1 1. The passivation layer (e.g., 212) is typically the top most layer of TFT devices which protects the devices from environmental damage, including chemically or mechanically induced damage. The passivation layer also provides stable and reliable TFT performance against prolonged thermal and electrical bias stress. Due to the sensitivity of metal oxide layers with respect to hydrogen and other environmental chemicals, high quality, low hydrogen containing, oxides such as silicon oxides described herein are provided as the passivation layer 212. In particular, in embodiments in which the passivation layer is disposed directly over and contacts the metal oxide layer of the gate, using the HDP CVD process using an inductively coupled plasma provides a silicon oxide composition having a low hydrogen content compared to silicon oxides produced from other forms of deposition. Although the passivation layer 212 is depicted as a single layer in FIG. 2I, multiple passivation layers are contemplated, and one such example is provided in reference to FIG. 3 described herein.
[0035] FIG. 3 depicts a first passivation layer 302 formed over the source and drain electrodes 210A, 210B, and a portion of the MO channel layer 208 using a CCP CVD process, followed by a second passivation layer 304 deposited using an HDP CVD process using an inductively coupled plasma to form bottom gate TFT 300. Here, as the second passivation layer 304 formed on the outermost or uppermost layer of the TFT is formed using an HDP CVD process using an inductively coupled plasma, it has a high quality, stable, and low hydrogen content composition capable of protecting the MO channel layer from environmental damage and enhancing electron mobility in the MO channel. In some embodiments, which can be combined with other embodiments described herein, the MO channel layer 208 is pretreated using a capacitively coupled plasma before depositing the first passivation layer 302 using CCP CVD. The first passivation layer 302 has a thickness of less than 100 nm. The second passivation layer 304 has a thickness of about 10 nm to about 300 nm. Without being bound by theory, it is believed that depositing a second passivation layer 304 over a first passivation layer 302 is capable of increasing the electron mobility of the MO channel layer 208 disposed below the first passivation layer 302.
[0036] FIG. 4 depicts an embodiment of a bottom gate TFT 400 with an etch stop layer 402 deposited over the gate insulation layer 206 and gate electrode 204. The etch stop layer 402 is deposited by an HDP CVD process using an inductively coupled plasma and is then patterned to formed source electrode 410A and drain electrode 410B using any method of forming source and drain electrodes described herein.
[0037] A passivation layer 404 is deposited over the source and drain electrodes 410A, 410B, and over the etch stop layer 402. The passivation layer 404 is deposited using any method of deposition disclosed herein, such as CCP CVD, or HDP CVD. FIG. 5 depicts an embodiment of a bottom gate TFT 500 with a first etch stop layer 502 deposited by using CCP CVD deposition process, followed by a second etch stop layer 504 deposited by an HDPCVD process using an inductively coupled plasma. Source and drain electrodes 510A, 51 OB are formed in the first and second etch stop layers 502, 504. A passivation layer 506 is deposited thereon using any method disclosed herein, such as by CCP CVD, or by HDPCVD process using an inductively coupled plasma.
[0038] FIG. 6 is a flow diagram of an exemplary method of fabricating an MO TFT structure according to an embodiment. In operation 602, a buffer layer (e.g., 202) is formed over a substrate (e.g., 102). In operation 604, a gate layer (e.g., 203) is deposited over the buffer layer and in operation 606, at least a portion of the gate layer is etched to form a gate electrode (e.g., 204). In operation 608, a Gl layer (e.g., 206) is deposited over the gate electrode and in operation 610, a patterned metal oxide layer (e.g., 208) is formed over the Gl layer. In operation 612, a passivation layer or an etch stop layer is deposited over the patterned metal oxide layer using HDP CVD using an inductively coupled plasma.
[0039] FIGS. 7A-7G are schematic cross-sectional views of an MO TFT 730 and an LTPS TFT 720 (collectively TFT 700) at various stages of fabrication according to an embodiment. A first buffer layer 702 is formed over the substrate 102 in a similar manner as described with reference in FIG. 2A. A silicon layer is deposited over the buffer layer 702 and then etched using any of the methods described herein to form a low temperature polycrystalline silicon (LTPS) layer 704. A Gl layer 706 is deposited thereon and a gate 708 is formed using methods of patterning described herein. An interlayer dielectric (ILD) layer 710 is deposited over the Gl layer 706 and the gate 708. Suitable materials used for the ILD layer include silicon nitride, silicon oxide, and silicon oxynitride. Additionally, while shown as a single layer, it is contemplated that the ILD layer 710 may comprise multiple layers, each of which may comprise a different chemical composition. The ILD layer is deposited using any method described herein, such as using HDP CVD or CCP CVD. A portion of the ILD layer 710 and a portion of the Gl layer 706 is etched down to the LTPS layer 704 to form a first lower opening 71 1A and a second lower opening 71 1 B. A first metal layer 713 is formed (as shown in FIG. 7B). As shown in FIG. 7C, the first metal layer 713 is patterned to form a lower source via 712A, an intermediate source electrode pad 712C, an intermediate drain electrode pad 712D, and a lower drain via 712B of the LTPS TFT 720. Additionally, the first metal layer 713 is patterned to form a gate electrode 714 of the MO TFT 730.
[0040] With respect to the LTPS TFT 720, the lower source via 712A extends up to an intermediate source electrode pad 712C and the lower drain via 712B extends up to an intermediate drain electrode pad 712D. A second buffer layer 716 is then formed thereon as depicted in FIG. 7D. A metal oxide layer 717 is deposited over the second buffer layer 716 as shown in FIG. 7E, and in FIG. 7F, a portion of the metal oxide layer
717 is patterned to form an MO channel layer 718 of the MO TFT 730. The second buffer layer 716 is patterned to form a first upper opening 721A extending down to the intermediate source electrode pad 712C, and a second upper opening 721 B extending down to the intermediate drain electrode pad 712D of the LTPS TFT 720. A second metal layer (not shown) is deposited and patterned to form an upper source via 722A extending from the intermediate source electrode pad 712C to an upper source electrode pad 722C and an upper drain electrode via 722B extending from the intermediate drain electrode pad 712D to an upper drain electrode pad 722D of the LTPS TFT 720 as shown in FIG. 7G. The lower source via 712A, intermediate source electrode pad 712C, upper source via 722A, and upper source electrode pad 722C together form the source electrode 742A. The lower drain via 712B, intermediate drain electrode pad 712D, upper drain electrode via 722B, and upper drain electrode pad 722D together form the drain electrode 742B of the LTPS TFT 720.
[0041] An MO TFT source electrode 732A and an MO TFT drain electrode 732B is formed over the MO channel layer 718 of the MO TFT 730. A passivation layer 724 is deposited by an HDP CVD process using an inductively coupled plasma to form the MO TFT 730 and the LTPS TFT 720 of the structure 700.
[0042] FIG. 8 is a schematic cross-sectional view of a TFT structure 800 including an MO TFT 830 and an LTPS TFT 820 with a passivation layer 804, and an etch stop layer 802 according to an embodiment. The layers of the TFT structure 800 are deposited in a similar manner as illustrated in FIGS. 7A-7E. The etch stop layer 802 is deposited by an HDP CVD process using an inductively coupled plasma over the MO channel layer
718 of the MO TFT 830. The etch stop layer 802 is patterned and an MO TFT source electrode via 832A is formed extending from the MO channel layer 718 to the MO TFT source electrode pad 832C. An MO TFT drain electrode 832B is formed extending from the MO channel layer 718 to the MO TFT drain pad 832D in the MO TFT 830. The passivation layer 804 is deposited either by CCP CVD or by HDP CVD.
[0043] Referring to the LTPS TFT 820 depicted in FIG. 8, an upper source electrode via 822A is formed extending from the intermediate source electrode pad 712C to an upper source electrode pad 822C and an upper drain electrode via 822B is formed extending from the intermediate drain electrode pad 712D to an upper drain electrode pad 822D of the LTPS TFT 820. The lower source via 712A, intermediate source electrode pad 712C, upper source via 822A, and upper source electrode pad 822C together form the source electrode 842A. The lower drain via 712B, intermediate drain electrode pad 712D, upper drain electrode via 822B, and upper drain electrode pad 822D together form the drain electrode 842B of the LTPS TFT 820.
[0044] FIG. 9 is a schematic cross-sectional view of a TFT structure 900 including an MO TFT 930 and an LTPS TFT 920 with a passivation layer 906 according to an embodiment. Layers 702, 706, 708, and 710 of the TFT structure 900 are formed in a manner described with reference to FIG. 7A. In the same plane as the LTPS gate 708, an MO TFT gate 908 is formed in the MO TFT 930. The ILD layer 710 is formed thereon and a second buffer layer 902 is formed over the ILD layer 710. A source electrode 922A and a drain electrode 922B are formed in the second buffer layer 902, the ILD layer 710, and the Gl layer 706 extending to the LTPS layer 704 of the LTPS TFT 920. A source electrode 932A and a drain electrode 932B is formed around a metal oxide layer 904 in the MO TFT 930. The passivation layer 906 is formed thereon by HDP CVD using inductively coupled plasma. It has been discovered that a complementary structure including a p-type LTPS TFT and an n-type MO TFT can be formed suitable for use in applications such as a semiconductor based circuit. Conventional n-type MO TFT structures include MO channel layers having electron mobility of less than 30 cm2/Vsec, such as about 10 cm2/Vsec. In contrast, conventional p-type LTPS TFT structures include layers with electron mobility of about 80 cm2/Vsec to about 100 cm2/Vsec. Thus, the present disclosure has found that the difference of electron mobility between the LTPS TFT structure and the MO TFT structure is improved by increasing electron mobility in the MO channel layer of the MO TFT structure using the methods described herein. The electron mobility of the MO channel layer of the present disclosure is greater than 30 cm2/Vsec, such as greater than 50 cm2/Vsec, such as about 80 cm2/Vsec to about 100 cm2/Vsec, or about 100 cm2/Vsec to about 400 100 cm2/Vsec. Moreover, the methods described herein use less masks as the conventional methods of forming structures that include an LTPS TFT and MO TFT.
[0045] FIG. 10 is a schematic cross-sectional view of an MO TFT 1030 and an LTPS TFT 1020 (collectively TFT structure 1000) with an etch stop layer (ESL) 1006, and a passivation layer 1008 according to an embodiment. In the TFT structure 1000, a second buffer layer 1002 is formed over the ILD layer 710. The MO channel layer 1004 is formed in the ESL 1006, and the ESL 1006 is formed using an HDP CVD process using an inductively coupled plasma. A source electrode 1022A and a drain electrode 1022B is formed in the LTPS TFT 1020 and a source electrode 1032A and a drain electrode 1032B is formed in the MO TFT 1030. The passivation layer 1008 is formed by CCP CVD or HDP CVD. In some embodiments, which can be combined with other embodiments described herein, MO channel layer of the MO TFT is disposed in the same plane as the gate of the LTPS TFT. In some embodiments, which can be combined with other embodiments described herein, the MO channel layer of the MO TFT is disposed in a different plane as the gate electrode of the LTPS TFT. In some aspects hereof, an MO channel layer may undergo a pretreatment process prior to depositing a layer over the MO channel layer by HDP CVD using ICP. An example pretreatment and deposition process is shown in method 1 100 of FIG. 1 1 and summarized in Table 1 below.
Table 1 : Example Pretreatment and Deposition by HDP CVD using ICP Process
Parameter Pretreatment gas Pretreatment Deposition Post-
(e.g., 1 102) Plasma (e.g., (e.g., Deposition
_ 1 104) _ 1 106) _
Time (seconds) 5-60 2-32 26-260 5-15
Temperature (°C) 70-250 70-250 70-250 70-250
Pressure (mT) 15-120 15-120 80-120 0 T ICP Power (W/cm2) 0 2.3-3.5 2.3-3.5 0
N2O (sccm/cm2) 0.45-0.58 0.45-0.58 0.45-0.58 0
Ar (sccm/cm2) 0.0-0.58 0.0-0.58 0 0
SiH4 (sccm/cm2) 0 0 0.02-0.09 0
[0046] Operation 1 102 of FIG. 1 1 includes a pretreatment process using a pretreatment gas to pretreat a film layer hereof. The pretreatment gas includes nitrous oxide gas, argon gas, or a combination of an oxygen containing gas and argon gas to the processing region 124 of the process chamber in operation 1 102 of FIG. 1 1. The oxygen containing gas is one or more of N2O gas, NO gas, 02 gas, and O3 gas, such as N2O gas.
[0047] Prior to operation 1 102, the substrate 102 is positioned within the processing region 124 to provide a spacing between the diffuser 1 16 and the substrate 102 of about 100 mm to about 300 mm. Introducing the pretreatment gas includes introducing the N2O gas at about 0.3 sccm/cm2 to about 0.7 sccm/cm2 and an argon gas at about 0 sccm/cm2 to about 0.7 sccm/cm2. As used herein, the unit“sccm/cm2” refers to standard cubic centimeter of volumetric gas flow per square centimeter of substrate surface area. The pretreatment gas introduced to the process volume includes a N2O gas to argon gas ratio of about 1 :0 to about 1 :2 by volume, such as about 3:1 to about 1 :1. In some embodiments, which can be combined with other embodiments described herein, argon gas is not used with N2O gas.
[0048] A pretreatment process pressure of the process volume is about 10 mT to about 150 mT, such as about 12 mT to about 120 mT. The pretreatment process temperature of the substrate is about 70 °C to about 350 °C, such as about 70 °C to about 250 °C and the pretreatment process time is about 5 seconds to about 60 seconds, such as about 10 seconds to about 40 seconds. In some embodiments, which can be combined with other embodiments described herein, the pretreatment gas is introduced into the process volume prior to be energized into a plasma. [0049] In operation 1 104, a plasma pretreatment is provided which includes energizing the pretreatment gas within the process volume at an ICP coil energy supplied at a frequency of about 1 MHz to about 30 MHz, such as about 2 MHz to about 15 MHz. In some embodiments, which can be combined with other embodiments described herein, the plasma treatment conditions described in Table 1 and in operation 1 104 is used to pretreat an MO channel layer after operation 1 102. Alternatively, the MO channel layer can be pretreated using the conditions provided in operation 1 104 without pretreating using the conditions provided with reference to operation 1 102. It has been found that a low ICP coil frequency reduces damage associated with energized plasma, increases uniformity, and reduces energy consumption. High plasma energy frequency, such as for microwave chemical vapor deposition, uses power having frequencies over 100 MHz, such as 100 GHz in its processes. High frequency can be used in the HDP process described herein, however, the ICP coil frequency of about 1 MHz to about 30 MHz, such as about 2 MHz to about 15 MHz energizes the pretreatment gas to produce plasma. Energizing the pretreatment gas includes providing electrical power at a power density of about 2.3 W/cm2 to about 5.3 W/cm2. As used herein, the term“power density” refers to an amount of electrical power provided per square centimeter of an exposed substrate surface area. The temperature of the substrate is maintained at about 70 °C to about 350 °C, such as about 70 °C to about 250 °C. The plasma pretreatment time is about 2 seconds to about 32 seconds. In some embodiments, which can be combined with other embodiments described herein, the pretreatment gas is converted to a plasma formed in situ prior to depositing a silicon oxide layer as described herein. Alternatively, the plasma is formed ex situ and introduced to the process volume. It is believed that the plasma pretreatment process enhances the metal oxide TFT characteristics and performance under thermal bias stress. The plasma pretreatment is performed prior to forming the etch stop layer(s) and/or the passivation layer(s). In some embodiments, which can be combined with other embodiments described herein, the combination of the stated range of gas flow rates, power densities and frequencies produce a low plasma density, which is adequate for preparation of the exposed film surface for subsequent deposition of the silicon oxide layer, and provides low ion bombardment and low potential to damage the partially fabricated TFT structure. [0050] In operation 1 106, silane (SihU) gas is introduced at about 0.02 sccm/cm2 to about 0.09 sccm/cm2 to form a silicon oxide interface (e.g., ESL or passivation layer interfacing the MO channel layer). In some embodiments, which can be combined with other embodiments described herein, the plasma conditions in operation 1 104 are maintained during and after the addition of SihU gas at a ratio of N2O gas flow to SihU gas flow of about 5: 1 to about 40:1 by volume. In some embodiments, the MO channel layer is not exposed to the pretreatment process described in operations 1 102 and 1 104. In particular, the process conditions of operation 1 106 as described in the“deposition” column of Table 1 , are applied to the MO channel layer without pretreatment. The processing region 124 volume pressure is maintained at about 80 mT to about 12 mT. The SihU gas is introduced for about 26 seconds to about 260 seconds. A silicon oxide interface layer (e.g., passivation layer or ESL) is formed with a thickness of about 200 angstroms to about 2000 angstroms, such as about 500 angstroms to about 2000 angstroms. The silicon oxide interface layer produced by HDP CVD using an inductively coupled plasma has a hydrogen content at 250°C of about 1.9% and the interface layer produced by CCP has a hydrogen content at 250°C of about 3.5%, based on atomic percentages. An additional operation (e.g., post deposition column depicted in Table 1 ) includes annealing for about 5 to about 15 seconds maintaining a temperature of about 70 °C to about 250 °C. Without being bound by theory, it is believed that the top surface of the exposed MO channel layer and/or the interface between the MO channel layer and the layer deposited thereon by HDP CVD using ICP is chemically and/or physically modified by one or more of operation 1 102, operation 1 104, operation 1 106, and the post deposition operation. It is believed that the high electron mobility is achieved by increasing electron carrier densities in the MO channel layer and/or at the interface between the MO channel layer and the layer deposited thereover. The MO channel layer has a mobility of greater than 30 cm/Vsec, such as greater than 60 cm/Vsec.
Example
[0051] Exemplary silicon oxide deposition processes are provided and summarized in Table 2.
[0052] Table 2: Example Process Conditions for HDP CVD using ICP
Figure imgf000020_0001
[0053] Several TFT samples with silicon oxide layer deposited therein were formed using the process conditions summarized in Table 2. As can be seen, each of the layers deposited provided a wet etch rate (WER) below 2600 angstroms/minute, even at low substrate processing temperatures, such as 80°C and 85°C. The WER performance was significantly better than WERs that are typical for other forms of deposition which typically have WER above 4000, or above 6000, or above 8000 angstroms/minute. The WER values were normalized to thermal oxide WER which has a WER of 1000A/min. The Si- O peak position was found to be consistently high over a wide temperature range of about 100 °C to about 300 °C demonstrating high film quality and controllability over a wide range. The columing“spacing” is defined by the distance between the diffuser and the substrate in mils.
[0054] Additionally hydrogen concentration and film density was measured for an example film deposited using HDP CVD using an inductively coupled plasma. The hydrogen content, particularly at low temperatures, was considerably lower than the hydrogen content typically found using other processes. Other processes typically have hydrogen concentrations greater than 5%, such as about 6% at temperatures lower than 150 °C. The hydrogen concentration measured in the example film deposited using HDP CVD using an inductively coupled plasma had a hydrogen concentration of about 2.7% at about 120 °C, 1.8% at about 225 °C, and 1.7% at about 340 °C. The film density of the example film deposited using HDP CVD using an inductively coupled plasma had a film density at about 2.3 g/cm3 at about 250 °C, as measured by x-ray reflectivity, which is higher than a typical film density of a silicon oxide film deposited by other depositions. These films have a film density of 2.2 g/cm3 or lower at about 250 °C.
[0055] As compared to complementary metal oxide semiconductor (CMOS), such as p-type poly-Si + n-type poly Si structures, the TFT structures described herein, using a p-type LTPS TFT, and a n-type MO TFT, reduces the numbers of masks needed to form a TFT structure having improved performance, stability, and electron mobility.
[0056] In summation, methods of making thin-film transistors (TFT) are provided including depositing an interface layer using inductively coupled plasma high density plasma processes over a metal oxide layer to improve electron mobility. The deposition process includes pretreating the metal oxide layer with N2O gas or N2O gas with argon gas, energizing the gas to form an inductively coupled plasma, and then introducing SiFU gas to deposit the interface layer including silicon oxide. The interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.
[0057] While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

What is claimed is:
1. A method of forming a thin film transistor comprising:
depositing a buffer layer over a substrate;
forming a gate layer over the buffer layer;
etching at least a portion of the gate layer to form a gate electrode;
depositing a gate insulating (Gl) layer over the buffer layer and the gate electrode; forming a metal oxide channel layer over the Gl layer; and
depositing a passivation layer by high density plasma chemical vapor deposition (HDP CVD) using inductively coupled plasma (ICP), wherein high density plasma comprises an electron or ion plasma density greater than 1.0E1 1/cm3.
2. The method of claim 1 , wherein depositing the passivation layer comprises depositing an interfacial passivation layer by chemical vapor deposition using capacitively coupled plasma (CCP) and depositing an upper passivation layer with HDP CVD using ICP.
3. The method of claim 1 , further comprising pretreating the metal oxide channel layer before depositing the passivation layer, wherein the pretreating the metal oxide channel layer comprises exposing the metal oxide channel layer to an inductively coupled plasma.
4. The method of claim 3, wherein the inductively coupled plasma is formed from nitrous oxide (N2O), Ar, or a combination thereof.
5. The method of claim 1 , wherein depositing the passivation layer comprises energizing N2O gas and silane (S1H4) gas to form the inductively coupled plasma and exposing the inductively coupled plasma to the metal oxide channel layer.
6. A method of forming a thin film transistor comprising:
depositing a buffer layer over a substrate; forming a gate layer at least partially over the buffer layer;
depositing a gate insulating (Gl) layer over the buffer layer and the gate layer; forming a metal oxide channel layer over the Gl layer;
depositing an etch stop layer by high density plasma chemical vapor deposition (HDP CVD) using inductively coupled plasma (ICP), wherein high density plasma comprises an electron or ion plasma density greater than 1.0E1 1/cm3;
forming a source electrode and a drain electrode in the etch stop layer; and depositing a passivation layer.
7. The method of claim 6, wherein depositing the etch stop layer comprises depositing an interfacial etch stop layer by chemical vapor deposition using capacitively coupled plasma (CCP) and depositing an upper etch stop layer with HDP CVD using ICP.
8. The method of claim 6, wherein depositing an etch stop layer by HDP CVD comprises introducing a N2O gas and S1H4 gas to a process volume at a N2O gas and S1H4 gas ratio of about 5:1 to about 40: 1 , wherein the substrate is disposed within the process volume.
9. The method of claim 8, wherein depositing an etch stop layer by HDP CVD comprises setting an ICP coil energy at a frequency of about 1 MHz to about 15 MHz.
10. The method of claim 6 further comprising:
introducing N2O gas to a process volume of a process chamber at a N2O gas flow rate of about 0.3 sccm/cm2 to about 0.7 sccm/cm2, wherein the substrate is disposed in the process volume;
energizing the N2O gas at a power density of about 2.3 W/cm2 to about 5.3 W/cm2; and
introducing S1H4 gas at a S1H4 gas flow rate of about 0.02 sccm/cm2 to about 0.09 sccm/cm2.
1 1. The method of claim 10, wherein introducing N2O gas to the process volume comprises introducing argon gas to the process volume, wherein the process volume comprises a pressure of about 15 mT to about 120 mT and a process temperature of about 70 °C to about 350 °C.
12. A method of forming a thin film transistor comprising:
forming a low temperature polysilicon thin-film transistor (LTPS TFT) on a substrate; and
forming a metal oxide thin-film transistor (MO TFT) comprising a metal oxide channel layer on the substrate, wherein forming the LTPS TFT and the MO TFT comprises depositing a silicon oxide layer by HDP CVD using ICP over the metal oxide channel layer, wherein HDP comprises an electron or ion plasma density greater than 1.0E1 1/cm3.
13. The method of claim 12, wherein an electron mobility of the metal oxide channel layer is greater than 30 cm2/Vsec.
14. The method of claim 12, wherein forming the LTPS TFT and forming the MO TFT comprises:
depositing a first buffer layer over the substrate;
forming a low temperature polysilicon (LTPS) layer over the first buffer layer; depositing a Gl layer over the first buffer layer and the LTPS layer;
forming a gate layer at least partially over the Gl layer;
depositing an interlayer dielectric layer (ILD) over the Gl layer and the gate layer; depositing a second buffer layer;
forming the metal oxide channel layer over the second buffer layer;
depositing the silicon oxide layer by HDP CVD using inductively coupled plasma (ICP) over the metal oxide channel layer.
15. The method of claim 14, wherein forming the LTPS TFT further comprises forming LTPS source and drain electrodes before depositing the silicon oxide layer, and forming the MO TFT further comprises forming MO source and drain electrodes before depositing the silicon oxide layer, wherein the silicon oxide layer is an etch stop layer.
16. The method of claim 14, wherein forming the LTPS TFT further comprises forming LTPS source and drain electrodes after depositing the silicon oxide layer, and forming the MO TFT further comprises forming MO source and drain electrodes after depositing the silicon oxide layer, wherein the silicon oxide layer is a passivation layer.
17. The method of claim 12, wherein the silicon oxide layer comprises a thickness of about 500 angstroms to about 2000 angstroms.
18. The method of claim 12, further comprising pretreating the metal oxide channel layer with inductively coupled plasma comprising nitrogen and oxygen, and depositing a silicon oxide layer, wherein pretreating the metal oxide channel layer and depositing the silicon oxide layer comprises a process time of about 80 seconds to about 350 seconds.
19. The method of claim 18, wherein pretreating the metal oxide channel layer comprises:
introducing N2O gas to a process volume of a process chamber at a N2O gas flow rate per substrate surface area of about 0.3 sccm/cm2 to about 0.7 sccm/cm2, wherein the substrate is disposed therein; and
energizing the N2O gas at a power density of about 2.3 W/cm2 to about 5.3 W/cm2.
20. The method of claim 18, wherein depositing the silicon oxide layer comprises: introducing SiFU gas at a SiFU gas flow rate of about 0.02 sccm/cm2 to about 0.09 sccm/cm2 to form the silicon oxide layer and at a process temperature of about 70 °C to about 350 °C.
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