JP2015198223A - Display device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which can reduce shift of a threshold voltage of a thin film transistor; and to provide a method for manufacturing the display device.SOLUTION: According to an embodiment, a display device includes a thin film transistor TR provided on an insulating substrate 10. The thin film transistor TR includes: a channel region SCC; an oxide semiconductor layer SC having a source region SCS and a drain region SCD which are provided respectively on opposite sides of the channel region; a gate electrode GE provided opposite to the channel region and on the side opposite to the insulating substrate; a gate insulation film which is provided between the channel region and the gate electrode and includes a silicon oxide layer composed mostly of silicon oxide, and has a nitride region 12a which contains nitride in the vicinity of a lateral face exposed on the outside of the oxide semiconductor layer and the gate electrode; a source electrode SE which contacts the source region; and a drain electrode DE which contacts the drain region.

Description

  Embodiments described herein relate generally to a display device having a thin film transistor and a method for manufacturing the display device.

  In recent years, a display device including a thin film transistor (TFT) as a semiconductor device has been put into practical use. Examples of the display device include various flat display devices such as a liquid crystal display device and an organic electroluminescence display device.

  Recently, a TFT including an oxide semiconductor layer typified by indium gallium zinc oxide (IGZO) has been actively studied. As these TFTs, a top gate type TFT including an oxide semiconductor layer and a gate electrode disposed opposite to each other with a gate insulating film interposed between channel regions of the oxide semiconductor layer has been proposed.

  In such a TFT, for example, when a gate bias temperature stress is applied, the charge distribution in the film changes due to the movement of working ions in the gate insulating film, or in the channel region of the oxide semiconductor thin layer. The threshold voltage shifts to the negative side due to factors such as fluctuations in the amount of oxygen. For this reason, it is difficult to obtain stable transistor characteristics.

JP 2007-259883 A

  An object of an embodiment of the present invention is to provide a display device capable of reducing a shift in threshold voltage of a thin film transistor and a method for manufacturing the display device.

  The display device according to the embodiment includes an insulating substrate and a thin film transistor provided on the insulating substrate. The thin film transistor includes an oxide semiconductor layer having a channel region and a source region and a drain region provided on both sides of the channel region, and a channel region of the oxide semiconductor layer on the side opposite to the insulating substrate. A gate insulating film including a silicon oxide layer mainly composed of silicon oxide and provided between the gate electrode and the channel region and the gate electrode provided opposite to each other, the oxide semiconductor layer and the gate A gate insulating film having a nitride region containing nitride in the vicinity of a side surface exposed to the outside of the electrode, a source electrode in contact with the source region, and a drain electrode in contact with the drain region are provided.

In the method for manufacturing a display device according to the embodiment, an oxide semiconductor layer is formed on an insulating substrate, and a gate insulating layer including a silicon oxide layer containing silicon oxide as a main component is formed on the oxide semiconductor layer. And forming a gate layer on the gate insulating layer, forming a resist pattern on the gate layer, patterning the gate insulating layer and the gate layer using the resist pattern as a mask, and forming a gate insulating film And forming a gate electrode on the gate insulating film, exposing the side surface of the gate insulating film and the oxide semiconductor layer to be a source region and a drain region, and exposing the exposed side surface of the gate insulating film and the oxidation the things semiconductor layer, exposed to gas containing at least ammonia (NH _3), as well as reduce the resistance of the source region and the drain region A nitride region containing nitride is formed in the vicinity of a side surface of the gate insulating film, an interlayer insulating film is formed on the gate electrode and the oxide semiconductor layer, and the source region and the drain region are formed on the interlayer insulating film. First and second contact holes reaching each of the first and second contact holes are formed, a source electrode in contact with the source region from the first contact hole and a drain region from the second contact hole are formed on the interlayer insulating film. A contact drain electrode is formed.

FIG. 1 is a cross-sectional view schematically illustrating a configuration example of an array substrate of a display device according to an embodiment. 2 is an enlarged cross-sectional view of a thin film transistor on the array substrate shown in FIG. FIG. 3 is a cross-sectional view showing an example of a manufacturing process of the array substrate having the thin film transistor according to the present embodiment. FIG. 4 is a cross-sectional view showing an example of a manufacturing process of the array substrate having the thin film transistor according to the present embodiment. FIG. 5 is a cross-sectional view showing an example of a manufacturing process of the array substrate having the thin film transistor according to the present embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
It should be noted that the disclosure is merely an example, and those skilled in the art can appropriately modify the gist of the invention and can be easily conceived, and are naturally included in the scope of the present invention. In addition, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part in comparison with actual aspects for the sake of clarity of explanation, but are merely examples, and the interpretation of the present invention is not limited. It is not limited. In addition, in the present specification and each drawing, elements similar to those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description may be omitted as appropriate.

  FIG. 1 is a cross-sectional view schematically showing a configuration example of an array substrate applicable to the display device of the present embodiment. The display device can be used by being incorporated into various electronic devices such as a smartphone, a tablet terminal, a mobile phone, a notebook type PC, a portable game machine, an electronic dictionary, or a television device.

  As shown in FIG. 1, the array substrate SUB1 is formed by using an insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The array substrate SUB1 includes a thin film transistor TR formed on the insulating substrate 10. The thin film transistor TR constitutes a part of a display pixel provided on the array substrate SUB1 or a part of a drive circuit provided on the array substrate SUB1. The array substrate SUB1 includes pixel electrodes (not shown) that constitute liquid crystal display elements and organic electroluminescence elements.

In the configuration example shown in FIG. 1, an undercoat layer (first insulating layer) 11 is formed on the inner surface 10 </ b> A of the insulating substrate 10. The undercoat layer 11 is formed of, for example, silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), or the like. The thin film transistor TR includes a semiconductor layer SC provided on the undercoat layer 11, a gate electrode GE provided on the semiconductor layer SC with a gate insulating film (second insulating layer) 12 interposed therebetween, and a third electrode covering the gate electrode GE. It has a source electrode SE and a drain electrode DE provided on the insulating layer 13, and constitutes a top gate type thin film transistor.

That is, on the undercoat layer 11, for example, an oxide semiconductor layer SC is formed as a semiconductor layer constituting the thin film transistor TR. Further, the pixel electrode is formed on the undercoat layer 11 similarly to the oxide semiconductor layer SC.
Such an oxide semiconductor layer SC and a pixel electrode are formed of an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn), for example. As a typical example of forming the oxide semiconductor layer SC, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), zinc oxide tin (ZnSnO), zinc oxide (ZnO) is used. ) And the like.

  The oxide semiconductor layer SC is, for example, patterned in a substantially rectangular shape, and has a relatively high resistance channel region SCC and source regions that are lower in resistance than the channel region SCC and located on both sides of the channel region SCC. SCS and drain region SCD. A first boundary region (depletion layer) is formed between the channel region SCC and the source region SCS, and a second boundary region (depletion layer) is formed between the channel region SCC and the drain region SCD. In this embodiment, the term “layer” is used as a concept including a film or a film.

FIG. 2 is an enlarged sectional view showing a part of the thin film transistor TR. As shown in FIGS. 1 and 2, a gate insulating film 12 is formed on the channel region SCC of the oxide semiconductor layer SC. The gate insulating film 12 is not formed on the source region SCS and the drain region SCD of the oxide semiconductor layer SC, and is exposed. Such a gate insulating film 12 includes a silicon oxide layer mainly composed of silicon oxide (SiO _x ). In the present embodiment, the entire gate insulating film 12 is formed of a silicon oxide layer. Note that the gate insulating film 12 may be a stacked film of a silicon oxide layer containing silicon oxide (SiO _x ) as a main component and another insulating layer. Even in the case of using a stacked film, the gate insulating film is preferably formed so that the silicon oxide layer is in contact with the channel region SCC of the oxide semiconductor layer SC.

Both side surfaces of the gate insulating film 12 are positioned substantially aligned with both end surfaces of the channel region SCC in the channel length direction, and are exposed to the oxide semiconductor layer SC. As will be described later, both side surfaces of the gate insulating film 12 are nitrided and impregnated with nitrogen (N ₂ ). As a result, a region near both side surfaces forms a nitride region (block region) 12a containing nitride.

  The gate electrode GE constituting the thin film transistor TR is formed on the gate insulating film 12 and is located above the channel region SCC of the oxide semiconductor layer SC. The gate electrode GE is made of a material having a sufficiently low contact resistance with the gate insulating film 12, for example, copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta). ), Chromium (Cr) or the like, or an alloy containing these metal materials. For example, the gate electrode GE is electrically connected to a gate wiring (not shown) provided in the same layer as the gate electrode GE or a control wiring of a drive circuit.

The source region SCS, the drain region SCD, and the gate electrode GE of the oxide semiconductor layer SC are covered with an interlayer insulating layer (third insulating layer) 13. The interlayer insulating layer 13 also covers the side surfaces of the gate insulating film 12 and the surface of the undercoat layer 11. As a material for forming the interlayer insulating layer 13, silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), silicon nitride (SiN _x ), or the like can be used.

  The source electrode SE and the drain electrode DE constituting the thin film transistor TR are formed on the interlayer insulating layer 13. The source electrode SE is in contact with the source region SCS of the oxide semiconductor layer SC through a contact hole CH1 that penetrates the interlayer insulating layer 13. The drain electrode DE is in contact with the drain region SCD of the oxide semiconductor layer SC through a contact hole CH2 that penetrates the interlayer insulating layer 13. These source electrode SE and drain electrode DE are, for example, any one of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), and chromium (Cr). These metal materials or an alloy containing at least one of them is formed.

  The source electrode SE and the drain electrode DE of the thin film transistor TR constituting the display pixel are connected to a source wiring and a pixel electrode (not shown), respectively. The source electrode SE and the drain electrode DE of the thin film transistor TR constituting the drive circuit are respectively connected to control wirings of the drive circuit (not shown).

  The array substrate SUB1 having such a structure may have its surface, that is, the source electrode SE and the drain electrode DE, and the interlayer insulating layer 13 covered with a protective film (not shown).

  Next, an example of a method for manufacturing the array substrate SUB1 applied to the display device of the present embodiment will be described.

First, as illustrated in FIG. 3A, the undercoat layer 11 is formed on the inner surface 10 </ b> A of the insulating substrate 10. Thereafter, an oxide semiconductor material is formed on the undercoat layer 11 and then patterned into island shapes to form a plurality of oxide semiconductor layers SC. Here, a transparent glass substrate was used as the insulating substrate 10. The undercoat layer 11 is formed of silicon oxide (SiO _x ) using, for example, a plasma CVD (Chemical Vapor Deposition) method. The oxide semiconductor layer SC is formed, for example, by forming a semiconductor layer made of indium gallium zinc oxide (IGZO) on the undercoat layer 11 using a sputtering method or the like and then patterning the semiconductor layer into an island shape. Formed. Although not shown, a pixel electrode is simultaneously formed on the undercoat layer 11 when forming the oxide semiconductor layer SC.

Subsequently, as illustrated in FIG. 3B, a gate insulating layer 12B for forming the gate insulating film 12 is formed over the oxide semiconductor layer SC. In the illustrated example, the gate insulating layer 12B is also formed on the undercoat layer 11 where the oxide semiconductor layer SC is not formed. The gate insulating layer 12B is formed of silicon oxide (SiO _x ) using, for example, a plasma CVD method.

Next, as shown in FIG. 3C, thermal annealing is performed in an atmosphere containing at least oxygen (O ₂ ). Here, thermal annealing is performed after the formation of the gate insulating layer 12B, but it may be performed in another process.

Thereafter, as shown in FIG. 4A, a gate layer GA for forming a gate electrode GE is formed on the gate insulating layer 12B. The gate layer GA was formed using a sputtering method or the like.
Subsequently, as shown in FIG. 4B, a resist pattern 20 is formed on the gate layer GA. The resist pattern 20 is formed by, for example, a photosensitive resin. Such a resist pattern 20 is located immediately above a region where the oxide semiconductor layer SC should maintain a high resistance state, that is, a region where the channel region SCC is formed, and has a low resistance in the oxide semiconductor layer SC. It is not arranged immediately above the region, that is, the region where the source region SCS and the drain region SCD are formed.

  Next, as shown in FIG. 4C, the gate insulating layer 12B and the gate layer GA are collectively patterned using the resist pattern 20 as a mask to form the gate insulating film 12 and the gate electrode GE, and the oxidation is performed. The regions to be the source region SCS and the drain region SCD of the physical semiconductor layer SC are exposed. Thereafter, the resist pattern 20 is removed.

For patterning of the gate insulating layer 12B and the gate layer GA, a reactive ion etching method (RIE) which is a kind of plasma dry etching method was used. At this time, as the etching gas, a gas containing at least reducing fluorine or a gas containing at least reducing fluorine and hydrogen can be used. Specifically, examples of the gas containing at least fluorine include a mixed gas of tetrafluoromethane (CF ₄ ) and oxygen (O ₂ ). Further, examples of the gas containing at least fluorine and hydrogen include a mixed gas of perfluorocyclobutane (C ₄ F ₈ ), hydrogen (H ₂ ), and argon (Ar).

  When patterning the gate insulating layer 12B and the gate layer GA, the gate insulating layer 12B is etched by a plasma dry etching method using a gas containing at least fluorine, thereby forming an oxide semiconductor layer to be a source region and a drain region. It is possible to expose the SC and reduce the exposed oxide semiconductor layer SC to assist in lowering the resistance.

  As described above, although the resistance value of the oxide semiconductor layer SC varies depending on the gas conditions used for dry etching, the resistance value of the exposed portion of the oxide semiconductor layer SC in this process is supplemented so as to be 1E10Ω / □ or less. By reducing the resistance, it is possible to reduce the burden during the process of reducing the resistance in the subsequent steps.

Next, as shown in FIG. 5A, the exposed oxide semiconductor layer SC and both side surfaces of the gate gate insulating film 12 are exposed to a gas containing at least ammonia (NH ₃ ). For example, plasma containing at least ammonia (NH ₃ ) gas is applied to both sides of the exposed oxide semiconductor layer SC and the gate insulating film 12. By exposing the exposed oxide semiconductor layer SC to a gas containing ammonia (NH ₃ ), the oxide semiconductor layer SC is reduced by hydrogen (H ₂ ), and the resistance is reduced. That is, low resistance regions are formed on both sides of a region maintained in a relatively high resistance state. The low resistance regions correspond to the source region SCS and the drain region SCD, respectively, and the high resistance region between them corresponds to the channel region SCC. Here, the resistance value of the source region SCS and the drain region SCD in the oxide semiconductor layer SC is, for example, 4 kΩ / □ due to the low resistance treatment.
At the same time, both side surfaces of the gate insulating film 12 are nitrided with ammonia (NH ₃ ) gas, and a region near the side surface forms a nitride region (block region) 12a made of SiO _x N _y containing nitrogen. As described above, both the side surfaces of the gate insulating film 12 can be nitrided simultaneously with the resistance reduction process (process) of the oxide semiconductor layer SC.

Subsequently, as shown in FIG. 5B, the gate electrode GE, the gate insulating film 12, the oxide semiconductor layer SC exposed from the gate insulating film 12, and the undercoat layer in which the oxide semiconductor layer SC is not formed An interlayer insulating layer 13 was formed on 11. The interlayer insulating layer 13 is formed of silicon oxide (SiO _x ) using, for example, a plasma CVD method.

If a material having a relatively high hydrogen content is used for the interlayer insulating layer 13 even in silicon oxide (SiO _x ), hydrogen diffuses to the channel region SCC of the oxide semiconductor layer SC in a later process, and the TFT characteristics greatly vary. Resulting in. Therefore, it is desirable to use silicon oxide (SiO _x ) with a low hydrogen content.

  Next, as shown in FIG. 5C, the first contact hole CH1 reaching the source region SCS of the oxide semiconductor layer SC and the second contact hole CH2 reaching the drain region SCD are formed in the interlayer insulating film 13, respectively. Form. The first contact hole CH1 and the second contact hole CH2 were formed by reactive ion etching (RIE) using a resist pattern not described in detail as a mask. At this time, a gas containing at least fluorine was used as the etching gas. For this reason, it becomes possible to suppress the resistance increase due to the etching gas in a part of the source region SCS exposed from the first contact hole CH1 and a part of the drain region SCD exposed from the second contact hole CH2.

Subsequently, as shown in FIG. 5D, a source electrode SE that contacts the source region SCS from the first contact hole CH1 and a drain electrode DE that contacts the drain region SCD from the second contact hole CH2 are formed. The source electrode SE and the drain electrode DE were formed by forming a metal film on the interlayer insulating layer 13 using a sputtering method or the like and then patterning the metal film. As the metal film, for example, a laminated film of molybdenum (Mo), aluminum (Al), titanium (Ti), or the like can be used.
Through the above steps, the array substrate SUB1 including the thin film transistor TR is manufactured.

According to the display device configured as described above, it is possible to form the thin film transistor TR using the oxide semiconductor layer SC as the semiconductor layer and adopting the top gate structure. Both side portions of the gate insulating film 12 exposed to the oxide semiconductor layer SC and the gate electrode GE are nitrided to form a nitride region 12a containing nitrogen. The nitride region 12a functions as a block region for trapping hydrogen (H ⁺ ) that attempts to enter the gate insulating film 12. Thereby, the increase of hydrogen ions in the gate insulating film 12 and the accompanying decrease in resistance of the channel region SCC can be suppressed, and fluctuations in the threshold voltage can be prevented. Therefore, for example, even when a gate bias temperature stress is applied, variation in threshold voltage can be reduced, and a thin film transistor having stable transistor characteristics can be obtained.
Further, the nitriding treatment of the gate insulating film can be performed simultaneously with the resistance reduction processing of the oxide semiconductor layer, and the nitriding treatment of the gate insulating film can be performed without increasing the number of manufacturing steps.
As described above, according to the present embodiment, it is possible to provide a display device that can reduce the shift of the threshold voltage of the thin film transistor and a method for manufacturing the display device.

  The display device including the above-described thin film transistor is applied to various flat panel display devices such as a liquid crystal display device, an organic EL display device, another self-luminous display device, or an electronic paper display device having an electrophoretic element. can do. Further, it goes without saying that the same configuration or manufacturing process as that of the above embodiment can be applied without any particular limitation from a small-sized display device to a large-sized display device.

  Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  All configurations and manufacturing steps that can be implemented by those skilled in the art based on the configurations and manufacturing steps described above as the embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to. In addition, it is understood that other functions and effects brought about by the above-described embodiment are apparent from the description of the present specification or can be appropriately conceived by those skilled in the art to be brought about by the present invention.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... Insulating substrate, 11 ... Undercoat layer (1st insulating layer),
12 ... Gate insulating film (second insulating layer), 12a ... Nitride region (block region),
13 ... Interlayer insulating film (third insulating layer), SUB1 ... Array substrate,
TR ... thin film transistor, GE ... gate electrode, SC ... oxide semiconductor layer,
SCC ... channel region, SCS ... source region, SCD ... drain region,
SE ... Source electrode, DE ... Drain electrode, CH1, CH2 ... Contact hole

Claims (6)

An insulating substrate, and a thin film transistor provided on the insulating substrate,
The thin film transistor
An oxide semiconductor layer having a channel region and a source region and a drain region respectively provided on both sides of the channel region;
A gate electrode provided on a side opposite to the insulating substrate and facing a channel region of the oxide semiconductor layer;
A gate insulating film that is provided between the channel region and the gate electrode and includes a silicon oxide layer containing silicon oxide as a main component, and nitrided in the vicinity of a side surface exposed to the outside of the oxide semiconductor layer and the gate electrode A gate insulating film having a nitride region containing a material;
A source electrode in contact with the source region;
A drain electrode in contact with the drain region;
A display device comprising:   The display device according to claim 1, wherein the oxide semiconductor layer is formed of an oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn).   3. The display device according to claim 1, wherein the gate insulating film is provided with the silicon oxide layer in contact with the channel region, and has a nitride region in the vicinity of both side surfaces where the silicon oxide layer is exposed. Forming an oxide semiconductor layer over an insulating substrate;
Forming a gate insulating layer including a silicon oxide layer containing silicon oxide as a main component over the oxide semiconductor layer;
Forming a gate layer on the gate insulating layer;
Forming a resist pattern on the gate layer;
Using the resist pattern as a mask, the gate insulating layer and the gate layer are patterned to form a gate insulating film and a gate electrode on the gate insulating film, and a side surface of the gate insulating film, and a source region and a drain region Exposing the oxide semiconductor layer to be
The exposed side surface of the gate insulating film and the oxide semiconductor layer are exposed to a gas containing at least ammonia (NH ₃ ) to reduce the resistance of the source region and the drain region and nitride near the side surface of the gate insulating film. Forming a nitrided region containing matter,
Forming an interlayer insulating film on the gate electrode and the oxide semiconductor layer;
Forming first and second contact holes reaching the source region and the drain region, respectively, in the interlayer insulating film;
A method for manufacturing a display device, comprising: forming a source electrode in contact with the source region from the first contact hole and a drain electrode in contact with the drain region from the second contact hole on the interlayer insulating film.   The method for manufacturing a display device according to claim 4, wherein the oxide semiconductor layer is formed using an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). A plasma containing ammonia (NH ₃ ) gas is applied to the exposed side surfaces of the oxide semiconductor layer and the gate insulating film to reduce the oxide semiconductor layer and nitride a side region of the gate insulating film. Item 6. A method for manufacturing a display device according to Item 4 or 5.

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