JP5658978B2 - Thin film transistor circuit board and manufacturing method thereof - Google Patents

Description

  Embodiments described herein relate generally to a thin film transistor circuit board and a method for manufacturing the same.

  Thin film transistors (hereinafter sometimes referred to simply as TFTs) are widely used in various flat display devices such as liquid crystal display devices and organic electroluminescence display devices.

Amorphous silicon TFTs used in large flat display devices have a relatively low mobility of about 1 cm ² / (V · s), but are easy to form uniformly over a large area and are low in cost. There are advantages such as. However, in recent years, there has been a demand for larger size and higher definition, and active matrix type organic EL display devices that require a large driving current have been developed. Low cost, high uniformity, high reliability, high mobility New active materials are needed.

  Recently, an oxide semiconductor has attracted attention as a material applicable to a channel layer of a TFT. For example, TFTs using a transparent and conductive oxide semiconductor thin film mainly composed of zinc oxide (ZnO) as a channel layer are being actively developed. Such an oxide semiconductor thin film can be formed over a large area at a relatively low temperature, and can achieve higher mobility than amorphous silicon. For example, a TFT using an In—Ga—Zn—O-based (hereinafter referred to as IGZO) amorphous oxide has received the most attention.

  In general, the structure of an IGZO-TFT is mainly an inverted staggered bottom gate structure. However, the TFT having such a structure has a problem that the channel length cannot be reduced, and it is difficult to reduce the circuit area and to improve the performance (improve the ON current).

  Further, in the TFT having such a structure, it is necessary to protect the back channel side. If the back channel side is not protected, the amount of oxygen in the channel region of the oxide semiconductor thin film fluctuates in the process after the TFT formation, resulting in unstable transistor characteristics. Specifically, the channel region becomes a resistor, and it is likely to cause a problem that it does not function as a switching element or the threshold voltage of the thin film transistor greatly fluctuates.

JP 2010-182818 A

  An object of the present embodiment is to provide a thin film transistor circuit substrate capable of reducing manufacturing costs and obtaining stable transistor characteristics, and a method for manufacturing the same.

According to this embodiment,
An oxide semiconductor thin film is formed on an insulating substrate, a gate insulating layer is formed on the oxide semiconductor thin film, a gate layer is formed on the gate insulating layer, and a resist pattern is formed on the gate layer. Then, using the resist pattern as a mask, the gate insulating layer and the gate layer are collectively patterned to form a gate electrode on the gate insulating film, and the oxide semiconductor thin film to be a source region and a drain region The exposed oxide semiconductor thin film is exposed to a gas containing at least silane (SiH ₄ ), and after being exposed to the gas containing silane, an interlayer insulating film is continuously formed. First and second contact holes reaching the source region and the drain region, respectively, are formed, and the source is formed from the first contact hole. Source electrode in contact with the band, and the second to form a drain electrode that contacts the drain region from the contact hole, a thin film transistor circuit substrate manufacturing method characterized in that there is provided.

According to this embodiment,
An oxide semiconductor thin film formed on an insulating substrate and having a channel region, a source region and a drain region on both sides of the channel region, and the source region and the oxide region formed on the channel region of the oxide semiconductor thin film A gate insulating film exposing the drain region, a gate electrode formed on the gate insulating film, and covering the oxide semiconductor thin film, the gate insulating film, and the gate electrode, and reaching the source region An interlayer insulating film having a first contact hole to be formed and a second contact hole reaching the drain region; a source electrode in contact with the source region from the first contact hole; and a drain from the second contact hole to the drain A drain electrode in contact with the region, and the oxide semiconductor thin film Te, the source region and the drain region, the upper surface side than the bottom side TFT circuit board, which is a low resistance is provided.

FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor circuit substrate 1 in the present embodiment. FIG. 2 is a view for explaining a method of manufacturing the thin film transistor circuit substrate 1 in the present embodiment. FIG. 3 is a diagram for explaining a method of manufacturing the thin film transistor circuit substrate 1 in the present embodiment. FIG. 4 is a diagram for explaining a method of manufacturing the thin film transistor circuit substrate 1 in the present embodiment. FIG. 5 is a view for explaining a method of manufacturing the thin film transistor circuit substrate 1 in the present embodiment. FIG. 6 is a diagram illustrating an example of measurement results of the gas species to which the oxide semiconductor thin film is exposed and the resistance value of the oxide semiconductor thin film after being exposed to the gas species. FIG. 7 is an enlarged schematic cross-sectional view of an oxide semiconductor thin film of a thin film transistor manufactured by the manufacturing method of this embodiment. FIG. 8 is a diagram illustrating an example of transistor characteristics (IV characteristics) of the thin film transistor manufactured by the manufacturing method of the present embodiment. FIG. 9 is a diagram illustrating an example of transistor characteristics of a thin film transistor manufactured by the manufacturing method of the comparative example.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor circuit substrate 1 in the present embodiment.

  That is, the thin film transistor circuit substrate 1 is formed by using an insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The thin film transistor circuit substrate 1 includes a thin film transistor A formed on an insulating substrate 10. In the illustrated example, the thin film transistor circuit substrate 1 includes a pixel electrode PE constituting a liquid crystal display element or an organic electroluminescence element.

  An undercoat layer 11 is formed on the insulating substrate 10. The undercoat layer 11 is made of, for example, silicon oxide (SiO). On the undercoat layer 11, an oxide semiconductor thin film SC constituting the thin film transistor A is formed. Further, the pixel electrode PE is formed on the undercoat layer 11 similarly to the oxide semiconductor thin film SC.

  Such an oxide semiconductor thin film SC and the pixel electrode PE are formed of an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn), for example. As typical examples of forming the oxide semiconductor thin film SC, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), zinc oxide tin (ZnSnO), and zinc oxide (ZnO). ) And the like.

  The oxide semiconductor thin film SC includes a channel region SCC having a relatively high resistance, and a source region SCS and a drain region SCD that are lower in resistance than the channel region SCC and located on both sides of the channel region SCC. doing.

  A gate insulating film 12 is formed on the channel region SCC of the oxide semiconductor thin film SC. The gate insulating film 12 is not formed on the source region SCS and the drain region SCD of the oxide semiconductor thin film SC, but exposes them. Further, the gate insulating film 12 is not formed on the undercoat layer 11 and the pixel electrode PE. Such a gate insulating film 12 is formed of, for example, silicon oxide (SiO).

  The gate electrode G constituting the thin film transistor A is formed on the gate insulating film 12 and is located above the channel region SCC of the oxide semiconductor thin film SC. The gate electrode G is, for example, one of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), chromium (Cr), or any of these. It is formed of an alloy containing at least one.

  The oxide semiconductor thin film SC, the gate insulating film 12, and the gate electrode G are covered with an interlayer insulating film 13. This interlayer insulating film 13 is also disposed on the undercoat layer 11. In the interlayer insulating film 13, a first contact hole CH1 reaching the source region SCS of the oxide semiconductor thin film SC and a second contact hole CH2 reaching the drain region SCD are formed.

  The source electrode S and the drain electrode D constituting the thin film transistor A are formed on the interlayer insulating film 13. The source electrode S is in contact with the source region SCS of the oxide semiconductor thin film SC from the first contact hole CH1 that penetrates the interlayer insulating film 13. The drain electrode D is in contact with the drain region SCD of the oxide semiconductor thin film SC from the second contact hole that penetrates the interlayer insulating film 13. These source electrode S and drain electrode D are, for example, any one of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), and chromium (Cr). Or it is formed with the alloy containing at least 1 of these.

  The surface of the thin film transistor circuit substrate 1 having such a structure, that is, the source electrode S and the drain electrode D, and the interlayer insulating film 13 may be covered with a protective film (not shown).

  Next, an example of the method for manufacturing the thin film transistor circuit substrate 1 of the present embodiment will be described.

  First, as shown in FIG. 2A, after forming the undercoat layer 11 on the insulating substrate 10, the oxide semiconductor thin film SC is formed. Here, a transparent glass substrate was prepared as the insulating substrate 10. The undercoat layer 11 is formed of silicon oxide (SiO) using, for example, a plasma CVD (Chemical Vapor Deposition) method.

  The oxide semiconductor thin film SC was formed, for example, by forming a semiconductor layer made of indium gallium zinc oxide (IGZO) on the undercoat layer 11 using a sputtering method or the like and then patterning the semiconductor layer. When forming such an oxide semiconductor thin film SC, a condition was selected in which the initial resistance value of the oxide semiconductor thin film SC was 1E10Ω / □ or more. Although not shown, when the oxide semiconductor thin film SC is formed, the pixel electrode PE is also formed on the undercoat layer 11 at the same time.

  Subsequently, as shown in FIG. 2B, a gate insulating layer 12A for forming the gate insulating film 12 is formed on the oxide semiconductor thin film SC. In the illustrated example, the gate insulating layer 12A is also formed on the undercoat layer 11 where the oxide semiconductor thin film SC is not formed. The gate insulating layer 12A is formed of silicon oxide (SiO) using, for example, a plasma CVD method.

As a condition for forming the gate insulating layer 12A, at least in the initial stage of formation, a mixed gas containing at least silane (SiH ₄ ) and nitrous oxide (N ₂ O) is introduced, and the SiH ₄ / N ₂ O flow rate ratio is 1. % Or less. As an example, _SiH 4 / _{N 2} O flow ratio _{is SiH 4 / N 2 O = 15} / 2000sccm = 0.75%, pressure during formation by regulating the 120 Pa, the temperature during film formation was made 270 ° C. .

  When forming the gate insulating layer 12A covering the oxide semiconductor thin film SC, it is important to reduce the contact between the silane gas and the oxide semiconductor thin film SC as much as possible. That is, by setting the silane gas ratio to be relatively small, reduction by the silane gas on the surface of the oxide semiconductor thin film SC can be suppressed, and a reduction in resistance of the oxide semiconductor thin film SC can be suppressed. As a result, the oxide semiconductor thin film SC covered with the gate insulating layer 12A may be slightly lower in resistance than the initial resistance value, but is maintained in a relatively high resistance state.

  Subsequently, as shown in FIG. 2C, a gate layer GA for forming the gate electrode G is formed on the gate insulating layer 12A. The gate layer GA was formed using a sputtering method or the like.

  Subsequently, as shown in FIG. 3D, a resist pattern 20 is formed on the gate layer GA. The resist pattern 20 is made of, for example, a photosensitive resin. Such a resist pattern 20 is located in a region where a high resistance state is to be maintained in the oxide semiconductor thin film SC, that is, immediately above a region where a channel region is formed, and the resistance is reduced in the oxide semiconductor thin film SC. In other words, it is not arranged immediately above the region where the source region and the drain region are formed.

  Subsequently, as shown in FIG. 3E, the gate insulating layer 12A and the gate layer GA are collectively patterned using the resist pattern 20 as a mask to form the gate electrode G on the gate insulating film 12. At the same time, the oxide semiconductor thin film SC that becomes the source region and the drain region is exposed. Thereafter, the resist pattern 20 is removed.

For patterning of the gate insulating layer 12A and the gate layer GA, a reactive ion etching method (RIE), which is a kind of plasma dry etching method, was used. At this time, as the etching gas, a gas containing at least reducing fluorine or a gas containing at least reducing fluorine and hydrogen can be used. Specifically, examples of the gas containing at least fluorine include a mixed gas of tetrafluoromethane (CF ₄ ) and oxygen (O ₂ ). Examples of the gas containing at least fluorine and hydrogen include a mixed gas of perfluorocyclobutane (C ₄ F ₈ ), hydrogen (H ₂ ), and argon (Ar).

  When patterning the gate insulating layer 12A and the gate layer GA, an oxide semiconductor thin film that becomes a source region and a drain region by etching the gate insulating layer 12A by a plasma dry etching method using a gas containing at least fluorine. In addition to exposing the SC, the exposed oxide semiconductor thin film SC can be reduced to assist in lowering the resistance.

  As described above, although the resistance value of the oxide semiconductor thin film SC varies depending on the gas conditions used for dry etching, the resistance value of the exposed portion of the oxide semiconductor thin film SC in this process is supplemented so as to be 1E10Ω / □ or less. By reducing the resistance, it is possible to reduce the burden during the process of reducing the resistance in the subsequent steps.

Subsequently, as shown in FIG. 3F, thermal annealing is performed in an atmosphere containing at least oxygen (O ₂ ). Here, thermal annealing was performed for 1 hour at a temperature of 300 ° C. in a mixed gas atmosphere of oxygen (O ₂ ) and nitrogen (N ₂ ). The mixing ratio of oxygen (O ₂ ) and nitrogen (N ₂ ) was, for example, 5: 1 of O ₂ : N ₂ =. Further, the temperature range of this thermal annealing is preferably in the range of 250 ° C to 340 ° C. In such thermal annealing, by using an atmosphere containing at least oxygen gas, oxygen vacancies in the oxide semiconductor thin film SC can be prevented and a change in resistance value can be suppressed.

Subsequently, as shown in FIG. 4G, the exposed oxide semiconductor thin film SC is exposed to a gas containing at least silane (SiH ₄ ), and after being exposed to the gas containing silane, the interlayer is continuously formed. An insulating film 13 is formed. In the illustrated example, the interlayer insulating film 13 includes the gate electrode G, the gate insulating film 12, the oxide semiconductor thin film SC exposed from the gate insulating film 12, and the undercoat layer 11 where the oxide semiconductor thin film SC is not formed. Also formed on top. The interlayer insulating film 13 is formed of silicon oxide (SiO) using, for example, a plasma CVD method.

In performing the plasma CVD method for forming such an interlayer insulating film 13, first, only silane (SiH ₄ ) gas or silane (SiH ₄ ), nitrous oxide (N ₂ O), and argon ( A mixed gas containing Ar) is introduced, adjusted to a desired pressure, and treated for 120 seconds. When only silane gas is introduced, a gas used for forming the silicon oxide (SiO) interlayer insulating film 13 is further introduced. Alternatively, when a mixed gas of silane, nitrous oxide, and argon is introduced, it is not necessary to introduce additional gas. Thus, the gas necessary for forming the interlayer insulating film 13 is introduced and the flow rate thereof is adjusted.

The step of “exposing the exposed oxide semiconductor thin film SC to a gas containing at least silane (SiH ₄ )” is performed at the time of pressure adjustment of the gas before the formation of the interlayer insulating film 13 by the plasma CVD method. Is called. That is, the process of reducing the resistance of the oxide semiconductor thin film SC is performed in a preparation stage (at the time of gas pressure adjustment) before the interlayer insulating film 13 is formed. For this reason, the process only for the purpose of reducing resistance is not required.

  When the exposed oxide semiconductor thin film SC is exposed to a gas containing silane, the oxide semiconductor thin film SC is reduced by silane and the resistance is reduced. That is, low resistance regions are formed on both sides of a region maintained in a relatively high resistance state. The low resistance regions correspond to the source region SCS and the drain region SCD, respectively, and the high resistance region between them corresponds to the channel region SCC. Here, the resistance value of the source region SCS and the drain region SCD in the oxide semiconductor thin film SC became 4 kΩ / □ by being exposed to a gas containing silane.

Then, after the pressure adjustment of the gas necessary for forming the interlayer insulating film 13 is completed, the interlayer insulating film 13 made of silicon oxide is formed by introducing power to excite the gas into a plasma state. As an example of the conditions for forming the interlayer insulating film 13, the SiH ₄ / N ₂ O / Ar flow rate ratio is SiH ₄ / N ₂ O / Ar = 50/1600/450 sccm, and the temperature during formation is 250 ° C. . The temperature range for forming the interlayer insulating film 13 is preferably in the range of 200 ° C to 300 ° C. In order to obtain the denseness required for the interlayer insulating film 13, a lower limit of the temperature range is required to be 200 ° C. or higher. On the other hand, in order to avoid an increase in resistance due to deoxidation of the oxide semiconductor thin film SC, particularly from the channel region SCC, the upper limit of the temperature range needs to be 300 ° C. or lower.

  When a material having a relatively high hydrogen content is used for the interlayer insulating film 13 such as silicon nitride (SiN) or silicon oxide (SiO), hydrogen diffuses to the channel region SCC of the oxide semiconductor thin film SC in a later step. Therefore, it is desirable to use silicon oxide (SiO) having a low hydrogen content because TFT characteristics greatly vary.

  Subsequently, as shown in FIG. 4H, the interlayer insulating film 13 reaches the first contact hole CH1 reaching the source region SCS of the oxide semiconductor thin film SC and the drain region SCD of the oxide semiconductor thin film SC. Second contact holes CH2 to be formed are respectively formed. The first contact hole CH1 and the second contact hole CH2 are formed by reactive ion etching (RIE) using a resist pattern not described in detail as a mask. At this time, a gas containing at least fluorine was used as the etching gas. For this reason, it becomes possible to suppress the resistance increase due to the etching gas in a part of the source region SCS exposed from the first contact hole CH1 and a part of the drain region SCD exposed from the second contact hole CH2.

  Subsequently, as shown in FIG. 4I, the source electrode S that is in contact with the source region SCS from the first contact hole CH1, and the drain electrode D that is in contact with the drain region SCD from the second contact hole CH2 are formed. To do. These source electrode S and drain electrode D were formed by forming a metal film by sputtering or the like and then patterning the metal film. For example, the metal film is a laminated film of molybdenum (Mo), aluminum (Al), titanium (Ti), or the like.

  Through the above steps, the thin film transistor circuit substrate 1 including the thin film transistor A is manufactured.

In the method of manufacturing the thin film transistor circuit substrate 1 described above, as shown in FIG. 3F, after the gate insulating layer 12A and the gate layer GA are patterned, thermal annealing is performed in an atmosphere containing at least oxygen (O ₂ ). Instead, after the gate insulating layer 12A shown in FIG. 2B is formed and before the gate layer GA shown in FIG. 2C is formed, thermal annealing is performed in a nitrogen atmosphere. May be performed.

That is, as shown in FIG. 5, thermal annealing is performed for one hour at a temperature of 320 ° C. in a nitrogen (N ₂ ) atmosphere with the oxide semiconductor thin film SC not exposed from the gate insulating layer 12A. Since the oxide semiconductor thin film SC is annealed in a state protected by the gate insulating layer 12A, nonuniformity does not occur in the oxide semiconductor thin film SC, and defect recovery is performed.

  In this case, the thermal annealing in FIG. 3F can be omitted. The subsequent steps are as described above.

  As described above, the thin film transistor A manufactured in the present embodiment has a coplanar type top gate structure, which can reduce the channel length and improve the performance, and the gate insulating film 12 and the gate over the channel region SCC. Since it is covered with the electrode G or the like, there is an advantage that a change in film quality of the channel region SCC can be suppressed. On the other hand, in the oxide semiconductor thin film SC, the channel region SCC maintains a high resistance, and a region that becomes a source region SCS from the channel region SCC to the source electrode S and a drain region SCD from the channel region SCC to the drain electrode D are formed. It is necessary to reduce the resistance.

  In the present embodiment, the reducing silane gas used in the process of forming the interlayer insulating film 13 covering these regions in the state where the source region SCS and the drain region SCD are to be formed is exposed in the oxide semiconductor thin film SC. It is possible to reduce the resistance to 10 kΩ / □ or less by exposing to. As described above, since the resistance reduction process is performed at the time of gas pressure adjustment in the process of forming the interlayer insulating film 13, another process such as a hydrogen plasma process is added only for the resistance reduction of the oxide semiconductor thin film SC. This makes it possible to simplify the process. Therefore, the manufacturing cost can be reduced.

  Further, when patterning the gate insulating layer 12A and the gate layer GA, by using a reducing fluorine gas or a mixed gas containing fluorine and hydrogen as a gas species applied by the plasma dry etching method, a favorable shape after etching is obtained. Further, the resistance of the exposed oxide semiconductor thin film SC can be reduced, and the subsequent resistance reduction treatment can be easily performed.

  FIG. 6 is a diagram illustrating an example of measurement results of the gas species to which the oxide semiconductor thin film SC is exposed and the resistance value of the oxide semiconductor thin film SC after being exposed to the gas species.

Here, as the oxide semiconductor thin film SC, IGZO having a film thickness of 50 nm and an initial resistance value of 5E12Ω / □ was formed on a glass substrate and exposed to each gas type. “Silane (SiH ₄ ) gas flow only” corresponds to the plasma CVD process in FIG. 4G described in the present embodiment, and corresponds to a so-called hydrogen plasma treatment (“H ₂ gas, with plasma discharge”). It was confirmed that the resistance value of the oxide semiconductor thin film SC can be reduced to a level equivalent to that in the case of (1). “Silane (SiH ₄ ) / nitrous oxide (N ₂ O) / argon (Ar) gas flow only” also corresponds to the step (G) of FIG. 4 described in this embodiment, and the oxide semiconductor thin film It was confirmed that the resistance value of SC can be reduced.

Also, “tetrafluoromethane (CF ₄ ) / oxygen (O ₂ ) gas, with plasma discharge” or “perfluorocyclobutane (C ₄ F ₈ ) / hydrogen (H ₂ ) / argon (Ar) gas, with plasma discharge "Corresponds to the plasma dry etching step of FIG. 3E described in the present embodiment, and it was confirmed that the resistance of the oxide semiconductor thin film SC can be auxiliary reduced.

  In the present embodiment, at least in the initial stage of forming the gate insulating layer 12A, the resistance of the oxide semiconductor thin film SC including the region serving as the channel region is suppressed by setting the conditions with a small amount of silane gas. Is possible.

  In addition, after forming the gate insulating layer 12A and before patterning the gate insulating layer 12A (that is, in a state where the regions to be the source region and the drain region of the oxide semiconductor thin film SC are not exposed), a nitrogen atmosphere is used. A region that becomes a channel region of the oxide semiconductor thin film SC by performing thermal annealing or by performing thermal annealing in an atmosphere containing oxygen after exposing the regions that become the source region and the drain region of the oxide semiconductor thin film SC. As a result, it is possible to reduce defects at the interface between the oxide semiconductor thin film SC and the gate insulating film 12. For this reason, fluctuations in the film quality (mainly oxygen vacancies in the film) of the oxide semiconductor thin film SC during the process can be suppressed, and the transistor characteristics can be stabilized.

  Further, the interlayer insulating film 13 is formed using a material having a low hydrogen content, thereby reducing hydrogen diffusion in a thermal annealing process performed in a subsequent process for forming a liquid crystal display device, an organic EL display device, or the like. Thus, the resistance change in the channel region SCC of the oxide semiconductor thin film SC can be suppressed, and the transistor characteristics can be stabilized.

  The thin film transistor circuit substrate 1 formed through the steps (A) to (I) described above is then incorporated into a display device through a manufacturing process of a liquid crystal display element or an organic electroluminescence element. The thin film transistor circuit substrate formed by using the above-described steps (A) to (I), although a heating process at around 250 ° C. may be performed in a step after the step (I) in a step of forming a flat layer or the like. According to this, the oxide semiconductor thin film SC is stabilized, and it is possible to suppress fluctuations in transistor characteristics.

  Next, a characteristic structure of the thin film transistor A manufactured by the manufacturing method of this embodiment will be described.

  FIG. 7 is an enlarged schematic cross-sectional view of the oxide semiconductor thin film SC of the thin film transistor A manufactured by the manufacturing method of the present embodiment.

  That is, in the oxide semiconductor thin film SC, the source region SCS and the drain region SCD exposed from the gate insulating film 12 have lower resistance on the upper surface side than on the bottom surface side. This is because the oxide semiconductor thin film SC was exposed to silane gas using the gate insulating film 12 or the like as a mask, so that the surface of the oxide semiconductor thin film SC that was in contact with the silane gas was reduced and the oxygen concentration was reduced. That is, the oxygen concentration in the source region SCS and the drain region SCD of the oxide semiconductor thin film SC is higher than the bottom surface in contact with the undercoat layer 11 in the process of being exposed to the silane gas (that is, the interlayer later). The portion covered with the insulating film 13 or in contact with the source electrode S or the drain electrode D) is lower. For this reason, the resistance value on the upper surface side is lower than the resistance value on the bottom surface side. Such a difference in resistance value is a feature of the thin film transistor A manufactured by the manufacturing method of the present embodiment.

  FIG. 8 is a diagram illustrating an example of transistor characteristics (IV characteristics) of the thin film transistor manufactured by the manufacturing method of the present embodiment. In this embodiment, as described above, the source region and the drain region of the oxide semiconductor thin film made of IGZO are formed by silane gas flow. In this case, as shown, it was confirmed that the threshold voltage was substantially constant regardless of the channel length L. As described above, according to the thin film transistor manufactured by the manufacturing method of the present embodiment, the threshold voltage has no channel length dependency, and stable IV characteristics can be obtained.

  FIG. 9 is a diagram illustrating an example of transistor characteristics (IV characteristics) of the thin film transistor manufactured by the manufacturing method of the comparative example. In the comparative example, the source region and the drain region of the oxide semiconductor thin film made of IGZO were formed by hydrogen plasma treatment instead of the silane gas flow. In this case, as shown in the figure, the threshold voltage changes depending on the channel length L, and particularly when the channel length is short, the threshold voltage shifts to the negative side. This is because the resistance of the entire IGZO is reduced and the hydrogen diffusion proceeds to the channel side, making the channel non-uniform.

  Therefore, it is effective to apply the silane gas flow as described in this embodiment when forming the source region and the drain region by the resistance reduction treatment of the oxide semiconductor thin film. In particular, it is extremely effective to apply the manufacturing method described in this embodiment to downsize a thin film transistor having stable transistor characteristics (having a relatively short channel length).

  As described above, according to the present embodiment, it is possible to provide a thin film transistor circuit substrate and a thin film transistor circuit substrate manufacturing method capable of reducing the manufacturing cost and obtaining stable transistor characteristics.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Thin-film transistor circuit board 10 ... Insulating substrate 11 ... Undercoat layer 12 ... Gate insulating film 12A ... Gate insulating layer 13 ... Interlayer insulating film A ... Thin-film transistor SC ... Oxide semiconductor thin film G ... Gate electrode GA ... Gate layer S ... Source electrode D ... Drain electrode

Claims (9)

Forming an oxide semiconductor thin film on an insulating substrate;
Forming a gate insulating layer on the oxide semiconductor thin film;
Forming a gate layer on the gate insulating layer;
Forming a resist pattern on the gate layer;
Using the resist pattern as a mask, the gate insulating layer and the gate layer are collectively patterned to form a gate electrode on the gate insulating film and to expose the oxide semiconductor thin film to be a source region and a drain region. ,
Exposing the exposed oxide semiconductor thin film to a gas containing at least silane (SiH ₄ );
Forming an interlayer insulating film continuously after exposure to the gas containing silane,
Forming first and second contact holes reaching the source region and the drain region, respectively, in the interlayer insulating film;
A method of manufacturing a thin film transistor circuit substrate, comprising: forming a source electrode in contact with the source region from the first contact hole; and a drain electrode in contact with the drain region from the second contact hole.   2. The method of manufacturing a thin film transistor circuit board according to claim 1, wherein the interlayer insulating film is formed of silicon oxide. The interlayer insulating film is formed using a plasma CVD method in which a gas containing at least silane is introduced,
3. The step of exposing the oxide semiconductor thin film to a gas containing at least silane is performed at the time of adjusting the pressure of the gas before the start of the formation of the interlayer insulating film by the plasma CVD method. Manufacturing method of a thin film transistor circuit board. The gate insulating layer is formed using a plasma CVD method,
At least in the initial stage of forming the gate insulating layer, a gas containing at least silane (SiH ₄ ) and nitrous oxide (N ₂ O) is introduced, and the SiH ₄ / N ₂ O flow rate ratio is 1% or less. 4. The method of manufacturing a thin film transistor circuit substrate according to claim 1, wherein:   5. The method of manufacturing a thin film transistor circuit substrate according to claim 1, wherein after the oxide semiconductor thin film is exposed, thermal annealing is performed in an atmosphere containing oxygen. 6.   5. The method of manufacturing a thin film transistor circuit substrate according to claim 1, wherein thermal annealing is performed in a nitrogen atmosphere after forming the gate insulating layer and before forming the gate layer. 6. .   7. The thin film transistor according to claim 1, wherein when patterning the gate insulating layer and the gate layer, the gate insulating layer is etched by a plasma dry etching method with a gas containing at least fluorine. 8. A method of manufacturing a circuit board.   8. The method of manufacturing a thin film transistor circuit board according to claim 7, wherein a mixed gas containing at least fluorine and hydrogen is used in the plasma dry etching.   The oxide semiconductor thin film is formed of an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). A method for producing a thin film transistor circuit board according to claim 1.

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