CN113994458A

CN113994458A - Method of forming inductively coupled high density plasma film for thin film transistor structures

Info

Publication number: CN113994458A
Application number: CN202080044751.7A
Authority: CN
Inventors: 元泰景; 崔寿永; 任东吉; 吴宗凯; 李永东; 桑杰·D·亚达夫; 金正倍; 王志远
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2019-06-17
Filing date: 2020-06-17
Publication date: 2022-01-28
Also published as: JP2022537958A; WO2020257314A1; KR20220020380A; KR102601596B1; CN114008743A; JP2024028772A; KR20220020379A; KR102624643B1; KR20230169244A; WO2020257324A1; JP7394887B2

Abstract

Embodiments of the present disclosure generally relate to a method of fabricating a Thin Film Transistor (TFT). More particularly, embodiments described herein relate to a method of depositing an insulating layer over a metal oxide layer using an inductively coupled plasma high density plasma process to improve electron mobility. The high density plasma comprises greater than 1.0E11/cm³Electron or ion plasma density. N for metal oxide layer₂O gas or N₂And performing pretreatment on inductively coupled plasma formed by the O gas and the argon gas. From SiH₄Gas and N₂An inductively coupled plasma formed from O gas is used to deposit an insulating layer, such as a silicon oxide layer. The silicon oxide layer is an etching stop layer, or the silicon oxide layer is a passivation layer of the TFT structure. The present disclosure is applicable to MO TFT structures and complementary MO TFT and LTPS TFT structures.

Description

Method of forming inductively coupled high density plasma film for thin film transistor structures

Background

FIELD

Embodiments of the present disclosure generally relate to methods of fabricating Thin Film Transistors (TFTs). More particularly, embodiments described herein relate to a method of depositing a layer in a thin film transistor having high electron mobility.

Description of the prior art

Thin Film Transistors (TFTs) are metal oxide semiconductor devices used in integrated circuits and displays to control the operation of pixels. TFTs are of great interest in display applications due to their high resolution, low power consumption, and high speed operation for LCD and OLED displays. Current materials used in the layers making up the TFT typically have limited electron mobility due to the method of depositing the layers relative to each other and to the metal oxide layer of the TFT.

Accordingly, there is a need in the art for improved TFTs and methods of fabricating TFTs. In particular, insulating layers such as passivation layers and etch stop layers for TFTs with lower hydrogen content, higher density, lower wet etch rate and lower plasma damage are needed.

Disclosure of Invention

In one embodiment, a method of forming a thin film transistor is provided that includes depositing a buffer layer over a substrate and forming a gate layer over the buffer layer. A portion of the gate layer is etched to form a gate electrode and a Gate Insulating (GI) layer is deposited over the buffer layer and the gate electrode. A metal oxide layer is deposited over the GI layer. A passivation layer is deposited over the metal oxide layer using high density plasma chemical vapor deposition (HDP CVD) of Inductively Coupled Plasma (ICP). The high density plasma comprises greater than 1.0E11/cm³Electron or ion plasma density.

In another embodiment, a method of fabricating a thin film transistor is provided that includes depositing a buffer layer over a substrate and forming a gate layer at least partially over the buffer layer. A Gate Insulating (GI) layer is deposited over the buffer layer and the gate layer, and a metal oxide layer is deposited over the GI layer. An etch stop layer is deposited using high density plasma chemical vapor deposition (HDP CVD) of Inductively Coupled Plasma (ICP), and a source electrode and a drain electrode are formed in the etch stop layer. A passivation layer is deposited thereon using an Inductively Coupled Plasma (ICP) based or a Capacitively Coupled (CCP) based chemical vapor deposition process such as HDP CVD.

In another embodiment, a method is provided that includes forming a low temperature polysilicon thin film transistor (LTPS TFT) on a substrate and forming a metal oxide thin film transistor (MO TFT) on the substrate. The MO TFT includes a metal oxide channel layer. Metal oxygen in MO TFT by HDP CVD using ICPA silicon oxide layer is deposited over the oxide channel layer and the layers of the LTPS TFT. HDP comprises greater than 1.0E11/cm³Electron or ion plasma density.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

FIG. 1 is a schematic cross-sectional view of a chamber according to an embodiment.

Fig. 2A-2H are schematic cross-sectional views of a metal oxide TFT at various stages of fabrication according to an embodiment.

Fig. 2I is a schematic cross-sectional view of a metal oxide TFT with a passivation layer according to an embodiment.

Fig. 3 is a schematic cross-sectional view of a metal oxide TFT with two passivation layers according to an embodiment.

Fig. 4 is a schematic cross-sectional view of a metal oxide TFT with an Etch Stop Layer (ESL) and a passivation layer according to an embodiment.

Fig. 5 is a schematic cross-sectional view of a metal oxide TFT having two etch stop layers and a passivation layer according to an embodiment.

FIG. 6 is a flow diagram of an example method of fabricating a MO TFT structure in accordance with one embodiment.

Fig. 7A-7G are schematic cross-sectional views of a metal oxide TFT and a Low Temperature Polysilicon (LTPS) TFT at various stages of fabrication, according to an embodiment.

Fig. 7G is a schematic cross-sectional view of MO TFT and LTPS TFT with passivation layers according to an embodiment.

Fig. 8 is a schematic cross-sectional view of MO TFT and LTPS TFT with passivation layer and etch stop layer according to an embodiment.

Fig. 9 is a schematic cross-sectional view of MO TFT and LTPS TFT with passivation layers according to an embodiment.

Fig. 10 is a schematic cross-sectional view of MO TFT and LTPS TFT with an etch stop layer and a passivation layer according to an embodiment.

FIG. 11 is a flow diagram of an example Inductively Coupled Plasma (ICP) High Density Plasma (HDP) process, according to one embodiment.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

The present disclosure generally relates to a method of fabricating a TFT. The TFT has an active channel including a metal oxide such as Indium Gallium Zinc Oxide (IGZO) and/or zinc oxide. One or more passivation layers and/or one or more Etch Stop Layers (ESLs) are disposed over the metal oxide. The interface between the metal oxide and the layer disposed over the metal oxide provides predetermined TFT characteristics for use in some TFT applications. In particular, the method of processing and depositing layers over metal oxides affects TFT characteristics.

Provided herein are methods of fabricating a Thin Film Transistor (TFT) including depositing a layer over a metal oxide channel layer using an inductively coupled plasma high density plasma process to improve electron mobility at an interface of the metal oxide channel layer and/or MO channel layer and the layer deposited by high density plasma chemical vapor deposition using an inductively coupled plasma. As used herein, the term "high density plasma" refers to an electron or ion plasma having a density greater than, wherein the high density plasma comprises greater than 1.0E11/cm³Electron or ion plasma density. The deposition process comprises the use of N₂O gas or with N₂Pretreating the metal oxide layer with O gas and argon gas, exciting the gas to form inductively coupled plasma, and introducing SiH₄An interfacial layer comprising silicon oxide is gas deposited. The interface layer is an etching stop layer, or the interface layer is a passivation layer of a TFT structure.

Fig. 1 is a schematic cross-sectional view of a chamber 100 that may be used to implement embodiments described herein. Suitable chambers are available from applied materials, Inc., Santa Clara, Calif. It should be understood that the chambers described below are exemplary chambers, and that other chambers, including chambers from other manufacturers, may be used or modified together to accomplish aspects of the present disclosure. The chamber 100 is configured to generate an inductively coupled high density plasma.

The chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. A lid assembly 106 is disposed at an upper end of the chamber body 104. The substrate support assembly 108 is at least partially disposed within the interior volume of the chamber body 104. The substrate support assembly 108 includes a substrate support 110 and a shaft 112 extending from the substrate support 110. The substrate support 110 has a support surface 114 for supporting at least one substrate 102. In one embodiment, which may be combined with other embodiments described herein, the substrate 102 is a large area substrate, such as a substrate having a surface area typically of about 1 square meter or more. However, the substrate 102 is not limited to any particular size or shape. In one aspect, the term "substrate" refers to any polygonal, square, rectangular, curved, or other non-circular workpiece.

The lid assembly 106 includes a diffuser 116 that extends across at least a portion of the upper end of the chamber body 104. One or more gas inlets 118 are coupled through the lid assembly to communicate process gases from at least one gas source 120 to the diffuser 116. One or more gases from the gas source 120 flow through the diffuser 116 and into the processing region 124 between the diffuser 116 and the substrate support 110. One or more gases are provided to the processing region 124 through a plurality of holes or openings (not shown) in the processing region 124 on a side facing the diffuser 116. A flow controller 122 (e.g., a Mass Flow Control (MFC) device) is disposed between each diffuser inlet 118 and the gas source 120 to control the flow rate of gas from the gas source 120 to the diffuser 116. In one embodiment, which may be combined with other embodiments described herein, diffuser 116 is composed of a ceramic material, such as Al₂O₃. The pump 126 is in fluid communication with the interior space of the chamber and is therefore in fluid communication therewithThe geographic region 124 is in fluid communication. The pump 126 may operate in conjunction with the mass flow controller 122 to control the pressure within the processing region 124 and to evacuate gases and byproducts from the processing region 124.

Here, the lid assembly 106 includes at least one recess 128, the recess 128 extending inwardly from an upper outer surface of the recess 128, with one or more inductively coupled plasma generating components, coils 130, located therein and supported above at least one dielectric plate 132. Each dielectric plate 132 provides a physical barrier between the processing region 124 and the exterior of the chamber 100 and has the structural strength necessary to withstand the structural loads created by the presence of atmospheric pressure in the recess 128 and vacuum pressure in the interior space of the chamber body 104. Each coil 130 is connected to a power source 134 and ground 138. In one embodiment, which may be combined with other embodiments described herein, each coil 130 is connected to a power source 134 through a matching box 136, the matching box 136 having matching circuitry for adjusting electrical characteristics (such as impedance) of the coil 130 to "match" the electrical characteristics of the plasma formed in the processing region 124. Each coil 130 is configured to generate an electromagnetic field within the processing region that excites the gas in the processing region 124 into an inductively coupled high density plasma. A controller 158 is coupled to the chamber 100 and is configured to control aspects of the chamber 100 during processing.

Fig. 2A-2I are schematic diagrams of a Metal Oxide (MO) TFT200 at various stages of fabrication according to an embodiment. As shown in fig. 2A, the TFT200 is fabricated by first depositing a buffer layer 202 over the substrate 102. Substrate 102 may comprise any suitable material, such as glass, soda lime glass, polymers, and semiconductors used in the manufacture of flat panel displays. Suitable substrates 102 include silicon-based substrates, insulator-based substrates, germanium-based substrates, and one or more common layers typically found in CMOS structures. It should be understood that other materials are also contemplated. The buffer layer 202 is formed by physical vapor deposition or other suitable deposition method, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD). In the field of other embodiments that may be used with the description hereinIn some embodiments of the combination of embodiments, the buffer layer 202 is conformally formed using Capacitively Coupled Plasma (CCP) or by High Density Plasma (HDP), such as inductively coupled high density plasma in the chamber 100, as described with reference to fig. 1. Buffer layer 202 is comprised of a material that includes p-type silicon (e.g., boron doped silicon), a metal nitride (e.g., aluminum nitride or tungsten nitride), a metal oxide (e.g., vanadium oxide), or a combination thereof. In some embodiments, which can be combined with other embodiments described herein, buffer layer 202 includes silicon oxide (SiO)_x) Silicon nitride (Si)_xN_y) And combinations thereof. Unless otherwise specified, any layer of the TFT may be deposited using any suitable deposition method known in the industry and/or described herein.

As shown in fig. 2B, a gate layer 203 is deposited over the buffer layer 202. Suitable materials for gate layer 203 include chromium, molybdenum, copper, aluminum, tungsten, titanium, and combinations thereof. The gate layer 203 may be formed by Physical Vapor Deposition (PVD) or other suitable deposition method, such as electroplating, electroless plating, or Chemical Vapor Deposition (CVD). As shown in fig. 2C, the gate layer 203 is patterned to form a gate electrode 204. Patterning includes forming a photolithographic mask or hard mask (not shown) over gate layer 203 and exposing gate layer 203 to the etchants mentioned herein as "etching". Depending on the material used in the gate layer 203, the gate layer 203 is patterned by exposing the portions of the gate layer 203 not covered by the mask to a wet etchant or by exposing the portions of the gate layer 203 not covered by the mask to an etching plasma. In some embodiments, which can be combined with other embodiments described herein, the gate layer 203 is patterned by etching portions of the gate layer 203 not covered by the mask with an etching plasma comprising sulfur hexafluoride gas, oxygen gas, chlorine gas, or a combination thereof. The described etch plasma and etch process may be used for any patterning and etching of any layer described herein.

As shown in fig. 2D, a Gate Insulating (GI) layer 206 is deposited over the gate electrode 204. GI layer 206 is formed using any deposition method described herein and known in the industry. In some embodiments, which may be combined with other embodiments described herein, the GI layer 206 is formed using HDP CVD or CCP CVD. In CCP, opposing electrodes, such as parallel plate electrodes, are provided, one of which is coupled to ground and the other to a power source, and a gas is introduced between them to form the actual capacitor. By powering the powered electrode, electrical energy is capacitively coupled into the gas to form a plasma of the gas. The ion density of the plasma is a function of the power delivered into the gas. In ICP plasma, in contrast, a coil surrounds or is above the region of the gas in which the plasma is to be formed, and electrical energy flowing through the coil is electromagnetically coupled into the gas to ionize or otherwise excite gas atoms or molecules. Also, the plasma ion density is a function of the energy coupled into the gas. In CCP systems, one of the electrodes is also typically a substrate support, and thus the power that can be coupled into the gas is limited by the potential negative impact of that power on the substrate. In contrast, with an ICP arrangement, the power to ionize gas atoms and molecules is decoupled from the circuit components that hold the substrate, and higher power can be used to impart higher energy to the plasma, thereby achieving higher ion density in the plasma without adversely affecting the substrate.

As shown in fig. 2E, an active layer such as a Metal Oxide (MO) layer 207 is disposed over the GI layer 206. MO layer 207 is deposited by a suitable deposition method such as Physical Vapor Deposition (PVD). MO layer 207 is patterned using any of the patterning methods described herein, such as by a wet etch process. In one embodiment, which may be combined with other embodiments described herein, the MO channel layer 208 includes oxygen (O) and at least one of: indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf). Examples of the MO channel layer 208 include, but are not limited to, InGaZnO, InZnO, InGaSnO, InZnSnO, InGaZnSnO, InSnO, HfInZnO, GaZnO, InO, alsnnzno, ZnO, ZnSnO, AlZnO, AlZnSnO, HfZnO, SnO, and alsnnznino. Suitable materials for MO layer 207 include IGZO and/or zinc oxide. As shown in fig. 2F, the MO layer 207 is patterned by etching to form a MO channel layer 208. Any MO layer and/or MO channel layer may be a 1114 mol% InGaZnO layer.

As shown in fig. 2G, a metal layer 210 is formed over the MO channel layer 208 and the exposed GI layer 206 by Physical Vapor Deposition (PVD) or other suitable deposition method, such as electroplating, electroless plating, or Chemical Vapor Deposition (CVD). Unless otherwise specified, any process of PVD, electroplating, electroless plating, or CVD may be used for any of the metal layers described herein. The metal layer 210 is then patterned to form a source electrode 210A and a drain electrode 210B, and an opening 211 formed therebetween. The metal layer 210 is patterned using any suitable method described herein, such as a Back Channel Etch (BCE) process. Unless otherwise specified, each of the source, drain, and gate electrodes described herein may comprise a conductive material, such as copper, titanium, tantalum, or any conductive metal. It should be understood that other materials are also contemplated.

The opening 211 above the MO channel layer 208 exposes a portion of the MO channel layer 208 at the bottom of the MO channel layer 208. As shown in fig. 2I, a passivation layer 212 is formed over the MO channel layer 208, the exposed GI layer 206, and the source and

drain electrodes

210A and 210B by an HDP CVD process using an inductively coupled plasma. The processes shown and described in fig. 2A-2I disclose the fabrication of an embodiment of a gate covered by a passivation layer. The MO channel layer 208 within the opening 211 is pretreated after forming the source and drain electrodes, but before depositing a passivation or etch stop layer on the source and drain electrodes, before performing the HDP CVD process using ICP. The top surface of the MO channel layer 208 and/or the interface between the MO channel layer 208 and a layer to be deposited on the MO channel layer 208 (e.g., an ESL or passivation layer) is believed to be chemically modified to have high electron mobility.

The sequence of operations for an HDP CVD process using an inductively coupled plasma is described herein with reference to fig. 11. The passivation layer (e.g., 212) is typically the topmost layer of the TFT device to protect the device from environmental damage, including chemically or mechanically induced damage. The passivation layer also provides stable and reliable TFT performance against long-term thermal and electrical bias stress. Due to the sensitivity of the metal oxide layer to hydrogen and other environmental chemicals, high quality, low hydrogen containing oxides, such as silicon oxides described herein, are provided as the passivation layer 212. In particular, in embodiments where the passivation layer is disposed directly over and contacts the metal oxide layer of the gate, the HDP CVD process using the inductively coupled plasma provides a silicon oxide composition having a low hydrogen content compared to silicon oxide produced by other forms of deposition. Although the passivation layer 212 is depicted as a single layer in fig. 2I, multiple passivation layers are contemplated and one such example is provided with reference to fig. 3 described herein.

Fig. 3 depicts a first passivation layer 302 formed over the source and

drain electrodes

210A and 210B and a portion of the MO channel layer 208 using a CCP CVD process, followed by a second passivation layer 304 deposited using an HDP CVD process of an inductively coupled plasma to form the bottom-gate TFT 300. Here, since the second passivation layer 304 formed on the outermost or uppermost layer of the TFT is formed using an HDP CVD process using an inductively coupled plasma, it has a high-quality, stable, and low hydrogen content composition, capable of protecting the MO channel layer from environmental damage and enhancing electron mobility in the MO channel. In some embodiments, which may be combined with other embodiments described herein, the MO channel layer 208 is pretreated with a capacitively coupled plasma prior to depositing the first passivation layer 302 using CCP CVD. The first passivation layer 302 has a thickness of less than 100 nm. The second passivation layer 304 has a thickness of about 10nm to about 300 nm. Without being bound by theory, it is believed that depositing the second passivation layer 304 over the first passivation layer 302 can increase the electron mobility of the MO channel layer 208 disposed below the first passivation layer 302.

Fig. 4 depicts an embodiment of a bottom-gate TFT 400 having an etch stop layer 402 deposited over the gate insulating layer 206 and the gate electrode 204. Etch stop layer 402 is deposited by an HDP CVD process using an inductively coupled plasma and then patterned to form source electrode 410A and drain electrode 410B using any of the methods of forming source and drain electrodes described herein.

A passivation layer 404 is deposited over the source electrode 410A and the drain electrode 410B and over the etch stop layer 402. The passivation layer 404 is deposited using any of the deposition methods disclosed herein, such as CCP CVD or HDP CVD. Fig. 5 depicts an embodiment of a bottom-gate TFT 500 having a first etch stop layer 502 deposited by using a CCP CVD deposition process followed by a second etch stop layer 504 deposited by an HDP CVD process using an inductively coupled plasma. A source electrode 510A and a drain electrode 510B are formed in the first etch stop layer 502 and the second etch stop layer 504. The passivation layer 506 is deposited thereon using any method disclosed herein, such as by CCP CVD, or by HDP CVD processes using inductively coupled plasma.

Fig. 6 is a flow chart of an exemplary method of fabricating a MO TFT structure according to an embodiment. In operation 602, a buffer layer (e.g., 202) is formed over a substrate (e.g., 102). In operation 604, a gate layer (e.g., 203) is deposited over the buffer layer, and in operation 606, at least a portion of the gate layer is etched to form a gate electrode (e.g., 204). In operation 608, a GI layer (e.g., 206) is deposited over the gate electrode, and in operation 610, a patterned metal oxide layer (e.g., 208) is formed over the GI layer. In operation 612, a passivation layer or etch stop layer is deposited over the patterned metal oxide layer using HDP CVD with an inductively coupled plasma.

Fig. 7A-7G are schematic cross-sectional views of MO TFT730 and LTPS TFT 720 (collectively referred to as TFT 700) at various stages of fabrication according to an embodiment. A first buffer layer 702 is formed over the substrate 102 in a manner similar to that described with reference to fig. 2A. A silicon layer is deposited over the buffer layer 702 and then etched using any of the methods described herein to form a Low Temperature Polysilicon (LTPS) layer 704. A GI layer 706 is deposited on the low temperature polysilicon layer 704 and a gate 708 is formed using the patterning methods described herein. An interlayer dielectric (ILD) layer 710 is deposited over the GI layer 706 and the gate 708. Suitable materials for the ILD layer include silicon nitride, silicon oxide, and silicon oxynitride. Further, while shown as a single layer, it is contemplated that ILD layer 710 may comprise multiple layers, each of which may comprise a different chemical composition. The ILD layer is deposited using any of the methods described herein, such as using HDP CVD or CCP CVD. A portion of the ILD layer 710 and a portion of the GI layer 706 are etched down to the LTPS layer 704 to form a first lower opening 711A and a second lower opening 711B. A first metal layer 713 is formed (as shown in fig. 7B). As shown in fig. 7C, the first metal layer 713 is patterned to form a lower source via 712A, an intermediate source electrode pad 712C, an intermediate drain electrode pad 712D, and a lower drain via 712B of the LTPS TFT 720. In addition, the first metal layer 713 is patterned to form the gate electrode 714 of the MO TFT 730.

With respect to the LTPS TFT 720, the lower source via 712A extends up to the intermediate source electrode pad 712C, and the lower drain via 712B extends up to the intermediate drain electrode pad 712D. As shown in fig. 7D, a second buffer layer 716 is then formed thereon. As shown in fig. 7E, a metal oxide layer 717 is deposited over the second buffer layer 716, and in fig. 7F, a portion of the metal oxide layer 717 is patterned to form the MO channel layer 718 of the MO TFT 730. The second buffer layer 716 is patterned to form a first upper opening 721A extending down to the middle source electrode pad 712C and a second upper opening 721B extending down to the middle drain electrode pad 712D of the LTPS TFT 720. A second metal layer (not shown) is deposited and patterned to form an upper source via 722A extending from the intermediate source electrode pad 712C to the upper source electrode pad 722C and an upper drain electrode via 722B extending from the intermediate drain electrode pad 712D to the upper drain electrode pad 722D of the LTPS TFT 720, as shown in fig. 7G. Lower source via 712A, intermediate source electrode pad 712C, upper source via 722A, and upper source electrode pad 722C together form source electrode 742A. The lower drain via 712B, the intermediate drain electrode pad 712D, the upper drain electrode via 722B, and the upper drain electrode pad 722D together form a drain electrode 742B of the LTPS TFT 720.

The MO TFT source electrode 732A and the MO TFT drain electrode 732B are formed on the MO channel layer 718 of the MO TFT 730. Passivation layer 724 is deposited by an HDP CVD process using an inductively coupled plasma to form MO TFT730 and LTPS TFT 720 of structure 700.

FIG. 8 is a schematic cross-sectional view of a TFT structure 800 including a MO TFT830 and a LTPS TFT820 with a passivation layer 804 and an etch stop layer 802, according to an embodiment. The layers of the TFT structure 800 are deposited in a manner similar to that shown in fig. 7A-7E. The etch stop layer 802 is deposited over the MO channel layer 718 of the MO TFT830 by a HDP CVD process using an inductively coupled plasma. The etch stop layer 802 is patterned and MO TFT source electrode via 832A is formed extending from the MO channel layer 718 to the MO TFT source electrode pad 832C. The MO TFT drain electrode 832B is formed to extend from the MO channel layer 718 to a MO TFT drain pad 832D in the MO TFT 830. Passivation layer 804 is deposited by CCP CVD or by HDP CVD.

Referring to the LTPS TFT820 depicted in fig. 8, an upper source electrode via 822A extending from the middle source electrode pad 712C to the upper source electrode pad 822C is formed, and an upper drain electrode via 822B extending from the middle drain electrode pad 712D to the upper drain electrode pad 822D of the LTPS TFT820 is formed. Lower source via 712A, intermediate source electrode pad 712C, upper source via 822A, and upper source electrode pad 822C together form source electrode 842A. The lower drain via 712B, the intermediate drain electrode pad 712D, the upper drain electrode via 822B, and the upper drain electrode pad 822D together form a drain electrode 842B of the LTPS TFT 820.

Fig. 9 is a schematic cross-sectional view of a TFT structure 900 including a MO TFT930 with a passivation layer 906 and a LTPS TFT920 according to an embodiment.

Layers

702, 706, 708, and 710 of TFT structure 900 are formed in the manner described with reference to fig. 7A. The MO TFT gate 908 is formed in the MO TFT930 on the same plane as the LTPS gate 708. An ILD layer 710 is formed thereon, and a second buffer layer 902 is formed over the ILD layer 710. A source electrode 922A and a drain electrode 922B are formed in the second buffer layer 902, the ILD layer 710, and the GI layer 706 extending to the LTPS layer 704 of the LTPS TFT 920. A source electrode 932A and a drain electrode 932B are formed around the metal oxide layer 904 in the MO TFT 930. Passivation layer 906 is formed thereon by HDP CVD using inductively coupled plasma. It has been found that complementary structures including p-type LTPS TFTs and n-type MO TFTs can be formed suitable for applications such as semiconductor-based circuits. Conventional n-type MO TFT structures include a TFT having a thickness of less than 30cm²Vsec, such as about 10cm²An electron mobility/Vsec MO channel layer. In contrast, conventional p-type LTPS TFT structures include TFT structures having a height of about 80cm²a/Vsec to about 100cm²Electron transport of/VsecA layer of rate. Accordingly, the present disclosure has found that the difference in electron mobility between LTPS TFT structures and MO TFT structures is improved by increasing electron mobility in the MO channel layer of the MO TFT structures using the methods described herein. The MO channel layer of the present disclosure has an electron mobility greater than 30cm²Vsec, such as greater than 50cm²Vsec, such as about 80cm²a/Vsec to about 100cm²Vsec, or about 100cm²a/Vsec to about 400100cm²and/Vsec. Furthermore, the methods described herein use fewer masks than conventional methods of forming structures including LTPS TFTs and MO TFTs.

Fig. 10 is a schematic cross-sectional view of a MO TFT1030 and LTPS TFT1020 (collectively referred to as TFT structure 1000) with an Etch Stop Layer (ESL)1006 and a passivation layer 1008, according to an embodiment. In the TFT structure 1000, a second buffer layer 1002 is formed over the ILD layer 710. The MO channel layer 1004 is formed in the ESL 1006, and the ESL 1006 is formed using an HDP CVD process of inductively coupled plasma. A source electrode 1022A and a drain electrode 1022B are formed in the LTPS TFT1020, and a source electrode 1032A and a drain electrode 1032B are formed in the MO TFT 1030. The passivation layer 1008 is formed by CCP CVD or HDP CVD. In some embodiments, which may be combined with other embodiments described herein, the MO channel layer of the MO TFT is disposed in the same plane as the gate of the LTPS TFT. In some embodiments, which may be combined with other embodiments described herein, the MO channel layer of the MO TFT is disposed in a different plane than the gate electrode of the LTPS TFT. In some aspects thereof, the MO channel layer may undergo a pretreatment process before a layer is deposited on the MO channel layer by HDP CVD using ICP. An example pretreatment and deposition process is shown in method 1100 of fig. 11 and summarized in table 1 below.

Table 1: HDP CVD pretreatment and deposition examples by Using ICP Process

Operation 1102 of fig. 11 includes a pretreatment process for pretreating a film layer thereof with a pretreatment gas. Operation in FIG. 11At 1102, a pre-process gas including nitrous oxide gas, argon gas, or a combination of oxygen and argon gases is provided to the processing region 124 of the processing chamber. The oxygen-containing gas being N₂O gas, NO gas, O₂Gas, O₃One or more of the gases, such as N₂And (4) O gas.

Prior to operation 1102, the substrate 102 is positioned within the processing region 124 to provide a spacing of about 100mm to about 300mm between the diffuser 116 and the substrate 102. Introducing the pretreatment gas comprises introducing the pretreatment gas at a rate of about 0.3sccm/cm²To about 0.7sccm/cm²Introduction of N₂O gas and at about 0sccm/cm²To about 0.7sccm/cm²Argon gas was introduced. As used herein, the unit "sccm/cm²"refers to the standard cubic centimeter volumetric gas flow rate per square centimeter of substrate surface area. The pre-treatment gas introduced into the processing space comprises about 1:0 to about 1:2, such as about 3:1 to about 1:1, by volume of N₂The ratio of O gas to argon gas. In some embodiments that may be combined with other embodiments described herein, argon is not present with N₂O gas is used together.

The pre-treatment pressure of the process space is about 10mT to about 150mT, such as about 12mT to about 120 mT. The pre-treatment temperature of the substrate is from about 70 ℃ to about 350 ℃, such as from about 70 ℃ to about 250 ℃, and the pre-treatment time is from about 5 seconds to about 60 seconds, such as from about 10 seconds to about 40 seconds. In some embodiments, which can be combined with other embodiments described herein, a pretreatment gas is introduced into the process space before being excited into a plasma.

In operation 1104, a plasma pre-treatment is provided that includes energizing a pre-treatment gas within the process space with ICP coil energy supplied at a frequency of about 1MHz to about 30MHz, such as about 2MHz to about 15 MHz. In some embodiments, which may be combined with other embodiments described herein, the plasma processing conditions described in table 1 and operation 1104 are used to pre-process the MO channel layer after operation 1102. Alternatively, the MO channel layer may be pre-processed using the conditions provided in operation 1104 without being pre-processed using the conditions provided with reference to operation 1102. It has been found that low ICP coil frequency reduces the losses associated with exciting the plasmaBad, increasing uniformity and reducing energy consumption. High plasma energy frequencies, such as for microwave chemical vapor deposition, use power at frequencies in excess of 100MHz, such as 100GHz, in the process of microwave chemical vapor deposition. High frequencies may be used for the HDP process described herein, however, an ICP coil frequency of about 1MHz to about 30MHz, such as about 2MHz to about 15MHz, excites the pretreatment gas to generate the plasma. Exciting the pretreatment gas comprises exciting the pretreatment gas at about 2.3W/cm²To about 5.3W/cm²The power density of (a) provides electrical power. As used herein, the term "power density" refers to the amount of electrical power provided per square centimeter of exposed substrate surface area. The temperature of the substrate is maintained at about 70 ℃ to about 350 ℃, such as about 70 ℃ to about 250 ℃. The plasma pretreatment time is about 2 seconds to about 32 seconds. In some embodiments, which can be combined with other embodiments described herein, the pretreatment gas is converted to an in situ formed plasma prior to depositing the silicon oxide layer as described herein. Alternatively, the plasma is formed ex situ and introduced into the processing space. It is believed that the plasma pretreatment process enhances the characteristics and performance of the metal oxide TFT under thermal bias stress. A plasma pretreatment is performed prior to forming the etch stop layer and/or the passivation layer. In some embodiments, which can be combined with other embodiments described herein, the combination of the ranges of gas flow rate, power density, and frequency produces a low plasma density that is sufficient to prepare the exposed film surface for subsequent silicon oxide layer deposition and provides low potential and low ion bombardment that damages portions of the fabricated TFT structure.

In operation 1106, at about 0.02sccm/cm²To about 0.09sccm/cm²Introduction of Silane (SiH)₄) Gas to form a silicon oxide interface (e.g., an ESL or passivation layer interfacing with the MO channel layer). In some embodiments, which can be combined with other embodiments described herein, the ratio of between about 5:1 to about 40:1 is N₂O gas flow and SiH₄Ratio of gas flows SiH addition₄Plasma conditions in operation 1104 are maintained during and after the gas. In some embodiments, the MO channel layer is not exposed to the pretreatment processes described in

operations

1102 and 1104. In particular, will be as in Table 1The process conditions of operation 1106 described in the "deposit" column apply to the MO channel layer without pretreatment. The spatial pressure of the processing region 124 is maintained at about 80mT to about 12 mT. SiH₄The gas is introduced for about 26 seconds to about 260 seconds. The silicon oxide interfacial layer (e.g., passivation layer or ESL) is formed to have a thickness of about 200 angstroms to about 2000 angstroms, such as about 500 angstroms to about 2000 angstroms. On an atomic percent basis, the hydrogen content of the silicon oxide interfacial layer produced by HDP CVD using inductively coupled plasma at 250 ℃ was about 1.9%, while the hydrogen content of the interfacial layer produced by CCP at 250 ℃ was about 3.5%. Additional operations (e.g., post-deposition columns described in table 1) include annealing for about 5 seconds to about 15 seconds to maintain a temperature of about 70 ℃ to about 250 ℃. Without being bound by theory, it is believed that the interface between the exposed top surface of the MO channel layer and/or the MO channel layer and the layer deposited thereon by HDP CVD using ICP is chemically and/or physically modified by one or more of

operations

1102, 1104, 1106, and post-deposition operations. It is believed that high electron mobility is achieved by increasing the electron carrier density in the MO channel layer and/or at the interface between the MO channel layer and a layer deposited over the MO channel layer. The mobility of the MO channel layer is greater than 30cm/Vsec, such as greater than 60 cm/Vsec.

Examples of the present invention

An exemplary silicon oxide deposition process is provided and summarized in table 2.

TABLE 2 exemplary Process conditions for HDP CVD Using ICP

Several TFT samples in which silicon oxide layers were deposited were formed using the process conditions summarized in table 2. It can be seen that each layer deposited provides a Wet Etch Rate (WER) of less than 2600 angstroms per minute even at low substrate processing temperatures, e.g., 80 ℃ and 85 ℃. The WER performance is significantly better than typical WERs of other deposition forms, with typical WERs typically higher than 4000, or higher than 6000, or higher than 8000 angstroms/minute. The WER value is normalized to the thermal oxide WER, which is 1000A/min. The Si — O peak position was found to be always high over a wide temperature range of about 100 ℃ to about 300 ℃, indicating high film quality and controllability over a wide range. The column "pitch" is defined by the distance (in mils) between the diffuser and the substrate.

In addition, for example films deposited by HDP CVD using inductively coupled plasma, the hydrogen concentration and film density were measured. Particularly at low temperatures, the hydrogen content is much lower than what is typically found using other processes. Other processes typically have a hydrogen concentration greater than 5%, for example about 6% at temperatures below 150 ℃. The hydrogen concentration measured in the exemplary films deposited by HDP CVD using inductively coupled plasma was about 2.7% at about 120 ℃, 1.8% at about 225 ℃ and 1.7% at about 340 ℃. Film density of an exemplary film deposited by HDP CVD using inductively coupled plasma has about 2.3g/cm at about 250 deg.C³Is higher than the typical film density of silicon oxide films deposited by other depositions, as measured by x-ray reflectance. These films had a film density of 2.2g/cm at about 250 deg.C³Or lower.

The TFT structures described herein use p-type LTPS TFTs and n-type MO TFTs to reduce the number of masks required to form TFT structures with improved performance, stability, and electron mobility compared to Complementary Metal Oxide Semiconductor (CMOS), such as p-type poly-silicon + n-type poly-silicon structures.

In summary, a method of fabricating a Thin Film Transistor (TFT) is provided that includes depositing an interfacial layer over a metal oxide layer using an inductively coupled plasma high density plasma process to enhance electron mobility. The deposition process comprises the use of N₂O gas or with N₂Pretreating the metal oxide layer with O gas and argon gas, exciting the gas to form inductively coupled plasma, and introducing SiH₄The gas is flowed to deposit an interfacial layer comprising silicon oxide. The interface layer is an etching stop layer, or the interface layer is a passivation layer of a TFT structure.

While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of forming a thin film transistor comprising the steps of:

depositing a buffer layer over a substrate;

forming a gate layer over the buffer layer;

etching at least a portion of the gate layer to form a gate electrode;

depositing a Gate Insulation (GI) layer over the buffer layer and the gate electrode;

forming a metal oxide channel layer over the GI layer; and

depositing the passivation layer by high density plasma chemical vapor deposition (HDP CVD) using Inductively Coupled Plasma (ICP), wherein the high density plasma comprises greater than 1.0E11/cm³Electron or ion plasma density.

2. The method of claim 1, wherein depositing the passivation layer comprises depositing an interface passivation layer by chemical vapor deposition using Capacitively Coupled Plasma (CCP) and depositing an upper passivation layer by HDP CVD using ICP.

3. The method of claim 1, further comprising pretreating the metal oxide channel layer prior to depositing the passivation layer, wherein the pretreating the metal oxide channel layer comprises exposing the metal oxide channel layer to an inductively coupled plasma.

4. The method of claim 3, wherein the inductively coupled plasma is formed from nitrous oxide (N)₂O), Ar, or a combination thereof.

5. The method of claim 1, wherein depositing the passivation layer comprisesExcitation of N₂O gas and Silane (SiH)₄) Forming the inductively coupled plasma and exposing the inductively coupled plasma to the metal oxide channel layer.

6. A method of forming a thin film transistor, comprising:

depositing a buffer layer over a substrate;

forming a gate layer at least partially over the buffer layer;

depositing a Gate Insulating (GI) layer over the buffer layer and the gate layer;

forming a metal oxide channel layer over the GI layer;

depositing an etch stop layer by high density plasma chemical vapor deposition (HDP CVD) using Inductively Coupled Plasma (ICP), wherein the high density plasma comprises greater than 1.0E11/cm³Electron or ion plasma density of (a);

forming a source electrode and a drain electrode in the etch stop layer; and

and depositing a passivation layer.

7. The method of claim 6, wherein depositing the etch stop layer comprises depositing an interfacial etch stop layer by chemical vapor deposition using Capacitively Coupled Plasma (CCP) and depositing an upper etch stop layer using HDP CVD using ICP.

8. The method of claim 6, wherein depositing an etch stop layer by HDP CVD comprises depositing an etch stop layer with N of about 5:1 to about 40:1₂O gas and SiH₄Gas ratio of N₂O gas and SiH₄A gas is introduced into a process space, wherein the substrate is disposed within the process space.

9. The method of claim 8, wherein depositing an etch stop layer by HDP CVD comprises setting an ICP coil energy at a frequency of about 1MHz to about 15 MHz.

10. The method of claim 6, further comprising the steps of:

at a rate of about 0.3sccm/cm²To about 0.7sccm/cm²N of (A)₂Flow rate of O gas to convert N₂Introducing an O gas into a process volume of a process chamber, wherein the substrate is disposed in the process volume;

at about 2.3W/cm²To about 5.3W/cm²Exciting said N with a power density of₂O gas; and

at about 0.02sccm/cm²To about 0.09sccm/cm²SiH of₄Gas flow rate introduction of SiH₄A gas.

11. The method of claim 10, wherein N is substituted₂Introducing O gas into the process space comprises introducing argon gas into the process space, wherein the process space comprises a pressure of about 15mT to about 120mT and a process temperature of about 70 ℃ to about 350 ℃.

12. A method of forming a thin film transistor, comprising:

forming a low temperature polysilicon thin film transistor (LTPS TFT) on a substrate; and

forming a metal oxide thin film transistor (MO TFT) comprising a metal oxide channel layer on the substrate, wherein forming the LTPS TFT and the MO TFT comprises depositing a silicon oxide layer over the metal oxide channel layer by HDP CVD using ICP, wherein HDP comprises greater than 1.0E11/cm³Electron or ion plasma density.

13. The method of claim 12 wherein the electron mobility of the metal oxide channel layer is greater than 30cm²/Vsec。

14. The method of claim 12, wherein forming the LTPS TFT and forming the MO TFT comprise:

depositing a first buffer layer over the substrate;

forming a Low Temperature Polysilicon (LTPS) layer over the first buffer layer;

depositing a GI layer over the first buffer layer and the LTPS layer;

forming a gate layer at least partially over the GI layer;

depositing an interlayer dielectric layer (ILD) over the GI layer and the gate layer;

depositing a second buffer layer;

forming the metal oxide channel layer over the second buffer layer;

depositing the silicon oxide layer over the metal oxide channel layer by HDP CVD using Inductively Coupled Plasma (ICP).

15. The method of claim 14, wherein forming the LTPS TFT further comprises forming LTPS source and drain electrodes prior to depositing the silicon oxide layer, and forming the MO TFT further comprises forming MO source and drain electrodes prior to depositing the silicon oxide layer, wherein the silicon oxide layer is an etch stop layer.

16. The method of claim 14, wherein forming the LTPS TFT further comprises forming LTPS source and drain electrodes after depositing the silicon oxide layer, and forming the MO TFT further comprises forming MO source and drain electrodes after depositing the silicon oxide layer, wherein the silicon oxide layer is a passivation layer.

17. The method of claim 12, wherein the silicon oxide layer comprises a thickness of about 500 angstroms to about 2000 angstroms.

18. The method of claim 12, further comprising pretreating the metal oxide channel layer with an inductively coupled plasma comprising nitrogen and oxygen and depositing a silicon oxide layer, wherein pretreating the metal oxide channel layer and depositing the silicon oxide layer comprise a treatment time of about 80 seconds to about 350 seconds.

19. The method of claim 18, wherein pretreating the metal oxide channel layer comprises:

at a rate of about 0.3sccm/cm²To about 0.7sccm/cm²N per substrate surface area₂Flow rate of O gas to convert N₂Introducing an O gas into a process volume of a process chamber, wherein the substrate is disposed in the process volume; and

at about 2.3W/cm²To about 5.3W/cm²Exciting said N with a power density of₂And (4) O gas.

20. The method of claim 18, wherein depositing the silicon oxide layer comprises:

at about 0.02sccm/cm²To about 0.09sccm/cm²SiH of₄Gas flow rate and introduction of SiH at a process temperature of about 70 ℃ to about 350 ℃₄Gas to form the silicon oxide layer.