JP2022537958A - Method for forming a thin film transistor - Google Patents

Abstract

Embodiments disclosed herein generally relate to methods of forming thin film transistors (TFTs). The method includes forming one or more metal oxide layers and/or polysilicon layers. A gate interface (GI) layer is formed on the one or more metal oxide layers and/or polysilicon layers using a high density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP). deposited. Depositing the GI layer using an HDP-CVD layer results in an unexpectedly high mobility of the metal oxide layer deposited thereon. [Selection drawing] Fig. 2G

Description

[0001] Embodiments of the present disclosure generally relate to methods and, more particularly, to methods of forming thin film transistors.

[0002] A thin film transistor (TFT) is a type of metal-oxide-semiconductor field effect transistor (MOSFET) made by depositing thin films of active semiconductor layers, dielectric layers, and metal contacts onto a supporting substrate. be. Glass substrates are common because one application of TFTs is liquid crystal displays (LCDs).

[0003] TFTs have attracted a great deal of attention in display applications due to the high resolution, low power consumption, and high speed operation of LCD and organic light emitting diode (OLED) displays. TFTs are built into the panel of the display. The data line and gate line voltage signals from the display module in the display system are sent to the TFTs of the pixel circuits and/or gate driver circuits on the periphery of the display panel to control the display image by turning on/off the TFTs. Improved responsivity due to higher TFT mobility and/or reduced crosstalk between pixels reduces image distortion. Many display products, including LCD televisions (TVs) and monitors, include TFTs in their panels. Many modern high resolution, high quality electronic visual display devices employ TFT-intensive active matrix displays. One of the beneficial aspects of TFT technology is the use of separate TFTs for each pixel of the display. Each TFT acts as a switch or current source in a pixel circuit or gate driver circuit to control voltage and current through data and gate signal lines, thereby enhancing control of the display image. The high current of the high mobility TFTs allows fast updating of the display image, which improves image quality by minimizing distortion of the data and gate signal voltages.

[0004] One of the drawbacks of TFTs in the art is that the mobility of the conductive channel can be unacceptably low. In addition, the method of forming the TFT may not provide good control of the channel mobility. Finally, it can be difficult to change the mobility of a channel after it has already been deposited.

[0005] Therefore, there is a need in the art for a method of forming a TFT that can increase the mobility of the channel.

[0006] Embodiments disclosed herein generally relate to methods of forming TFTs. The method includes depositing a layer that alters the mobility of the underlying channel.

[0007] One exemplary method of forming a thin film transistor device includes forming a metal oxide layer over a first portion of a substrate and forming a gate insulator (GI) over the first portion of the substrate. forming a layer; forming a gate electrode over the GI layer; and etching one or more remaining portions of the GI layer. Forming the GI layer includes depositing a silicon-containing layer in a high density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP). HDP-CVD processes have ICP power densities from about 2.3 W/cm ² to about 5.3 W/cm ² and ICP frequencies from about 2 MHz to about 13.56 MHz.

[0008] Another exemplary method of forming a thin film transistor device is to form a first metal oxide layer over a first portion of a substrate, the first portion of the substrate being a first forming a first metal oxide layer over a first portion of the substrate corresponding to a thin film transistor (TFT); and in contact with the first metal oxide layer over the first portion of the substrate. forming an interfacial gate insulator (GI) layer of a first TFT and forming an underlying layer over a second portion of the substrate, the second portion of the substrate corresponding to the second TFT; and the lower layer is in contact with the bottom surface of the second metal oxide layer of the second TFT, forming the interfacial GI layer and the lower layer over the first portion and the second portion. depositing a first silicon-containing layer, the first silicon-containing layer being deposited in a high density plasma-enhanced chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP); The process has an ICP power density of about 2.3 W/cm ² to about 5.3 W/cm ² and an ICP frequency of about 2 MHz to about 13.56 MHz. forming an interface gate insulator (GI) layer of a first TFT in contact with a first metal oxide layer over a first portion of a substrate comprising depositing one silicon-containing layer; forming a bottom layer over the second portion of the second TFT, forming a second metal oxide layer of the second TFT with the bottom surface in contact with the bottom layer, and in contact with the interfacial layer; forming the bulk GI layer of the first TFT and forming the GI layer of the second TFT in contact with the top surface of the second metal oxide layer, forming the bulk GI layer and the GI layer; comprises depositing a second silicon-containing layer over the first portion and the second portion in a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP). forming a bulk GI layer of the first TFT in contact with the top surface of the second metal oxide layer to form a GI layer of the second TFT; and a second silicon over the first portion. forming a first gate electrode of the first TFT over the containing layer and forming a second gate electrode of the second TFT over the second silicon containing layer over the second portion; , the interfacial GI layer of the first TFT, the bulk GI layer of the first TFT, the GI layer of the second TFT, and the bottom layer of the second TFT, the first portion and the second TFT. removing one or more remaining portions of the second silicon-containing layer from the portion; depositing an interlevel dielectric (ILD) layer over the plate.

[0009] Yet another exemplary method of forming a thin film transistor device is to form a polysilicon layer over a first portion of a substrate, the first portion of the substrate being a polysilicon thin film transistor (TFT). forming a polysilicon layer over the first portion of the substrate and a first gate insulator over the polysilicon layer in the first portion of the substrate and over the second portion; GI) layer, the second portion of the substrate corresponding to the metal oxide (MOx) TFTs, over the polysilicon layer in the first portion of the substrate and over the second portion; depositing a gate insulator (GI) layer; forming a first gate electrode of a polysilicon TFT on the first GI layer and forming a shield metal of the MOx TFT; forming a first interlevel dielectric (ILD) layer over the GI layer, the first gate electrode, and the shield metal; and metal of the MOx TFT over the first ILD layer in the second portion of the substrate. forming an oxide layer and forming a second GI layer on the metal oxide layer by high density plasma chemical vapor deposition (HDP-CVD) using inductively coupled plasma (ICP); The HDP-CVD process has an ICP power density of about 2.3 W/cm ² to about 5.3 W/cm ² and an ICP frequency of about 2 MHz to about 13.56 MHz. forming a second GI layer over the metal oxide layer; forming a second gate electrode over the second GI layer; a first ILD layer; a metal oxide layer; and forming a second ILD layer over the second gate electrode.

[0010] So that the features of the disclosure described above may be understood in detail, the disclosure summarized above will now be described more particularly with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the attached drawings merely depict exemplary embodiments and are therefore not to be considered limiting of its scope, as other equally effective embodiments are permissible.

1 is a schematic cross-sectional view showing a chamber according to one embodiment; FIG. 1 is a schematic cross-sectional view showing a TFT according to one embodiment; FIG. 1 is a schematic cross-sectional view showing a TFT according to one embodiment; FIG. 1 is a schematic cross-sectional view showing a TFT according to one embodiment; FIG. 1 is a flow diagram of a method of forming a TFT according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. FIG. 4 is a flow diagram of a method of forming two transistor structures according to one embodiment. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 2 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG. FIG. 4 is a flow diagram of a method of forming two transistor structures according to one embodiment. 1 is a schematic cross-sectional view showing two transistor structures according to one embodiment; FIG.

[0022] To facilitate understanding, where possible, identical reference numbers are used to designate identical elements that are common to the drawings. It is believed that elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration.

[0023] Embodiments disclosed herein generally relate to methods of forming TFTs. The method includes depositing one or more metal oxide layers and/or polysilicon layers. A GI layer is deposited over the one or more metal oxide layers and/or polysilicon layers. Depositing the GI layer using HDP-CVD results in unexpectedly high mobilities of metal oxide and/or polysilicon layers deposited underneath. Selective placement of the GI layer controls the mobility of the underlying layer, depending on whether the GI layer is deposited by HDP-CVD or by a CVD process using CCP. Depositing a GI layer allows the mobility of the underlying layer to be controlled after layer deposition, ie the mobility may be enhanced after deposition as well as during deposition. Embodiments disclosed herein can be useful for, but not limited to, forming TFTs that include channels with enhanced mobility.

[0024] As used herein, the term "about" refers to a variation on the order of ±10% from the nominal value. It should be understood that such variations may be included in any value provided herein.

[0025] In various embodiments of the present disclosure, layers or other materials are referred to as being etched. Etching of these materials includes, but is not limited to, reactive ion etching (RIE), dry etching, wet etching, plasma etching, microloading, selective etching of any of the above, combinations of the above, and any other It should be understood that any conventional method used in semiconductor manufacturing, such as a suitable method, can be used. Where method steps are described herein as etching two or more materials, or two or more portions of the same material, the etching may occur simultaneously in the same etching process, or the etching may use different etching processes. can be done in separate substeps. For example, a step describing etching a metal and a dielectric includes a first etching sub-step using a first etching process that etches the metal, and a step using a second etching process that etches the dielectric. and a second etching substep.

[0026] Figure 1 is a schematic cross-sectional view of a chamber 100 according to one embodiment. A suitable chamber is available from Applied Materials, Inc., located in Santa Clara, California. It is understood that the systems described below are exemplary chambers and that other chambers, including chambers from other manufacturers, can be used together or modified to achieve aspects of the present disclosure. sea bream. Chamber 100 is configured to produce HDP.

[0027] As shown, the chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. As shown in FIG. A lid assembly 106 is positioned at the upper end of the chamber body 104 . Substrate support assembly 108 is disposed at least partially within an interior region of chamber body 104 . Substrate support assembly 108 includes substrate support 110 and shaft 112 . Substrate support 110 has a support surface 114 for supporting at least one substrate 102 .

[0028] In one embodiment, which can be combined with other embodiments described herein, substrate 102 is a large area substrate, such as a substrate typically having a surface area of about 1 m ² or more. However, substrate 102 is not limited to any particular size or shape. For example, the term "substrate" refers to any polygonal, square, rectangular, curved, or other non-circular workpiece, such as glass substrates or polymer substrates used in the manufacture of flat panel displays. Substrate 102 can be any of silicon-based substrates, semiconductor substrates, insulating substrates, germanium-based substrates, and generally one or more general purpose layers as would be present in a complementary metal-oxide-semiconductor (CMOS) device structure. suitable materials for Substrate 102 may comprise a transparent material such as rigid glass or flexible polyimide (PI), which substrates are used in LCD or OLED display applications such as televisions, tablets, laptops, mobile phones or other displays. can be useful when Substrate 102 may have any number of metal, semiconductor, or insulating layers thereon.

[0029] Lid assembly 106 includes diffuser 116 at the upper end of chamber body 104 . Diffuser 116 includes one or more diffuser inlets 118 that are connectable to at least one gas source 120 . Diffuser 116 provides one or more gases from gas source 120 to processing region 124 between diffuser 116 and substrate support 110 . One or more gases are supplied to processing region 124 through a plurality of holes (not shown) in diffuser 116 . A flow controller 122 , such as a mass flow control (MFC) device, is positioned between each of the diffuser inlets 118 and the gas source 120 to control the flow of gas from the gas source 120 to the diffuser 116 . A pump 126 is in fluid communication with the processing region 124 . Pump 126 is operable to control the pressure within processing region 124 and to exhaust gases and byproducts from processing region 124 .

[0030] Lid assembly 106 includes at least one cavity 128 having one or more inductively coupled plasma generating components (alternatively referred to as coils) 130 formed therein. Coil 130 is supported by at least one dielectric plate 132 . Each dielectric plate 132 provides a physical barrier with structural strength to withstand structural loads caused by the presence of atmospheric pressure within cavity 128 and the presence of vacuum pressure in the interior region of chamber body 104 . Each coil 130 is connected to a power supply 134 and ground 138 . In one embodiment, which can be combined with other embodiments described herein, each coil 130 is connected to power supply 134 through a matching box 136 having a matching circuit for adjusting electrical properties such as impedance of coil 130. be done. In some embodiments, a first capacitor 137 is electrically connected between coil 130 and matching box 136 . In some embodiments, a termination capacitor 139 is electrically connected between coil 130 and ground 138 . Each coil 130 is configured to generate an electromagnetic field that energizes the gas in the process region 124 to generate a high density plasma (HDP).

[0031] In one embodiment, the electron density generated in the chamber is greater than about 1E11/ ^cm3 . In one embodiment, the ion plasma density generated in the chamber is greater than about 1E11/cm ³ . In one embodiment, the ICP power density used to generate the HDP is approximately 5.3 W/cm ² . In one embodiment, the ICP frequency used to generate HDP is from about 2 MHz to about 13.56 MHz.

[0032] Controller 190 is coupled to chamber 100 and configured to control aspects of chamber 100 during processing. As shown, controller 190 includes central processing unit (CPU) 191 , memory 192 , and support circuitry (alternatively referred to as I/O) 193 . CPU 191 is used in industrial environments to control various processes and hardware (e.g., pattern generators, motors, and other hardware) and to monitor processes (e.g., processing time and substrate position or location). any form of computer processor. Memory 192 is connected to CPU 191 and may be any type of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. one or more of Software instructions and data for directing CPU 191 may be coded and stored in memory 192 . Further, the CPU 191 is connected with a support circuit 193 for supporting the CPU in the conventional ^* method. Support circuits 193 include conventional cache, power supplies, clock circuits, input/output circuits, subsystems, and the like. A program (or computer instructions) readable by controller 190 determines which tasks can be performed on substrate 102 . The program may be software readable by controller 190 and may include, for example, code for monitoring and controlling process parameters (eg, pressure, temperature, gas flow rates) of chamber 100 .

[0033] Figures 2A-2H are schematic cross-sectional views illustrating a method of forming a TFT 200 according to one embodiment. FIG. 3 is a flow diagram of a method 300 of forming a TFT 200 according to the same embodiment. For ease of explanation, FIGS. 2A-2H, 3, 8, and 11 are described with reference to chamber 100 of FIG. However, it should be noted that ICP-CVD chambers other than chamber 100 can be utilized with method 300 . Method 300 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191 , cause chamber 100 to perform method 300 .

[0034] As shown, a TFT 200 is formed on a substrate 102 (Fig. 2A).

[0035] The method 300 begins at step 310 where a metal oxide layer 204 is formed, as shown in Figure 2B. Metal oxide layer 204 is formed by any conventional method used in the art. In some embodiments, metal oxide layer 204 is deposited over substrate 102 . In one embodiment, which can be combined with other embodiments described herein, metal oxide layer 204 comprises oxygen (O), indium (In), zinc (Zn), gallium (Ga), oxygen ( O), tin (Sn), aluminum (Al), and at least one of hafnium (Hf). Examples of metal oxide layer 204 include In--Ga--Zn--O, In--Zn--O, In--Ga--Sn--O, In--Zn--Sn--O, In--Ga--Zn--Sn--O, In—Sn—O, Hf—In—Zn—O, Ga—Zn—O, In—O, Al—Sn—Zn—O, Zn—O, Zn—Sn—O, Al—Zn—O, Al— Including, but not limited to, Zn--Sn--O, Hf--Zn--O, Sn--O, Al--Sn--Zn--In--O, and the like. Step 310 may include doping metal oxide layer 204 with an n-type or p-type dopant such as boron (B) or nitrogen (N). Metal oxide layer 204 may have a thickness of about 30 nm to about 50 nm. A metal oxide layer film may be formed in a first sub-step and etched in a second sub-step to form the metal oxide layer 204 . In other embodiments, metal oxide layer 204 is deposited using selective deposition to produce metal oxide layer 204 with a desired shape.

[0036] At step 340, the GI layer 206 is deposited, as shown in Figure 2C. A GI layer 206 is deposited over at least a portion of the metal oxide layer 204 . GI layer 206 is in direct contact with metal oxide layer 204 . GI layer 206 comprises an insulating material such as silicon, silicon oxide (Si _x O _y ), silicon nitride (SiN _x ), other insulating materials, or combinations thereof. GI layer 206 may have a thickness of about 200 Å to about 8000 Å. Step 340 is performed using high density plasma chemical vapor deposition (HDP-CVD).

[0037] Step 340 includes nitrous oxide (N2O) at a flow rate of from about 0.40 sccm/ _cm2 to about 0.60 sccm/ ^cm2 and silane ( _SiH4 ) from about 0.01 sccm/ ^cm2 to about 0.60 sccm/ ^cm2 . N2O to _SiH4 ratio of about ₅ to about 40, a chamber pressure of about 75 ^mTorr to about 150 mTorr, a chamber temperature of about 70° C. to about 350° C., and a chamber temperature of about 80. C. to about 160.degree. C. for about 20 seconds to about 900 seconds. Step 340 uses HDP-CVD at an ICP power density of about 2 W/cm ² to about 6 W/cm ² , such as about 2.3 W/cm ² to about 5.3 W/cm ² at a frequency of about 1 MHz to about 15 MHz. , for example, at an ICP frequency of about 2 MHz to about 13.56 MHz, an applied bias power of about 0 W to about 200 W, and an ICP power of about 4000 W to about 10000 W. In some embodiments, silicon tetrafluoride ( _SiF4 ), disilane ( _Si2H6 ), oxygen gas ( _O2 ), ozone (O3), Ar, nitrogen gas _{( N2} ), ammonia _{( NH3} ), He or a mixture of the above are flowed in parallel. The spacing between the substrate and the gas source can be from about 7000mm to about 8000mm.

[0038] The GI layer 206 may be deposited at a rate of about 700 A/min to about 1500 A/min. The refractive index of the GI layer can be from about 1.8 to about 2.0. The percentage of silicon-hydrogen (Si—H) bonds can be from about 0.1% to about 12%. The percentage of silicon-nitrogen (Si—N) bonds can be from about 10% to about 25%. The peak position of silicon-oxygen bonds (Si—O) measured by spectroscopy can be from about 1050 1/cm to about 1100 1/cm. The stress of the GI layer 206 is from about -450 MPa to about 700 MPa. Exemplary process variables for step 340 in which GI layer 206 comprises Si _x N _y are shown in Table 1. Exemplary process variables for step 340 in which GI layer 206 comprises Si _x O _y are shown in Table 2.

[0039] Table 1 _: Exemplary process variables for step 340 for a GI layer comprising _SixNy . A blank cell indicates that the variable does not apply.

[0040] Table 2: Exemplary process variables for step 340 for a GI layer comprising Si _x O _y . A blank cell indicates that the variable does not apply.

[0041] In a capacitively-coupled plasma-enhanced chemical vapor deposition (CCP-CVD) process, opposing electrodes, such as parallel plate electrodes, are provided, one electrode coupled to ground and the other coupled to a power supply, between which a gas is introduced. to form, in effect, a capacitor capacitor. By powering the powered electrodes, electrical energy is capacitively coupled to the gas to form its plasma. The ion density of the plasma is a function of the power transferred to the gas. In ICP, on the other hand, a coil surrounds or overlies a gas region where a plasma is formed, and electrical energy flowing through the coil electromagnetically couples into the gas, ionizing or otherwise ionizing gas atoms or molecules. energize. Again, the ion density of the plasma is a function of the energy bound into the gas. In a CCP system, one of the electrodes is usually also the substrate support, so the power that can be coupled to the gas is limited by its potential adverse effects on the substrate. In contrast, when the ICP method is used, the power for ionizing gas atoms and molecules is separated from the circuit components that hold the substrate, and higher power can be used to impart high energy to the plasma. The ion density in the plasma can be increased without adversely affecting the substrate. In this way, HDP can be produced from an ICP source (ie, an HDP-CVD process).

[0042] It has been found that deposition of a GI layer 206 comprising SiO _x using HDP-CVD results in increased mobility of the underlying metal oxide layer 204, unexpectedly. The mobility of the metal oxide layer 204 (eg, InGaZnO ₄ ) can be from less than 15 cm ² /Vs to greater than about 150 cm ² /Vs, eg, up to about 450 cm ² /Vs, or higher. Moreover, the mobility at saturation of the metal oxide layer 204 can be greater than about 3000 cm ² /Vs. When using a CVD process with CCP to deposit _SiOx on the same metal oxide layer 204, there is no such increase in mobility or mobility at saturation. It is believed that deposition of the GI layer 206 using HDP-CVD causes chemical transformation of the underlying metal oxide layer 204, resulting in higher mobility. At the interface between the metal oxide layer 204 and the GI layer 206, the carrier density increases and the mobility of the metal oxide layer can be increased. In a metal oxide layer 204 comprising indium (In), the diffusion of In atoms from the metal oxide layer into the GI layer 206 can result in increased carrier generation and thus higher mobility. In addition, structural changes may occur in the metal oxide layer 204 to further increase mobility, such as healing of atomic defects through atomic diffusion.

[0043] At step 350, a gate electrode 208 is formed, as shown in Figure 2D. In some embodiments, gate electrode 208 is formed over GI layer 206 . The gate electrode 208 is made of molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, MoW, TiCu, MoCu, MoCuMo, TiCuTi , MoWCu, MoWCuMoW, conductive metal oxides such as indium tin oxide (InSnO) (ITO) and indium zinc oxide (InZnO) (IZO), or any combination thereof, and the like. It can be any conductive material. In some embodiments, gate electrode 208 is deposited in a single step. In another embodiment, the material of the gate electrode 208 is deposited in a first sub-step to form the metal layer, and one or more remaining portions of the metal layer are etched to create the gate electrode 208. be. Gate electrode 208 is configured to be connected to a gate line signal as a power supply (not shown) to supply a voltage across the layers of TFT 200 .

[0044] At step 360, one or more remaining portions 206 ^* of the GI layer 206 (Fig. 2D) are etched, as shown in Fig. 2E. In some embodiments, gate electrode 208 acts as a mask for etching GI layer 206 to a desired size and shape. In some embodiments, the wet etch rate (WER) of GI layer 206 is from about 200 Å/min to about 7000 Å/min. Step 360 may include dry etching.

[0045] At step 370, an interlevel dielectric (ILD) layer 210 is formed, as shown in Figure 2F. In some embodiments, ILD layer 210 is formed over gate electrode 208 and metal oxide layer 204 . ILD layer 210 may be a single silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating material, or Including insulating materials such as combinations. In some embodiments, ILD layer 210 is deposited using the same process parameters as step 330 . The ILD layer 210 may be planarized, such as by chemical mechanical polishing (CMP). The ILD layer 210 can be deposited using HDP-CVD or a CVD process using CCP.

[0046] Sequence 380 results in the formation of source electrode 212, drain electrode 214, source electrode via 216, and drain electrode via 218 in ILD layer 210, as shown in Figure 2G. Sequence 380 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, in a first step, a portion of ILD layer 210 is etched such that a portion of metal oxide layer 204 is exposed. In a second step, portions of the ILD that expose portions of metal oxide layer 204 are filled with a conductive material to form source electrode 212 , drain electrode 214 , source electrode via 216 , and drain electrode via 218 . be. The conductive material may be an alloy metal including Mo, Cr, Cu, Ti, Ta, W, MoW, a combination of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, a conductive material such as ITO or IZO. any combination of conductive materials, including conductive metal oxides, etc., or any combination thereof.

[0047] In step 390, a passivation layer 220 is formed as shown in Figure 2H. In some embodiments, passivation layer 220 is formed over ILD layer 210 , source electrode 212 , and drain electrode 214 . Passivation layer 220 may comprise any material used for ILD layer 210 or buffer layer 202 . Passivation layer 220 can be deposited using HDP-CVD or a CVD process using CCP. In some embodiments, passivation layer 220 is deposited using the same process parameters as step 330 . Passivation layer 220 may be planarized, such as by chemical mechanical polishing (CMP).

[0048] In some embodiments, a buffer layer (not shown) is disposed over substrate 102 and under metal oxide layer 204 . The buffer layer may be made of silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Contains insulating material.

[0049] In some embodiments, TFT 200 further includes a secondary buffer layer (not shown) disposed above the buffer layer and below metal oxide layer 204 . A shield metal (not shown) is disposed above the buffer layer, within the secondary buffer layer, and below the metal oxide layer 204 . The secondary buffer layer may comprise any of the buffer layer materials described above. The shield metal can include any of the gate electrode 208 materials described above. The shield metal reduces the exposure of TFT 200 to unwanted electromagnetic waves.

[0050] Figures 4A-4J are cross-sectional views illustrating two transistor structures 400 according to one embodiment. FIG. 5 is a flow diagram of a method 500 of forming two transistor structures 400 according to the same embodiment. For ease of explanation, FIGS. 4A-4J, 5, 6, and 7 are described with reference to chamber 100 of FIG. However, it should be noted that ICP-CVD chambers other than chamber 100 can be utilized with method 500 . Method 500 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191 , cause chamber 100 to perform method 500 .

[0051] As shown, two transistor structures 400 include a substrate 102 (Fig. 4A).

[0052] The method 500 begins at step 510 where the first metal oxide layer 204A is formed, as shown in Figure 4B. In some embodiments, a first metal oxide layer 204A is formed over the first portion 491 of the substrate 102 (or over the buffer layer 202, if present). Step 510 may be performed similarly to step 310 .

[0053] At step 540, the GI layer 206 (alternatively referred to as the interfacial GI layer) is deposited as shown in Figure 4C. A GI layer is deposited over at least a portion of the first metal oxide layer 204A. GI layer 206 is in direct contact with metal oxide layer 204A. Step 540 may be performed similarly to step 340 .

[0054] In step 550, a second metal oxide layer 204B is formed, as shown in Figure 4D. In some embodiments, the second metal oxide layer 204B is formed on the second portion 492 of the substrate 102 over the GI layer 206. FIG. Step 550 may be performed similarly to step 510 .

[0055] In step 555, a secondary GI layer (alternatively referred to as the bulk layer) 406 is deposited as shown in Figure 4E. A secondary GI layer 406 is deposited over the GI layer 206 and the second metal oxide layer 204B. Secondary GI layer 406 is in direct contact with second metal oxide layer 204B. Secondary GI layer 406 may include any material included in GI layer 206 . Deposition of the secondary GI layer includes a CVD process using CCP. Step 555 may be performed similarly to step 340 .

[0056] At step 560, a first gate electrode 208A and a second gate electrode 208B are formed as shown in Figure 4F. In some embodiments, first and second gate electrodes 208 A, 208 B are formed over secondary GI layer 406 . A first gate electrode 208A is formed over the first metal oxide layer 204A and a second gate electrode 208B is formed over the second metal oxide layer 204B. Step 560 may be performed similarly to step 350 .

[0057] At step 570, one or more remaining portions 206 ^* of the GI layer 206 and one or more remaining portions 406 ^* of the secondary GI layer 406 (Figure 4F) are etched, as shown in Figure 4G. In some embodiments, the first gate electrode 208A and the second gate electrode 208B act as a mask to etch the GI layer 206 to a desired size and shape, leaving the first GI layer portion (alternatively A first secondary GI portion (alternatively called a bulk GI layer) 406A, an underlayer 206B, and a GI layer 406B are formed. Similarly, in some embodiments, the first gate electrode 208A and the second gate electrode 208B act as a mask for etching the secondary GI layer 406 to a desired size and shape, and the first GI layer 406 is etched to a desired size and shape. Layer portion 206A, first secondary GI portion 406A, bottom layer 206B, and GI layer 406B are formed. Forming the lower layer 206B and the first GI layer portion 206A in a single step 570 reduces the total number of masking and etching steps. In addition, the reduction in masking and etching steps increases throughput and reduces operator cost of ownership (CoO). Step 570 also reduces the size of the two transistor structures 400, thus reducing the display space including the two transistor structures 400. FIG. Step 570 may be performed similarly to step 360 .

[0058] In step 580, an ILD layer 210 is formed, as shown in Figure 4H. In some embodiments, an ILD layer is formed over the first and second gate electrodes 208A, 208B. Step 580 may be performed similarly to step 370 .

[0059] Sequence 590 results in ILD layer 210 having first source electrode 212A, second source electrode 212B, first drain electrode 214A, second drain electrode 214B, and first drain electrode 214A, as shown in FIG. 4I. A source electrode via 216A, a second source electrode via 216B, a first drain electrode via 218A, and a second drain electrode via 218B are formed. Sequence 590 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, a portion of the ILD layer 210 is first stepped such that a portion of the first metal oxide layer 204A is exposed and a portion of the second metal oxide layer 204B is exposed. etched with In a second step, the ILD first metal oxide layer 204A is exposed to form source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B. The portion is filled with a conductive material. Sequence 590 may be implemented similarly to sequence 380 .

[0060] In step 595, a passivation layer 220 is formed as shown in Figure 4J. In some embodiments, passivation layer 220 is formed over ILD layer 210, source electrodes 212A, 212B, and drain electrodes 214A, 214B. Step 595 may be performed similarly to step 390 . Thus, in the two transistor structures 400, two TFTs 401A, 401B are formed. The two TFTs 401A, 401B can be connected in series or in parallel. The two TFTs 401A, 401B may receive the same input voltage signal or may receive different voltage signals.

[0061] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be made of silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Contains insulating material.

[0062] In some embodiments, the two transistor structure 400 further includes a secondary buffer layer (not shown) disposed above the buffer layer and below the metal oxide layer 204A and the lower layer 206B. include. One or more shield metals (not shown) are disposed over the buffer layer, within the secondary buffer layer, and under one or both of the metal oxide layers 204A, 204B.

[0063] Figure 6 is a diagram illustrating two transistor structures 600 according to one embodiment. Method 500 can also be used to form two transistor structures 600, as described in more detail below.

[0064] As shown, two transistor structures 600 include a first TFT 601A and a second TFT 601B. The first TFT 601A can be similar to the first TFT 401A (FIG. 4J). However, since the first TFT 601A does not include a secondary GI layer, step 555 can be omitted.

[0065] The second TFT 601B may be similar to the second TFT 401B (Fig. 4J). However, step 550 is performed after step 560 because the second metal oxide layer 204B is located above the ILD layer 210 . Also, the second source electrode 212B and the second drain electrode 214B directly contact the second metal oxide layer 204B and do not include source or drain electrode vias.

[0066] In some embodiments, the two transistor structure 600 further includes a secondary buffer layer (not shown) disposed over the buffer layer. One or more shield metals (not shown) are disposed over the buffer layer, within the secondary buffer layer, and under one or both of the metal oxide layers 204A, 204B.

[0067] The two TFTs 601A, 601B may be connected in series or in parallel. The two TFTs 601A, 601B may receive the same input voltage signal or different voltage signals.

[0068] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be made of silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Contains insulating material.

[0069] Figure 7 illustrates two transistor structures 700 according to one embodiment. Method 500 can also be used to form two transistor structures 700, as described in more detail below.

[0070] As shown, two transistor structures 700 include a first TFT 701A and a second TFT 701B. The first TFT 701A is similar to the first TFT 401A (FIG. 4J). However, the first TFT 701A does not include a secondary GI layer, so step 555 can be omitted. The two transistor structures 700 also include an etch stop layer (ESL) 710 located above the ILD layer 210 and below the passivation layer 220 . ESL 710 may be formed in a subsequent step after step 550 . Formation of ESL 710 may be performed similar to step 370 . ESL 710 may include any material included in ILD layer 210 . A first source electrode 212A and a first drain electrode 214A are disposed over the ESL 710 . Disposed within the ESL 710 and ILD layer 210 are a first source electrode via 216A and a first drain electrode via 218A.

[0071] The second TFT 701B is similar to the second TFT 401B (Fig. 4J). However, step 550 is performed after step 560 because second metal oxide layer 204B is located over ESL 710 . A second source electrode 212B and a second drain electrode 214B are disposed over the ESL 710 . Disposed within the ESL 710 are a second source electrode via 216B and a second drain electrode via 218B.

[0072] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be made of silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Contains insulating material.

[0073] In some embodiments, the two transistor structure 700 further includes a secondary buffer layer (not shown) disposed over the buffer layer. One or more shield metals (not shown) are disposed over the buffer layer, within the secondary buffer layer, and under one or both of the second metal oxide layers 204A, 204B.

[0074] The two TFTs 701A, 701B may be connected in series or in parallel. The two TFTs 701A, 701B may receive the same input voltage signal or different voltage signals.

[0075] Figure 8 illustrates two transistor structures 800 according to one embodiment. Method 300 can also be used to form two transistor structures 800, as described in more detail below.

[0076] As shown, two transistor structures 800 include a first TFT 801A and a second TFT 801B. The first TFT 801A can be similar to TFT 200 (FIG. 2H). The second TFT 801B can be similar to TFT 200 (FIG. 2H). However, the GI layer and gate electrode are not included. Two transistor structures 800 may be formed using method 300 wherein step 310 further includes depositing a second metal oxide layer 204B.

[0077] In some embodiments, a buffer layer (not shown) is disposed over substrate 102 and under metal oxide layer 204A. The buffer layer may be made of silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Contains insulating material.

[0078] The two transistor structure 800 further includes a buffer layer 202 disposed over the substrate 102 . Buffer layer 202 may be silicon dioxide (SiO _x ), silicon nitride (SiN _x ), multilayer silicon nitride/silicon oxide (SiN _x /SiO _y ), silicon oxynitride (SiON), other insulating materials, combinations thereof, or the like. of insulating material. A secondary buffer layer 203 is disposed over the buffer layer 202 . Secondary buffer layer 203 comprises any of the materials contained in buffer layer 202 . Shield metal 808B is disposed above buffer layer 202, within secondary buffer layer 203, and below metal oxide layer 204B. Shield metal 908B is configured to be connected to a gate line signal as a power supply (not shown) for supplying voltage across the layers of TFT 801B.

[0079] In some embodiments, the two transistor structures 800 include additional shield metal disposed above the buffer layer 202, within the secondary buffer layer 203, and below the first metal oxide layer 204A. Including further.

[0080] The two TFTs 801A, 801B may be connected in series or in parallel. Also, the two TFTs 801A, 801B may receive the same input voltage signal or different voltage signals.

[0081] Figures 9A-9N are schematic cross-sectional views illustrating two transistor structures 900 according to one embodiment. FIG. 10 is a flow diagram of a method 1000 of forming two transistor structures 900 according to the same embodiment. Although the method steps are described in conjunction with FIGS. 1, 9A-9N, and 10, one skilled in the art will recognize that any system configured to perform the steps of method 1000 in any order is described herein. will be understood to fall within the scope of the embodiments described herein. For ease of explanation, FIGS. 9A-9N and 10 are described with reference to chamber 100 of FIG. However, it should be noted that ICP-CVD chambers other than chamber 100 can be utilized in conjunction with method 1000 . Method 1000 may be stored on or accessible to controller 190 as a computer-readable medium containing instructions that, when executed by CPU 191 , cause chamber 100 to perform method 1000 .

[0082] As shown, two transistor structures 900 include a substrate 102 (Fig. 9A).

[0083] The method 1000 begins at step 1005 where a polysilicon layer 904A is deposited, as shown in Figure 9B. In some embodiments, polysilicon layer 904A is deposited over substrate 102 (or over buffer layer 202, if present). Polysilicon layer 904A may be deposited using any desired method. Step 1005 includes doping polysilicon layer 904A with an n-type or p-type dopant (eg, B or N), such as by ion implantation.

[0084] In step 1010, a first GI layer 206 is deposited, as shown in Figure 9C. In some embodiments, a first GI layer is deposited over at least a portion of polysilicon layer 904A. Step 1010 may be performed similarly to step 340 .

[0085] At step 1020, a first gate electrode 208A and a shield metal 908B are formed as shown in Figure 9D. In some embodiments, first gate electrode 208 A and shield metal 908 B are formed over first GI layer 206 . A first gate electrode 208A is formed over polysilicon layer 904A. In some embodiments, a metal layer is deposited in a first sub-step, and one or more remaining portions of the metal layer are deposited in a second sub-step to form the first gate electrode 208A and the shield metal 908B. is removed. Step 1020 may be performed similarly to step 350 .

[0086] At step 1025, a secondary ILD layer 910 is formed, as shown in Figure 9E. In some embodiments, a secondary ILD layer 910 is formed over the first gate electrode 208A and the shield metal 908B. Secondary ILD layer 910 includes any of the materials of ILD layer 210 . Step 1025 may be performed similarly to step 370 .

[0087] Sequence 1030 results in the formation of secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A in secondary ILD layer 910, as shown in Figure 9F. be done. Sequence 1030 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, a portion of secondary ILD layer 910 is etched in a first step to expose a portion of polysilicon layer 904A. Portions of the secondary ILD layer 910 are removed from the conductive material in a second step to form secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A. is filled with Secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A are connected to first source electrode 212A, first drain electrode 214A, first source electrode via 216A, and any of the materials included in the first drain electrode via 218A. Sequence 1030 may be implemented similarly to sequence 380 .

[0088] In step 1035, a secondary buffer layer 203 is formed, as shown in Figure 9G. In some embodiments, secondary buffer layer 203 is deposited over secondary source electrode 912A, secondary drain electrode 914A, secondary source electrode via 916A, and secondary drain electrode via 918A. The secondary buffer layer 203 can be deposited using HDP-CVD or CVD processes using CCP.

[0089] In step 1040, a second metal oxide layer 204B is formed, as shown in Figure 9H. In some embodiments, a second metal oxide layer 204B is formed over secondary buffer layer 203 . Step 1040 may be performed similarly to step 510 .

[0090] At step 1050, a secondary GI layer 406 is deposited, as shown in Figure 9I. A secondary GI layer 406 is deposited over the second metal oxide layer 204B. Secondary GI layer 406 is in direct contact with second metal oxide layer 204B. Step 1050 may be performed similarly to step 555 .

[0091] In step 1060, a second gate electrode 208B is formed as shown in Figure 9J. In some embodiments, a second gate electrode 208B is formed over secondary GI layer 406 . A second gate electrode 208B is formed over the second metal oxide layer 204B. Step 1060 may be performed similarly to step 350 .

[0092] At step 1065, one or more remaining portions 406 ^* of the secondary GI layer 406 (Fig. 9J) are etched, as shown in Fig. 9K. In some embodiments, second gate electrode 208B acts as a mask for etching secondary GI layer 406 to a desired size and shape. Step 1065 may be performed similarly to step 360 .

[0093] At step 1070, an ILD layer 210 is formed, as shown in Figure 9L. In some embodiments, an ILD layer 210 is formed over the second gate electrode 208B and the metal oxide layer 206B. Step 1070 may be performed similarly to step 370 .

[0094] Sequence 1075 results in the formation of source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B in the ILD layer 210, as shown in Figure 9M. Sequence 1075 may include any conventional method of forming gate and drain electrode structures used in the art. First source electrode via 216A and first drain electrode via 218A electrically contact secondary source electrode 912A and secondary drain electrode 914A, respectively. Sequence 1075 may be implemented similarly to sequence 380 .

[0095] At step 1080, a passivation layer 220 is formed, as shown in Figure 9N. In some embodiments, passivation layer 220 is deposited over ILD layer 210, source electrodes 212A, 212B, and drain electrodes 214A, 214B. Step 1080 may be performed similarly to step 390 . Thus, two transistor structures 400 are formed with a first TFT (alternatively called a polysilicon TFT) 901A and a second TFT (alternatively called a metal oxide (MOx) TFT) 901B.

[0096] In some embodiments, a shield metal 908B is formed over the secondary ILD layer 910. FIG. In these embodiments, step 1020 is separated into two sub-steps and the sub-step in which shield metal 908B is formed is performed after step 1025. FIG.

[0097] In some embodiments, the sequence 1030 is not performed, so the secondary source electrode, secondary source electrode via, secondary drain electrode, and secondary drain electrode via are not formed. In these embodiments, first source electrode via 216A and first drain electrode via 216A are also located in secondary ILD layer 910 and secondary buffer layer 203 . Thus, first source electrode via 216A and first drain electrode via 218A are in direct electrical contact with polysilicon layer 904A.

[0098] In some embodiments, polysilicon layer 904 is P-type doped (eg, with B) and metal oxide layer 204B is N-type doped (eg, with N).

[0099] The two TFTs 901A, 901B may be connected in series or in parallel. Also, the two TFTs 901A, 901B may receive the same input voltage signal or different voltage signals.

[0100] Figure 11 is a diagram illustrating two transistor structures 1100 according to one embodiment. Method 300 can also be used to form two transistor structures 1100, as described in more detail below.

[0101] As shown, the two transistor structure 1100 includes a first TFT 1101A and a second TFT 1101B. The first TFT 1101A can be similar to TFT 200 (FIG. 2I). However, instead of the first metal layer, a polysilicon layer 904A is included. Step 310 thus forms only the second metal oxide layer 904B. Also included is step 1005 . The second TFT 1101B is similar to TFT 200 (FIG. 2I). The two transistor structure 1100 further includes a buffer layer 202 located above the substrate 102 and below the ILD layer 210 . The two transistor structure 1100 further includes a shield metal 908B. Shield metal 908B is disposed above substrate 102, within buffer layer 202, and below metal oxide layer 904B. GI layer 206A does not increase the mobility of polysilicon layer 904A underlying GI layer 206A.

[0102] In some embodiments, the GI layer 206 is etched in step 360 such that there is a GI layer both over the entire surface 904S of the polysilicon layer 904A and over the metal oxide layer 204B. be.

[0103] In some embodiments, the GI layer 206 is not etched, so the GI layer 206 is disposed as one layer over both the polysilicon layer 904A and the metal oxide layer 204B.

[0104] The two TFTs 1101A, 1101B may be connected in series or in parallel. Also, the two TFTs 1101A, 1101B may receive the same input voltage signal or different voltage signals.

[0105] The two TFTs in each of the two transistor structures described above (e.g., the two transistor structures 400, 600, 700, 800, 900, 1100) are used for liquid crystal display (LCD) or organic light emitting diode (OLED) display pixels. circuit, or as a gate driver in a panel (GIP) circuit. For example, each TFT in the two transistor structure can be used as a switching TFT or driving TFT in an OLED pixel circuit. The two transistor structures each have a first TFT (e.g. TFT 401A, 601A, 701A, 801A, 901B, TFT 401A, 601A, 701A, 801A, 901B, 1101B). The first TFT has a higher mobility than the second TFT because the GI layer is deposited over the metal oxide layer in the first TFT, and the GI layer is deposited by HDP-CVD. . A GI layer in direct contact with a metal oxide layer, a GI layer deposited by HDP-CVD, increases the mobility of the underlying metal oxide layer, which is described in detail above in the description of method 300. there is According to one embodiment, the first TFT has a mobility greater than about 30 cm2/Vs and the second TFT has a mobility less than about 30 cm2/Vs.

[0106] One or more optional steps may be included in any of the methods 300, 500, 1000 described above. Optionally, any of the disclosed metal oxide layers can be pretreated. The pretreatment includes a gas containing nitrous oxide (N ₂ O) at a flow rate of about 0.40 sccm/cm ² to about 0.60 sccm/cm ² and a gas containing argon gas (Ar) at a flow rate of about 0 sccm/cm ² (i.e., , no co-flow of Ar) to about 0.60 sccm/cm ² at a chamber pressure of about 1 mTorr to about 300 mTorr, a temperature of about 25° C. to about 400° C., and a time period of about 1 second to about 600 seconds. including. In one example, the pretreatment includes a gas comprising nitrous oxide (N ₂ O) at a flow rate of about 0.40 sccm/cm ² to about 0.60 sccm/cm ² and a gas comprising argon gas (Ar) at a flow rate of about 0 sccm/cm 2 . cm ² (i.e., no co-flow of Ar) to about 0.60 sccm/cm ² , a chamber pressure of about 10 mTorr to about 150 mTorr, a temperature of about 50° C. to about 300° C., and a temperature of about 1 second to about 45 seconds. including flushing between In some embodiments, nitrogen dioxide ₍ NO2), neon gas (Ne), helium gas (He), or mixtures of the above may also be co-flowed. Pretreatment can increase the mobility of the pretreated metal oxide layer. Pretreatment can be performed in a static chamber, or can be performed with a source in a dynamic chamber, such as chamber 100 described above.

[0107] Optionally, a seed layer may be deposited over any of the metal oxide layers disclosed herein. A seed layer is deposited over at least a portion of the metal oxide layer. The seed layer improves adhesion of layers (eg, GI layers) deposited thereon. The seed layer can have a thickness of about 1 nm to about 100 nm. Deposition of the seed layer can include a CVD process using CCP. For example, seed layer deposition may include a CVD process using CCP, then a GI layer is deposited over the interfacial seed layer, the GI layer being deposited by an HDP-CVD process. Due to the thinness of the seed layer, the metal oxide layer under the seed layer is still affected by the HDP-CVD process, which advantageously increases the mobility of the metal oxide layer. In any of the above embodiments, removal of one or more remaining portions of the seed GI layer may also be performed.

[0108] Metal oxide layer formation, optional metal oxide layer pretreatment, optional seed layer deposition, and GI layer deposition (hereinafter collectively referred to as the MO/GI process) can be performed in a single step without a vacuum break. It can be performed in one chamber (eg, chamber 100). In another embodiment, the MO/GI processes can be performed in an integrated system with multiple chambers without vacuum breaks, and each MO/GI process can be performed in any chamber. Alternatively, any of the MO/GI steps can be performed in any number of chambers and a vacuum break can be included during the MO/GI steps.

[0109] In one example, the formation of the metal oxide layer is performed in a first chamber, the substrate is transferred under vacuum to a second chamber, and the GI layer is deposited in the second chamber. In another example, metal oxide layer formation is performed in a first chamber, the substrate is transferred to a second chamber with a vacuum break, and the GI layer is deposited in the second chamber.

[0110] As described above, a method of forming a TFT and a method of forming two transistor structures are provided. The method includes depositing one or more metal oxide layers and/or polysilicon layers. A GI layer is deposited using an HDP-CVD process over the metal oxide layer(s).

[0111] Depositing the GI layer using HDP-CVD results in unexpectedly high mobility of the metal oxide and/or polysilicon layers deposited thereon. Selective placement of the GI layer controls the mobility of the underlying layer, depending on whether the GI layer is deposited by HDP-CVD or by a CVD process using CCP. Depositing a GI layer allows the mobility of the underlying layer to be controlled after layer deposition, ie the mobility may be enhanced after deposition as well as during deposition.

[0112] While the foregoing is directed to embodiments of the disclosure, other and further embodiments of the disclosure are contemplated without departing from its basic scope as determined by the following claims. It is possible.

Claims (20)

A method of forming a thin film transistor, comprising:
forming a metal oxide layer over the first portion of the substrate;
depositing a gate insulator (GI) layer over the metal oxide layer, the silicon-containing layer being deposited in a high density plasma-enhanced chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP); said HDP-CVD process comprising depositing
an ICP power density of about 2.3 W/cm ² to about 5.3 W/cm ² ;
depositing a gate insulator (GI) layer over the metal oxide layer having an ICP frequency of about 2 MHz to about 13.56 MHz;
forming a gate electrode on the GI layer;
and etching one or more remaining portions of the GI layer. pretreating the metal oxide layer prior to depositing the GI layer, comprising exposing the metal oxide layer to a pretreatment ICP. 2. The method of claim 1, further comprising pretreating the oxide layer. _3. The method of claim 2, wherein the pretreatment ICP is formed from nitrous oxide (N2O), argon (Ar), or combinations thereof. depositing a bulk GI layer over the GI layer, comprising a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP). 2. The method of claim 1, further comprising: depositing a seed layer over the metal oxide layer prior to depositing the GI layer, comprising a CVD process using CCP, wherein the seed layer has a thickness of less than about 100 nm; 2. The method of claim 1, further comprising depositing a seed layer over said metal oxide layer prior to depositing a GI layer. 2. The method of claim 1, wherein depositing the GI layer comprises heating the substrate to a temperature of about 70<0>C to about 350<0>C. forming an interlevel dielectric (ILD) layer over the gate electrode;
forming a source electrode, a source electrode via, a drain electrode, and a drain electrode via in the ILD layer;
2. The method of claim 1, further comprising forming a passivation layer over said source electrode, said drain electrode, and said ILD layer. 2. The method of claim 1, further comprising forming a polysilicon layer or an additional metal oxide layer over the second portion of the substrate. A method of forming a thin film transistor device, comprising:
forming a first metal oxide layer over a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT); forming a first metal oxide layer on the
depositing an interfacial gate insulator (GI) layer of the first TFT in contact with the first metal oxide layer over the first portion of the substrate;
forming a lower layer over a second portion of the substrate, the second portion of the substrate corresponding to a second TFT, the lower layer being the second portion of the second TFT; forming the interfacial GI layer and the bottom layer in contact with the bottom surface of the metal oxide layer of 2,
depositing a first silicon-containing layer over the first portion and the second portion, the first silicon-containing layer being deposited by high density plasma chemistry using inductively coupled plasma (ICP) deposited in a vapor phase deposition (HDP-CVD) process, the HDP-CVD process comprising:
an ICP power density of about 5.3 W/cm ² ;
depositing a first silicon-containing layer over the first portion and the second portion having an ICP frequency from about 2 MHz to about 13.56 MHz; depositing an interfacial gate insulator (GI) layer of the first TFT in contact with the first metal oxide layer above and forming a bottom layer over a second portion of the substrate; ,
forming the second metal oxide layer of the second TFT with the bottom surface in contact with the underlying layer;
depositing a bulk GI layer of the first TFT in contact with the interfacial GI layer and forming a GI layer of the second TFT in contact with a top surface of the second metal oxide layer; forming the bulk GI layer and the GI layer includes a second silicon-containing process over the first portion and the second portion in a chemical deposition process (CVD) using a capacitively coupled plasma (CCP); depositing a bulk GI layer of the first TFT in contact with the interfacial GI layer and a GI of the second TFT in contact with a top surface of the second metal oxide layer; forming a layer;
forming a first gate electrode of the first TFT over the first portion and forming a second gate electrode of the second TFT over the second portion;
to form the interfacial GI layer of the first TFT, the bulk GI layer of the first TFT, the GI layer of the second TFT, and the bottom layer of the second TFT, the removing one or more remaining portions of the second silicon-containing layer from the first portion and the second portion;
forming an interlevel dielectric (ILD) layer over the substrate. 10. The method of claim 9, wherein depositing the interfacial GI layer and forming the underlying layer are included in the same step. The first gate electrode and the second gate electrode are made of molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof. 10. The method of claim 9, comprising: 10. The method of claim 9, wherein the bulk GI layer comprises silicon oxide (Si _x O _y ) and the first metal oxide layer comprises In-Ga-Zn-O. 10. The method of claim 9, wherein the bulk GI layer has a higher atomic concentration of indium (In) atoms than the interfacial GI layer. A method of forming a thin film transistor device, comprising:
Forming a polysilicon layer over a first portion of a substrate, the first portion of the substrate corresponding to a polysilicon thin film transistor (TFT). forming a layer;
depositing a first gate insulator (GI) layer over the polysilicon layer of the first portion of the substrate and over a second portion of the substrate, the second portion of the substrate comprising: depositing a first gate insulator (GI) layer over the polysilicon layer in the first portion of the substrate and over a second portion corresponding to a metal oxide (MOx) TFT;
forming a first gate electrode on the first GI layer of the polysilicon TFT and forming a shield metal of the MOx TFT;
forming a first interlevel dielectric (ILD) layer over the first GI layer, the first gate electrode, and the shield metal;
forming a metal oxide layer of the MOx TFT over the first ILD layer of the second portion of the substrate;
forming a second GI layer on the metal oxide layer, the silicon-containing layer being deposited in a high density plasma-enhanced chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP); said HDP-CVD process comprising:
an ICP power density of about 2.3 W/cm ² to about 5.3 W/cm ² ;
forming a second GI layer on the metal oxide layer having an ICP frequency of about 2 MHz to about 13.56 MHz;
forming a second gate electrode on the second GI layer;
forming a second ILD layer over the first ILD layer, the metal oxide layer, and the second gate electrode. 15. The method of claim 14, wherein the shield metal comprises molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof. 15. The method of claim 14, wherein forming the first ILD layer comprises an HDP-CVD process. 15. The method of claim 14, further comprising forming a passivation layer over said second ILD layer. 15. The method of claim 14, further comprising forming a buffer layer over said first ILD layer. 15. The method of claim 14, wherein said MOx TFT has a mobility greater than 30 cm< ² >/Vs. 15. The method of claim 14, wherein depositing the first GI layer comprises the HDP-CVD process.

Images