WO2020240725A1 - ヘテロ接合バイポーラトランジスタおよびその作製方法 - Google Patents

ヘテロ接合バイポーラトランジスタおよびその作製方法 Download PDF

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WO2020240725A1
WO2020240725A1 PCT/JP2019/021213 JP2019021213W WO2020240725A1 WO 2020240725 A1 WO2020240725 A1 WO 2020240725A1 JP 2019021213 W JP2019021213 W JP 2019021213W WO 2020240725 A1 WO2020240725 A1 WO 2020240725A1
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layer
emitter
collector
nitride semiconductor
type
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French (fr)
Japanese (ja)
Inventor
拓也 星
佑樹 吉屋
悠太 白鳥
杉山　弘樹
井田　実
松崎　秀昭
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NTT Inc
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Nippon Telegraph and Telephone Corp
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Priority to US17/612,463 priority Critical patent/US12142672B2/en
Priority to JP2021521646A priority patent/JP7147972B2/ja
Priority to PCT/JP2019/021213 priority patent/WO2020240725A1/ja
Publication of WO2020240725A1 publication Critical patent/WO2020240725A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H10D62/136—Emitter regions of BJTs of heterojunction BJTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides

Definitions

  • the present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.
  • Nitride semiconductors such as gallium nitride (GaN) are promising as power devices with high withstand voltage characteristics and high-frequency devices with high output because they have a large bandgap and high dielectric breakdown electric field strength.
  • GaN has a hexagonal wurtzite structure as a stable phase and has polarization in the c-axis direction.
  • High electron mobility transistors (HEMTs) that form an AlGaN / GaN interface with high-concentration two-dimensional electron gas by utilizing the effect of polarization generated in the c-axis direction have been actively studied. ..
  • HBTs heterojunction bipolar transistors
  • HBTs are expected to be applied to high frequency and power applications because of their characteristics of being able to increase the current density and power density.
  • HBTs are composed of an emitter, a base, and a collector.
  • HBTs using nitride semiconductors are manufactured as shown below.
  • a GaN sub-collector and a GaN collector are formed on a substrate such as sapphire via a buffer made of GaN or AlN.
  • the GaN subcollector is formed as an n + type, and the GaN collector is formed as an n type (or unintentionally doped: UID).
  • the sub-collector layer is doped with a high concentration in order to reduce the resistance. Further, the thickness of the collector layer is a trade-off between the carrier running time and the withstand voltage, and the thinner the collector layer, the higher the cutoff frequency (ft), but the lower the withstand voltage. Therefore, design in consideration of these trade-offs.
  • a p-type doped GaN base layer is formed on the collector layer. The higher the base doping concentration, the higher the maximum oscillation frequency (fmax) of the high frequency element, so that the base layer is made as high as possible.
  • the concentration of the base is increased, the recombination current near the emitter-base interface increases and the current gain decreases. Therefore, a material having a bandgap larger than that of the base is usually applied to the emitter layer.
  • the emitter layer is made of AlGaN.
  • a high-concentration n-type doped GaN contact layer for emitter contact is formed on the AlGaN emitter (Non-Patent Documents 1 and 2).
  • Non-Patent Documents 3 and 4 Even in the above-mentioned HBT using nitride semiconductors, device characteristics that make use of the features such as high current gain and current density have already been reported (Non-Patent Documents 3 and 4). However, the high frequency performance of these reported HBTs is inferior to that of the above-mentioned HEMTs, and there is a problem in particularly increasing the maximum oscillation frequency fmax. The biggest factor that limits the performance of HBTs using nitride semiconductors is the high concentration of impurities in the P-type layer.
  • bizcyclopentadienyl magnesium Cp2-Mg
  • Mg bizcyclopentadienyl magnesium
  • Non-Patent Document 5 In order to solve such a low hole concentration of GaN, a technique using two-dimensional hole gas generated by polarization has been reported (Non-Patent Document 5).
  • n + GaN which is an emitter contact layer is grown on a self-supporting substrate made of GaN
  • an undoped AlGaN (50 mn, Al composition 0.1) emitter layer an undoped GaN (20 nm) and Mg-doped p-type GaN (Mg: 1x10 19 cm -3 , 80 nm) is formed as a base layer.
  • the plane orientation of GaN on a general GaN substrate is Ga polarity (III polarity, + C axis direction).
  • the interface between the AlGaN emitter and undoped GaN is two-dimensionally positive due to the effects of piezoelectric polarization and spontaneous polarization. Pore gas is formed.
  • an HBT having a lower base resistance can be produced.
  • the place where the two-dimensional hole gas is formed is the interface with the undoped GaN formed on AlGaN. Therefore, it is necessary to form AlGaN, which is a wide-gap material, on the substrate side (lower side) of the base.
  • the emitter layer has a wider gap than the base layer for the purpose of improving the current gain as described above. Therefore, since it is necessary to form AlGaN on the lower side of the base, it is necessary to make AlGaN act as an emitter, and the emitter must be below the base, that is, a so-called collector top (or collector up) type HBT. Don't get.
  • the collector top structure has the advantage that the base-collector capacitance can be lowered if the collector electrode can be made small, but since the emitter mesa diameter cannot be made small, the injection current density cannot be increased, and the high frequency characteristics and current such as the surface level can not be increased. There is concern about the effect on gain and withstand voltage. If the above-mentioned structure is forcibly applied to the emitter up, AlGaN will be further formed on the p-GaN, but in this case, the band bends in the direction of canceling the holes due to the effect of polarization. , The characteristics will be impaired.
  • Non-Patent Document 5 a technique of manufacturing a device with N polarity (-C plane growth) can be considered.
  • the polarization axis of the crystal is reversed as compared with the group III polar plane growth. Therefore, in order to form a two-dimensional hole gas, a buffer layer necessary for N-polar growth is first formed on the substrate, then a sub-collector layer and a collector layer are grown, and then on p-type GaN.
  • a heterostructure called undoped GaN / undoped AlGaN may be formed.
  • a buffer layer obtained by surface-nitriding a sapphire substrate, a special buffer layer using the C surface of a SiC substrate, or the like is required. Even if such a special buffer layer is used, the crystal quality (defect density and flatness) is inferior to that of a general group III polar plane.
  • the above-mentioned structure by N-polar growth forms undoped GaN on the p-type GaN layer and further grows AlGaN, but the growth conditions of p-type GaN are significantly different from those of ordinary GaN because it is doped with Mg. ing. It is not easy to form high quality GaN or AlGaN on such p-type GaN.
  • the current gain of HBTs is greatly affected by the quality of the emitter and the emitter-base interface. Therefore, it is assumed that it is difficult to obtain a desired current gain characteristic in the structure by N-polar growth in which the p-type GaN is grown first.
  • a heterojunction bipolar transistor using a nitride semiconductor is expected to have a higher withstand voltage than a field effect transistor structure, but the resistance can be lowered by increasing the hole concentration in the base layer. There is a problem that it is difficult to improve the high frequency characteristics because it is difficult.
  • the present invention has been made to solve the above problems, and to enable higher frequency characteristics of a heterojunction bipolar transistor using a nitride semiconductor without forming a collector top structure. With the goal.
  • an emitter contact layer made of an n-type nitride semiconductor and a nitride having a band gap larger than that of the nitride semiconductor constituting the emitter contact layer are formed on a first substrate.
  • a collector layer composed of an n-type nitride semiconductor having the same band gap as the nitride semiconductor constituting the p-type base layer, and an n-type sub-collector layer composed of the same nitride semiconductor as the collector layer.
  • Sub-collector layer, collector layer, p-type base layer, base layer, emitter layer, and emitter contact layer are formed on the second substrate in this order with the main surface as the Group V polar surface.
  • the fifth step of forming the emitter electrode on the emitter contact layer is provided.
  • the fifth step includes a step of thinning the emitter layer at a portion where the base electrode is formed and a step of forming the base electrode on the thinned emitter layer.
  • an eighth step of forming the second metal layer is provided, and in the second step, the first substrate and the second substrate are brought together in a state of facing the first metal layer and the second metal layer. to paste together.
  • the emitter contact layer, the base layer, the p-type base layer, the collector layer, and the sub-collector layer are each composed of GaN, and the emitter layer is composed of AlGaN.
  • the heterojunction bipolar transistor according to the present invention has a sub-collector layer formed on a substrate and made of a nitride semiconductor having a relatively high concentration of n-type, and a sub-collector formed on the sub-collector layer. It is composed of an n-type collector layer composed of the same nitride semiconductor as the layer and a nitride semiconductor having the same band gap as the nitride semiconductor constituting the collector layer formed on the collector layer and is p-type. An undoped base layer formed on the p-type base layer and composed of the same nitride semiconductor as the p-type base layer, and formed on the base layer.
  • an emitter layer made of a nitride semiconductor having a band gap larger than that of the nitride semiconductor constituting the base layer, and a nitride semiconductor having a band gap smaller than that of the nitride semiconductor forming the emitter layer formed on the emitter layer.
  • the sub-collector layer, collector layer, p-type base layer, base layer, emitter layer, and emitter contact layer are provided with an emitter electrode formed above and a collector electrode connected to the sub-collector layer. It is formed on the substrate in a surface state.
  • the emitter layer at the portion where the base electrode is formed is formed thinner than the other regions.
  • a metal layer formed between the substrate and the sub-collector layer and serving as a collector electrode is provided.
  • the emitter contact layer, the base layer, the p-type base layer, the collector layer, and the sub-collector layer are made of GaN, and the emitter layer is made of AlGaN.
  • the sub-collector layer, the collector layer, the p-type base layer, the base layer, the emitter layer, and the emitter contact layer are placed on the substrate with the main surface as a group V polar surface. Since it is formed, the high frequency characteristics of the heterojunction bipolar transistor using a nitride semiconductor can be made higher without forming a collector top structure.
  • FIG. 1A is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of an intermediate process for explaining a
  • FIG. 1E is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1F is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1G is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1H is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1I is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1J is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1K is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1L is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1M is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1N is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1O is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 1P is a cross-sectional view showing a state of an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2 is a band diagram showing a band lineup of heterojunction bipolar transistors according to the embodiment.
  • the emitter contact layer 105, the emitter layer 106, the base layer 107, the p-type base layer 108, the collector layer 109, and the sub-collector layer 110 are mainly placed on the first substrate 101 in this order. Crystal growth occurs with the surface as a group III polar surface (first step).
  • the first substrate 101 is not particularly limited as long as it can carry out general GaN, AlGaN, or InGaN crystal growth and can carry out peeling or removal of the first substrate 101 described later. ..
  • the first substrate 101 can be made of, for example, silicon or sapphire (Al 2 O 3 ).
  • the emitter contact layer 105 is composed of a nitride semiconductor (for example, GaN) having a relatively high concentration of n-type, such as an impurity concentration of 1 ⁇ 10 19 / cm 3 or more. Since the emitter contact layer 105 is in contact with an emitter electrode described later to form an emitter contact, the emitter contact layer 105 is formed by increasing the doping concentration to some extent.
  • a nitride semiconductor for example, GaN
  • the emitter layer 106 is composed of a nitride semiconductor (for example, AlGaN) having a bandgap larger than that of the nitride semiconductor constituting the emitter contact layer 105.
  • the emitter layer 106 is a layer for forming a two-dimensional hole gas by the effect of polarization in the c-axis direction of the nitride semiconductor. It also functions as an emitter of a heterojunction bipolar transistor.
  • the emitter layer 106 can be composed of, for example, AlGaN having a uniform composition, but it can also have a "graded AlGaN" structure in which the Al composition gradually increases from the side of the emitter contact layer 105 to the side of the base layer 107. .. Further, the Al composition of the emitter layer 106 at the portion in contact with the emitter contact layer 105 may be set to 0. By doing so, the band offset of the heterojunction at the emitter / emitter contact interface described later becomes small, and it becomes difficult to form a two-dimensional electron gas at this interface.
  • the base layer 107 is composed of an undoped nitride semiconductor (for example, GaN) having a bandgap smaller than that of the nitride semiconductor constituting the emitter layer 106.
  • the base layer 107 is formed on the emitter layer 106 when viewed from the first substrate 101. Since the base layer 107 forms the main surface as a group III polar surface, two-dimensional hole gas is formed at the interface between the base layer 107 and the emitter layer 106.
  • the p-type base layer 108 is made of the same nitride semiconductor (for example, GaN) as the base layer 107 to form a p-type.
  • Mg is generally used as the p-type dopant for forming the p-type base layer 108 into the p-type. Since the p-type base layer 108 is doped in a p-type, the band of the base layer 107 is strongly bent toward the interface with the emitter layer 106, and a two-dimensional hole gas is formed.
  • the collector layer 109 is composed of an n-type nitride semiconductor (for example, GaN) having the same bandgap as the nitride semiconductor constituting the p-type base layer 108.
  • the collector layer 109 is doped with n-type impurities at a relatively low concentration.
  • the sub-collector layer 110 is made of the same nitride semiconductor (for example, GaN) as the collector layer 109, and has a relatively high concentration of n-type impurities such as 1 ⁇ 10 19 / cm 3 or more.
  • the sub-collector layer 110 also functions as a collector contact, and is formed in a state where the doping concentration is increased to some extent, like the emitter contact layer 105.
  • the nucleation layer 102, the sacrificial layer 103, and the etch stop layer 104 are formed on the first substrate 101, and the emitter contact layer 105 is formed on the nucleation layer 102, the sacrifice layer 103, and the etch stop layer 104.
  • the nucleation layer 102 is a layer that becomes a nucleus at the initial stage of growth when general GaN, AlGaN, and InGaN are grown on the first substrate 101, which is a dissimilar material.
  • the material and growth conditions of the nucleation layer 102 are changed according to the material constituting the first substrate 101 and the material of the layer growing on the first substrate 101.
  • the nucleation layer 102 is formed so that the layer above the nucleation layer 102 has the group III polar plane as the main plane orientation.
  • most of the general GaN growth techniques can be carried out within the range of known techniques by growing and folding the group III polar plane as the main plane orientation.
  • the sacrificial layer 103 is a layer that is sacrificed when the etch stop layer 104 is exposed after removing the first substrate 101, which will be described later. Further, the sacrificial layer 103 grows to a thickness of about several ⁇ m, reduces the penetration dislocation density, and also functions as a layer for improving the crystal quality of the upper layer than the etch stop layer 104. Further, since the nucleation layer 102 is adjusted so that the group III polar plane is the main plane orientation, the main surface of the layer above the sacrificial layer 103 is the group III polar plane.
  • the etch stop layer 104 is a layer for stopping etching when removing the nucleation layer 102 and 103 sacrificial layer after removing the first substrate 101, which will be described later.
  • the above-mentioned nucleation layer 102, sacrificial layer 103, etch stop layer 104, emitter contact layer 105, emitter layer 106, base layer 107, p-type base layer 108, collector layer 109, and sub-collector layer 110 are well-known crystals. It can be formed by growth technology. For example, each of the above-mentioned layers can be sequentially epitaxially grown on the first substrate 101 by a metalorganic chemical vapor deposition method, a molecular beam epitaxy method, a hydride vapor phase growth method, or the like.
  • the nucleation layer 102, the sacrificial layer 103, the etch stop layer 104, the emitter contact layer 105, the emitter layer 106, the base layer 107, the p-type base layer 108, the collector layer 109, and the sub-collector layer 110 are in the same growth apparatus. It is not necessary to form the film by continuously epitaxially growing it at one time.
  • the nucleation layer 102, the sacrificial layer 103, the etch stop layer 104, the emitter contact layer 105, the emitter layer 106, the base layer 107, and the p-type base layer 108 are sequentially and continuously formed in the same growth apparatus.
  • the growth can be interrupted once and heat treatment can be performed using another heat treatment apparatus.
  • holes are inactivated by carriers gas and H contained in raw materials in the growth of p-type GaN (p + GaN) at a higher concentration. There is. For this reason, a technique for activating acceptors by growing p + GaN and then heat-treating it in an atmosphere without H is generally used.
  • the first substrate 101 is carried out from the growth apparatus and carried into another heat treatment layer as described above.
  • High temperature heat treatment can also be carried out. By doing so, it is possible to reduce the deterioration of the surface state of the p-type base layer 108 due to atmospheric exposure.
  • the acceptor is returned to the growth apparatus to grow the collector layer 109 and the sub-collector layer 110.
  • the acceptor of the p-type base layer 108 may be inactivated again.
  • a growth device by a molecular beam epitaxy method capable of growing the collector layer 109 and the sub-collector layer 110 under an ultra-high vacuum is used.
  • a first metal layer 111 to be a collector electrode is formed on the sub-collector layer 110 (7th step).
  • the first metal layer 111 can be formed by depositing a predetermined metal by a deposition technique such as an electron beam deposition method, a resistance heating vapor deposition method, a sputtering method, or a plating method.
  • the first metal layer 111 also functions as an adhesive layer in the bonding described later, and also functions as a sub-collector layer.
  • the first metal layer 111 is made of, for example, Ti / Al / Ni / Au in order to form an ohmic connection with the sub-collector layer 110. Further, after each metal constituting the first metal layer 111 is deposited, heat treatment may be performed in order to form an ohmic connection with the sub-collector layer 110. The surface of the first metal layer 111 may be greatly roughened by this heat treatment, and the flatness may be impaired. In such a case, after the heat treatment, the surface of the first metal layer 111 is flattened by a technique such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the first metal layer 111 can also be composed of a metal having a Schottky contact relationship with GaN constituting the collector. Considering the operation of the heterojunction bipolar transistor, it is assumed that the emitter is grounded, and in this case, a reverse bias is applied between the base and the collector. Therefore, even in the case of Schottky contact as described above, the current is not limited. In this case, since the annealing treatment for forming the ohmic is not necessary in some cases, it becomes easy to secure the flatness of the first metal layer 111, which is advantageous in manufacturing the device by joining described later.
  • the second substrate 121 is prepared, and the second metal layer 122 is formed on the prepared second substrate 121 (8th step).
  • the second metal layer 122 can be formed by depositing a predetermined metal by a deposition technique such as an electron beam deposition method, a resistance heating vapor deposition method, a sputtering method, or a plating method.
  • the first substrate 101 and the second substrate 121 are bonded together (second step).
  • the first substrate 101 and the second substrate 121 are bonded together with the sub-collector layer 110 facing the side of the second substrate 121.
  • the first metal layer 111 and the second metal layer 122 are used as the adhesive layer, and the first substrate 101 and the second substrate are in a state of facing the first metal layer 111 and the second metal layer 122. Bond with 121.
  • the bonding surface of the first metal layer 111 and the bonding surface of the second metal layer 122 are bonded by a predetermined wafer bonding technique.
  • the above-mentioned bonding can be performed by a technique such as an atomic diffusion bonding method or a surface activation bonding method.
  • a technique such as an atomic diffusion bonding method or a surface activation bonding method.
  • the first substrate 101 is removed, and as shown in FIG. 1F, the sub-collector layer 110, the collector layer 109, the p-type base layer 108, the base layer 107, the emitter layer 106, the emitter contact layer 105, and the etch stop layer 104 are removed.
  • the sacrificial layer 103 and the nucleation layer 102 are formed on the second substrate 121 in this order with the main surface as the group V polar surface.
  • the above-mentioned layers are formed on the second substrate 121 via the second metal layer 122 and the first metal layer 111.
  • the first substrate 101 when the first substrate 101 is composed of Si, the first substrate 101 can be removed by a dry etching technique using a well-known fluorine-based gas such as SF 6 .
  • a well-known fluorine-based gas such as SF 6 .
  • the nucleation layer 102 and the sacrificial layer 103 are removed.
  • a general dry etching technique may be used to remove the nucleation layer 102 and the sacrificial layer 103.
  • the etch stop layer 104 is made of AlGaN, it is necessary to stop the etching at the etch stop layer 104 by selective etching with the sacrificial layer 103 made of GaN.
  • the sacrificial layer 103 made of GaN.
  • a high etching selectivity can be obtained with respect to AlGaN, which is suitable for the above-mentioned processing.
  • the sub-collector layer 110 and the collector layer 109 constituting the heterojunction bipolar transistor,
  • the p-type base layer 108, the base layer 107, the emitter layer 106, and the emitter contact layer 105 are formed on the second substrate 121 in this order with the main surface as the group V polar surface (third). Process).
  • the first metal layer 111 is formed, and the first metal layer 111 and the second metal layer 122 are joined to each other.
  • the second substrate 121 may be directly bonded to the sub-collector layer 110 by a direct bonding method.
  • a step of separately exposing a part of the sub-collector layer 110 by dry etching or the like and depositing the collector electrode is added here.
  • an annealing treatment for forming ohmic is further performed. Further, in this case, if a technique such as laser lift-off is used, even if the first substrate 101 is composed of sapphire, it can be removed.
  • a resist pattern 112 is formed on the emitter contact layer 105.
  • a resist pattern 112 can be formed by forming a known resist film on the emitter contact layer 105 by a technique such as coating and then exposing and developing it by a well-known lithography technique.
  • the resist pattern 112 is used as a mask, the emitter contact layer 105 exposed to the side thereof is etched and patterned to form a mesa-shaped emitter contact layer 105a as shown in FIG. 1J. (4th step).
  • the etching described above stops etching at the emitter layer 106.
  • the above-mentioned etching can be stopped by using the selective etching technique of the emitter contact layer 105 made of AlGaN and the emitter layer 106 made of GaN by dry etching. In this way, after patterning by etching, the resist pattern 112 is removed (see FIG. 1K).
  • the laminated structure of the sub-collector layer 110, the collector layer 109, the p-type base layer 108, the base layer 107, and the emitter layer 106 is patterned into a mesa shape by the same lithography technology and etching technology as described above.
  • a sub-collector layer 110a, a collector layer 109a, a p-type base layer 108a, a base layer 107a, and an emitter layer 106a having a mesa structure are formed.
  • This mesa structure is formed larger than the emitter contact layer 105a in a plan view.
  • the emitter contact layer 105a is arranged at the center of the mesa structure formed by the sub-collector layer 110a, the collector layer 109a, the p-type base layer 108a, the base layer 107a, and the emitter layer 106a. Therefore, in a plan view, a part of the emitter layer 106a is exposed around the emitter contact layer 105a.
  • a protective film 113 is formed to cover the sub-collector layer 110a, the collector layer 109a, the p-type base layer 108a, the base layer 107a, the emitter layer 106a, and the emitter contact layer 105a. Further, the protective film 113 is formed with an opening 113a penetrating the protective film 113 around the emitter contact layer 105a.
  • the opening 113a can be formed by a known lithography technique and etching technique. The upper surface of the emitter layer 106a is exposed at the bottom of the opening 113a.
  • the protective film 113 is made of a material having high thermal resistance such as SiN because the high temperature treatment is performed in the subsequent step.
  • the opening 113a is formed at a position where the base electrode is formed.
  • the emitter layer 106a exposed at the bottom of the opening 113a is thinned.
  • the base electrode 114 that is ohmic-connected to the p-type base layer 108a.
  • the base electrode 114 is made of an electrode material capable of forming ohmic contacts on the p-type base layer 108a.
  • the base resistance is reduced by forming a high-concentration two-dimensional hole gas at the interface between the emitter layer 106a and the base layer 107a by utilizing the effect of polarization.
  • the emitter layer 106a made of AlGaAs since the emitter layer 106a made of AlGaAs has a high resistance, it may be difficult to reduce the contact resistance between the base electrode 114 and the p-type base layer 108a. Therefore, the emitter layer 106a at the portion where the base electrode 114 is formed is thinned.
  • the concentration of the two-dimensional hole gas depends on the thickness of the emitter layer 106a. Therefore, if the emitter layer 106a is completely removed until it penetrates the base layer 107a, the two-dimensional hole gas Disappears and the contact resistance increases. Therefore, from the viewpoint of contact resistance and two-dimensional hole gas concentration, it is necessary to find an optimum value for the thickness of the emitter layer 106a at the portion where the base electrode 114 is formed. For example, if the contact resistance between the base electrode and the base can be sufficiently reduced without thinning the emitter layer 106a, the above-mentioned process of thinning the emitter layer 106a can be omitted.
  • the emitter electrode 115 is formed on the emitter contact layer 105a (sixth step). An opening is formed in a part of the first metal layer 111 on the upper surface of the emitter contact layer 105a, and the emitter electrode 115 is formed in this portion. It is made of a material capable of forming ohmic contact with respect to the emitter contact layer 105a, which forms the emitter electrode 115.
  • the heat treatment is performed with the base electrode 114 and the emitter electrode 115 formed as described above. By this heat treatment, each electrode becomes ohmic contact and the resistance is lowered. Further, the first metal layer 111 and the second metal layer 122 used for bonding form ohmic contact with the sub-collector layer 110a and serve as collector electrodes.
  • a heterojunction bipolar transistor including 114, an emitter electrode 115, and a collector electrode connected to the sub-collector layer 110a can be obtained.
  • the sub-collector layer 110a, the collector layer 109a, the p-type base layer 108a, the base layer 107a, the emitter layer 106a, and the emitter contact layer 105a have a second substrate with the main surface as a group V polar surface. It will be formed on 121.
  • the formation of the emitter electrode is not limited to the formation of the emitter contact layer 105a and then the emitter electrode 115 having a width smaller than the mesa width of the emitter contact layer 105a in a plan view.
  • the emitter electrode can be used as a mask to process the emitter layer into a mesa shape.
  • the emitter electrode is made of a material in which the shape of the emitter electrode does not significantly deteriorate (change) due to heat treatment, and heating conditions in which the emitter electrode does not change significantly are appropriately set. Further, it is also possible to form an emitter electrode over the entire area above the emitter contact layer before forming the mesa shape, perform heat treatment, and then form the emitter layer into the mesa shape. In this case, since the metal surface constituting the emitter electrode may be greatly roughened after the heat treatment, it may be necessary to flatten the surface of the emitter electrode formed in the entire area by a technique such as chemical mechanical polishing. ..
  • the order of electrode formation and processing into a mesa shape is not limited to the above-mentioned process order.
  • the formation of the emitter electrode and the processing into the mesa shape of the emitter layer are performed first by the self-alignment step to form the emitter electrode, and then the base electrode is formed and the processing into the mesa shape of the base layer or the like is performed. It may be in the order of implementation.
  • the heat treatment after the electrodes are formed is collectively performed after the emitter electrode and the base electrode are formed, but the present invention is not limited to this, and the emitter electrode, the base electrode, and the collector electrode are each subjected to the heat treatment. On the other hand, heat treatment for optimum ohmic connection can be performed.
  • the sub-collector layer 110 is directly bonded to the second substrate 121 without using the first metal layer 111 and the second metal layer 122 to expose a part of the sub-collector layer 110 and a collector electrode is formed therein. , Perform heat treatment for ohmic connection of collector electrodes.
  • This heterojunction bipolar transistor is characterized by a band lineup of an emitter contact layer 105a, an emitter layer 106a, a base layer 107a, and a p-type base layer 108a.
  • the nitride semiconductor has built-in spontaneous polarization and piezoelectric polarization in the c-axis direction.
  • a GaN-based HEMT formed on a general group III polar plane
  • a heterostructure of an undoped AlGaN layer / undoped GaN layer is formed so that the AlGaN layer is arranged on the surface side when viewed from the substrate side.
  • the band of the AlGaN layer bends upward (high energy side) toward the surface side due to the difference in the magnitude of polarization between the AlGaN layer and the GaN layer, and the band of the GaN layer is reversed. It bends downward toward the surface side (AlGaN side). In this way, a two-dimensional electron gas is formed.
  • the heterojunction bipolar transistor in the embodiment has an N-polar surface on the surface side when viewed from the substrate (sub-collector layer 110a), and has an emitter contact layer 105a made of n + GaN on the surface side under the emitter layer 106a made of undoped AlGaN. It has a heterostructure.
  • the surface side is an N-polar surface, the direction of the polarization electric field is reversed as shown in FIG. 2, and the band of the emitter layer 106a is banded toward the surface side (the side of the emitter contact layer 105a). Will be able to bend down.
  • the emitter contact layer 105a is strongly doped in the n-type, the depletion layer hardly spreads, the bending of the band is almost limited to the AlGaN side, and the influence of the two-dimensional electron gas is small.
  • the band of the emitter layer 106a is strongly bent downward toward the surface (emitter contact layer 105a), and as a result, this polarization electric field is canceled. In the direction, the band of the base layer 107a is bent upward toward the surface. Further, the p-type base layer 108a made of GaN similarly doped in p-type is depleted only in the region of the base layer 107a / emitter layer 106a because the depletion layer hardly spreads. As a result of the bands being bent upward toward the interface between the base layer 107a and the emitter layer 106a, the conduction band is lifted to the higher energy side than the Fermi level, and a two-dimensional hole gas is formed.
  • the sub-collector layer, the collector layer, the p-type base layer, the base layer, the emitter layer, and the emitter contact layer are placed on the substrate with the main surface as a group V polar surface. Therefore, the high frequency characteristics of the heterojunction bipolar transistor using the nitride semiconductor can be made higher without forming a collector top structure.

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