WO2020228334A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2020228334A1
WO2020228334A1 PCT/CN2019/127854 CN2019127854W WO2020228334A1 WO 2020228334 A1 WO2020228334 A1 WO 2020228334A1 CN 2019127854 W CN2019127854 W CN 2019127854W WO 2020228334 A1 WO2020228334 A1 WO 2020228334A1
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layer
groove
semiconductor substrate
metal silicide
semiconductor structure
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PCT/CN2019/127854
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP19928607.1A priority Critical patent/EP3971992A4/en
Priority to US17/087,431 priority patent/US11302789B2/en
Publication of WO2020228334A1 publication Critical patent/WO2020228334A1/zh
Priority to US17/717,115 priority patent/US20220238665A1/en

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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to the field of semiconductors, in particular to a semiconductor structure and a method of forming the same.
  • a contact structure in the dielectric layer for electrical connection between semiconductor devices is a widely used process.
  • the contact structure can be directly electrically connected to the gate, source/drain of the transistor, or Used for electrical connection between layers.
  • a metal silicide is usually formed on the surface of the gate and source/drain of the contact structure to be formed by metal deposition and rapid annealing processes. (silicide).
  • the existing process of forming a contact structure includes: providing a semiconductor substrate in which a gate structure is formed, and forming active/drain regions in the semiconductor substrate on both sides of the gate structure; Cobalt metal layer is deposited on the surface of the drain region and the semiconductor substrate; rapid thermal annealing is performed to make the cobalt metal layer react with the silicon in the gate structure and the source/drain region to form metal silicide; remove unreacted metal; in the metal silicide And forming an interlayer dielectric layer on the surface of the gate structure; etching the interlayer dielectric layer to form a contact hole exposing the surface of the metal silicide in the dielectric layer; filling the contact hole with metal to form a metal plug.
  • the technical problem to be solved by the present invention is how to reduce the leakage current between the connection structure such as the metal plug and the metal silicide layer and the semiconductor substrate.
  • the present invention provides a semiconductor structure, including:
  • a semiconductor substrate having a source region and a drain region in the semiconductor substrate, and a groove in the source region and the drain region;
  • the metal silicide layer is located on the surface of the peripheral sidewall of the groove;
  • An insulating layer located on the bottom surface of the groove, and the edge of the insulating layer is in contact with the bottom surface of the metal silicide layer on the sidewalls around the groove;
  • a conductive layer is filled in the groove and located on the metal silicide layer and the insulating layer.
  • the contact structure further includes a buffer layer covering the insulating layer and correspondingly covering the metal silicide layer on the sidewall of the groove.
  • the buffer layer includes a titanium nitride layer and a titanium layer located on the titanium nitride layer, or includes a tantalum nitride layer and a tantalum layer located on the tantalum nitride layer, or includes a gallium layer and The gallium nitride layer on the gallium layer.
  • the material of the metal silicide layer includes one or more of cobalt silicide, nickel silicide, platinum silicide, tantalum silicide, molybdenum silicide, and titanium silicide.
  • the material of the insulating layer includes one or more of cobalt oxide, nickel oxide, platinum oxide, tantalum oxide, molybdenum oxide, and titanium oxide.
  • the thickness of the metal silicide layer is 10-50 nm, and the thickness of the insulating layer is 1-2 nm.
  • a gate structure is formed on the semiconductor substrate, and the source region and the drain region are respectively located in the semiconductor substrate on both sides of the gate structure.
  • the semiconductor substrate further has a dielectric layer, and the dielectric layer has a metal plug therein, and the metal plug is connected to the contact structure.
  • the present invention also provides a method for forming a semiconductor structure, including:
  • a conductive layer is formed on the insulating layer, and the conductive layer fills the groove.
  • a buffer layer is formed on the insulating layer.
  • a dielectric layer is formed on the semiconductor substrate, and the dielectric layer has through holes exposing the surface of the source region and the drain region; A groove is formed in the source region and the drain region at the bottom of the through hole; a metal silicide layer is formed on the sidewall of the groove.
  • a dielectric layer covering the metal silicide layer, the conductive layer and the semiconductor substrate is formed; a metal plug is formed in the dielectric layer, and the metal plug is connected to the conductive layer.
  • the material of the insulating layer includes one or more of cobalt oxide, nickel oxide, platinum oxide, tantalum oxide, molybdenum oxide, and titanium oxide.
  • the thickness of the metal silicide layer is 10-50 nm, and the thickness of the insulating layer is 1-2 nm.
  • a gate structure is formed on the semiconductor substrate, and the source region and the drain region are respectively formed in the semiconductor substrate on both sides of the gate structure.
  • a metal silicide layer is formed on the sidewall of the groove to reduce the contact resistance
  • an insulating layer is formed on the bottom of the groove, so that when the current is passed down from the conductive layer, the The insulating layer forms a barrier, so the current will be blocked by the insulating layer in the vertical direction, and can only flow to the sidewall of the groove, and will not leak vertically into the semiconductor substrate at the bottom of the insulating layer, thereby reducing This reduces the current impact on the source and drain regions, and reduces the probability of device defects.
  • the source and drain regions are arranged laterally. Therefore, when the current flows laterally from the conductive layer to the source and drain regions, it is easier to realize the gap between the source and drain regions. The current is conducted, and the leakage current from the source region to the semiconductor substrate or the drain region to the semiconductor substrate can be reduced, thereby effectively improving the conduction performance of the field effect transistor.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • 2-8 are structural schematic diagrams of the formation process of a semiconductor structure according to an embodiment of the present invention.
  • the present invention provides a semiconductor structure and a method of forming the same.
  • a metal silicide layer is formed on the sidewall of a groove to reduce contact resistance
  • an insulating layer is formed on the bottom of the groove. Therefore, when the current is transmitted downward from the conductive layer, the insulating layer can be used to form a barrier. Therefore, the current will be blocked by the insulating layer in the vertical direction, and can only flow to the sidewall of the groove. Vertical leakage into the semiconductor substrate at the bottom of the insulating layer, thereby reducing the current impact on the source and drain regions, and reducing the probability of device defects.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • the semiconductor structure of this embodiment includes:
  • a semiconductor substrate 200 having a source region and a drain region 201 therein, and a groove 209 is provided in the source region and the drain region 201;
  • the metal silicide layer 203 is located on the surface of the peripheral sidewall of the groove 209;
  • the insulating layer 204 is located on the bottom surface of the groove 209, and the edge of the insulating layer 204 is in contact with the bottom surface of the metal silicide layer 203 on the sidewalls around the groove 209;
  • the conductive layer 208 is filled in the groove 209 and is located on the metal silicide layer 203 and the insulating layer 204.
  • the material of the semiconductor substrate 200 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator ( GOI); or other materials, such as Group III-V compounds such as gallium arsenide.
  • the semiconductor substrate 200 in this embodiment is a silicon semiconductor substrate.
  • the semiconductor substrate 200 has active regions (not shown in the figure), and trench isolation structures (not shown in the figure) for isolating the active regions.
  • a semiconductor device (not shown in the figure) may be formed on the active region of the semiconductor substrate 200, and the semiconductor device includes a transistor.
  • the transistor includes a gate structure located on the surface of the semiconductor substrate 200 and a source region or a drain region 201 in the semiconductor substrate located on both sides of the gate structure.
  • the gate structure may include a gate dielectric layer on the surface of the semiconductor substrate 200, a gate electrode on the gate dielectric layer, and sidewall spacers on the sidewall surfaces of the gate electrode and the gate dielectric layer.
  • the source and drain regions 201 are doped with impurity ions.
  • the metal silicide layer 203 is located on the sidewall of the groove 209, and the metal silicide layer 203 has a hollow ring shape.
  • the metal silicide 203 can reduce the conductive layer or the conductive plug and the source and drain regions 201 However, the metal silicide 203 has a certain junction leakage current.
  • the material of the metal silicide layer 203 includes one or more of cobalt silicide, nickel silicide, platinum silicide, tantalum silicide, molybdenum silicide, and titanium silicide. In one embodiment, the thickness of the metal silicide layer 203 is 10-50 nm.
  • a metal silicide layer 203 is formed on the sidewall of the groove 209 to reduce the contact resistance
  • an insulating layer 204 is formed on the bottom of the groove 209, so that when the current passes downward from the conductive layer 208 ,
  • the insulating layer 204 can be used to form a barrier, so the current will be blocked by the insulating layer 204 in the vertical direction and can only flow to the sidewall of the groove 209 (in the direction of the arrow as shown in FIG. 1), It will not leak vertically into the semiconductor substrate 200 at the bottom of the insulating layer 204, thereby reducing the current impact on the source and drain regions 201, and reducing the probability of device defects.
  • the source and drain regions 201 are arranged laterally. Therefore, when current flows laterally from the conductive layer 208 to the source and drain regions, it is easier to realize the source and drain regions. The current is conducted therebetween, and the leakage current from the source region to the semiconductor substrate 200 or the drain region to the semiconductor substrate 200 can be reduced, so that the conduction performance of the field effect transistor can be effectively improved.
  • the material of the insulating layer 204 is a non-conductive insulating material.
  • the material of the insulating layer 204 is one of cobalt oxide, nickel oxide, platinum oxide, tantalum oxide, molybdenum oxide, and titanium oxide. There are many types.
  • the thickness of the insulating layer 204 is 1-2 nm. When the current is transmitted downward from the conductive layer 208, the insulating layer can better block the current.
  • the insulating layer 204 has the same metal elements as the metal silicide layer 203 to simplify the manufacturing process. For example, when the material of the metal silicide layer 203 is cobalt silicide, the material of the insulating layer 204 is Cobalt oxide.
  • the contact structure further includes a buffer layer 207 covering the insulating layer 204 and correspondingly covering the metal silicide layer 203 on the sidewall of the groove 209.
  • the buffer layer 207 plays a role of blocking metal diffusion of the conductive layer 208, buffering stress, and matching the adhesion between the film layers.
  • the buffer layer 207 may include a titanium nitride layer and a layer located on the titanium nitride layer.
  • the titanium layer includes either a tantalum nitride layer and a tantalum layer on the tantalum nitride layer, or a gallium layer and a gallium nitride layer on the gallium layer.
  • the buffer layer 207 includes a titanium nitride layer 205 and a titanium layer 206 located on the titanium nitride layer 205.
  • the thickness of the titanium nitride layer 205 is 2-4 nanometers, and the titanium layer The thickness of 206 is 2-4 nanometers.
  • the conductive layer 208 fills the groove, and the material of the conductive layer 45 may be a conductive material such as copper and tungsten.
  • the semiconductor substrate 200 further has a dielectric layer 202, the dielectric layer 202 has a through hole exposing a part of the surface of the source region and the drain region 201, and the position of the through hole and the groove 209 Corresponding to the position of, the conductive layer 208 extends upward to fill the through hole.
  • the buffer layer 207 may also cover the sidewall of the through hole.
  • the semiconductor substrate 200 further has a dielectric layer 202 on the dielectric layer 202, and the dielectric layer 202 has a through hole exposing part of the surface of the source region and the drain region 201, and a conductive insert is formed in the through hole.
  • the conductive plug is located above the conductive layer 208, and the conductive plug is electrically connected to the conductive layer.
  • the dielectric layer 202 can be a single-layer or multi-layer stack structure, silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) Silicon dioxide) or BPSG (Boron-phosphorus-doped silicon dioxide), low dielectric constant materials, other suitable materials and/or combinations of the above.
  • 2-8 are structural schematic diagrams of the formation process of a semiconductor structure according to an embodiment of the present invention.
  • a semiconductor substrate 200 is provided, and the semiconductor substrate 200 has a source region and a drain region 201 therein.
  • the semiconductor substrate 200 has active regions (not shown in the figure), and trench isolation structures (not shown in the figure) for isolating the active regions.
  • a semiconductor device (not shown in the figure) may be formed on the active region of the semiconductor substrate 200, and the semiconductor device includes a transistor.
  • the source and drain regions 201 are the source/drain regions of a transistor, a gate structure (not shown in the figure) is also formed on the semiconductor substrate 200, and the source and drain regions 201 are respectively Located in the semiconductor substrate 200 on both sides of the gate structure.
  • the gate structure may include a gate dielectric layer on the surface of the semiconductor substrate 200, a gate electrode on the gate dielectric layer, and sidewall spacers on the sidewall surfaces of the gate electrode and the gate dielectric layer.
  • the material of the gate dielectric layer may be silicon oxide or a high-K dielectric material, and the material of the gate electrode may be polysilicon or metal.
  • a dielectric layer 202 may be formed on the semiconductor substrate 200, and the dielectric layer 202 has through holes 209 exposing part of the surface of the source region and the drain region 201.
  • through holes 209 are formed in the dielectric layer by an etching process.
  • the dielectric layer 202 may not be formed on the semiconductor substrate 200, and the source and drain regions 201 are directly etched subsequently to form grooves in the source and drain regions 201.
  • grooves 210 are in the source and drain regions 201.
  • the purpose of forming the groove 210 in this application is to facilitate the subsequent formation of metal silicide on the sidewall of the groove 210 and the formation of an insulating layer at the bottom of the groove, so that the formed metal silicide has a certain height, and is subsequently formed at the bottom of the groove. After the insulating layer and the conductive layer are formed on the insulating layer, it is ensured that the current of the conductive layer can flow to the opposite source region or the drain region through the metal silicide without affecting the conduction between the source region and the drain region.
  • the source and drain regions 201 at the bottom of the through hole 209 are etched along the through hole 209 in the dielectric layer 202, and grooves 210 are formed in the source and drain regions 201, and the source and drain regions are etched 201 can use wet and dry etching processes.
  • the width of the groove 210 is smaller than the width of the source region (or drain region) 201, and the depth of the groove 210 is smaller than the depth of the source region (or drain region) 201.
  • a patterned mask layer may be formed on the semiconductor substrate, and the patterned mask layer has exposed source and drain regions 201 Part of the surface opening; the source and drain regions 201 are etched using the patterned mask layer as a mask, and grooves are formed in the source and drain regions 201.
  • the number of the grooves 210 in the source region or the drain region 201 may be one or more (two or more).
  • a metal silicide layer 203 is formed on the surface of the peripheral sidewall of the groove 210.
  • the material of the insulating layer 204 is a non-conductive insulating material.
  • the material of the insulating layer 204 is one of cobalt oxide, nickel oxide, platinum oxide, tantalum oxide, molybdenum oxide, and titanium oxide. There are many types.
  • the thickness of the insulating layer 204 is 1-2 nm. When the current is transmitted downward from the conductive layer 208, the insulating layer can better block the current.
  • the insulating layer 204 has the same metal elements as the metal silicide layer 203 to simplify the manufacturing process. For example, when the material of the metal silicide layer 203 is cobalt silicide, the material of the insulating layer 204 is Cobalt oxide.
  • the formation process of the metal silicide layer 201 is: forming a metal layer on the sidewall and bottom surface of the groove 210, the sidewall and bottom surface of the through hole 209, and the surface of the dielectric layer 202 ( Figure Not shown in), the material of the metal layer is one or more of cobalt, nickel, platinum, tantalum, molybdenum and titanium; the rapid thermal annealing process is performed, and the metal in the metal layer is related to the source and drain regions 201
  • the silicon in the metal reacts to form a metal silicide layer; the unreacted metal layer on the sidewalls of the through hole 209 and the surface of the dielectric layer 202 is removed, and the unreacted metal layer can be removed by wet etching; the groove is removed by etching
  • the metal silicide layer at the bottom of the groove 210 forms a metal silicide layer 203 on the peripheral sidewall surface of the groove 210, and an anisotropic dry etching process can be used to remove the metal silicide
  • an insulating layer 204 is formed on the bottom surface of the groove 209.
  • the insulating layer 204 is formed by forming an insulating material layer on the sidewall and bottom surface of the groove 210, the sidewall surface of the through hole 209, and the surface of the dielectric layer 202, and The insulating material layer is formed by a deposition process; the sidewall surface of the groove 210, the sidewall surface of the through hole 209, and the insulating material layer on the surface of the dielectric layer 202 are etched away, forming an insulating layer on the bottom surface of the groove 210 In the layer 204, the edge of the insulating layer 204 is in contact with the bottom surface of the metal silicide layer 201 on the sidewalls around the groove 210.
  • the material of the insulating layer 204 is a non-conductive insulating material.
  • the material of the insulating layer 204 is one of cobalt oxide, nickel oxide, platinum oxide, tantalum oxide, molybdenum oxide, and titanium oxide. Many kinds.
  • the thickness of the insulating layer 204 is 1-2 nm. When the current is transmitted downward from the conductive layer 208, the insulating layer can better block the current.
  • the insulating layer 204 has the same metal elements as the metal silicide layer 203 to simplify the manufacturing process. For example, when the material of the metal silicide layer 203 is cobalt silicide, the material of the insulating layer 204 is Cobalt oxide.
  • a conductive layer 208 is formed on the insulating layer 204, and the conductive layer 208 fills the grooves.
  • the conductive layer 208 not only fills the groove 210 (refer to FIG. 5), but also fills the through hole 209 (refer to FIG. 5).
  • the conductive layer 208 may only fill the groove 210 (refer to FIG. 5).
  • the material of the conductive layer 208 may be Cu, Al, W or other conductive materials.
  • a buffer layer 207 is formed on the insulating layer 204.
  • the buffer layer 207 may include a titanium nitride layer and a titanium layer on the titanium nitride layer, or a tantalum nitride layer and a tantalum layer on the tantalum nitride layer, or a gallium layer and a titanium layer on the tantalum nitride layer.
  • the buffer layer 207 includes a titanium nitride layer 205 and a titanium layer 206 located on the titanium nitride layer 205.
  • the thickness of the titanium nitride layer 205 is 2-4 nanometers, and the titanium layer The thickness of 206 is 2-4 nanometers.
  • the buffer layer 207 may also cover the sidewall surface of the through hole.
  • FIG. 7 is a schematic top view of the semiconductor structure shown in FIG. 6 after the conductive layer 208 is formed in an embodiment, and the dielectric layer 202 and the buffer layer 207 are not shown in FIG. 7.
  • the source region and the drain region 201 are respectively located in the semiconductor substrate on both sides of the gate structure 300.
  • the source region and the drain region 201 each have a groove, and the sidewalls of the groove have metal silicide.
  • the object layer 203 has an insulating layer 204 at the bottom of the groove (refer to FIG. 6 ).
  • the conductive layer 208 is located on the insulating layer 204, and the conductive layer 208 fills the groove.
  • FIG. 7 is a schematic top view of the semiconductor structure shown in FIG. 6 after the conductive layer 208 is formed.
  • the dielectric layer 202 and the buffer layer 207 are not shown in FIG.
  • the source region and the drain region 201 are respectively located in the semiconductor substrate on both sides of the gate structure 300.
  • the source region and the drain region 201 each have a groove, and the sidewalls of the groove have metal silicide.
  • the object layer 203, the bottom of the groove has an insulating layer 204 (refer to FIG. 6), the conductive layer 208 is located on the insulating layer 204, and the conductive layer 208 fills the groove, and then a conductive layer can be formed on the conductive layer 208 208 is electrically connected to the metal layer 301.
  • FIG. 8 is a schematic top view of the semiconductor structure shown in FIG. 6 after the conductive layer 208 is formed.
  • the dielectric layer 202 and the buffer layer 207 are not shown in FIG. 8.
  • the source region and the drain region 201 are respectively located in the semiconductor substrate on both sides of the gate structure 300.
  • the source region and the drain region 201 respectively have several grooves, and the source region and the drain region 201 respectively have two grooves.
  • the grooves are described as an example.
  • Each groove has a metal silicide layer 203 on its peripheral sidewalls, and an insulating layer 204 is provided on the bottom of each groove (refer to FIG. 6).
  • the conductive layer 208 is located on the insulating layer 204.
  • the conductive layer 208 fills the groove, and then a metal layer 302 that electrically connects the corresponding conductive layers 208 on the source region and the drain region 201 can be formed on the conductive layer 208.

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Abstract

一种半导体结构及其形成方法，其中所述半导体结构，包括：半导体衬底（200），所述半导体衬底（200）中具有源区和漏区（201），所述源区和漏区（201）中具有凹槽（209）；金属硅化物层（203），位于所述凹槽（209）的四周侧壁表面；绝缘层（204），位于凹槽（209）的底部表面，且所述绝缘层（204）的边缘与凹槽（209）四周侧壁上的所述金属硅化物层（203）底部表面接触；导电层（208），填充在所述凹槽（209）中并位于所述金属硅化物层（203）及所述绝缘层（204）上。上述半导体结构能够防止电流泄露到源区和漏区（201）底部的半导体衬底（200）中。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体领域，尤其涉及一种半导体结构及其形成方法。
背景技术
目前，在半导体制造过程中，在介质层形成接触结构用于半导体器件之间的电连接是一种广泛使用的工艺，接触结构可直接与晶体管的栅极、源/漏极电连接，还可以用于层与层之间的电连接。为了降低接触结构与晶体管的栅极、源/漏极电连接的接触电阻，通常会通过金属沉积及快速退火工艺在待形成接触结构的栅极、源/漏极表面上形成一层金属硅化物(silicide)。
现有形成接触结构的过程包括：提供半导体衬底，所述半导体衬底中形成有栅极结构，栅极结构两侧的半导体衬底中形成有源/漏区；在栅极结构、源/漏区和半导体衬底表面沉积钴金属层；进行快速热退火，以使钴金属层与栅极结构、源/漏区中的硅反应生成金属硅化物；去除未反应的金属；在金属硅化物以及栅极结构表面形成层间介质层；刻蚀所述层间介质层，在介质层中形成暴露出金属硅化物表面的接触孔；在接触孔中填充金属形成金属插塞。
但是现有的金属插塞与金属硅化物层这样的连接结构与半导体衬底之间还是存在漏电流。
发明内容
本发明所要解决的技术问题是怎样减小金属插塞与金属硅化物层这样的连接结构与半导体衬底之间漏电流。
本发明提供了一种半导体结构，包括：
半导体衬底，所述半导体衬底中具有源区和漏区，所述源区和漏区中具有凹槽；
金属硅化物层，位于所述凹槽的四周侧壁表面；
绝缘层，位于所述凹槽的底部表面，且所述绝缘层的边缘与所述凹槽四周侧壁上的所述金属硅化物层底部表面接触；
导电层，填充在所述凹槽中并位于所述金属硅化物层及所述绝缘层上。
可选的，所述接触结构还包括缓冲层，所述缓冲层覆盖所述绝缘层以及对应覆盖所述凹槽侧壁上的所述金属硅化物层。
可选的，所述缓冲层包括氮化钛层和位于所述氮化钛层上的钛层，或者包括氮化钽层和位于所述氮化钽层上钽层，或者包括镓层与位于所述镓层上氮化镓层。
可选的，所述金属硅化物层的材料包括硅化钴、硅化镍、硅化铂、硅化钽、硅化钼及硅化钛中的一种或多种。
可选的，所述绝缘层的材料包括氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种。
可选的，所述金属硅化物层的厚度为10-50nm，绝缘层的厚度为1-2nm。
可选的，所述半导体衬底上形成有栅极结构，所述源区和漏区分别位于栅极结构两侧的半导体衬底中。
可选的，所述半导体衬底上还具有介质层，所述介质层中具有金属插塞，所述金属插塞与所述接触结构连接。
本发明还提供了一种半导体结构的形成方法，包括：
提供半导体衬底，所述半导体衬底中具有源区和漏区；
在所述源区和漏区中形成凹槽；
在所述凹槽的四周侧壁表面上形成金属硅化物层；
和在所述凹槽的底部表面形成绝缘层；
在所述绝缘层上形成导电层，所述导电层填充满所述凹槽。
可选的，在形成所述导电层之前，在所述绝缘层上形成缓冲层。
可选的，在所述源区和漏区中形成金属硅化物层之前，在所述半导体衬底上形成介质层，所述介质层中具有暴露出源区和漏区表面的通孔；在通孔底部的源区和漏区中形成凹槽；在凹槽的侧壁形成金属硅化物层。
可选的，在形成导电层后，形成覆盖所述金属硅化物层、导电层和半导体衬底的介质层；在所述介质层中形成金属插塞，所述金属插塞与导电层连接。
可选的，所述绝缘层的材料包括氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种。
可选的，所述金属硅化物层的厚度为10-50nm，绝缘层的厚度为1-2nm。
可选的，所述半导体衬底上形成有栅极结构，所述源区和漏区分别形成在栅极结构两侧的半导体衬底中。
与现有技术相比，本发明技术方案具有以下优点：
本发明的半导体结构，通过在凹槽的侧壁形成金属硅化物层以降低接触电阻，并且所述凹槽的底部上形成有绝缘层，从而当电流从导电层向下传递时，可利用所述绝缘层形成一道屏障，因而电流在垂直方向上会被所述绝缘层阻挡，只能流向所述凹槽的侧壁方向，不会垂直的泄露进绝缘层底部的半导体衬底中，从而降低了电流对源区和漏区的冲击力，降低了器件产生缺陷了几率。
尤其是，针对平面型场效应晶体管而言，其源区和漏区横向排布，因此当电流从导电层横向流通至源区和漏区中时，则更易于实现源区和漏区之间的电流导通，并能够减小源区至半导体衬底或漏区至半导体衬底之间的漏电流，从而可有效提高场效应晶体管的导通性能。
附图说明
图1为本发明实施例半导体结构的结构示意图；
图2-8本发明一实施例半导体结构的形成过程的结构示意图。
具体实施方式
如背景技术所言，但是现有的金属插塞(接触结构)与金属硅化物层这样的连接结构与半导体衬底之间还是存在漏电流。
研究发现，现有的晶体管在工作时，绝大部分电流会通过沟道从漏极到源极，但是也有很小的电流从漏极到衬底，带来漏电流。
为此，本发明提供了一种半导体结构及其形成方法，所述半导体结构，通过在凹槽的侧壁形成金属硅化物层以降低接触电阻，并且所述凹槽的底部上形成有绝缘层，从而当电流从导电层向下传递时，可利用所述绝缘层形成一道屏障，因而电流在垂直方向上会被所述绝缘层阻挡，只能流向所述凹槽的侧壁方向，不会垂直的泄露进绝缘层底部的半导体衬底中，从而降低了电流对源区和漏区的冲击力，降低了器件产生缺陷了几率。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1为本发明实施例半导体结构的结构示意图。
参考图1，本实施例的半导体结构，包括：
半导体衬底200，所述半导体衬底200中具有源区和漏区201，所述源区和漏区201中具有凹槽209；
金属硅化物层203，位于所述凹槽209的四周侧壁表面；
绝缘层204，位于凹槽209的底部表面，且所述绝缘层204的边缘与凹槽209四周侧壁上的所述金属硅化物层203底部表面接触；
导电层208，填充在所述凹槽209中并位于所述金属硅化物层203及所述绝缘层204上。
具体的，所述半导体衬底200的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述半导体衬底200为硅半导体衬底。
在所述半导体衬底200中具有有源区(图中未示出)，以及隔离各有源区的沟槽隔离结构(图中未示出)。所述半导体衬底200的有源区上可以形成半导体器件(图中未示出)，所述半导体器件包括晶体管。
在一实施例中，所述晶体管包括位于半导体衬底200表面栅极结构，位于栅极结构两侧的半导体衬底内中源区或漏区201。
所述栅极结构可以包括位于半导体衬底200表面的栅介质层和位于栅介质层上的栅电极，以及位于栅电极和栅介质层两侧侧壁表面的侧墙。源区和漏区201中掺杂有杂质离子。
所述金属硅化物层203位于凹槽209的侧壁，所述金属硅化物层203呈中空的环状，所述金属硅化物203能减小导电层或导电插塞与源区和漏区201的接触电阻，但是金属硅化物203存在一定的结漏电流。所述金属硅化物层203的材料包括硅化钴、硅化镍、硅化铂、硅化钽、硅化钼及硅化钛中的一种或多种。在一实施例中，所述金属硅化物层203的厚度为10-50nm。
本实施例中，通过在凹槽209的侧壁形成金属硅化物层203以降低接触电阻，并且所述凹槽209的底部上形成有绝缘层204，从而当电流从导电层208向下传递时，可利用所述绝缘层204形成一道屏障，因而电流在垂直方向上会 被所述绝缘层204阻挡，只能流向所述凹槽209的侧壁(如图1所示的箭头方向)方向，不会垂直的泄露进绝缘层204底部的半导体衬底200中，从而降低了电流对源区和漏区201的冲击力，降低了器件产生缺陷了几率。
尤其是，针对平面型场效应晶体管而言，其源区和漏区201横向排布，因此当电流从导电层208横向流通至源区和漏区中时，则更易于实现源区和漏区之间的电流导通，并能够减小源区至半导体衬底200或漏区至半导体衬底200之间的漏电流，从而可有效提高场效应晶体管的导通性能。
所述绝缘层204的材料为不导电的绝缘材料，在一实施例中，所述绝缘层204的材料为氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种，所述绝缘层204的厚度为1-2nm，当电流从导电层208向下传递时，所述绝缘层能更好的对电流产生阻挡。在一实施例中，所述绝缘层204具有与金属硅化物层203相同的金属元素，以简化制作的工艺，比如金属硅化物层203的材料为硅化钴时，所述绝缘层204的材料为氧化钴。
所述接触结构还包括缓冲层207，所述缓冲层207覆盖所述绝缘层204以及对应覆盖所述凹槽209侧壁上的所述金属硅化物层203。所述缓冲层207起到阻挡导电层208的金属扩散、缓冲应力、匹配各膜层之间粘附力的作用，所述缓冲层207可以包括氮化钛层和位于所述氮化钛层上的钛层，或者包括氮化钽层和位于所述氮化钽层上钽层，或者包括镓层与位于所述镓层上氮化镓层。本实施例中，所述缓冲层207包括氮化钛层205和位于所述氮化钛层205上的钛层206，所述氮化钛层205的厚度为2-4纳米，所述钛层206的厚度为2-4纳米。
所述导电层208填充满凹槽，所述导电层45的材料可以是铜、钨等导电材料。
在一实施例中，所述半导体衬底200上还具有介质层202，所述介质层202中具有暴露出源区和漏区201部分表面的通孔，所述通孔的位置与凹槽209的位置对应，所述导电层208向上延伸填充满通孔。所述缓冲层207也可以覆盖所述通孔的侧壁。
在另一实施例中，所述半导体衬底200上还具有介质层202，所述介质层202中具有暴露出源区和漏区201部分表面的通孔，所述通孔中形成有导电插 塞，所述导电插塞位于导电层208上方，导电插塞与导电层电连接。
所述介质层202可以为单层或多层堆叠结构，氧化硅、氮化硅、氮氧化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数材料、其它适合的材料及/或上述的组合。
下面结合附图对本发明的半导体结构的形成过程进行详细的描述。图2-8本发明一实施例半导体结构的形成过程的结构示意图。
参考图2，提供半导体衬底200，所述半导体衬底200中具有源区和漏区201。
在所述半导体衬底200中具有有源区(图中未示出)，以及隔离各有源区的沟槽隔离结构(图中未示出)。所述半导体衬底200的有源区上可以形成半导体器件(图中未示出)，所述半导体器件包括晶体管。
在一实施例中，所述源区和漏区201为晶体管的源/漏区，所述半导体衬底200上还形成有栅极结构(图中未示出)，源区和漏区201分别位于栅极结构两侧的半导体衬底200中。所述栅极结构可以包括位于半导体衬底200表面的栅介质层和位于栅介质层上的栅电极，以及位于栅电极和栅介质层两侧侧壁表面的侧墙。所述栅介质层的材料可以为氧化硅或高K介质材料，所述栅电极的材料可以为多晶硅或金属。
本实施例中，所述半导体衬底200上可以形成介质层202，所述介质层202中具有暴露出源区和漏区201部分表面的通孔209。在一实施例中，通过刻蚀工艺在所述介质层中形成通孔209。
在其他实施中，所述半导体衬底200上可以不形成介质层202，后续直接刻蚀源区和漏区201，在源区和漏区201中形成凹槽。
参考图3，在所述源区和漏区201中凹槽210。
本申请中形成凹槽210的目的是方便后续在凹槽210的侧壁形成金属硅化物以及凹槽的底部形成绝缘层，并使形成的金属硅化物具有一定的高度，后续在凹槽底部形成绝缘层和在绝缘层上形成导电层后，保证所述导电层的电流能通过金属硅化物流动到相对的源区或漏区中，不会影响源区和漏区之间的导通。
本实施例中，沿介质层202中的通孔209刻蚀通孔209底部的源区和漏区201，在源区和漏区201中形成凹槽210，刻蚀所述源区和漏区201可以采用湿法和干法刻蚀工艺。所述形成凹槽210的宽度小于源区(或漏区)201的宽度，凹槽210的深度小于源区(或漏区)201的深度。
在其他实施例中，当半导体衬底200上未形成介质层时，可以在半导体衬底上形成图形化的掩膜层，所述图形化的掩膜层中具有暴露出源区和漏区201部分表面的开口；以所述图形化的掩膜层为掩膜刻蚀所述源区和漏区201，在所述源区和漏区201中形成凹槽。
所述源区或漏区201中的凹槽210的数量可以为一个或多个(大于等于两个)。
参考图4，在所述凹槽210的四周侧壁表面上形成金属硅化物层203。
所述绝缘层204的材料为不导电的绝缘材料，在一实施例中，所述绝缘层204的材料为氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种，所述绝缘层204的厚度为1-2nm，当电流从导电层208向下传递时，所述绝缘层能更好的对电流产生阻挡。在一实施例中，所述绝缘层204具有与金属硅化物层203相同的金属元素，以简化制作的工艺，比如金属硅化物层203的材料为硅化钴时，所述绝缘层204的材料为氧化钴。
在一实施例中，所述金属硅化物层201的形成过程为：在所述凹槽210的侧壁和底部表面、通孔209的侧壁和底部表面以及介质层202表面形成金属层(图中未示出)，所述金属层的材料为钴、镍、铂、钽、钼及钛中的一种或几种；进行快速热退火工艺，金属层中的金属与源区和漏区201中的硅反应，形成金属硅化物层；去除所述通孔209侧壁以及介质层202表面未反应的金属层，去除所述未反应的金属层可以采用湿法刻蚀；刻蚀去除凹槽210底部的金属硅化物层，在凹槽210的四周侧壁表面上形成金属硅化物层203，去除所述凹槽210底部的金属硅化物层可以采用各向异性的干法刻蚀工艺。
参考图5，在所述凹槽209的底部表面形成绝缘层204。
在一实施例中，所述绝缘层204的形成过程为：在所述凹槽210的侧壁和底部表面以及通孔209的侧壁表面以及介质层202的表面上形成绝缘材料层，所述绝缘材料层通过沉积工艺形成；刻蚀去除所述凹槽210的侧壁表面以及通 孔209的侧壁表面以及介质层202的表面的绝缘材料层，在所述凹槽210的底部表面形成绝缘层204，所述绝缘层204的边缘与凹槽210四周侧壁上的所述金属硅化物层201底部表面接触。
所述绝缘层204的材料为不导电的绝缘材料，在一实施例中，所述绝缘层204的材料为氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种。所述绝缘层204的厚度为1-2nm，当电流从导电层208向下传递时，所述绝缘层能更好的对电流产生阻挡。在一实施例中，所述绝缘层204具有与金属硅化物层203相同的金属元素，以简化制作的工艺，比如金属硅化物层203的材料为硅化钴时，所述绝缘层204的材料为氧化钴。
参考图6，在所述绝缘层204上形成导电层208，所述导电层208填充满凹槽。
本实施例中，所述导电层208不仅填充满凹槽210(参考图5)，所述导电层208还填充满通孔209(参考图5)。
在其他实施例中，当半导体衬底200上未形成介质层202时，所述导电层208可以仅填充满凹槽210(参考图5)。
所述导电层208的材料可以为Cu、Al、W或其他的导电材料。
在一实施例中，在形成所述导电层208之前，在所述绝缘层204上形成缓冲层207。
所述缓冲层207可以包括氮化钛层和位于所述氮化钛层上的钛层，或者包括氮化钽层和位于所述氮化钽层上钽层，或者包括镓层与位于所述镓层上氮化镓层。本实施例中，所述缓冲层207包括氮化钛层205和位于所述氮化钛层205上的钛层206，所述氮化钛层205的厚度为2-4纳米，所述钛层206的厚度为2-4纳米。
所述缓冲层207除了覆盖凹槽的侧壁表面，所述缓冲层207还可以覆盖所述通孔的侧壁表面。
参考图7，图7为一实施例中在形成导电层208后，图6所示的半导体结构的俯视结构示意图，图7中介质层202和缓冲层207未示出。如图7所示，源区和漏区201分别位于栅极结构300两侧的半导体衬底中，源区和漏区201分别具有一个凹槽，所述凹槽的四周侧壁上具有金属硅化物层203，凹槽底部 具有绝缘层204(参考图6)，导电层208位于所述绝缘层204上，且所述导电层208填充满凹槽。
一实施例，请参考图7，图7为在形成导电层208后，图6所示的半导体结构的俯视结构示意图，图7中介质层202和缓冲层207未示出。如图7所示，源区和漏区201分别位于栅极结构300两侧的半导体衬底中，源区和漏区201分别具有一个凹槽，所述凹槽的四周侧壁上具有金属硅化物层203，凹槽底部具有绝缘层204(参考图6)，导电层208位于所述绝缘层204上，且所述导电层208填充满凹槽，后续可以在导电层208上形成与导电层208电连接的金属层301。
在另一实施例，参考图8，图8为在形成导电层208后，图6所示的半导体结构的俯视结构示意图，图8中介质层202和缓冲层207未示出。如图8所示，源区和漏区201分别位于栅极结构300两侧的半导体衬底中，源区和漏区201分别具有若干凹槽，以源区和漏区201分别具有两个凹槽作为示例进行说明，每个凹槽的四周侧壁上具有金属硅化物层203，每个凹槽底部具有绝缘层204(参考图6)，导电层208位于所述绝缘层204上，且所述导电层208填充满凹槽，后续可以在导电层208上形成将源区和漏区201上对应的若干导电层208电连接的金属层302。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (15)

  1. 一种半导体结构，其特征在于，包括：
    半导体衬底，所述半导体衬底中具有源区和漏区，所述源区和漏区中具有凹槽；
    金属硅化物层，位于所述凹槽的四周侧壁表面；
    绝缘层，位于所述凹槽的底部表面，且所述绝缘层的边缘与所述凹槽四周侧壁上的所述金属硅化物层底部表面接触；
    导电层，填充在所述凹槽中并位于所述金属硅化物层及所述绝缘层上。
  2. 如权利要求1所述的半导体结构，其特征在于，所述接触结构还包括缓冲层，所述缓冲层覆盖所述绝缘层以及对应覆盖所述凹槽侧壁上的所述金属硅化物层。
  3. 如权利要求2所述的半导体结构，其特征在于，所述缓冲层包括氮化钛层和位于所述氮化钛层上的钛层，或者包括氮化钽层和位于所述氮化钽层上钽层，或者包括镓层与位于所述镓层上氮化镓层。
  4. 如权利要求1所述的半导体结构，其特征在于，所述金属硅化物层的材料包括硅化钴、硅化镍、硅化铂、硅化钽、硅化钼及硅化钛中的一种或多种。
  5. 如权利要求1所述的半导体结构，其特征在于，所述绝缘层的材料包括氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种。
  6. 如权利要求1所述的半导体结构，其特征在于，所述金属硅化物层的厚度为10-50nm，绝缘层的厚度为1-2nm。
  7. 如权利要求1所述的半导体结构，其特征在于，所述半导体衬底上形成有栅极结构，所述源区和漏区分别位于栅极结构两侧的半导体衬底中。
  8. 如权利要求1所述的半导体结构，其特征在于，所述半导体衬底上还具有介质层，所述介质层中具有金属插塞，所述金属插塞与所述接触结构连接。
  9. 一种半导体结构的形成方法，其特征在于，包括：
    提供半导体衬底，所述半导体衬底中具有源区和漏区；
    在所述源区和漏区中形成凹槽；
    在所述凹槽的四周侧壁表面上形成金属硅化物层；
    和在所述凹槽的底部表面形成绝缘层；
    在所述绝缘层上形成导电层，所述导电层填充满所述凹槽。
  10. 如权利要求9所述的半导体结构的形成方法，其特征在于，在形成所述导电层之前，在所述绝缘层上形成缓冲层。
  11. 如权利要求9所述的半导体结构的形成方法，其特征在于，在所述源区和漏区中形成金属硅化物层之前，在所述半导体衬底上形成介质层，所述介质层中具有暴露出源区和漏区表面的通孔；在通孔底部的源区和漏区中形成凹槽；在凹槽的侧壁形成金属硅化物层。
  12. 如权利要求9所述的半导体结构的形成方法，其特征在于，在形成导电层后，形成覆盖所述金属硅化物层、导电层和半导体衬底的介质层；在所述介质层中形成金属插塞，所述金属插塞与导电层连接。
  13. 如权利要求9所述的半导体结构的形成方法，其特征在于，所述绝缘层的材料包括氧化钴、氧化镍、氧化铂、氧化钽、氧化钼及氧化钛中的一种或多种。
  14. 如权利要求9所述的半导体结构的形成方法，其特征在于，所述金属硅化物层的厚度为10-50nm，绝缘层的厚度为1-2nm。
  15. 如权利要求9所述的半导体结构的形成方法，其特征在于，所述半导体衬底上形成有栅极结构，所述源区和漏区分别形成在栅极结构两侧的半导体衬底中。
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