WO2022241667A1 - 半导体结构及其形成方法与工作方法 - Google Patents

半导体结构及其形成方法与工作方法 Download PDF

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WO2022241667A1
WO2022241667A1 PCT/CN2021/094532 CN2021094532W WO2022241667A1 WO 2022241667 A1 WO2022241667 A1 WO 2022241667A1 CN 2021094532 W CN2021094532 W CN 2021094532W WO 2022241667 A1 WO2022241667 A1 WO 2022241667A1
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Prior art keywords
gate
gate structure
source
region
layer
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PCT/CN2021/094532
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English (en)
French (fr)
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金吉松
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Priority to PCT/CN2021/094532 priority Critical patent/WO2022241667A1/zh
Priority to CN202180094562.5A priority patent/CN116941020A/zh
Publication of WO2022241667A1 publication Critical patent/WO2022241667A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure, a forming method and a working method thereof.
  • an isolation layer can be formed at the boundary of the transistors, and at the same time, in order to reduce the area of the isolation layer and improve the integration degree of the formed semiconductor structure.
  • the prior art introduces single diffusion break (Single Diffusion Break, referred to as SDB) technology and double diffusion break (Double Diffusion Break, referred to as DDB) technology.
  • the technical problem solved by the present invention is to provide a semiconductor structure and its forming method and working method, which can improve the performance of the semiconductor structure and improve the integration degree of the formed semiconductor structure.
  • an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a first region, and the first region includes a plurality of first active regions arranged along a first direction and a first isolation region located between adjacent first active regions; a plurality of first fins located on the substrate, the plurality of first fins are parallel to the first direction and arranged along the second direction , the second direction is perpendicular to the first direction, the first fin crosses the adjacent first active region and the first isolation region between the first active regions; A plurality of first gate structures on the first isolation region, the first gate structures straddling the first fin along the second direction; a plurality of first electrical interconnection structures, the first electrical interconnection The connecting structure is electrically connected to the first gate structure.
  • an isolation layer on the substrate the isolation layer covers part of the sidewall of the first fin, and the top surface of the isolation layer is lower than that of the first fin.
  • a top surface a top surface; a first gate structure comprising a first portion on a surface of the first fin and a second portion on a surface of the isolation layer; the first electrical interconnection structure is electrically connected to the second portion.
  • the first dielectric layer is located on the substrate, and the first dielectric layer covers the sidewall of the first gate structure.
  • the first electrical interconnection structure includes several plugs respectively located on the top surface of the first gate structure and an interconnection layer located on the several plugs, and the several plugs are separated from each other.
  • the top surface of the first gate structure is lower than the top surface of the first dielectric layer, and part of the plugs are also located in the first dielectric layer.
  • the first electrical interconnection structure includes a plug located adjacent to the top surface of the first gate structure and an interconnection layer located on the plug, and the plug is also located adjacent to the The surface of the first dielectric layer between the first gate structures.
  • the top surface of the first gate structure is lower than the top surface of the first dielectric layer, and part of the plugs are also located in the first dielectric layer.
  • a second gate structure located on the first active region, the second gate structure straddling the first fin along the second direction.
  • the substrate further includes a second region; a plurality of second fins located on the second region, and the plurality of second fins are parallel to the first direction and arranged along the second direction a plurality of third gate structures located on the second region, the third gate structures straddling the second fin, and part of the third gate structures and the second gate structures connect.
  • the substrate further includes a second region, the second region includes a plurality of second active regions arranged along the first direction and a plurality of second active regions located between adjacent second active regions The second isolation region; a plurality of third fins located on the second region, the plurality of third fins are parallel to the first direction and arranged along the second direction, and the third fins straddle the adjacent The second active region and the second isolation region between the second active region; a plurality of fourth gate structures located on the second isolation region, the fourth gate structure along the The second direction spans the third fin, and the fourth gate structure and the first gate structure are spaced apart from each other in the second direction; a plurality of second electrical interconnection structures, the second electrical An interconnection structure is electrically connected to the fourth gate structure.
  • a fifth gate structure located on the second active region, the fifth gate structure straddles the third fin along the second direction, and the fifth The gate structure is connected to the second gate structure.
  • it further includes: a first source-drain doped layer in the first fin located on both sides of each of the first gate structures and on both sides of the second gate structure, and the first source There are first source-drain ions in the drain doped layer; a second source-drain doped layer in the second fin located on both sides of each third gate structure, and the second source-drain doped layer has The second source-drain ion.
  • the conductivity type of the first source-drain ion is different from that of the second source-drain ion; the first source-drain ion includes N-type ions or P-type ions; the second source-drain ion includes P-type ions or N-type ions.
  • it further includes: a first source-drain doped layer in the first fin located on both sides of each of the first gate structures and on both sides of the second gate structure, and the first source There are first source-drain ions in the drain doped layer; a third source-drain doped layer in the third fin located on both sides of each of the fourth gate structures and on both sides of the fifth gate structure, so The third source-drain doped layer contains third source-drain ions.
  • the conductivity type of the first source-drain ion is different from that of the third source-drain ion; the first source-drain ion includes N-type ions or P-type ions; the third source-drain ion includes P-type ions or N-type ions.
  • the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region, and the first region includes a plurality of first active regions arranged along a first direction and a first isolation region located between adjacent first active regions; a plurality of first fins are formed on the first region, and the first fins are parallel to the first direction and along the second arranged in a direction, the second direction is perpendicular to the first direction, and the first fins straddle the adjacent first active regions and the first isolation region between the first active regions; A plurality of first gate structures are formed on the first isolation region, and the first gate structures straddle the first fin along the second direction; a plurality of first gate structures are formed on the first gate structures. An electrical interconnection structure, the first electrical interconnection structure is electrically connected to the first gate structure.
  • the isolation layer covers part of the sidewall of the first fin, and the top of the isolation layer The surface is lower than the top surface of the first fin.
  • the first fin and before forming the first gate structure further comprising: forming a plurality of first dummy gate structures in the first isolation region, the first dummy gate structures across the first fin; forming a first dielectric layer on the substrate, the first dielectric layer covers the sidewall of the first dummy gate structure and exposes the first dummy gate structure of the top surface.
  • the method for forming the first gate structure includes: removing the first dummy gate structure, forming a first gate opening in the first dielectric layer; forming the first gate structure.
  • the first electrical interconnection structure is located at the in the second dielectric layer.
  • the method for forming the first electrical interconnection structure includes: forming a plurality of contact holes separated from each other in the second dielectric layer, the bottoms of the contact holes respectively exposing each of the first gate structures forming a plug in the contact hole; forming an interconnection layer on the plug.
  • the method further includes: etching back part of the first gate structure until the top surface of the first gate structure is lower than the top surface of the first dielectric layer.
  • the method for forming the first electrical interconnection structure includes: forming a contact hole in the second dielectric layer, and the bottom of the contact hole exposes a plurality of adjacent first gate structures and the first gate structure. a top surface of the first dielectric layer between the gate structures; forming a plug in the contact hole; forming an interconnection layer on the plug.
  • the method further includes: etching back part of the first gate structure until the top surface of the first gate structure is lower than the top surface of the first dielectric layer.
  • the present invention also provides a working method of a semiconductor structure, including: providing a semiconductor structure, the semiconductor structure includes: a substrate, the substrate includes a first region, and the first region includes A plurality of first active regions and a first isolation region located between adjacent first active regions; a plurality of first fins located on the substrate, a plurality of first fins and a first fin One direction is parallel and arranged along a second direction, the second direction is perpendicular to the first direction, and the first fin spans between adjacent first active regions and between the first active regions a first isolation region; a plurality of first gate structures located on the first isolation region, the first gate structure straddling the first fin along the second direction; a plurality of first interconnects
  • the first electrical interconnection structure is electrically connected to the first gate structure; the working method includes: applying a voltage to the first electrical interconnection structure, so that the bottom of the first gate structure The channel region is turned off.
  • the semiconductor structure further includes: a first source-drain doped layer located in the first fins on both sides of each of the first gate structures, and the first source-drain doped layer has The first source-drain ion; the working method also includes: when the first source-drain ion is an N-type ion, applying a negative pressure to the first electrical interconnection structure; when the first source-drain ion is a P type ions, applying a positive voltage to the first electrical interconnection structure.
  • the semiconductor structure provided by the present invention includes a plurality of first active regions and a first isolation region between adjacent active regions, spanning between the adjacent first active regions and the first active regions The first fin portion of the first isolation region between them, a plurality of first gate structures located on the first isolation region, the first gate structure straddling the first fin portion, electrically connected to the first gate structure A number of first electrical interconnect structures are connected.
  • the first electrical interconnection structure provides an off signal to the first gate structure, so that the channel in the first fin portion of the first isolation region is in an off state, so that the first gate structure In the invalid state, the first active regions on both sides of the first isolation region are electrically isolated, and there is no need to remove the first gate structure to form an isolation structure to achieve the isolation effect, which is beneficial in the case of high integration of semiconductor structures Effective electrical isolation can still be realized; and, the first fin spans the adjacent first active region and the first isolation region between the first active regions, and there is no need to cut off the first fin of the first fin.
  • An isolation region avoids the layout-dependent effect caused by the cut-off structure of the first fin, which is beneficial to improving the performance of the semiconductor structure.
  • a first fin is formed across the first isolation region between the adjacent first active region and the first active region, and a fin portion across the first isolation region is formed on the first isolation region.
  • a plurality of first gate structures of the first fin forming a plurality of first electrical interconnection structures on the first gate structures;
  • An off signal so that the channel region at the bottom of the first gate structure is in an off state, thereby realizing electrical isolation between the first active regions on both sides of the first isolation region, without removing the first gate structure
  • the means of forming the isolation structure achieves the isolation effect, which is beneficial to achieve effective electrical isolation under the condition of high integration of the semiconductor structure; and, the first fin crosses the adjacent first active region and the first The first isolation region between the active regions does not need to cut off the first isolation region of the first fin, avoiding the layout-dependent effect caused by the cut-off structure of the first fin, which is beneficial to improving the performance of the semiconductor structure.
  • the first electrical interconnection structure by applying a voltage to the first electrical interconnection structure, provides an off signal to the first gate structure, so that the channel region at the bottom of the first gate structure is in the Off state, so as to realize the electrical isolation between the first active regions on both sides of the first isolation region, without removing the first gate structure to form an isolation structure to achieve the isolation effect, which is conducive to the integration of semiconductor structures Effective electrical isolation can still be achieved under high conditions; and the first fin spans the adjacent first active region and the first isolation region between the first active regions, without cutting the first fin
  • the first isolation region of the fin portion avoids the layout-dependent effect caused by the cut-off structure of the first fin portion, which is beneficial to improving the performance of the semiconductor structure.
  • 1 to 2 are structural schematic diagrams of a semiconductor structure in an embodiment
  • 3 to 25 are structural schematic diagrams corresponding to each step of the semiconductor structure formation process in an embodiment of the present invention.
  • 26 to 32 are structural schematic diagrams of the formation process of the semiconductor structure in another embodiment of the present invention.
  • 1 and 2 are schematic top view structural diagrams of a semiconductor structure in an embodiment.
  • the semiconductor structure includes: a substrate 100, the substrate 100 includes a first active region A1, an isolation region B1 and a second active region A2 arranged along a first direction X, and the isolation region B1 is located between the first active area A1 and the second active area A2; several first fins 101 and several second fins 102 located on the substrate 100, the first fins 101 and The second fins 102 are arranged along the second direction Y, the first direction X is perpendicular to the second direction Y, the first fins 101 and the second fins 102 have isolation openings 103 inside, The isolation opening 103 runs through the first fin 101 and the second fin 102 along the second direction Y, and the isolation opening 103 is located on the isolation region B1; The plurality of first gate structures 104 on the region A1 and the second active region A2, the plurality of second gate structures 105 located in the isolation region B1, the first gate structures 104 and the second gate The pole structure 105 spans the first fin 101 and the second fin 102 .
  • the second gate structure 105 on the isolation region B1 is also removed to form a gate opening , and then an isolation structure 106 is formed in the gate opening, and the isolation effect is realized through the isolation structure 106 .
  • the isolation opening 103 will affect the surrounding device layout during the manufacturing process of the miniaturized semiconductor device, that is, It will produce a local dependence effect (Layout Dependence Effect, LDE), which is not conducive to the performance of the semiconductor structure; on the other hand, each isolation region forms a gate structure and this gate structure is removed to form an isolation structure, which will cause the semiconductor structure integration is reduced.
  • LDE Local Dependence Effect
  • an embodiment of the present invention provides a semiconductor structure, the first electrical interconnection structure is connected to a plurality of first gate structures located on the first isolation region, and the first electrical interconnection structure is connected to the The first gate structure provides an off signal, so that the channel region at the bottom of the first gate structure is in an off state, so that the first gate structure becomes invalid, thereby realizing the first active region on both sides of the first isolation region.
  • 3 to 25 are structural schematic diagrams corresponding to each step in the formation process of the semiconductor structure in an embodiment of the present invention.
  • Fig. 3 is a top view of a semiconductor structure
  • Fig. 4 is a schematic cross-sectional structural diagram of Fig. 3 along the C1-C1 direction
  • a substrate 200 is provided, and the substrate 200 includes a first region I, and the first The region I includes a plurality of first active regions A1 arranged along the first direction X and a first isolation region B1 located between adjacent first active regions A1.
  • the substrate 200 further includes a second region II, the first region I and the second region II are arranged along a second direction Y, and the second direction Y and the first direction X is vertical; in other embodiments, the second region may not be included.
  • the second region II does not include an isolation region; in another embodiment, the second region II includes a plurality of second active regions arranged along the first direction X and adjacent The second isolation region between the second active regions.
  • the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium.
  • first fins 201 are formed on the first region I, the first fins 201 are parallel to the first direction X and arranged along the second direction Y, and the first fins 201 span Adjacent to the first active region A1 and a first isolation region B1 between the first active regions A1.
  • it further includes: forming a plurality of second fins 202 on the second region II, the second fins 202 being parallel to the first direction X and arranged along the second direction Y.
  • the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin can also be germanium , silicon germanium, silicon carbide, gallium arsenide or indium gallium.
  • FIG. 5 is a schematic cross-sectional view along the second direction Y.
  • an isolation layer 203 is formed on the substrate 200, and the isolation layer 203 covers the first fin. 201 and part of the sidewalls of the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202 .
  • the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing part of the initial isolation layer to form the isolation layer 203, and The top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202 .
  • the material of the isolation layer 203 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 203 is silicon oxide.
  • the isolation layer 203 After forming the isolation layer 203, it further includes: forming a plurality of first gate structures on the first isolation region B1, the first gate structures straddling the first gate structures along the second direction Y Fin 201; a second gate structure is formed on the first active region A1, and the second gate structure crosses the first fin 201 along the second direction Y; A third gate structure is formed on the region II, the third gate structure straddles the second fin 202 along the second direction, and part of the third gate structure and the second gate structure Connecting: forming a first dielectric layer on the substrate 200, the first dielectric layer covering the sidewall of the first gate structure.
  • the specific formation process includes:
  • FIG. 6 is a top view of a semiconductor structure
  • FIG. 7 is a schematic cross-sectional structure diagram of FIG. 6 along the direction C2-C2
  • FIG. 8 is a schematic cross-sectional structure diagram of FIG.
  • a plurality of first dummy gate structures 204 are formed on the isolation region B1, and the first dummy gate structures 204 straddle the first fin portion 201 on the first isolation region B1.
  • the first dummy gate structure 204 includes a first portion located on the surface of the first fin 201 and a second portion located on the isolation layer 203 .
  • it further includes: forming several second dummy gate structures 205 on the first active region A1, the second dummy gate structures 205 straddling the first active region A1 The first fin portion 201; forming a third dummy gate structure 206 on the second region II, the third dummy gate structure 206 straddles the second fin portion 202, part of the third dummy gate The structure 206 is connected to the second dummy gate structure 205 , and part of the third dummy gate structure 206 is connected to the first dummy gate structure 204 .
  • the first dummy gate structure 204 , the second dummy gate structure 205 and the third dummy gate structure 206 are formed simultaneously.
  • the method for forming the first dummy gate structure 204 includes: forming a first dummy gate dielectric layer (not shown) on the isolation layer 203; A first dummy gate layer (not marked); forming a first side wall (not marked) on the sidewalls of the first dummy gate layer and the first dummy gate dielectric layer.
  • the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.
  • the material of the first dummy gate layer is polysilicon.
  • the method for forming the second dummy gate structure 205 includes: forming a second dummy gate dielectric layer (not shown) on the isolation layer 203; A second dummy gate layer (not marked); forming a second side wall (not marked) on the sidewalls of the second dummy gate layer and the second dummy gate dielectric layer.
  • the material of the second dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer is also the same as that of the first dummy gate layer .
  • the method for forming the third dummy gate structure 206 includes: forming a third dummy gate dielectric layer (not shown) on the isolation layer 203; A third dummy gate layer (not marked); a third spacer (not marked) is formed on the sidewalls of the third dummy gate layer and the third dummy gate dielectric layer.
  • the material of the third dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the third dummy gate layer is also the same as that of the first dummy gate layer .
  • the sectional directions of FIG. 9 and FIG. 7 are consistent, and the sectional directions of FIG. 10 and FIG. 8 are consistent, with the first dummy gate structure 204 and the second dummy gate structure 205 as
  • the first fin portion 201 is etched with a mask to form a number of first source and drain openings (not marked) in the first fin portion 201; the third dummy gate structure 206 is used as a mask to etch the
  • the second fin portion 202 forming a number of second source and drain openings (not marked) in the second fin portion 202; forming a first source and drain doped layer 207 in the first source and drain opening;
  • a second source-drain doped layer 208 is formed in the two source-drain openings.
  • the method for forming the first source-drain doped layer 207 in the first source-drain opening includes: forming a first epitaxial layer (not labeled) in the first source-drain opening by an epitaxial growth process. ); performing in-situ doping on the first epitaxial layer during the epitaxial growth process, and doping first source-drain ions into the first epitaxial layer to form the first source-drain doped layer 207 .
  • the method for forming the second source-drain doped layer 208 in the second source-drain opening includes: forming a second epitaxial layer (not labeled) in the second source-drain opening by using an epitaxial growth process. ); performing in-situ doping on the second epitaxial layer during the epitaxial growth process, and doping second source-drain ions into the second epitaxial layer to form the second source-drain doped layer 208 .
  • the electrical types of the first source-drain ions and the second source-drain ions are different; the first source-drain ions are P-type ions, and the second source-drain ions are N-type ions. In other embodiments, the first source-drain ions may also be N-type ions, and the second source-drain ions may be P-type ions.
  • a first dielectric layer 209 is formed on the substrate 200, and the first dielectric layer 209 covers the first dummy gate structure 20, the second dummy gate structure 206 and the third dummy gate structure.
  • the sidewall of the pole structure 206 is consistent.
  • the method for forming the first dielectric layer 209 includes: forming a first initial dielectric layer (not shown) on the substrate 200, the first initial dielectric layer covering the first source and drain Doped layer 207, second source-drain doped layer 208, first dummy gate structure 204, second dummy gate structure 205, and third dummy gate structure 206; planarizing the first initial dielectric layer , until the top surfaces of the first dummy gate structure 204 , the second dummy gate structure 205 and the third dummy gate structure 206 are exposed, the first dielectric layer 209 is formed.
  • the material of the first dielectric layer 209 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be a low-K dielectric material (a low-K dielectric material refers to a low relative permittivity 3.9 dielectric material) or ultra-low K dielectric material (ultra-low K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5).
  • a low-K dielectric material refers to a low relative permittivity 3.9 dielectric material
  • ultra-low K dielectric material ultra-low K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5
  • FIG. 13 is a top view of a semiconductor structure
  • FIG. 14 is a schematic cross-sectional structure diagram of FIG. 13 along the E1-E1 direction.
  • a gate isolation structure 210 is formed therebetween.
  • the step of forming the gate isolation structure 210 includes: forming a mask layer (not shown) on the first dielectric layer 209, and the mask layer exposes the Part of the first dummy gate structure 204 and the third dummy gate structure 206 on the isolation layer 203 between the second region II; using the mask layer as a mask, etching part of the first dummy gate electrode structure 204 and part of the third dummy gate structure until the surface of the isolation layer 203 is exposed to form a groove (not shown); a gate isolation structure 210 is formed in the groove.
  • FIG. 15 is a top view of the semiconductor structure
  • FIG. 16 is consistent with the cutting direction of FIG. 11,
  • FIG. 17 is consistent with the cutting direction of FIG. 12.
  • the first dummy gate structure 204 is removed. Form a first gate opening (not marked) in the first dielectric layer 209; form a first gate structure 211 in the first gate opening; remove the second dummy gate structure 205, and A second gate opening (not shown) is formed in a dielectric layer 209; the second gate structure 212 is formed in the second gate opening; the third dummy gate structure 206 is removed, and the second gate structure 212 is formed in the first A third gate opening (not shown) is formed in a dielectric layer 209; the third gate structure 213 is formed in the third gate opening.
  • the first gate structure 211 includes a first portion 214 located on the surface of the first fin 201 and a second portion 215 located on the surface of the isolation layer 203 .
  • the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 204, the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 205 are specifically removed.
  • the dummy gate layer and the third dummy gate dielectric layer and the third dummy gate layer of the third dummy gate structure 206 are specifically removed.
  • the first gate structure 211 includes: a first gate dielectric layer (not shown) and a first gate layer (not marked) on the first gate dielectric layer;
  • the gate structure 212 includes: a second gate dielectric layer (not shown) and a second gate layer (not shown) on the second gate dielectric layer;
  • the third gate structure 213 includes: a third gate A dielectric layer (not shown) and a third gate layer (not shown) on the third gate dielectric layer.
  • materials of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer include high-K dielectric materials.
  • Materials of the first gate layer, the second gate layer and the third gate layer include metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.
  • the material of the first gate layer, the second gate layer and the third gate layer is tungsten.
  • Figure 18 is a top view of the semiconductor structure omitting the isolation layer, the first dielectric layer, and the second dielectric layer
  • Figure 19 is a schematic cross-sectional structure diagram along the C3-C3 direction of Figure 18, in the first dielectric layer 209 , forming a second dielectric layer 216 on the first gate structure 211 , the second gate structure 212 and the third gate structure 213 .
  • the material of the second dielectric layer 216 is silicon oxide; in other embodiments, the material of the second dielectric layer can also be a low-K dielectric material (a low-K dielectric material refers to a low relative permittivity 3.9 dielectric material) or ultra-low K dielectric material (ultra-low K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5).
  • a low-K dielectric material refers to a low relative permittivity 3.9 dielectric material
  • ultra-low K dielectric material ultra-low K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5
  • a plurality of contact holes are formed in the second dielectric layer 216, and the bottoms of the contact holes respectively expose the first The top surface of the second portion 215 of the gate structure 211; a plug 217 is formed in each of the contact holes.
  • the number of the plugs 217 is the same as the number of the first gate structures 211 , and each of the plugs 217 is respectively connected to the second portion 215 of the first gate structure 211 .
  • the top surface of the first gate structure 211 is flush with the top surface of the first dielectric layer 209, and the bottom surface of the plug 217 is flush with the top surface of the first dielectric layer 209. flat.
  • the top surface of the first gate structure 211 is lower than the top surface of the first dielectric layer 209, and the first gate The top surface of the structure 211 also has a cover layer, the top surface of the cover layer is flush with the top surface of the first dielectric layer, and part of the plugs 217 are also located in the first dielectric layer 209 .
  • the contact hole before forming the contact hole, it further includes: etching back part of the first gate structure 211 until the top surface of the first gate structure 211 is lower than the first dielectric layer 209 top surface.
  • a contact hole (not shown) may also be formed in the second dielectric layer 216, and the bottom of the contact hole exposes a phase
  • the bottom surface of the plug 218 is flush with the top surface of the first dielectric layer 209 .
  • the cut directions of FIG. 22 and FIG. 21 are consistent, and the bottom surface of the plug 218 may also be lower than the top surface of the first dielectric layer 209; Before opening the hole, etch back the first gate structure 211 until the top surface of the first gate structure 211 is lower than the top surface of the first dielectric layer 209 .
  • this embodiment further includes: forming source and drain plugs 220 on the first source and drain doped layer 207 on both sides of the first fin portion 201 on the first active region A1 .
  • FIG. 23 is a top view of the semiconductor structure
  • FIG. 24 is a schematic cross-sectional structure diagram of FIG. 23 along the C4-C4 direction
  • FIG. 25 is a simplified three-dimensional structure diagram of the semiconductor structure.
  • An upper interconnection layer 219 is formed on the plug 217, the plug 217 and the interconnection layer 219 form a first electrical interconnection structure, and the first electrical interconnection structure and the first gate structure 211
  • the second part 215 is electrically connected.
  • it also includes: forming a first conductive layer (not shown) on the first source-drain doped layer 207; forming a second conductive layer (not shown) on the second source-drain doped layer 208 icon).
  • the source-drain plug 220 also forms an interconnection structure with the interconnection layer 219 .
  • FIG. 25 is a simple circuit diagram of a semiconductor structure.
  • the interconnection layer 219 is Vdd
  • the source-drain plug 220 is connected to the Vdd
  • the plug 217 Connect with the Vdd.
  • the interconnection layer 219 is Vss
  • the source-drain plug 220 is connected to the Vss
  • the plug 217 is connected to the Vss.
  • 26 to 31 are structural schematic diagrams of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 26 is a top view of a semiconductor structure
  • FIG. 27 is a schematic cross-sectional structure diagram of FIG. 26 along the direction C5-C5.
  • the second region II of the substrate 200 includes A plurality of second active regions A2 arranged in the first direction X and a second isolation region B2 located between adjacent second active regions A2.
  • third fins 301 are formed in the second region II, the third fins 301 are parallel to the first direction X and arranged along the second direction Y, the third fins 301 straddle the first direction two active regions A2 and the second isolation region B2.
  • the forming method and material of the third fin portion 301 are the same as those of the first fin portion 201 , and will not be repeated here.
  • the isolation layer 203 also covers part of the sidewall surface of the third fin 301 .
  • FIG. 28 is a top view of a semiconductor structure.
  • the cross-sectional directions of FIG. 29 and FIG. 28 are consistent, and a plurality of fourth gate structures 302 are formed in the second isolation region B2, and the fourth gate The structure 302 straddles the third fin 301, and the fourth gate structure 302 and the first gate structure 211 are spaced apart from each other in the second direction Y; on the second active region A2 A plurality of fifth gate structures 303 are formed, the fifth gate structures 303 straddle the third fin portion 301 on the second active region A2, and the fifth gate structures 303 are connected to the second gate The pole structure 212 is connected.
  • the fourth gate structure 302 includes a third portion 304 located on the surface of the third fin 301 and a fourth portion 305 located on the surface of the isolation layer 203 .
  • the methods and materials for forming the fourth gate structure 302 and the fifth gate structure 303 are the same as those for forming the first gate structure 211 and the third gate structure 213 , and will not be repeated here.
  • the fourth gate structure 302 and the fifth gate structure 303 Before forming the fourth gate structure 302 and the fifth gate structure 303, it also includes: forming a third source and drain in the third fins on both sides of the fourth gate structure and the fifth gate structure
  • the doped layer 306, the third source-drain doped layer 306 contains third source-drain ions.
  • the conductivity type of the third source-drain ion is different from that of the first source-drain ion; the first source-drain ion includes N-type ions or P-type ions; the third source-drain ion includes P-type ions or N-type ions ion.
  • FIG. 29 is a top view of a semiconductor structure
  • FIG. 31 is a schematic cross-sectional structure diagram of FIG.
  • a second electrical interconnection structure 307 is formed in the second dielectric layer 216 , and the second electrical interconnection structure 307 is electrically connected to the fourth portion 305 of the fourth gate structure 302 .
  • the formation method and structure of the second electrical interconnection structure 307 are the same as the formation method and structure of the first electrical interconnection structure, and will not be repeated here.
  • it further includes: forming a third conductive layer (not shown) on the third source-drain doped layer 306 .
  • FIG. 32 is a simplified structural schematic diagram of a semiconductor structure.
  • the present invention also provides a semiconductor structure, including: a substrate 200, which includes a first region I , the first region I includes a plurality of first active regions A1 arranged along the first direction X and a first isolation region B1 located between adjacent first active regions A1; Several first fins 201 on 200, several first fins 201 are parallel to the first direction X and arranged along the second direction Y, the second direction Y is perpendicular to the first direction X, the first A fin 201 straddles the adjacent first active region A1 and the first isolation region B1 between the first active region A1; a plurality of first gates located on the first isolation region B1 structure 211, the first gate structure 211 spans the first fin 201 along the second direction Y; several first electrical interconnection structures, the first electrical interconnection structure and the first gate The pole structure 211 is electrically connected.
  • it further includes: an isolation layer 203 located on the substrate 200, the isolation layer 203 covers part of the sidewall of the first fin 201, and the top surface of the isolation layer 203 is lower than the The top surface of the first fin 201; the first gate structure 211 includes a first portion 214 located on the surface of the first fin 201 and a second portion 215 located on the surface of the isolation layer 203; the first interconnect The connecting structure is electrically connected with the second part 215 .
  • it further includes: a second gate structure 212 located on the first active region A1, and the second gate structure 212 crosses the first fin 201 along the second direction Y .
  • it further includes: a first dielectric layer 209 located on the substrate 200 , and the first dielectric layer 209 covers the sidewall of the first gate structure 211 .
  • the first electrical interconnection structure includes a plurality of plugs 217 respectively located on the top surface of the second portion 215 of the first gate structure 211 and an interconnection layer 219 located on the plurality of plugs 217 , several of the plugs 217 are separated from each other.
  • the top surface of the first gate structure 211 is flush with the top surface of the first dielectric layer 209 .
  • the top surface of the first gate structure 211 is lower than the top surface of the first dielectric layer 209, and part of the plug 217 is also located on the first dielectric layer 209. Inside.
  • it further includes: a second dielectric layer 216 located on the first dielectric layer 209 , and the first electrical interconnection structure is located in the second dielectric layer 216 .
  • the first electrical interconnection structure includes a plug 218 located adjacent to the top surface of the first gate structure 211 and an interconnection layer 219 located on the plug 218 , the plug 218 is also located on the surface of the first dielectric layer 209 between adjacent first gate structures 211 .
  • the top surface of the first gate structure 211 is flush with the top surface of the first dielectric layer 209 .
  • the top surface of the first gate structure 211 is lower than the top surface of the first dielectric layer 209, and part of the plug 218 is also located on the first dielectric layer 209. Inside.
  • the substrate 200 further includes a second region II.
  • the second region II does not include an isolation region; in another embodiment, the second region II further includes a plurality of second active regions arranged along the first direction X and adjacent A second isolation region between the second active regions.
  • it also includes: several second fins 202 located on the second region II, the second fins 202 are parallel to the first direction X and arranged along the second direction Y; A plurality of third gate structures 213 on the second region II, the third gate structures 213 cross the second fin 202, and part of the third gate structures 213 and the second gate The structure 212 is connected.
  • gate isolation structure 210 between part of the third gate structure 213 and the first gate structure 211, and the gate isolation structure 210 is located between the first region I and the second region II on the isolation layer 203.
  • it further includes: a first source-drain doped layer in the first fin portion 201 located on both sides of each of the first gate structures 211 and on both sides of the second gate structure 212 207, and the first source-drain doped layer 207 has first source-drain ions; the second source-drain doped layer in the second fin 202 located on both sides of each third gate structure 213 208.
  • the second source-drain doped layer 208 contains second source-drain ions.
  • the conductivity types of the first source-drain ions and the second source-drain ions are different; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions. Type ions or N-type ions.
  • it also includes: a first conductive layer (not shown) located on the first source-drain doped layer 207 and a second conductive layer (not shown) located on the second source-drain doped layer 208 icon).
  • the second region II includes a plurality of second active regions A2 arranged along the first direction X and located between adjacent second active regions A2. Between the second isolation area B2.
  • a plurality of third fins 301 are formed on the second region II, the plurality of third fins 301 are parallel to the first direction X and arranged along the second direction Y, and the third fins 301 straddle the phase Adjacent to the second active region A2 and the second isolation region B2 between the second active region A2; a plurality of fourth gate structures 302 located on the second isolation region B2, the fourth The gate structure 302 crosses the third fin 301 along the second direction Y, and the fourth gate structure 302 and the first gate structure 211 are spaced apart from each other in the second direction Y; A second electrical interconnection structure 307 , the second electrical interconnection structure 307 is electrically connected to the fourth gate structure 302 .
  • the structure of the second electrical interconnection structure is the same as that of the first electrical interconnection structure, which will not be repeated here.
  • the fourth gate structure 302 includes a third portion 304 located on the surface of the third fin 301 and a fourth portion 305 located on the surface of the isolation layer 203 , the second interconnect The connecting structure is electrically connected with the fourth part 305 .
  • it further includes: a fifth gate structure 303 located on the second active region A2, the fifth gate structure 303 crossing the third fin along the second direction Y portion 301 , and the fifth gate structure 303 is connected to the second gate structure 212 .
  • it further includes: a third source-drain doped layer 306 located in the third fin portion on both sides of each of the fourth gate structures 302 and on both sides of the fifth gate structure 303 ,
  • the third source-drain doped layer 306 contains third source-drain ions.
  • the conductivity type of the first source-drain ion is different from that of the third source-drain ion; the first source-drain ion includes N-type ions or P-type ions; the third source-drain ion includes P-type ions or N-type ions ion.
  • it further includes: a third conductive layer (not shown) located on the third source-drain doped layer 306 .
  • the present invention also provides a working method of a semiconductor structure, including: providing a semiconductor structure, the semiconductor structure includes: a substrate 200, the substrate 200 includes a first region I, and the first region I includes A plurality of first active regions A1 arranged in a direction X and a first isolation region B1 located between adjacent first active regions A1; several first fins 201 located on the substrate 200, A plurality of the first fins 201 are parallel to the first direction X and arranged along the second direction Y, the second direction Y is perpendicular to the first direction X, the first fins 201 span the adjacent The first active region A1 and the first isolation region B1 between the first active region A1; a plurality of first gate structures 211 located on the first isolation region B1, the first gate structure 211 across the first fin 201 along the second direction Y; several first electrical interconnection structures, the first electrical interconnection structures are electrically connected to the first gate structure 211; the working method The method includes: applying a voltage to the first electrical interconnection structure to turn off the
  • the semiconductor structure further includes: a first source-drain doped layer 207 located in the first fin portion 201 on both sides of each of the first gate structures 211, and the first source-drain doped layer 207 There are first source-drain ions; the working method further includes: when the first source-drain ions are N-type ions, applying a negative pressure to the first electrical interconnection structure; when the first source-drain ions are P-type ions apply positive pressure to the first electrical interconnection structure.
  • the channel region at the bottom of the first gate structure 211 is in an off state, so that the first gate structure 211 fails, thereby
  • the first gate structure 211 fails, thereby
  • the semiconductor structure further includes: a second region II, the second region II includes a plurality of second active regions A2 arranged along the first direction X and located adjacent to the second The second isolation region B2 between the active regions A2; a plurality of third fins 301, the plurality of third fins 301 are parallel to the first direction X and arranged along the second direction Y, the third fins 301 across the second isolation region B2 adjacent to the second active region A2 and between the second active region A2; a plurality of fourth gate structures 302 located on the second isolation region B2, The fourth gate structure 302 crosses the third fin portion 301 along the second direction Y, and the fourth gate structure 302 and the first gate structure 211 are mutually connected in the second direction Y spaced apart; several second electrical interconnection structures 307, the second electrical interconnection structures 307 are electrically connected to the fourth gate structure 302; the working method also includes: A voltage is applied to turn off the channel region at the bottom of the fourth gate structure 302 .
  • the semiconductor structure further includes: a third source-drain doped layer 306 located in the third fin portion on both sides of each of the fourth gate structures 302 and on both sides of the fifth gate structure 303 , the first There is a third source-drain ion in the three-source-drain doped layer 306, and the conductivity type of the third source-drain ion is opposite to that of the first source-drain ion; the working method includes: when the third source-drain ion is In the case of N-type ions, a negative pressure is applied to the second electrical interconnection structure; when the third source-drain ions are P-type ions, a positive pressure is applied to the second electrical interconnection structure.

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Abstract

一种半导体结构及其形成方法与工作方法，其中半导体结构包括：衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；位于所述衬底上的若干第一鳍部，若干所述第一鳍部与第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；位于所述第一隔离区上的多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接。本发明有利于在集成度高的半导体结构中实现相邻有源区之间的电隔离，有利于提高半导体结构的性能。

Description

半导体结构及其形成方法与工作方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法与工作方法。
背景技术
随着半导体器件集成度的提高，晶体管的关键尺寸不断缩小。然而，随着晶体管尺寸的急剧减小，栅第一介质层厚度与工作电压不能相应改变使抑制短沟道效应的难度加大，使晶体管的沟道漏电流增大。
为了使相邻的晶体管之间电隔离，可在晶体管的边界处形成隔离层，同时为了减小隔离层的面积，提高所形成半导体结构的集成度。现有技术引入了单扩散隔断(Single Diffusion Break，简称SDB)技术以及双扩散隔断(Double Diffusion Break，简称DDB)技术。
然而，现有方法在形成半导体结构的过程中仍存在诸多问题。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法与工作方法，能够提高半导体结构的性能，提高所形成的半导体结构的集成度。
为解决上述技术问题，本发明实施例提供一种半导体结构，包括：衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；位于所述衬底上的若干第一鳍部，若干所述第一鳍部与第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨 相邻所述第一有源区以及所述第一有源区之间的第一隔离区；位于所述第一隔离区上的多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接。
可选的，还包括：位于所述衬底上的隔离层，所述隔离层覆盖所述第一鳍部的部分侧壁，且所述隔离层的顶部表面低于所述第一鳍部的顶部表面；第一栅极结构包括位于所述第一鳍部表面的第一部分以及位于所述隔离层表面的第二部分；所述第一电互连结构与所述第二部分电连接。
可选的，位于所述衬底上的第一介质层，所述第一介质层覆盖所述第一栅极结构的侧壁。
可选的，所述第一电互连结构包括若干分别位于所述第一栅极结构顶部表面的插塞以及位于若干所述插塞上的互连层，若干所述插塞相互分立。
可选的，所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面，部分所述插塞还位于所述第一介质层内。
可选的，所述第一电互连结构包括位于相邻所述第一栅极结构顶部表面的插塞以及位于所述插塞上的互连层，所述插塞还位于相邻所述第一栅极结构之间的第一介质层表面。
可选的，所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面，部分所述插塞还位于所述第一介质层内。
可选的，还包括：位于所述第一有源区上的第二栅极结构，所述第二栅极结构沿所述第二方向横跨所述第一鳍部。
可选的，所述衬底还包括第二区；位于所述第二区上的若干第二鳍部，若干所述第二鳍部与所述第一方向平行且沿所述第二方向排列；位于所述第二区上的多个第三栅极结构，所述第三栅极结构横跨所述第二鳍部，且部分所述第三栅极结构与所述第二栅极结构连接。
可选的，所述衬底还包括第二区，所述第二区包括沿所述第一方向排布的多个第二有源区以及位于相邻所述第二有源区之间的第二隔离区；位于所述第二区上的若干第三鳍部，若干所述第三鳍部与所述第一方向平行且沿第二方向排列，所述第三鳍部横跨相邻所述第二有源区以及所述第二有源区之间的第二隔离区；位于所述第二隔离区上的多个第四栅极结构，所述第四栅极结构沿所述第二方向横跨所述第三鳍部，且所述第四栅极结构与所述第一栅极结构在第二方向上彼此间隔开；若干第二电互连结构，所述第二电互连结构与所述第四栅极结构电连接。
可选的，还包括：位于所述第二有源区上的第五栅极结构，所述第五栅极结构沿所述第二方向横跨所述第三鳍部，且所述第五栅极结构与所述第二栅极结构连接。
可选的，还包括：位于各所述第一栅极结构两侧以及所述第二栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；位于各所述第三栅极结构两侧的所述第二鳍部内的第二源漏掺杂层，所述第二源漏掺杂层内具有第二源漏离子。
可选的，所述第一源漏离子与所述第二源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第二源漏离子包括P型离子或N型离子。
可选的，还包括：位于所述第一源漏掺杂层上的第一导电层以及位于所述第二源漏掺杂层上的第二导电层。
可选的，还包括：位于各所述第一栅极结构两侧以及所述第二栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；位于各所述第四栅极结构两侧以及所述第五栅极结构两侧的所述第三鳍部内的第三源漏掺杂层，所述第三源漏掺杂层内具有第三源漏离子。
可选的，所述第一源漏离子与所述第三源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第三源漏离子包括P型离子或N型离子。
可选的，还包括：位于所述第一源漏掺杂层上的第一导电层以及位于所述第三源漏掺杂层上的第三导电层。
相应的，本发明还提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；在所述第一区上形成若干第一鳍部，所述第一鳍部与所述第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；在所述第一隔离区上形成多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；在所述第一栅极结构上形成若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接。
可选的，在形成所述第一鳍部之后，还包括：在所述衬底上形成隔离层，所述隔离层覆盖所述第一鳍部的部分侧壁，且所述隔离层的顶部表面低于所述第一鳍部的顶部表面。
可选的，在形成所述第一鳍部之后且形成第一栅极结构之前，还包括：在所述第一隔离区形成多个第一伪栅极结构，所述第一伪栅极结构横跨所述第一鳍部；在所述衬底上形成第一介质层，所述第一介质层覆盖所述第一伪栅极结构的侧壁且暴露出所述第一伪栅极结构的顶部表面。
可选的，所述第一栅极结构的形成方法包括：去除所述第一伪栅极结构，在所述第一介质层内形成第一栅极开口；在所述第一栅极开口内形成所述第一栅极结构。
可选的，在形成所述第一栅极结构之后，还包括：在所述第一介质层以及所述第一栅极结构上形成第二介质层，所述第一电互连结构位于所述第二介质层内。
可选的，所述第一电互连结构的形成方法包括：在所述第二介质层内形成多个相互分立的接触孔，所述接触孔底部分别暴露出各所述第一栅极结构的顶部表面；在所述接触孔内形成插塞；在所述插塞上形成互连层。
可选的，在形成所述接触孔之前，还包括：回刻蚀部分所述第一栅极结构，至所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面。
可选的，所述第一电互连结构的形成方法包括：在所述第二介质层内形成接触孔，所述接触孔底部暴露出相邻的多个所述第一栅极结构以及第一栅极结构之间的第一介质层的顶部表面；在所述接触孔内形成插塞；在所述插塞上形成互连层。
可选的，在形成所述接触孔之前，还包括：回刻蚀部分所述第一栅极结构，至所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面。
相应的，本发明还提供一种半导体结构的工作方法，包括：提供半导体结构，所述半导体结构包括：衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；位于所述衬底上的若干第一鳍部，若干所述第一鳍部与第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；位于所述第一隔离区上的多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接；所述工作方法包括：对所述第一电互连结构施加电压，使所述第一栅极结构底部的沟道区关断。
可选的，所述半导体结构还包括：位于各所述第一栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；所述工作方法还包括：当所述第一源漏离子为N型 离子时，对所述第一电互连结构施加负压；当所述第一源漏离子为P型离子，对所述第一电互连结构施加正压。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明提供的半导体结构，包括多个第一有源区以及位于相邻有源区之间的第一隔离区，横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区的第一鳍部，位于第一隔离区上的多个第一栅极结构，所述第一栅极结构横跨所述第一鳍部，与第一栅极结构电连接的若干第一电互连结构。所述第一电互连结构通过对所述第一栅极结构提供关断信号，以使位于第一隔离区的第一鳍部的内的沟道处于关断状态，使第一栅极结构处于失效状态，从而将第一隔离区两侧的第一有源区电隔离，不需要通过去除第一栅极结构形成隔离结构的手段达到隔离效果，从而有利于在半导体结构集成度高的情况下仍能实现有效电隔离；并且，第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区，不需要切断第一鳍部的第一隔离区，避免第一鳍部的切断结构造成布局依赖效应，有利于提高半导体结构的性能。
本发明提供的形成方法中，形成横跨相邻所述第一有源区和第一有源区之间的第一隔离区的第一鳍部，在所述第一隔离区上形成横跨所述第一鳍部的多个第一栅极结构，在所述第一栅极结构上形成若干第一电互连结构；通过第一电互连结构对所述第一栅极结构提供关断信号，使所述第一栅极结构底部的沟道区处于关断状态，从而实现第一隔离区两侧的第一有源区之间的电隔离，不需要通过去除第一栅极结构形成隔离结构的手段达到隔离效果，从而有利于在半导体结构集成度高的情况下仍能实现有效电隔离；并且，第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区，不需要切断第一鳍部的第一隔离区，避免第一鳍部的切断结构造成布局依赖效应，有利于提高半导体结构的性能。
本发明提供的工作方法，通过对第一电互连结构施加电压，使第 一电互连结构对所述第一栅极结构提供关断信号，使第一栅极结构底部的沟道区处于关断状态，从而实现第一隔离区两侧的第一有源区之间的电隔离，不需要通过去除第一栅极结构形成隔离结构的手段达到隔离效果，从而有利于在半导体结构集成度高的情况下仍能实现有效电隔离；并且，第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区，不需要切断第一鳍部的第一隔离区，避免第一鳍部的切断结构造成布局依赖效应，有利于提高半导体结构的性能。
附图说明
图1至图2是一实施例中半导体结构的结构示意图；
图3至图25是本发明一实施例中半导体结构形成过程各步骤对应的结构示意图；
图26至图32是本发明另一实施例中半导体结构形成过程的结构示意图。
具体实施方式
由背景技术可知，目前通常采用DDB或SDB技术来实现相邻晶体管之间的电隔离，但是仍存在诸多问题。现结合附图进行具体说明。
图1和图2是一实施例中半导体结构的俯视结构示意图。
参考图1，所述半导体结构包括：衬底100，所述衬底100包括沿第一方向X排布的第一有源区A1、隔离区B1和第二有源区A2，所述隔离区B1位于所述第一有源区A1和第二有源区A2之间；位于所述衬底100上的若干第一鳍部101和若干第二鳍部102，所述第一鳍部101和所述第二鳍部102沿第二方向Y排列，所述第一方向X与所述第二方向Y垂直，所述第一鳍部101和所述第二鳍部102内具有隔离开口103，所述隔离开口103沿所述第二方向Y贯穿所述第一鳍部101和所述第二鳍部102，且所述隔离开口103位于所述隔离区B1上；位于所述第一有源区A1和所述第二有源区A2上的若干第一栅极结构104，位于所述隔离区B1的若干第二栅极结构105，所述 第一栅极结构104和所述第二栅极结构105横跨所述第一鳍部101和第二鳍部102。
参考图2，在上述半导体结构中，为了实现第一有源区A1和第二有源区A2之间的电隔离，还会去除隔离区B1上的第二栅极结构105，形成栅极开口，然后在栅极开口中形成隔离结构106，通过隔离结构106实现隔离效果。
上述半导体结构中，一方面，由于在第一鳍部101和第二鳍部102内具有隔离开口103，在小型化半导体器件的制造过程中，隔离开口103会对周围的器件布局产生影响，即会产生局部依赖效应(Layout Dependence Effect，LDE)，不利于半导体结构的性能；另一方面，每一个隔离区形成一个栅极结构且这一栅极结构被移除形成隔离结构，会导致半导体结构的集成度降低。
为了解决上述问题，本发明实施例提供了一种半导体结构，第一电互连结构与位于第一隔离区上的多个第一栅极结构连接，通过对第一电互连结构施加电压对第一栅极结构提供关断信号，使第一栅极结构底部的沟道区处于关断状态，以使得第一栅极结构失效，从而实现第一隔离区两侧的第一有源区的电隔离，一方面，不需要去除第一栅极结构以形成隔离结构，可以提高半导体结构的集成度；另一方面，第一鳍部不需要在第一隔离区进行切断，从而可以避免第一鳍部的切断结构造成的布局效应依赖，有利于提高半导体结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图25是本发明一实施例中半导体结构形成过程各步骤对应的结构示意图。
参考图3和图4，图3是半导体结构的俯视图，图4是图3沿C1-C1方向的剖面结构示意图，提供衬底200，所述衬底200包括第一区Ⅰ，所述第一区Ⅰ包括沿第一方向X排布的多个第一有源区A1以及位于 相邻所述第一有源区A1之间的第一隔离区B1。
本实施例中，所述衬底200还包括第二区Ⅱ，所述第一区Ⅰ和所述第二区Ⅱ沿第二方向Y排布，所述第二方向Y与所述第一方向X垂直；在其他实施例中，也可以不包括第二区。
本实施例中，所述第二区Ⅱ不包括隔离区；在另一实施例中，所述第二区Ⅱ包括沿第一方向X排布的多个第二有源区以及位于相邻所述第二有源区之间的第二隔离区。
本实施例中，所述衬底200的材料为硅；在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟。
在所述第一区Ⅰ上形成若干第一鳍部201，所述第一鳍部201与所述第一方向X平行且沿所述第二方向Y排列，所述第一鳍部201横跨相邻所述第一有源区A1以及所述第一有源区A1之间的第一隔离区B1。
本实施例中，还包括：在所述第二区Ⅱ上形成若干第二鳍部202，所述第二鳍部202与所述第一方向X平行且沿所述第二方向Y排列。
本实施例中，所述第一鳍部201和所述第二鳍部202的材料为硅；在其他实施例中，所述第一鳍部和所述第二鳍部的材料还可以为锗、锗化硅、碳化硅、砷化镓或者镓化铟。
参考图5，图5是沿第二方向Y的剖面示意图，在形成所述第一鳍部201之后，在所述衬底200上形成隔离层203，所述隔离层203覆盖所述第一鳍部201和所述第二鳍部202的部分侧壁，且所述隔离层203的顶部表面低于所述第一鳍部201和第二鳍部202的顶部表面。
本实施例中，所述隔离层203的形成方法包括：在所述衬底200上形成初始隔离层(未图示)；刻蚀去除部分所述初始隔离层，形成所述隔离层203，所述隔离层203的顶部表面低于所述第一鳍部201和所述第二鳍部202的顶部表面。
所述隔离层203的材料采用绝缘材料，所述绝缘材料包括氧化硅或氮氧化硅；在本实施例中，所述隔离层203的材料采用氧化硅。
在形成所述隔离层203之后，还包括：在所述第一隔离区B1上形成多个第一栅极结构，所述第一栅极结构沿所述第二方向Y横跨所述第一鳍部201；在所述第一有源区A1上形成第二栅极结构，所述第二栅极结构沿所述第二方向Y横跨所述第一鳍部201；在所述第二区Ⅱ上形成第三栅极结构，所述第三栅极结构沿所述第二方向横跨所述第二鳍部202，且部分所述第三栅极结构与所述第二栅极结构连接；在所述衬底200上形成第一介质层，所述第一介质层覆盖所述第一栅极结构的侧壁。具体形成过程包括：
参考图6至图8，图6是半导体结构的俯视图，图7是图6沿C2-C2方向的剖面结构示意图，图8是图6沿D1-D2方向的剖面结构示意图，在所述第一隔离区B1上形成多个第一伪栅极结构204，所述第一伪栅极结构204横跨所述位于所述第一隔离区B1上的第一鳍部201。
本实施例中，所述第一伪栅极结构204包括位于所述第一鳍部201表面的第一部分以及位于所述隔离层203上的第二部分。
本实施例中，还包括：在所述第一有源区A1上形成若干第二伪栅极结构205，所述第二伪栅极结构205横跨位于所述第一有源区A1上的第一鳍部201；在所述第二区Ⅱ上形成第三伪栅极结构206，所述第三伪栅极结构206横跨所述第二鳍部202，部分所述第三伪栅极结构206与所述第二伪栅极结构205连接，部分所述第三伪栅极结构206与所述第一伪栅极结构204连接。
本实施例中，所述第一伪栅极结构204、所述第二伪栅极结构205和所述第三伪栅极结构206同时形成。
本实施例中，所述第一伪栅极结构204的形成方法包括：在所述隔离层203上形成第一伪栅介质层(未图示)；在所述第一伪栅介质层上形成第一伪栅极层(未标示)；在所述第一伪栅极层以及所述第 一伪栅介质层的侧壁上形成第一侧墙(未标示)。
本实施例中，所述第一伪栅介质层的材料采用氧化硅；在其他实施例中，所述第一伪栅介质层材料还可以采用氮氧化硅。
本实施例中，所述第一伪栅层的材料采用多晶硅。
本实施例中，所述第二伪栅极结构205的形成方法包括：在所述隔离层203上形成第二伪栅介质层(未图示)；在所述第二伪栅介质层上形成第二伪栅层(未标示)；在所述第二伪栅层和所述第二伪栅介质层的侧壁上形成第二侧墙(未标示)。
本实施例中，所述第二伪栅介质层的材料与所述第一伪栅介质层的材料相同，且所述第二伪栅层的材料与所述第一伪栅层的材料也相同。
本实施例中，所述第三伪栅极结构206的形成方法包括：在所述隔离层203上形成第三伪栅介质层(未图示)；在所述第三伪栅介质层上形成第三伪栅层(未标示)；在所述第三伪栅层和所述第三伪栅介质层的侧壁上形成第三侧墙(未标示)。
本实施例中，所述第三伪栅介质层的材料与所述第一伪栅介质层的材料相同，且所述第三伪栅层的材料与所述第一伪栅层的材料也相同。
参考图9和图10，图9和图7的剖切方向一致，图10和图8的剖切方向一致，以所述第一伪栅极结构204和所述第二伪栅极结构205为掩膜刻蚀所述第一鳍部201，在所述第一鳍部201内形成若干第一源漏开口(未标示)；以所述第三伪栅极结构206为掩膜刻蚀所述第二鳍部202，在所述第二鳍部202内形成若干第二源漏开口(未标示)；在所述第一源漏开口内形成第一源漏掺杂层207；在所述第二源漏开口内形成第二源漏掺杂层208。
本实施例中，在所述第一源漏开口内形成所述第一源漏掺杂层207的方法包括：采用外延生长工艺在所述第一源漏开口内形成第一 外延层(未标示)；在所述外延生长过程中对所述第一外延层进行原位掺杂，在所述第一外延层内掺入第一源漏离子，形成所述第一源漏掺杂层207。
本实施例中，在所述第二源漏开口内形成所述第二源漏掺杂层208的方法包括：采用外延生长工艺在所述第二源漏开口内形成第二外延层(未标示)；在所述外延生长过程中对所述第二外延层进行原位掺杂，在所述第二外延层内掺入第二源漏离子，形成所述第二源漏掺杂层208。
本实施例中，所述第一源漏离子与所述第二源漏离子的电学类型不同；所述第一源漏离子采用P型离子，所述第二源漏离子采用N型离子。在其他实施例中，所述第一源漏离子还可以采用N型离子，所述第二源漏离子采用P型离子。
参考图11和图12，图11和图9的剖切方向一致，图12和图10的剖切方向一致，在形成所述第一源漏掺杂层207和所述第二源漏掺杂层208之后，在所述衬底200上形成第一介质层209，所述第一介质层209覆盖所述第一伪栅极结构20、第二伪栅极结构206和所述第三伪栅极结构206的侧壁。
本实施例中，所述第一介质层209的形成方法包括：在所述衬底200上形成第一初始介质层(未图示)，所述第一初始介质层覆盖所述第一源漏掺杂层207、第二源漏掺杂层208、第一伪栅极结构204、第二伪栅极结构205以及第三伪栅极结构206；对所述第一初始介质层进行平坦化处理，直至暴露出所述第一伪栅极结构204、第二伪栅极结构205以及第三伪栅极结构206的顶部表面为止，形成所述第一介质层209。
本实施例中，所述第一介质层209的材料采用氧化硅；在其他实施例中，所述第一介质层的材料还可以为低K介质材料(低K介质材料指相对介电常数低于3.9的介质材料)或超低K介质材料(超低K介质材料指相对介电常数低于2.5的介质材料)。
参考图13和图14，图13是半导体结构的俯视图，图14是图13沿E1-E1方向的剖面结构示意图，在所述第一伪栅极结构204和所述第三伪栅极结构206之间形成栅极隔离结构210。
本实施例中，形成所述栅极隔离结构210的步骤包括：在所述第一介质层209上形成掩膜层(未图示)，所述掩膜层暴露出位于所述第一区Ⅰ和第二区Ⅱ之间隔离层203上的部分所述第一伪栅极结构204和第三伪栅极结构206；以所述掩膜层为掩膜，刻蚀部分所述第一伪栅极结构204和部分所述第三伪栅极结构，直至暴露出所述隔离层203的表面，形成凹槽(未标示)；在所述凹槽内形成栅极隔离结构210。
参考图15至图17，图15是半导体结构的俯视图，图16与图11的剖切方向一致，图17与图12的剖切方向一致，去除所述第一伪栅极结构204，在所述第一介质层209内形成第一栅极开口(未标示)；在所述第一栅极开口内形成第一栅极结构211；去除所述第二伪栅极结构205，在所述第一介质层209内形成第二栅极开口(未标示)；在所述第二栅极开口内形成所述第二栅极结构212；去除所述第三伪栅极结构206，在所述第一介质层209内形成第三栅极开口(未标示)；在所述第三栅极开口内形成所述第三栅极结构213。
本实施例中，所述第一栅极结构211包括位于所述第一鳍部201表面的第一部分214以及位于所述隔离层203表面的第二部分215。
本实施例中，具体去除所述第一伪栅极结构204的第一伪栅介质层和第一伪栅极层、所述第二伪栅极结构205的第二伪栅介质层和第二伪栅极层以及第三伪栅极结构206的第三伪栅介质层和第三伪栅极层。
本实施例中，所述第一栅极结构211包括：第一栅介质层(未图示)以及位于所述第一栅介质层上的第一栅极层(未标示)；所述第二栅极结构212包括：第二栅介质层(未图示)以及位于所述第二栅介质层上的第二栅极层(未标示)；所述第三栅极结构213包括：第 三栅介质层(未图示)以及位于所述第三栅介质层上的第三栅极层(未标示)。
本实施例中，所述第一栅介质层、所述第二栅介质层和所述第三栅介质层的材料包括高K介质材料。
所述第一栅极层、所述第二栅极层和所述第三栅极层的材料包括金属，所述金属包括：钨、铝、铜、钛、银、金、铅或者镍。本实施例中，所述第一栅极层、所述第二栅极层和所述第三栅极层的材料采用钨。
参考图18和图19，图18是半导体结构省略隔离层、第一介质层、第二介质层的俯视图，图19是图18沿C3-C3方向的剖面结构示意图，在所述第一介质层209、所述第一栅极结构211、第二栅极结构212以及所述第三栅极结构213上形成第二介质层216。
本实施例中，所述第二介质层216的材料采用氧化硅；在其他实施例中，所述第二介质层的材料还可以为低K介质材料(低K介质材料指相对介电常数低于3.9的介质材料)或超低K介质材料(超低K介质材料指相对介电常数低于2.5的介质材料)。
本实施例中，形成所述第二介质层216后，在所述第二介质层216内形成多个相互分立的接触孔(未标示)，所述接触孔底部分别暴露出各所述第一栅极结构211的第二部分215的顶部表面；在各所述接触孔内形成插塞217。
本实施例中，所述插塞217的数量与所述第一栅极结构211的数量相同，每个所述插塞217分别与所述第一栅极结构211的第二部分215连接。
本实施例中，所述第一栅极结构211的顶部表面与所述第一介质层209的顶部表面齐平，所述插塞217的底部表面与所述第一介质层209的顶部表面齐平。
在其他实施例中，参考图20，图20和图19的剖切方向一致， 所述第一栅极结构211顶部表面低于所述第一介质层209的顶部表面，所述第一栅极结构211顶部表面还具有覆盖层，所述覆盖层的顶部表面与所述第一介质层的顶部表面齐平，部分所述插塞217还位于所述第一介质层209内。
在该实施例中，在形成所述接触孔之前，还包括：回刻蚀部分所述第一栅极结构211，至所述第一栅极结构211的顶部表面低于所述第一介质层209的顶部表面。
在另一实施例中，参考图21，图21和图19的剖切方向一致，也可以在所述第二介质层216内形成一个接触孔(未标示)，所述接触孔底部暴露出相邻的多个第一栅极结构211的第二部分215的顶部表面以及第一栅极结构211之间的第一介质层209的顶部表面；在所述接触孔内形成插塞218。
在这一实施例中，所述插塞218的数量为一个，与多个第一栅极结构211的第二部分215同时电连接。
在这一实施例中，所述插塞218的底部表面与所述第一介质层209的顶部表面齐平。
在另一实施例中，参考图22，图22和图21的剖切方向一致，所述插塞218的底部表面也可以低于所述第一介质层209的顶部表面；在形成所述接触孔之前，回刻蚀所述第一栅极结构211，至所述第一栅极结构211的顶部表面低于所述第一介质层209的顶部表面。
继续参考图18，本实施例中，还包括：在第一有源区A1上的第一鳍部201两侧的第一源漏掺杂层207上形成源漏插塞220。
参考图23至图25，图23是半导体结构的俯视图，图24是图23沿C4-C4方向的剖面结构示意图，图25是半导体结构的简化立体结构图，形成所述插塞217后，在所述插塞217上形成上互连层219，所述插塞217和所述互连层219构成第一电互连结构，所述第一电互连结构与所述第一栅极结构211的第二部分215电连接。
本实施例中，还包括：在所述第一源漏掺杂层207上形成第一导电层(未图示)；在所述第二源漏掺杂层208上形成第二导电层(未图示)。
本实施例中，所述源漏插塞220也与所述互连层219构成互连结构。
参考图25，图25为半导体结构的简易电路图，当第一区I为PMOS区时，所述互连层219为Vdd，所述源漏插塞220与所述Vdd连接，所述插塞217与所述Vdd连接。
当第一区I为NMOS区时，所述互连层219为Vss，所述源漏插塞220与所述Vss连接，所述插塞217与所述Vss连接。
图26至图31是本发明另一实施例中半导体结构形成过程的结构示意图。
参考图26和图27，图26是半导体结构的俯视图，图27是图26沿C5-C5方向的剖面结构示意图，在这一实施例中，所述衬底200的第二区Ⅱ包括沿所述第一方向X排布的多个第二有源区A2和位于相邻所述第二有源区A2之间的第二隔离区B2。
在所述第二区Ⅱ形成若干第三鳍部301，所述第三鳍部301与所述第一方向X平行且沿第二方向Y排列，所述第三鳍部301横跨所述第二有源区A2和所述第二隔离区B2。
所述第三鳍部301的形成方法和材料与第一鳍部201的形成方法和材料相同，在此不再赘述。
所述隔离层203同样覆盖所述第三鳍部301的部分侧壁表面。
参考图28和图29，图28是半导体结构的俯视图，图29和图28的剖视方向一致，在所述第二隔离区B2形成多个第四栅极结构302，所述第四栅极结构302横跨所述第三鳍部301，且所述第四栅极结构302与所述第一栅极结构211在第二方向Y上彼此间隔开；在所述第二有源区A2上形成若干第五栅极结构303，所述第五栅极结构303 横跨所述第二有源区A2上的第三鳍部301，且所述第五栅极结构303与所述第二栅极结构212连接。
所述第四栅极结构302包括位于所述第三鳍部301表面的第三部分304以及位于所述隔离层203表面的第四部分305。
在这一实施例中，所述第四栅极结构302与第五栅极结构303的形成方法及材料与形成第一栅极结构211、第三栅极结构213相同，在此不再赘述。
在形成所述第四栅极结构302和所述第五栅极结构303之前，还包括：在第四栅极结构和第五栅极结构两侧的所述第三鳍部内形成第三源漏掺杂层306，所述第三源漏掺杂层306内具有第三源漏离子。
所述第三源漏离子与所述第一源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第三源漏离子包括P型离子或N型离子。
参考图30和图31，图29是半导体结构的俯视图，图31是图30沿C6-C6方向的剖面结构示意图，在所述第一介质层209上形成第二介质层216；在所述第二介质层216内形成第二电互连结构307，所述第二电互连结构307与所述第四栅极结构302的第四部分305电连接。
本实施例中，所述第二电互连结构307的形成方法与结构与第一电互连结构的形成方法与结构相同，在此不再赘述。
本实施例中，还包括：在第三源漏掺杂层306上形成第三导电层(未图示)。
结合参考图23、图24和图32，图32为半导体结构的简易结构示意图，相应的，本发明还提供了一种半导体结构，包括：衬底200，所述衬底200包括第一区Ⅰ，所述第一区Ⅰ包括沿第一方向X排布的多个第一有源区A1以及位于相邻所述第一有源区A1之间的第一隔离区B1；位于所述衬底200上的若干第一鳍部201，若干所述第一 鳍部201与第一方向X平行且沿第二方向Y排列，所述第二方向Y与所述第一方向X垂直，所述第一鳍部201横跨相邻所述第一有源区A1以及所述第一有源区A1之间的第一隔离区B1；位于所述第一隔离区B1上的多个第一栅极结构211，所述第一栅极结构211沿所述第二方向Y横跨所述第一鳍部201；若干第一电互连结构，所述第一电互连结构与所述第一栅极结构211电连接。
本实施例中，还包括：位于所述衬底200上的隔离层203，所述隔离层203覆盖所述第一鳍部201的部分侧壁，且所述隔离层203的顶部表面低于所述第一鳍部201的顶部表面；第一栅极结构211包括位于所述第一鳍部201表面的第一部分214以及位于所述隔离层203表面的第二部分215；所述第一电互连结构与所述第二部分215电连接。
本实施例中，还包括：位于所述第一有源区A1上的第二栅极结构212，所述第二栅极结构212沿所述第二方向Y横跨所述第一鳍部201。
本实施例中，还包括：位于所述衬底200上的第一介质层209，所述第一介质层209覆盖所述第一栅极结构211的侧壁。
本实施例中，所述第一电互连结构包括若干分别位于所述第一栅极结构211的第二部分215顶部表面的插塞217以及位于若干所述插塞217上的互连层219，若干所述插塞217相互分立。
本实施例中，所述第一栅极结构211的顶部表面与所述第一介质层209的顶部表面齐平。
参考图20，在另一实施例中，所述第一栅极结构211的顶部表面低于所述第一介质层209的顶部表面，部分所述插塞217还位于所述第一介质层209内。
本实施例中，还包括：位于所述第一介质层209上的第二介质层216，所述第一电互连结构位于所述第二介质层216内。
参考图21，在另一实施例中，所述第一电互连结构包括位于相邻所述第一栅极结构211顶部表面的插塞218以及位于所述插塞218 上的互连层219，所述插塞218还位于相邻所述第一栅极结构211之间的第一介质层209表面。
在这一实施例中，所述第一栅极结构211的顶部表面与所述第一介质层209的顶部表面齐平。
参考图22，在另一实施例中，所述第一栅极结构211的顶部表面低于所述第一介质层209的顶部表面，部分所述插塞218还位于所述第一介质层209内。
本实施例中，所述衬底200还包括第二区Ⅱ。
本实施例中，所述第二区Ⅱ不包括隔离区；在另一实施例中，所述第二区Ⅱ还包括沿第一方向X排布的多个第二有源区以及位于相邻所述第二有源区之间的第二隔离区。
本实施例中，还包括：位于所述第二区Ⅱ上的若干第二鳍部202，所述第二鳍部202与所述第一方向X平行且沿第二方向Y排列；位于所述第二区Ⅱ上的多个第三栅极结构213，所述第三栅极结构213横跨所述第二鳍部202，且部分所述第三栅极结构213与所述第二栅极结构212连接。
部分所述第三栅极结构213与所述第一栅极结构211之间具有栅极隔离结构210，所述栅极隔离结构210位于所述第一区Ⅰ和所述第二区Ⅱ之间的所述隔离层203上。
本实施例中，还包括：位于所述各所述第一栅极结构211两侧以及所述第二栅极结构212两侧的所述第一鳍部201内的第一源漏掺杂层207，且所述第一源漏掺杂层207内具有第一源漏离子；位于各所述第三栅极结构213两侧的所述第二鳍部202内的第二源漏掺杂层208，所述第二源漏掺杂层208内具有第二源漏离子。
本实施例中，所述第一源漏离子与所述第二源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第二源漏离子包括P型离子或N型离子。
本实施例中，还包括：位于所述第一源漏掺杂层207上的第一导电层(未图示)以及位于所述第二源漏掺杂层208上的第二导电层(未 图示)。
在另一实施例中，参考图29和图30，所述第二区Ⅱ包括沿第一方向X排布的多个第二有源区A2以及位于相邻所述第二有源区A2之间的第二隔离区B2。
所述第二区Ⅱ上形成有若干第三鳍部301，若干所述第三鳍部301与所述第一方向X平行且沿第二方向Y排列，所述第三鳍部301横跨相邻所述第二有源区A2以及所述第二有源区A2之间的第二隔离区B2；位于所述第二隔离区B2上的多个第四栅极结构302，所述第四栅极结构302沿所述第二方向Y横跨所述第三鳍部301，且所述第四栅极结构302与所述第一栅极结构211在第二方向Y上彼此间隔开；若干第二电互连结构307，所述第二电互连结构307与所述第四栅极结构302电连接。
在这一实施例中，所述第二电互连结构的结构与第一电互连结构相同，在此不再赘述。
在这一实施例中，所述第四栅极结构302包括位于所述第三鳍部301表面的第三部分304以及位于所述隔离层203表面的第四部分305，所述第二电互连结构与所述第四部分305电连接。
在这一实施例中，还包括：位于所述第二有源区A2上的第五栅极结构303，所述第五栅极结构303沿所述第二方向Y横跨所述第三鳍部301，且所述第五栅极结构303与所述第二栅极结构212连接。
在这一实施例中，还包括：位于各所述第四栅极结构302两侧以及所述第五栅极结构303两侧的所述第三鳍部内的第三源漏掺杂层306，所述第三源漏掺杂层306内具有第三源漏离子。
所述第一源漏离子与所述第三源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第三源漏离子包括P型离子或N型离子。
在这一实施例中，还包括：位于所述第三源漏掺杂层306上的第 三导电层(未图示)。
本发明还提供了一种半导体结构的工作方法，包括：提供一半导体结构，所述半导体结构包括：衬底200，所述衬底200包括第一区Ⅰ，所述第一区Ⅰ包括沿第一方向X排布的多个第一有源区A1以及位于相邻所述第一有源区A1之间的第一隔离区B1；位于所述衬底200上的若干第一鳍部201，若干所述第一鳍部201与第一方向X平行且沿第二方向Y排列，所述第二方向Y与所述第一方向X垂直，所述第一鳍部201横跨相邻所述第一有源区A1以及所述第一有源区A1之间的第一隔离区B1；位于所述第一隔离区B1上的多个第一栅极结构211，所述第一栅极结构211沿所述第二方向Y横跨所述第一鳍部201；若干第一电互连结构，所述第一电互连结构与所述第一栅极结构211电连接；所述工作方法包括：对所述第一电互连结构施加电压，使所述第一栅极结构211底部的沟道区关断。
所述半导体结构还包括：位于各所述第一栅极结构211两侧的所述第一鳍部201内的第一源漏掺杂层207，且所述第一源漏掺杂层207内具有第一源漏离子；所述工作方法还包括：当所述第一源漏离子为N型离子时，对所述第一电互连结构施加负压；当所述第一源漏离子为P型离子，对所述第一电互连结构施加正压。
通过对第一电互连结构施加电压对第一栅极结构211提供关断信号，使第一栅极结构211底部的沟道区处于关断状态，以使得第一栅极结构211失效，从而实现第一隔离区B1两侧的第一有源区A1的电隔离，一方面，不需要去除第一栅极结构211以形成隔离结构，可以提高半导体结构的集成度；另一方面，第一鳍部201不需要在第一隔离区B1进行切断，从而可以避免第一鳍部201的切断结构造成的布局效应依赖，有利于提高半导体结构的性能。
在另一实施例中，所述半导体结构还包括：第二区Ⅱ，所述第二区Ⅱ包括沿第一方向X排布的多个第二有源区A2以及位于相邻所述第二有源区A2之间的第二隔离区B2；若干第三鳍部301，若干所述 第三鳍部301与所述第一方向X平行且沿第二方向Y排列，所述第三鳍部301横跨相邻所述第二有源区A2以及所述第二有源区A2之间的第二隔离区B2；位于所述第二隔离区B2上的多个第四栅极结构302，所述第四栅极结构302沿所述第二方向Y横跨所述第三鳍部301，且所述第四栅极结构302与所述第一栅极结构211在第二方向Y上彼此间隔开；若干第二电互连结构307，所述第二电互连结构307与所述第四栅极结构302电连接；所述工作方法还包括：对所述第二电互连结构307施加电压，使所述第四栅极结构302底部的沟道区关断。
所述半导体结构还包括：位于各所述第四栅极结构302两侧以及所述第五栅极结构303两侧的所述第三鳍部内的第三源漏掺杂层306，所述第三源漏掺杂层306内具有第三源漏离子，所述第三源漏离子与所述第一源漏离子的导电类型相反；所述工作方法包括：当所述第三源漏离子为N型离子时，对所述第二电互连结构施加负压；当所述第三源漏离子为P型离子，对所述第二电互连结构施加正压。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (28)

  1. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；
    位于所述衬底上的若干第一鳍部，若干所述第一鳍部与第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；
    位于所述第一隔离区上的多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；
    若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接。
  2. 如权利要求1所述的半导体结构，其特征在于，还包括：位于所述衬底上的隔离层，所述隔离层覆盖所述第一鳍部的部分侧壁，且所述隔离层的顶部表面低于所述第一鳍部的顶部表面；第一栅极结构包括位于所述第一鳍部表面的第一部分以及位于所述隔离层表面的第二部分；所述第一电互连结构与所述第二部分电连接。
  3. 如权利要求1所述的半导体结构，其特征在于，还包括：位于所述衬底上的第一介质层，所述第一介质层覆盖所述第一栅极结构的侧壁。
  4. 如权利要求3所述的半导体结构，其特征在于，所述第一电互连结构包括若干分别位于所述第一栅极结构顶部表面的插塞以及位于若干所述插塞上的互连层，若干所述插塞相互分立。
  5. 如权利要求4所述的半导体结构，其特征在于，所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面，部分所述插塞还位于所述第一介质层内。
  6. 如权利要求3所述的半导体结构，其特征在于，所述第一电互连结构包括位于相邻所述第一栅极结构顶部表面的插塞以及位于所述插塞上的互连层，所述插塞还位于相邻所述第一栅极结构之间的第 一介质层表面。
  7. 如权利要求6所述的半导体结构，其特征在于，所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面，部分所述插塞还位于所述第一介质层内。
  8. 如权利要求1所述的半导体结构，其特征在于，还包括：位于所述第一有源区上的第二栅极结构，所述第二栅极结构沿所述第二方向横跨所述第一鳍部。
  9. 如权利要求8所述的半导体结构，其特征在于，所述衬底还包括第二区；位于所述第二区上的若干第二鳍部，若干所述第二鳍部与所述第一方向平行且沿所述第二方向排列；位于所述第二区上的多个第三栅极结构，所述第三栅极结构横跨所述第二鳍部，且部分所述第三栅极结构与所述第二栅极结构连接。
  10. 如权利要求8所述的半导体结构，其特征在于，所述衬底还包括第二区，所述第二区包括沿所述第一方向排布的多个第二有源区以及位于相邻所述第二有源区之间的第二隔离区；位于所述第二区上的若干第三鳍部，若干所述第三鳍部与所述第一方向平行且沿第二方向排列，所述第三鳍部横跨相邻所述第二有源区以及所述第二有源区之间的第二隔离区；位于所述第二隔离区上的多个第四栅极结构，所述第四栅极结构沿所述第二方向横跨所述第三鳍部，且所述第四栅极结构与所述第一栅极结构在第二方向上彼此间隔开；若干第二电互连结构，所述第二电互连结构与所述第四栅极结构电连接。
  11. 如权利要求10所述的半导体结构，其特征在于，还包括：位于所述第二有源区上的第五栅极结构，所述第五栅极结构沿所述第二方向横跨所述第三鳍部，且所述第五栅极结构与所述第二栅极结构连接。
  12. 如权利要求9所述的半导体结构，其特征在于，还包括：位于各所述第一栅极结构两侧以及所述第二栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；位于各所述第三栅极结构两侧的所述第二鳍部内的第二源漏掺 杂层，所述第二源漏掺杂层内具有第二源漏离子。
  13. 如权利要求12所述的半导体结构，其特征在于，所述第一源漏离子与所述第二源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第二源漏离子包括P型离子或N型离子。
  14. 如权利要求13所述的半导体结构，其特征在于，还包括：位于所述第一源漏掺杂层上的第一导电层以及位于所述第二源漏掺杂层上的第二导电层。
  15. 如权利要求11所述的半导体结构，其特征在于，还包括：位于各所述第一栅极结构两侧以及所述第二栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；位于各所述第四栅极结构两侧以及所述第五栅极结构两侧的所述第三鳍部内的第三源漏掺杂层，所述第三源漏掺杂层内具有第三源漏离子。
  16. 如权利要求15所述的半导体结构，其特征在于，所述第一源漏离子与所述第三源漏离子的导电类型不同；所述第一源漏离子包括N型离子或P型离子；所述第三源漏离子包括P型离子或N型离子。
  17. 如权利要求16所述的半导体结构，其特征在于，还包括：位于所述第一源漏掺杂层上的第一导电层以及位于所述第三源漏掺杂层上的第三导电层。
  18. 一种半导体结构的形成方法，其特征在于，包括：
    提供衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；
    在所述第一区上形成若干第一鳍部，所述第一鳍部与所述第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；
    在所述第一隔离区上形成多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；
    在所述第一栅极结构上形成若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接。
  19. 如权利要求18所述的半导体结构的形成方法，其特征在于，在形成所述第一鳍部之后，还包括：在所述衬底上形成隔离层，所述隔离层覆盖所述第一鳍部的部分侧壁，且所述隔离层的顶部表面低于所述第一鳍部的顶部表面。
  20. 如权利要求18所述的半导体结构的形成方法，其特征在于，在形成所述第一鳍部之后且形成第一栅极结构之前，还包括：在所述第一隔离区形成多个第一伪栅极结构，所述第一伪栅极结构横跨所述第一鳍部；在所述衬底上形成第一介质层，所述第一介质层覆盖所述第一伪栅极结构的侧壁且暴露出所述第一伪栅极结构的顶部表面。
  21. 如权利要求20所述的半导体结构的形成方法，其特征在于，所述第一栅极结构的形成方法包括：去除所述第一伪栅极结构，在所述第一介质层内形成第一栅极开口；在所述第一栅极开口内形成所述第一栅极结构。
  22. 如权利要求21所述的半导体结构的形成方法，其特征在于，在形成所述第一栅极结构之后，还包括：在所述第一介质层以及所述第一栅极结构上形成第二介质层，所述第一电互连结构位于所述第二介质层内。
  23. 如权利要求22所述的半导体结构的形成方法，其特征在于，所述第一电互连结构的形成方法包括：在所述第二介质层内形成多个相互分立的接触孔，所述接触孔底部分别暴露出各所述第一栅极结构的顶部表面；在所述接触孔内形成插塞；在所述插塞上形成互连层。
  24. 如权利要求23所述的半导体结构的形成方法，其特征在于，在形成所述接触孔之前，还包括：回刻蚀部分所述第一栅极结构， 至所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面。
  25. 如权利要求22所述的半导体结构的形成方法，其特征在于，所述第一电互连结构的形成方法包括：在所述第二介质层内形成接触孔，所述接触孔底部暴露出相邻的多个所述第一栅极结构以及第一栅极结构之间的第一介质层的顶部表面；在所述接触孔内形成插塞；在所述插塞上形成互连层。
  26. 如权利要求25所述的半导体结构的形成方法，其特征在于，在形成所述接触孔之前，还包括：回刻蚀部分所述第一栅极结构，至所述第一栅极结构的顶部表面低于所述第一介质层的顶部表面。
  27. 一种半导体结构的工作方法，其特征在于，包括：
    提供半导体结构，所述半导体结构包括：
    衬底，所述衬底包括第一区，所述第一区包括沿第一方向排布的多个第一有源区以及位于相邻所述第一有源区之间的第一隔离区；
    位于所述衬底上的若干第一鳍部，若干所述第一鳍部与第一方向平行且沿第二方向排列，所述第二方向与所述第一方向垂直，所述第一鳍部横跨相邻所述第一有源区以及所述第一有源区之间的第一隔离区；
    位于所述第一隔离区上的多个第一栅极结构，所述第一栅极结构沿所述第二方向横跨所述第一鳍部；
    若干第一电互连结构，所述第一电互连结构与所述第一栅极结构电连接；
    所述工作方法包括：对所述第一电互连结构施加电压，使所述第一栅极结构底部的沟道区关断。
  28. 如权利要求27所述的半导体结构的工作方法，其特征在于，所述半导体结构还包括：位于各所述第一栅极结构两侧的所述第一鳍部内的第一源漏掺杂层，且所述第一源漏掺杂层内具有第一源漏离子；所述工作方法还包括：当所述第一源漏离子为N型离子时，对所述第一电互连结构施加负压；当所述第一源漏离子为P型离子，对所述第一电互连结构施加正压。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823562A (zh) * 2020-06-18 2021-12-21 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070278576A1 (en) * 2006-05-13 2007-12-06 Samsung Electronics Co., Ltd. Fin field effect transistor and method for forming the same
CN102768957A (zh) * 2011-05-06 2012-11-07 中国科学院微电子研究所 鳍式场效应晶体管及其制造方法
CN103199010A (zh) * 2012-01-09 2013-07-10 台湾积体电路制造股份有限公司 FinFET及其形成方法
CN103219380A (zh) * 2012-01-24 2013-07-24 台湾积体电路制造股份有限公司 鳍式场效应晶体管及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070278576A1 (en) * 2006-05-13 2007-12-06 Samsung Electronics Co., Ltd. Fin field effect transistor and method for forming the same
CN102768957A (zh) * 2011-05-06 2012-11-07 中国科学院微电子研究所 鳍式场效应晶体管及其制造方法
CN103199010A (zh) * 2012-01-09 2013-07-10 台湾积体电路制造股份有限公司 FinFET及其形成方法
CN103219380A (zh) * 2012-01-24 2013-07-24 台湾积体电路制造股份有限公司 鳍式场效应晶体管及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823562A (zh) * 2020-06-18 2021-12-21 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

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