WO2020186450A1 - 薄膜晶体管及其制造方法、显示面板、显示装置 - Google Patents

薄膜晶体管及其制造方法、显示面板、显示装置 Download PDF

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Publication number
WO2020186450A1
WO2020186450A1 PCT/CN2019/078677 CN2019078677W WO2020186450A1 WO 2020186450 A1 WO2020186450 A1 WO 2020186450A1 CN 2019078677 W CN2019078677 W CN 2019078677W WO 2020186450 A1 WO2020186450 A1 WO 2020186450A1
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Prior art keywords
layer
shielding layer
semiconductor layer
region
drain
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English (en)
French (fr)
Inventor
邹灿
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2019/078677 priority Critical patent/WO2020186450A1/zh
Priority to CN201980073008.1A priority patent/CN113261113A/zh
Publication of WO2020186450A1 publication Critical patent/WO2020186450A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

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  • the embodiments of the present application relate to the field of display technology, and in particular to a thin film transistor, a method for manufacturing the thin film transistor, and a display panel and a display device using the thin film transistor.
  • Thin film transistors are a very important semiconductor device in active matrix display devices.
  • the active layer can be made of transparent oxide semiconductor materials represented by indium gallium zinc oxide. Such transparent oxide semiconductor materials have high mobility, The advantages of good uniformity and transparency can greatly improve the display effect of the active matrix display device.
  • the structures of thin film transistors that have been widely studied at present can generally be divided into two categories: bottom-gate structures and top-gate structures.
  • the embodiments of the present application aim to provide a thin film transistor, a manufacturing method thereof, a display panel, and a display device, so as to solve the technical problem of too many process masks for thin film transistors in the prior art.
  • a method for manufacturing a thin film transistor including:
  • one end of the semiconductor layer has a connecting part, and the connecting part is connected with the exposed part of the light shielding layer;
  • the light-shielding layer, the shielding layer, and the semiconductor layer are simultaneously patterned, so that on one side of the light-shielding layer, the end surface of the connecting portion is flush with the end surface of the exposed portion of the light-shielding layer, On the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer and the end surface of the semiconductor layer are flush with each other;
  • a source electrode and a drain electrode are provided, and the source electrode and the drain electrode are respectively electrically connected to the semiconductor layer.
  • the simultaneous patterning of the light shielding layer, the shielding layer and the semiconductor layer includes:
  • the areas on both sides of the buffer layer are exposed, and the exposed areas on both sides of the buffer layer are flexible areas.
  • the method further includes:
  • the insulating layer and the gate are processed at the same time to expose the areas on both sides of the semiconductor layer, and the portion of the gate and the semiconductor layer directly opposite is defined as the channel region.
  • the side exposed regions are respectively defined as the source region and the drain region.
  • the method further includes:
  • the performing surface treatment on the drain region and the source region includes:
  • the surface of the source region and the drain region are simultaneously activated.
  • the method further includes:
  • An interlayer insulating layer is formed on the gate, the source region, the drain region, and the flexible region.
  • the method further includes:
  • the source electrode and the drain electrode are respectively formed at the first groove and the second groove, the source electrode is electrically connected to the source region through the first groove, and the The drain is electrically connected to the drain region through the second groove.
  • the method further includes:
  • the source is electrically connected to the source region through the first via hole
  • the drain is electrically connected to the drain region through the second via hole.
  • a thin film transistor comprising: a substrate, a light shielding layer, a shielding layer, a semiconductor layer, an insulating layer, a gate, a source and a drain;
  • the light-shielding layer and the shielding layer are sequentially laminated on the substrate, and the light-shielding layer is partially exposed;
  • the semiconductor layer is laminated on the shielding layer and the exposed part of the light-shielding layer, one end of the semiconductor layer has a connecting part, and the connecting part is connected with the exposed part of the light-shielding layer; On one side, the end surface of the connecting portion is flush with the end surface of the exposed part of the light shielding layer, and on the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer, and the semiconductor layer The ends are flush with each other;
  • the source electrode and the drain electrode are respectively electrically connected to the semiconductor layer.
  • regions on both sides of the buffer layer are not shielded by the light shielding layer and the shielding layer, and regions of the buffer layer not shielded by the light shielding layer and the shielding layer are flexible regions.
  • regions on both sides of the semiconductor layer are not shielded by the insulating layer and the gate, and the portion directly opposite to the gate and the semiconductor layer is a channel region.
  • the side exposed areas are the source area and the drain area respectively.
  • both the source region and the drain region undergo surface activation treatment.
  • the thin film transistor further includes an interlayer insulating layer formed on the gate, the drain region, the source region, and the flexible region.
  • a first groove and a second groove corresponding to the source region and the drain region are respectively opened on the interlayer insulating layer;
  • the source electrode and the drain electrode are laminated at the first groove and the second groove respectively, and the source electrode is electrically connected to the source region through the first groove, and the drain The electrode is electrically connected to the drain region through the second groove.
  • first via hole and a second via hole respectively corresponding to the source region and the drain region on the interlayer insulating layer
  • the source is electrically connected to the source region through the first via hole
  • the drain is electrically connected to the drain region through the second via hole.
  • a display panel includes a substrate and a transparent thin film layer, a buffer layer, a switch array layer, and an organic light emitting display layer sequentially stacked on the substrate, and the switch array layer includes the thin film transistor described above.
  • a display device includes the above-mentioned display panel.
  • the connecting portion is connected to the exposed portion of the light shielding layer, and the end surface of the connecting portion is connected to the The end surface of the exposed part of the light shielding layer is flush.
  • the end surface of the light shielding layer, the end surface of the shielding layer and the end surface of the semiconductor layer are flush with each other; the light shielding can be realized
  • the layer and the semiconductor layer are simultaneously masked, and the light shielding layer and the semiconductor layer are not required to be masked separately. Therefore, in the process of preparing the thin film transistor, the number of masks is reduced, the production cost is reduced, and the productivity is reduced. Promote.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by one of the embodiments of the present application.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by one of the embodiments of the present application;
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor provided by another embodiment of the present application.
  • 4a to 4i are schematic diagrams of the manufacturing method of the thin film transistor shown in FIG. 3 at different stages;
  • FIG. 5 is a schematic structural diagram of a display panel provided by another embodiment of the application.
  • the thin film transistor 10 provided by one embodiment of the present application includes a substrate 11, a flexible substrate 12, a buffer layer 13, a light shielding layer 14, a shielding layer 15, a semiconductor layer 16, an insulating layer 17, a gate electrode 18, and an interlayer The insulating layer 19, the drain electrode 20 and the source electrode 21.
  • the base 11 serves as a substrate for carrying the thin film transistor 10, and a flexible substrate 12, a buffer layer 13, a light shielding layer 14 and a shielding layer 15 are sequentially formed on the base 11.
  • the light shielding layer 14 and the shielding layer 15 are formed in the middle of the buffer layer 13, that is, the areas on both sides of the buffer layer 13 are not shielded by the light shielding layer 14 and the shielding layer 15. 13
  • the area not blocked by the light-shielding layer 14 and the shielding layer 15 is the flexible area 142.
  • the setting of the flexible area 142 releases the thin film at the shielding layer of the current thin film transistor. The stress increases the flexibility of the thin film transistor 10.
  • One side area of the light shielding layer 14 is partially exposed, that is, it is not shielded by the shielding layer 15.
  • a semiconductor layer 16 is formed on the side of the shielding layer 15 away from the buffer layer 13, and the semiconductor layer 16 also covers an area of the light shielding layer 14 that is not shielded by the shielding layer 15. It can be understood that the semiconductor layer 16 has a connecting portion 168, and the connecting portion 168 is connected to the exposed portion of the light shielding layer 14. The semiconductor layer 16 is connected to the light shielding layer 14 through the connecting portion 168.
  • the connecting portion 168 and the exposed portion of the light shielding layer 14 are connected and aligned with each other, that is, the end surface of the connecting portion 168 is aligned with the end surface of the exposed portion of the light shielding layer 14
  • the shielding layer 15 and the semiconductor layer 16 are aligned with each other, that is, the light shielding layer 14, the shielding layer 15 and the The end faces of the semiconductor layer 16 are flush with each other, so the light-shielding layer 14, the shielding layer 15 and the semiconductor layer 16 together form a self-aligned structure, and the self-aligned structure can realize the shielding layer 14
  • the photomask is performed at the same time as the semiconductor layer 16, and the light shielding layer 14 and the semiconductor layer 16 do not need to be separately photomasked.
  • the number of photomasks is reduced and the production cost is reduced. Reduce, increase production capacity.
  • the number of etching processes is reduced, the damage caused by the excessive etching of the thin film transistor 10 is avoided, and the electrical performance of the thin film transistor 10 is improved.
  • An insulating layer 17 and a gate 18 are sequentially formed on the semiconductor layer 16, and regions on both sides of the semiconductor layer 16 are not covered by the insulating layer 17 and the gate 18, and the gate 18 and The portion facing the semiconductor layer 16 is defined as a channel region 164, and the exposed regions on both sides of the semiconductor layer 16 are defined as a source region 162 and a drain region 166, respectively.
  • the insulating layer 17 is located between the gate 18 and the channel region 164 of the semiconductor layer 16 so as to insulate the gate 18 and the channel region 164 from each other.
  • a source 21 and a drain 20 are formed on the source region 162 and the drain region 166 of the semiconductor layer 16 respectively.
  • the drain 20 is electrically connected to the drain region 166
  • the source 21 is electrically connected to the source region 162.
  • the interlayer insulating layer 19 is formed on the gate 18, the drain region 166, the source region 162, the connection portion 168 and the flexible region 142.
  • the interlayer insulating layer 19 is provided with a first groove 192 located above the source region 162, and the source electrode 21 is electrically connected to the source region 162 through the first groove 192;
  • the interlayer insulating layer 19 defines a second groove 194 above the drain region 166, and the drain electrode 20 is electrically connected to the drain region 166 through the second groove 194.
  • the self-aligned structure formed by the light-shielding layer 14, the shielding layer 15 and the semiconductor layer 16 of the thin film transistor 10 can realize the contrast between the light-shielding layer 14 and the semiconductor layer 16
  • the photomask is performed at the same time, and the light shielding layer 14 and the semiconductor layer 16 do not need to be separately photomasked. Therefore, in the process of preparing the thin film transistor 10, the number of photomasks is reduced, the production cost is reduced, and the productivity is increased.
  • the above-mentioned thin film transistor 10 connects the semiconductor layer 16 and the light shielding layer 14 by providing a connecting portion 168, so that the voltage at the source 21 is equal to the voltage on the light shielding layer 14, thereby shielding the flexible substrate 12 and The accumulated charge between the buffer layers 13 improves the electrical performance of the thin film transistor 10.
  • the substrate 11 is made of transparent materials such as glass, and is cleaned in advance.
  • the substrate 11 due to the relatively high content of metal impurities such as aluminum, barium, and sodium in the traditional alkali glass, the diffusion of metal impurities is likely to occur during the high-temperature treatment process, so the substrate 11 can also be made of alkali-free glass.
  • the base 11 can also be made of flexible materials.
  • the flexible substrate 12 is a substrate for supporting and protecting various elements that can be formed thereon, and when necessary, the flexible substrate 12 can be peeled from the base 11.
  • the flexible substrate 12 may be formed of various materials.
  • the flexible substrate 12 may be formed of a flexible insulating material.
  • flexible insulating materials may include polyimide (PI), polyetherimide (PEI), polyethylene terephthalate (PES), polycarbonate (PC), polystyrene (PS) , Styrene-acrylonitrile copolymer, and silicone acrylic resin.
  • the flexible substrate 12 may be formed of a flexible transparent insulating material.
  • the buffer layer 13 is used to prevent the impurities contained in the flexible substrate 12 from diffusing into the semiconductor layer 16 of the field effect transistor, so as to prevent the device performance of the field effect transistor from being affected. At the same time, the buffer layer 13 can enhance the adhesion between the light-shielding layer 14 and the flexible substrate 12, increase the contact firmness of the light-shielding layer 14 and the flexible substrate 12, thereby avoiding the light-shielding layer 14 from falling off, and improving the stability of the field effect transistor. Sex. Wherein, the material of the buffer layer 13 is an insulating material, such as SiOx, SiNx or any combination of the two.
  • the material of the light-shielding layer 14 is a conductive light-shielding material, which may be a common opaque metal material, such as copper, aluminum, and the like.
  • the light shielding layer 14 is made of a low-reflective material, so as to prevent the metal on the side of the thin film transistor 10 (ie, the gate 18, the source 21, and the drain 20) from reflecting light under the action of an external light source and causing poor display.
  • the shielding layer 15 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as the reaction source gas, and a series of hydrogenated amorphous silicon nitride is deposited on the light shielding layer 14 by an enhanced chemical vapor deposition (PECVD) method.
  • PECVD enhanced chemical vapor deposition
  • a-SiNx:H the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • the shielding layer 15 can prevent the phenomenon that the light shielding layer 14 is charged, thereby preventing the double-gate thin film transistor 10 (dual TFT) phenomenon.
  • the shielding layer 15 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the semiconductor layer 16 is formed by sputtering a high-mobility amorphous indium gallium zinc oxide (a-IGZO) target.
  • the amorphous indium gallium zinc oxide (a-IGZO) semiconductor has many excellent properties, a -IGZO semiconductor is superior to other amorphous semiconductors in performance.
  • the amorphous indium gallium zinc oxide thin film transistor 10 (a-IGZO-SFS) has been able to achieve a switching current ratio of ⁇ 10 10 , and the electron mobility of a-IGZO is between 2-50 cm 2 /Vs, which is a-Si 20-50 times that of the panel, and the wiring becomes thinner when it is prepared, which can achieve 4 times the resolution under the same transmittance.
  • the IGZO thin film transistor 10 has superior turn-off performance, and has the advantages of low leakage current and low power consumption.
  • the semiconductor layer 16 may be a variety of metal oxide semiconductors.
  • Quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO) based materials, such as indium gallium zinc oxide (InGaZnO) based materials, indium tin zinc oxide (InSnZnO) based materials, indium aluminum zinc oxide based Material (InAlZnO), material based on indium hafnium zinc oxide (InHfZnO), material based on tin gallium zinc oxide (SnGaZnO), material based on aluminum gallium zinc oxide (AlGaZnO), or based on tin aluminum zinc oxide (SnAlZnO) materials such as ternary metal oxides, and materials such as indium zinc oxide (InZnO)-based materials, tin-zinc oxide (SnZnO)-based materials, aluminum-zinc oxide (AlZnO)-based materials, zinc-magnesium-based materials Ox
  • the semiconductor layer 16 may also be amorphous silicon, polysilicon or organic material.
  • the insulating layer 17 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as reaction source gases, and a series of hydrogenated amorphous silicon nitride is deposited on the semiconductor layer 16 by an enhanced chemical vapor deposition (PECVD) method.
  • PECVD enhanced chemical vapor deposition
  • a-SiNx:H the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • the quality of the back interface of the active layer can be improved by adjusting the thickness of the insulating layer 17 to prevent the formation of leakage paths at the interface of the active layer.
  • the thickness of the insulating layer 17 is 100-400 nm. Because of its good interface characteristics, the prepared semiconductor device has a smaller leakage current, which improves the electrical performance of the device.
  • the insulating layer 17 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the material of the gate 18 can be selected from metals such as Al, Ti, Mo, Cu, Ni, ITO, a metal layer of a mixture, or a metal oxide.
  • the gate 18 may be a multilayer electrode.
  • the multilayer electrode includes a metal layer having Al, Ti, Mo, Cu, Ni, ITO, or a mixture thereof, and a transparent conductive oxide layer including a transparent conductive oxide material.
  • the transparent conductive oxide material may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ISZO), and the like.
  • the multilayer electrode may have a three-layer structure including a first transparent conductive oxide layer, a metal layer, and a second transparent conductive oxide layer.
  • the multilayer electrode may also have a two-layer structure including a transparent conductive oxide layer and a metal layer.
  • the interlayer insulating layer 19 can passivate the back channel of the semiconductor layer 16 and contribute to the improvement of the electrical characteristics of the thin film transistor 10.
  • the interlayer insulating layer 19 uses a silicon nitride insulating layer, which has excellent photoelectric properties, mechanical properties, and strong barriers to the diffusion of impurity particles and water vapor penetration.
  • the thinner silicon nitride gate insulating layer is not easy to block the diffusion phenomenon, and as the thickness of the interlayer insulating layer 19 increases, the concentration of contaminants at the interface of the semiconductor layer 16 decreases, but when the thickness exceeds a critical value, the contaminants The concentration will no longer decrease greatly and reach a minimum value, so the thickness of the interlayer insulating layer 19 is set to be 100-400 nm.
  • the interlayer insulating layer 19 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • one of the embodiments of the present application provides a method for manufacturing a thin film transistor 10. It should be noted that the above explanation of the embodiment of the thin film transistor 10 is also applicable to the method for manufacturing the thin film transistor 10 of this embodiment. In order to avoid redundancy, we will not expand it in detail here.
  • the manufacturing method of the thin film transistor 10 includes:
  • Step S21 forming the light shielding layer 14 and the shielding layer 15 on the substrate 11.
  • PECVD plasma-enhanced chemical vapor deposition
  • ECR-CVD electron cyclotron resonance chemical vapor deposition
  • the light shielding layer 14 is formed by a method or a sputtering method.
  • the shielding layer 15 is formed on the light-shielding layer 14.
  • the shielding layer 15 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as reaction source gases, and adopts an enhanced chemical vapor deposition (PECVD) method
  • PECVD enhanced chemical vapor deposition
  • a series of hydrogenated amorphous silicon nitride (a-SiNx:H) films are deposited on the light shielding layer 14.
  • the flexible substrate 12 and the buffer layer 13 need to be sequentially formed on the base 11 first.
  • a flexible substrate 12 is laminated on a base 11, and then on the flexible substrate 12, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor DeposiSion: PECVD in short), low pressure chemical vapor deposition Method (Low Pressure Chemical Vapor DeposiSion: LPCVD), atmospheric pressure chemical vapor deposition (ASmospheric Pressure Chemical Vapor DeposiSion: APCVD) or electronic cyclotron resonance chemical vapor deposition (ElecSron CycloSron Resonance Chemical Vapor DeposiSion: ECR-CVD)
  • the buffer layer 13 is formed by a method or a sputtering method.
  • the thickness range of the buffer layer 13 is The deposition temperature is less than or equal to 600°C.
  • the specific manufacturing method of the buffer layer 13 may be: putting copper or aluminum targets into a deposition chamber, depositing the buffer layer 13 on the flexible substrate 12 by sputtering or evaporation, and introducing nitrogen or oxygen during the deposition. According to the amount of raw materials added, the method can produce aluminum atoms with an atomic percentage of 0.05-30% of the total number of atoms in the copper alloy material, and a nitrogen or oxygen atomic percentage of 0.05--30% of the total number of atoms in the copper alloy material. 30%, the rest is copper alloy material.
  • non-copper and non-aluminum metal elements you can put the non-copper and non-aluminum metal together with copper and aluminum into the deposition chamber, and then deposit the buffer layer 13 on the flexible substrate 12 by sputtering or evaporation. In addition, nitrogen or oxygen is introduced during deposition.
  • the specific manufacturing method of the buffer layer 13 may also be: manufacturing nitrogen or oxygen, copper, and aluminum into a target in a set atomic ratio, and then depositing on the flexible substrate 12 to form the buffer layer 13.
  • nitrogen or oxygen, copper, aluminum and non-copper and non-aluminum metals can also be made into targets according to the set atomic ratio, and then deposited to form the buffer layer 13.
  • the buffer layer 13 may be a single-layer or multi-layer structure. When it is a multi-layer structure, the materials of each layer may be the same or different.
  • Step S22 Perform a patterning process on the shielding layer 15 so that the light shielding layer 14 is partially exposed.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of using photoresist, mask, exposure machine, etc., to form patterns including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present application.
  • a layer of photoresist is formed on the shielding layer 15, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and a photoresist reserved area
  • the non-reserved photoresist area is a side area of the shielding layer 15.
  • the side area of the shielding layer 15 where the photoresist is not reserved area is etched by an etching process, and the remaining photoresist is stripped to make The light shielding layer 14 is partially exposed.
  • Step S23 A semiconductor layer 16 is formed on the exposed portion of the shielding layer 15 and the light shielding layer 14. One end of the semiconductor layer 16 has a connecting portion 168, and the connecting portion 168 and the exposed portion of the light shielding layer 14 connection.
  • a semiconductor layer 16 is formed on the exposed portion of the shielding layer 15 and the light shielding layer 14 by a sputtering method.
  • the target material used for sputtering can be a variety of metal oxide semiconductors. Quaternary metal oxides such as materials based on indium tin gallium zinc oxide (InSnGaZnO), ternary metal oxides such as materials based on indium gallium zinc oxide (InGaZnO), and materials such as indium zinc oxide (InZnO) Binary metal oxides of materials, and unary metal oxides such as indium oxide (InO)-based materials, tin oxide (SnO)-based materials, or zinc oxide (ZnO)-based materials, and the like.
  • Step S24 simultaneously patterning the light-shielding layer 14, the shielding layer 15, and the semiconductor layer 16, so that on one side of the light-shielding layer 14, the connecting portion and the exposed part of the light-shielding layer Connected and the end surface of the connecting portion is flush with the end surface of the exposed part of the light shielding layer, on the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer and the semiconductor layer The end faces are flush with each other.
  • a layer of photoresist is coated on the semiconductor layer 16, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and photolithography
  • the photoresist reserved area where the photoresist non-reserved area is the area on both sides of the semiconductor layer 16, the light shielding layer 14, the shielding layer 15 and the photoresist non-reserved area are completely etched by an etching process In the regions on both sides of the semiconductor layer 16, the remaining photoresist is stripped to expose the regions on both sides of the buffer layer 13, and the exposed regions on both sides of the buffer layer 13 are flexible regions 142.
  • the connecting portion 168 and the exposed part of the light-shielding layer 14 are connected and aligned with each other, that is, the end face of the connecting part 168 and the end face of the exposed part of the light-shielding layer 14 Flush, on the other side of the light shielding layer 14, the light shielding layer 14, the shielding layer 15 and the semiconductor layer 16 are aligned with each other, that is, the light shielding layer 14, the shielding layer 15 and The end faces of the semiconductor layer 16 are flush with each other, and the light shielding layer 14, the shielding layer 15 and the semiconductor layer 16 together form a self-aligned structure.
  • Step S25 forming an insulating layer 17 and a gate 18 on the semiconductor layer 16 in sequence.
  • the insulating layer 17 can be made of oxide, nitride or oxynitride, and the insulating layer 17 can be a single-layer, double-layer or multilayer structure. Specifically, the insulating layer 17 may be SiNx, SiOx or Si(ON)x.
  • magnetron sputtering, thermal evaporation or other film forming methods are used to deposit a layer with a thickness of about ⁇ Grid 18.
  • Step S26 setting a source electrode and a drain electrode, the source electrode and the drain electrode are electrically connected to the semiconductor layer, respectively.
  • magnetron sputtering, thermal evaporation or other film forming methods are used to deposit a layer on the semiconductor layer with a thickness of about
  • the source and drain metal layer of the source and drain metal layer is coated with a layer of photoresist, and the photoresist is exposed and developed using a mask, so that the photoresist forms a photoresist non-retained area and a photoresist reserved area , wherein the photoresist reserved areas are on both sides of the semiconductor layer, and the photoresist unreserved areas are other areas; the source and drain metal films in the photoresist unreserved areas are completely etched by the etching process, and the remaining Photoresist is used to form the source 21 and the drain 20.
  • step S26 includes:
  • Step S261 patterning the insulating layer 17 and the gate 18 at the same time to expose areas on both sides of the semiconductor layer 16, and the insulating layer 17 and the gate 18 are located in the middle of the semiconductor layer 16.
  • the portion of the gate 18 directly opposite to the semiconductor layer 16 is defined as a channel region 164, and the exposed regions on both sides of the semiconductor layer 16 are defined as a source region 162 and a drain region 166, respectively.
  • a layer of photoresist is coated on the insulating layer 17 and the gate 18, and the photoresist is exposed and developed using a mask, so that the photoresist is formed into a photoresist
  • the unreserved area and the photoresist reserved area, where the unreserved photoresist area is the area on both sides of the insulating layer 17 and the gate 18, and the photoresist unreserved area is completely etched by an etching process
  • the regions on both sides of the insulating layer 17 and the gate 18 are stripped of the remaining photoresist, so that the regions on both sides of the semiconductor layer 16 are exposed.
  • Step S262 Perform surface treatment on the source region 162 and the drain region 166.
  • the surface of the source region 162 and the drain region 166 is activated by a plasma surface treatment instrument.
  • plasma cleaning usually includes the following processes: inorganic gas is excited into a plasma state; gas phase substances are adsorbed on the solid surface; adsorbed groups react with solid surface molecules to form product molecules; product molecules resolve to form a gas phase; reaction The residue comes off the surface.
  • Step S263 forming an interlayer insulating layer 19 on the gate 18, the source region 162, the drain region 166, the connecting portion 168, and the flexible region 142.
  • the thickness range of the interlayer insulating layer 19 is The method of depositing the insulating layer 17 is the same, and the interlayer insulating layer 19 can be deposited by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
  • the deposition temperature is less than or equal to 600°C.
  • the interlayer insulating layer 19 may be a single layer of silicon oxide material, silicon oxide material, or silicon nitride material to form a stack of multiple sub-layers.
  • Step S264 Pattern the interlayer insulating layer 19, and form a first groove 192 corresponding to the source region 162 and a second groove 192 corresponding to the drain region 166 on the interlayer insulating layer 19 Two grooves 194.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of using photoresist, mask, exposure machine, etc., to form patterns including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present invention.
  • a layer of photoresist is formed on the interlayer insulating layer 19, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and photoresist A reserved area, where the photoresist non-reserved area is the area above the source region 162 and the drain region 166.
  • the interlayer insulating layer 19 in the photoresist non-reserved area is etched away by an etching process, and then the The remaining photoresist forms the first groove 192 and the second groove 194.
  • Step S265 forming a source 21 and a drain 20 at the first groove 192 and the second groove 194 respectively, and the source 21 is electrically connected to the source region 162 through the first groove 192;
  • the drain 20 is electrically connected to the drain region 166 through the second groove 194.
  • magnetron sputtering, thermal evaporation, or other film forming methods are used to deposit a layer with a thickness of about 100% on the interlayer insulating layer 19, the first groove 192 and the second groove 194.
  • the source and drain metal layer of the source and drain metal layer is coated with a layer of photoresist, and the photoresist is exposed and developed using a mask, so that the photoresist forms a photoresist non-retained area and a photoresist reserved area ,
  • the photoresist reserved area is the area where the first groove 192 and the second groove 194 are located, and the photoresist unreserved area is other areas; the source and drain of the photoresist unreserved area are completely etched by the etching process
  • the metal film is peeled off the remaining photoresist to form the source 21 and the drain 20.
  • steps S264 and S265 may be replaced by the following steps: forming first via holes and corresponding to the source region 162 and the drain region 166 on the interlayer insulating layer 19, respectively.
  • the second via may be replaced by the following steps: forming first via holes and corresponding to the source region 162 and the drain region 166 on the interlayer insulating layer 19, respectively. The second via.
  • the source 21 is electrically connected to the source region 162 through the first via hole, and the drain 20 is electrically connected to the drain region 166 through the second via hole.
  • a photolithography process is used to form a mask layer above the interlayer insulating layer 19, and the first via hole and the second via hole are formed by dry etching.
  • Dry etching can use plasma etching, reactive ion etching, inductively coupled plasma etching and other methods.
  • the etching gas can be gas containing fluorine and chlorine, such as CF 4 , CHF 3 , SF 6 , CC1 2 Gas such as F 2 or a mixed gas formed by the above gas and O 2 .
  • another embodiment of the present application further provides a display panel 20, the display panel 20 includes a substrate 21, a transparent film layer 22, a buffer layer 23, a switch array layer 24, and an organic light emitting display layer 25.
  • the transparent film layer 22, the buffer layer 23, the switch array layer 24, and the organic light emitting display layer 25 are sequentially formed on the substrate 21.
  • the switch array layer 25 includes any one of the above-mentioned embodiments of the present application.
  • the organic light emitting display layer 25 includes an organic light emitting unit, and the organic light emitting unit is connected to the drain 20 of the thin film transistor 10 provided in any of the foregoing embodiments of the present application.
  • an embodiment of the present application further provides a display device, and the display device includes the display panel 20 provided in the foregoing embodiment of the present application.
  • the display device may be any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., or it may only be used to display electronic files (for example, video files, text files, etc.). ) Displayed to the on-screen display.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., or it may only be used to display electronic files (for example, video files, text files, etc.). ) Displayed to the on-screen display.
  • a thin film transistor 10 is provided in the display panel 20 of the display device of the present application.
  • the light shielding layer 14, the shielding layer 15, and the semiconductor layer 16 in the thin film transistor 10 are self-contained.
  • the alignment structure can realize the masking of the light shielding layer 14 and the semiconductor layer 16 at the same time, without the need for masking the light shielding layer 14 and the semiconductor layer 16 separately, so that the thin film transistor is prepared In the 10 process, the number of masks is reduced, the production cost is reduced, and the production capacity is increased.
  • the above-mentioned thin film transistor 10 connects the semiconductor layer 16 and the light shielding layer 14 by providing a connecting portion 168, so that the voltage at the source 21 is equal to the voltage on the light shielding layer 14, thereby shielding the flexible substrate 12 and The accumulated charge between the buffer layers 13 improves the electrical performance of the thin film transistor 10.

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Abstract

申请公开一种薄膜晶体管(10)及其制造方法、显示面板(20)、显示装置，其中薄膜晶体管的制造方法包括：在基底(11)上形成遮光层(14)和屏蔽层(15)；对屏蔽层(15)进行处理，使遮光层(14)部分显露；在屏蔽层(15)和遮光层(14)显露的部分上形成半导体层(16)，半导体层(16)具有连接部(168)，连接部(168)与遮光层(14)显露的部分连接；遮光层(14)、屏蔽层(15)和半导体层(16)形成自对准结构，能够实现对遮光层(14)和半导体层(16)同时进行光罩，而不需要对遮光层(14)和半导体层(16)单独进行光罩，因而在制备薄膜晶体管(10)的过程中，光罩次数减少，生产成本降低。

Description

薄膜晶体管及其制造方法、显示面板、显示装置 技术领域
本申请实施例涉及显示技术领域，尤其涉及一种薄膜晶体管、薄膜晶体管的制造方法以及使用该薄膜晶体管的显示面板、显示装置。
背景技术
薄膜晶体管是有源矩阵显示器件中一个非常重要的半导体器件，其中有源层可以选择以铟镓锌氧化物为代表的透明氧化物半导体材料制作，这类透明氧化物半导体材料具有迁移率高、均一性好、透明等优点，能够极大的提高有源矩阵显示器件的显示效果。目前被广泛研究的薄膜晶体管的结构一般可以分为两类：底栅型结构和顶栅型结构。
但是，当前顶栅型结构制程光罩次数过多，生产成本和产能受到严重影响。
发明内容
本申请实施例旨在提供一种薄膜晶体管及其制造方法、显示面板、显示装置，以解决现有技术中薄膜晶体管的制程光罩次数过多的技术问题。
本申请实施例解决其技术问题提供以下技术方案：
一种薄膜晶体管的制造方法，包括：
在基底上形成遮光层和屏蔽层；
对所述屏蔽层进行处理，使所述遮光层部分显露；
在所述屏蔽层和所述遮光层显露的部分上形成半导体层，所述半导体层的一端具有连接部，所述连接部与所述遮光层显露的部分连接；
对所述遮光层、所述屏蔽层和所述半导体层同时进行图案化处理，使得在所述遮光层的一侧，所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层的端面和所述半导体层的端面相互齐平；
在所述半导体层上依次形成绝缘层和栅极；以及
设置源极和漏极，所述源极和所述漏极分别与所述半导体层电连接。
可选地，所述对所述遮光层、所述屏蔽层和所述半导体层同时进行图案化处理，包括：
使所述缓冲层的两侧区域显露，所述缓冲层的两侧显露区域为可挠区域。
可选地，所述对所述遮光层、所述屏蔽层和所述半导体层同时进行图案化处理之后，还包括：
在所述半导体层上依次形成绝缘层和栅极；
对所述绝缘层和所述栅极同时进行处理，使半导体层的两侧区域显露，并将所述栅极与所述半导体层正对的部分定义为沟道区，所述半导体层的两侧显露区域分别定义为源极区和漏极区。
可选地，所述对所述绝缘层和所述栅极同时进行处理，使半导体层的两侧区域显露之后，还包括：
对所述漏极区和所述源极区同时进行表面处理。
可选地，所述对所述漏极区和所述源极区进行表面处理，包括：
对所述源极区和漏极区的表面同时进行活化处理。
可选地，所述对所述漏极区和所述源极区同时进行表面处理之后，还包括：
在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层。
可选地，在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层之后，所述方法还包括：
在所述层间绝缘层上形成分别与所述源极区和所述漏极区对应的第一凹槽和第二凹槽；
分别在所述第一凹槽和所述第二凹槽处分别形成所述源极和所述漏极,所述源极通过所述第一凹槽与所述源极区电连接,所述漏极通过所述第二凹槽与所述漏极区电连接。
可选地，在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层之后，所述方法还包括：
在所述层间绝缘层上形成分别与所述源极区和漏极区对应的第一过孔和第二过孔；
所述源极通过所述第一过孔与所述源极区电连接，所述漏极通过所述第二过孔与所述漏极区电连接。
本申请实施例解决其技术问题还提供以下技术方案：
一种薄膜晶体管，包括：基底、遮光层、屏蔽层、半导体层、绝缘层、栅极、源极和漏极；
所述基底上依次层叠所述遮光层和所述屏蔽层，且所述遮光层部分显露；
所述半导体层层叠于所述屏蔽层和所述遮光层显露的部分上，所述半导体层的一端具有连接部，所述连接部与所述遮光层显露的部分连接；在所述遮光层的一侧，所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层的端面和所述半导体层的端面相互齐平；
在所述半导体层上依次层叠所述绝缘层和所述栅极；
所述源极和所述漏极分别与所述半导体层电连接。
可选地，所述缓冲层的两侧区域未被所述遮光层和所述屏蔽层遮挡，所述缓冲层未被所述遮光层和所述屏蔽层遮挡的区域为可挠区域。
可选地，所述半导体层的两侧区域未被所述绝缘层和所述栅极遮挡，且所述栅极与所述半导体层正对的部分为沟道区，所述半导体层的两侧显露区域分别为源极区和漏极区。
可选地，所述源极区和所述漏极区均经过表面活化处理。
可选地，所述薄膜晶体管还包括层间绝缘层，所述层间绝缘层形成于所述栅极、所述漏极区、所述源极区和所述可挠区域上。
可选地，所述层间绝缘层上分别开设有与所述源极区和所述漏极区对应的第一凹槽和第二凹槽；
在所述第一凹槽和所述第二凹槽处分别层叠所述源极和所述漏极, 所述源极通过所述第一凹槽与所述源极区电连接,所述漏极通过所述第二凹槽与所述漏极区电连接。
可选地，在所述层间绝缘层上形成分别与所述源极区和漏极区对应的第一过孔和第二过孔；
所述源极通过所述第一过孔与所述源极区电连接，所述漏极通过所述第二过孔与所述漏极区电连接。
本申请实施例解决其技术问题还提供以下技术方案：
一种显示面板，包括基板以及在所述基板上依次层叠的透明薄膜层、缓冲层、开关阵列层以及有机发光显示层，所述开关阵列层包括以上所述的薄膜晶体管。
本申请实施例解决其技术问题还提供以下技术方案：
一种显示装置，包括以上所述的显示面板。
与现有技术相比较，在本申请实施例提供的薄膜晶体管中，在所述遮光层的一侧，所述连接部与所述遮光层显露的部分连接且所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层的端面和所述半导体层的端面相互齐平；能够实现对所述遮光层和所述半导体层同时进行光罩，而不需要对所述遮光层和所述半导体层单独进行光罩，因而在制备所述薄膜晶体管的过程中，光罩次数减少，生产成本降低，产能提升。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1是本申请其中一个实施例提供的一种薄膜晶体管的结构示意图；
图2是本申请其中一个实施例提供的一种薄膜晶体管的制造方法的流程图；
图3是本申请另一实施例提供的一种薄膜晶体管的制造方法的流程图；
图4a至图4i是图3示出的薄膜晶体管的制造方法在不同阶段的制备示意图；
图5为本申请又一实施例提供的一种显示面板的结构示意图。
具体实施方式
为了便于理解本申请，下面结合附图和具体实施例，对本申请进行更详细的说明。需要说明的是，当元件被表述“固定于”另一个元件，它可以直接在另一个元件上、或者其间可以存在一个或多个居中的元件。当一个元件被表述“连接”另一个元件，它可以是直接连接到另一个元件、或者其间可以存在一个或多个居中的元件。本说明书所使用的术语“垂直的”、“水平的”、“左”、“右”、“内”、“外”以及类似的表述只是为了说明的目的，并且仅表达实质上的位置关系，例如对于“垂直的”，如果某位置关系因为了实现某目的的缘故并非严格垂直，但实质上是垂直的，或者利用了垂直的特性，则属于本说明书所述“垂直的”范畴。
除非另有定义，本说明书所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。在本申请的说明书中所使用的术语只是为了描述具体地实施例的目的，不是用于限制本申请。本说明书所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
此外，下面所描述的本申请不同实施例中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
请参阅图1，本申请其中一个实施例提供的薄膜晶体管10包括基底11、柔性基板12、缓冲层13、遮光层14、屏蔽层15、半导体层16、绝 缘层17、栅极18、层间绝缘层19、漏极20和源极21。
所述基底11作为承载所述薄膜晶体管10的衬底，所述基底11上依次形成有柔性基板12、缓冲层13、遮光层14和屏蔽层15。
所述遮光层14和所述屏蔽层15形成于所述缓冲层13的中部，即所述缓冲层13的两侧区域未被所述遮光层14和所述屏蔽层15遮挡，所述缓冲层13未被所述遮光层14和所述屏蔽层15遮挡的区域为可挠区域142，相比于目前的薄膜晶体管，所述可挠区域142的设置释放了目前薄膜晶体管的屏蔽层处的薄膜应力，增加了薄膜晶体管10的可挠曲能力。
所述遮光层14的一侧区域部分显露，即未被所述屏蔽层15遮挡。
所述屏蔽层15远离所述缓冲层13的一侧形成有半导体层16，所述半导体层16还覆盖在所述遮光层14的未被所述屏蔽层15遮挡的一侧区域。可以理解的是，所述半导体层16具有连接部168，所述连接部168和所述遮光层14显露的部分相连接。所述半导体层16通过所述连接部168与所述遮光层14相连接。
在所述遮光层14的一侧，所述连接部168与所述遮光层14显露的部分连接且相互对齐,也即所述连接部168的端面与所述遮光层14显露的部分的端面齐平，在所述遮光层14的另一侧，所述遮光层14、所述屏蔽层15和所述半导体层16三者相互对齐，也即所述遮光层14、所述屏蔽层15和所述半导体层16的端面相互齐平，因此所述遮光层14、所述屏蔽层15和所述半导体层16共同形成一自对准结构，所述自对准结构能够实现对所述遮光层14和所述半导体层16同时进行光罩，而不需要对所述遮光层14和所述半导体层16单独进行光罩，因而在制备所述薄膜晶体管10的过程中，光罩次数减少，生产成本降低，产能提升。同时由于光罩次数的减少，减少了刻蚀工艺的次数，避免了由于薄膜晶体管10被过度刻蚀造成的损害，提高了薄膜晶体管10的电学性能。
所述半导体层16上依次形成有绝缘层17和栅极18，且所述半导体层16的两侧区域未被所述绝缘层17和所述栅极18遮盖，且将所述栅极18与所述半导体层16正对的部分定义为沟道区164，所述半导体层 16的两侧显露区域分别定义为源极区162和漏极区166。所述绝缘层17位于所述栅极18与所述半导体层16的所述沟道区164之间，从而使所述栅极18与所述沟道区164相互绝缘。
所述半导体层16的所述源极区162和所述漏极区166上分别形成源极21和漏极20。所述漏极20与所述漏极区166电连接，所述源极21与所述源极区162电连接。
所述层间绝缘层19形成于所述栅极18、漏极区166、源极区162、连接部168和可挠区域142上。所述层间绝缘层19在位于所述源极区162的上方开设有第一凹槽192，所述源极21通过所述第一凹槽192与所述源极区162电连接；所述层间绝缘层19在位于所述漏极区166的上方开设有第二凹槽194，所述漏极20通过所述第二凹槽194与所述漏极区166电连接。
在本实施例中，上述薄膜晶体管10的所述遮光层14、所述屏蔽层15和所述半导体层16共同形成的自对准结构，能够实现对所述遮光层14和所述半导体层16同时进行光罩，而不需要对所述遮光层14和所述半导体层16单独进行光罩，因而在制备所述薄膜晶体管10的过程中，光罩次数减少，生产成本降低，产能提升。同时上述薄膜晶体管10通过设置连接部168使所述半导体层16和所述遮光层14相连接，使源极21处的电压和所述遮光层14上的电压相等，进而屏蔽了柔性基板12和缓冲层13之间的累积电荷，提高了薄膜晶体管10的电学性能。
所述基底11采用玻璃等透明材料制成，且经过预先清洗。在一些实施例中，因传统碱玻璃中铝、钡和钠等金属杂质含量较高，容易在高温处理工艺中发生金属杂质的扩散，因此所述基底11也可以采用无碱玻璃制成。所述基底11也可采用柔性材料制成。
所述柔性基板12是用于支撑和保护可以在其上形成的多种元件的基板，在必要时，所述柔性基板12可与所述基底11剥离。所述柔性基板12可以由多种材料形成。例如，当场效应晶体管在诸如柔性显示设备的柔性应用中使用时，柔性基板12可以由柔性绝缘材料形成。柔性绝缘材料的示例可以包括聚酰亚胺(PI)、聚醚酰亚胺(PEI)、聚对苯二 甲酸乙二醇酯(PES)、聚碳酸酯(PC)、聚苯乙烯(PS)、苯乙烯-丙烯腈共聚物、以及硅丙烯酸树脂。而且，当场效应晶体管在具有高透射率的应用(诸如，透明显示设备)中使用时，柔性基板12可以由柔性透明绝缘材料形成。
所述缓冲层13用于阻挡柔性基板12中所含的杂质扩散进入场效应晶体管的半导体层16中，防止对场效应晶体管的器件性能产生影响。同时所述缓冲层13能够增强遮光层14与柔性基板12之间的密接性，增大遮光层14与柔性基板12的接触牢固度，进而避免遮光层14的脱落，提高了场效应晶体管的稳定性。其中,所述缓冲层13的材料为绝缘材料,如SiOx、SiNx或两者任意组合。
所述遮光层14的材料为导电性遮光材料，可以为普通的不透光金属材料，如铜、铝等材料。所述遮光层14采用低反射材料制成，从而可以防止薄膜晶体管10侧金属(即栅极18、源极21、漏极20)在外界光源作用下发生反光引起显示不良。
所述屏蔽层15是以氧化氮(N 2O)和甲硅烷(SiH 4)为反应源气体，采用增强化学气相沉积(PECVD)法在遮光层14上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜，所述氮化硅薄膜具有优良的绝缘耐压性能以及较好的界面特性。所述屏蔽层15可以防止出现遮光层14带电的现象，从而防止产生双栅极薄膜晶体管10(双TFT)现象。
在一些实施例中，所述屏蔽层15也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
所述半导体层16由高迁移率非晶铟镓锌氧化物(a-IGZO)靶材溅射而成，所述非晶铟镓锌氧化物(a-IGZO)半导体有着很多优异的性能，a-IGZO半导体在性能上优于其他非晶半导体。目前非晶铟镓锌氧化物薄膜晶体管10(a-IGZO-SFS)已经能够实现≥10 10的开关电流比，a-IGZO的电子迁移率在2-50cm 2/V-s之间，是a-Si面板的20-50倍，且其制备的时配线变细，可实现同等透过率下4倍的分辨率。另外，IGZO薄膜晶体管10的关断性能优越，具有漏电流低，功耗低的优点。
在一些实施例中，所述半导体层16可以为多种金属氧化物半导体。 诸如基于铟锡镓锌氧化物(InSnGaZnO)的材料的四元金属氧化物、诸如基于铟镓锌氧化物(InGaZnO)的材料、基于铟锡锌氧化物(InSnZnO)的材料、基于铟铝锌氧化物(InAlZnO)的材料、基于铟铪锌氧化物(InHfZnO)的材料、基于锡镓锌氧化物(SnGaZnO)的材料、基于铝镓锌氧化物(AlGaZnO)的材料、或者基于锡铝锌氧化物(SnAlZnO)的材料的三元金属氧化物、以及诸如基于铟锌氧化物(InZnO)的材料、基于锡锌氧化物(SnZnO)的材料、基于铝锌氧化物(AlZnO)的材料、基于锌镁氧化物(ZnMgO)的材料、基于锡镁氧化物(SnMgO)的材料、基于铟镁氧化物(InMgO)的材料、基于铟镓氧化物(InGaO)的材料的二元金属氧化物、基于铟氧化物(InO)的材料、基于锡氧化物(SnO)的材料、或者基于锌氧化物(ZnO)的材料的一元金属氧化物。
在其他一些实施例中，所述半导体层16还可以为非晶硅、多晶硅或有机材料。
所述绝缘层17是以氧化氮(N 2O)和甲硅烷(SiH 4)为反应源气体，采用增强化学气相沉积(PECVD)法在半导体层16上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜，所述氮化硅薄膜具有优良的绝缘耐压性能以及较好的界面特性。同时通过调整所述绝缘层17的厚度可改善有源层背面界面的质量，防止在所述有源层界面形成漏电的途径。所述绝缘层17的厚度为100-400nm，因为其良好的界面特性，所制备的半导体器件具有较小的泄露电流，提高了器件的电学性能。
在一些实施例中，所述绝缘层17也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
所述栅极18的材料可选择Al、Ti、Mo、Cu、Ni、ITO等金属、混合物的金属层或金属氧化物。
在一些实施例中，所述栅极18可以为多层电极。所述多层电极包括具有Al、Ti、Mo、Cu、Ni、ITO或其混合物的金属层和包括透明导电氧化物材料的透明导电氧化物层。所述透明导电氧化物材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟锡锌(ISZO)等。所述多层电极可以为包括第一透明导电氧化物层、金属层和第二透明导 电氧化物层的三层结构。所述多层电极也可以为包括透明导电氧化物层和金属层的两层结构。
所述层间绝缘层19能够对半导体层16的背沟道进行钝化，有助于薄膜晶体管10电学特性的提高。所述层间绝缘层19采用的是氮化硅绝缘层，所述氮化硅绝缘层具有优良的光电性能、机械性能以及强的阻挡杂质粒子扩散和水汽渗透等优点。较薄的所述氮化硅栅绝缘层不易阻隔扩散现象，并随着层间绝缘层19厚度的增加，半导体层16界面的污染物浓度随之降低，但当厚度超过一临界值，污染物浓度将不再大幅度降低而达到一极小值，因而设置所述层间绝缘层19的厚度为100-400nm。
在一些实施例中，所述层间绝缘层19也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
请参阅图2，本申请其中一个实施例提供一种薄膜晶体管10的制造方法，需要说明的是，上述对薄膜晶体管10的实施例的解释说明也适用于本实施例的薄膜晶体管10的制备方法，为避免冗余，在此不再详细展开。
所述薄膜晶体管10的制造方法包括：
步骤S21:在基底11上形成遮光层14和屏蔽层15。
具体地，在所述基底11上，采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor DeposiSion:筒称PECVD)方式或电子回旋谐振化学气相沉积(ElecSron CycloSron Resonance Chemical Vapor DeposiSion:筒称ECR-CVD)方式或溅射方式形成所述遮光层14。
然后在所述遮光层14上形成所述屏蔽层15，所述屏蔽层15是以氧化氮(N 2O)和甲硅烷(SiH 4)为反应源气体，采用增强化学气相沉积(PECVD)法在遮光层14上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜。
在一些实施例中，在基底11上形成遮光层14之前，还需先在基底11上依次形成柔性基板12和缓冲层13。
请参阅图4a,具体地，在基底11上层叠柔性基板12，然后在所述 柔性基板12上，采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor DeposiSion:筒称PECVD)方式、低压化学气相沉积方式(Low Pressure Chemical Vapor DeposiSion:筒称LPCVD)、大气压化学气相沉积(ASmospheric Pressure Chemical Vapor DeposiSion:筒称APCVD)方式或电子回旋谐振化学气相沉积(ElecSron CycloSron Resonance Chemical Vapor DeposiSion:筒称ECR-CVD)方式或溅射方式形成所述缓沖层13。所述缓冲层13的厚度范围为
Figure PCTCN2019078677-appb-000001
沉积温度小于或等于600℃。
所述缓冲层13的具体制作方法可为：将铜、铝靶材放入沉积腔室，通过溅射或者蒸镀在柔性基板12上沉积缓冲层13，并且在沉积时通入氮气或者氧气。该方法可以根据加入的原料的量，制作出铝原子占铜合金材料中总原子个数的原子百分比为0.05-30％、氮或氧占铜合金材料中总原子个数的原子百分比为0.05-30％、其余为铜的铜合金材料。此外，如果需要增加非铜非铝的金属元素，则可以将非铜非铝的金属与铜、铝一起放入沉积腔室，再通过溅射或者蒸镀在柔性基板12上沉积缓冲层13，并且在沉积时通入氮气或者氧气。
在一些实施例中，所述缓冲层13的具体制作方法也可以是：将氮或氧、铜、铝按照设定的原子比例制作成靶材，然后在柔性基板12上进行沉积以形成缓冲层13。另外，如果需要增加非铜非铝的金属元素，也可以将氮或氧、铜、铝和非铜非铝的金属按照设定的原子比例制作成靶材，然后进行沉积以形成缓冲层13。其中，所述缓冲层13可以为单层或多层结构，当为多层结构时，各层的材料可以相同或不相同。
步骤S22:对所述屏蔽层15进行图案化处理，使所述遮光层14部分显露。
请参阅图4b,具体地，所述图案化处理可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本申请实施例中所形成的结构选择相应的构图工艺。
在本实施例中，在所述屏蔽层15上形成一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，所述光刻胶不保留区域为所述屏蔽层15的一侧区域，通过刻蚀工艺刻蚀掉光刻胶不保留区域的屏蔽层15的一侧区域，剥离剩余的光刻胶，使所述遮光层14部分显露。
步骤S23:在所述屏蔽层15和所述遮光层14显露的部分上形成半导体层16，所述半导体层16的一端具有连接部168，所述连接部168与所述遮光层14显露的部分连接。
请参阅图4c,具体地，通过溅射法在所述屏蔽层15和所述遮光层14显露的部分上形成半导体层16。溅射所使用的靶材可以为多种金属氧化物半导体。诸如基于铟锡镓锌氧化物(InSnGaZnO)的材料的四元金属氧化物、诸如基于铟镓锌氧化物(InGaZnO)的材料的三元金属氧化物、以及诸如基于铟锌氧化物(InZnO)的材料的二元金属氧化物、以及诸如基于铟氧化物(InO)的材料、基于锡氧化物(SnO)的材料、或者基于锌氧化物(ZnO)的材料的一元金属氧化物等等。
步骤S24:对所述遮光层14、所述屏蔽层15和所述半导体层16同时进行图案化处理，使得在所述遮光层14的一侧，所述连接部与所述遮光层显露的部分连接且所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层的端面和所述半导体层的端面相互齐平。
请参阅图4d,具体地，在所述半导体层16上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶不保留区域为所述半导体层16的两侧区域，通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的所述遮光层14、所述屏蔽层15和所述半导体层16对应的两侧区域，剥离剩余的光刻胶，使所述缓冲层13的两侧区域显露，所述缓冲层13的两侧显露区域为可挠区域142。并且在所述遮光层14的一侧，所述连接部168与所述遮光层14显露的部分连接且相互对齐,也即所述连接部168的端面与所述遮光层14显露的部分的端面齐平，在所述遮光层14的另一侧，所述遮光层 14、所述屏蔽层15和所述半导体层16三者相互对齐，也即所述遮光层14、所述屏蔽层15和所述半导体层16的端面相互齐平，所述遮光层14、所述屏蔽层15和所述半导体层16共同形成一自对准结构。
步骤S25:在所述半导体层16上依次形成绝缘层17和栅极18。
请参阅图4e,具体地，可以采用等离子体增强化学气相沉积(PECVD)方法，在所述半导体层16上沉积厚度约为
Figure PCTCN2019078677-appb-000002
的绝缘层17，其中，绝缘层17材料可以选用氧化物、氮化物或者氮氧化物，绝缘层17可以为单层、双层或多层结构。具体地，绝缘层17可以是SiNx，SiOx或Si(ON)x。
然后在所述绝缘层17上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2019078677-appb-000003
的栅极18。
步骤S26:设置源极和漏极，所述源极和所述漏极分别与所述半导体层电连接。
具体地，采用磁控溅射、热蒸发或其它成膜方法在所述半导体层上沉积一层厚度约为
Figure PCTCN2019078677-appb-000004
的源漏金属层，在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域为所述半导体层的两侧，光刻胶不保留区域为其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的源漏金属薄膜，剥离剩余的光刻胶，形成所述源极21和漏极20。
请参阅图3，在一些实施例中，步骤S26包括：
步骤S261:对所述绝缘层17和所述栅极18同时进行图案化，使半导体层16的两侧区域显露，所述绝缘层17和所述栅极18位于所述半导体层16的中部，并将所述栅极18与所述半导体层16正对的部分定义为沟道区164，所述半导体层16的两侧显露区域分别定义为源极区162和漏极区166。
请参阅图4f,具体地，在所述绝缘层17和所述栅极18上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶不保留区域为所述绝缘层17 和所述栅极18的两侧区域，通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的所述绝缘层17和所述栅极18的两侧区域，剥离剩余的光刻胶，使半导体层16的两侧区域显露。
步骤S262:对所述源极区162和所述漏极区166进行表面处理。
具体地，通过等离子体表面处理仪对源极区162和漏极区166的表面进行活化处理。
请参阅图4g,具体地，通过使用氧(O 2)等离子体的氧化工艺把源极区162和漏极区166的表面进行氧化处理，从而能够保持沟道的可靠性而不需要保护膜。同时依靠等离子体中活性粒子的"活化作用"达到去除物体表面污渍的目的。从反应机理来看，等离子体清洗通常包括以下过程:无机气体被激发为等离子态；气相物质被吸附在固体表面；被吸附基团与固体表面分子反应生成产物分子；产物分子解析形成气相；反应残余物脱离表面。
步骤S263:在所述栅极18、所述源极区162、所述漏极区166和所述连接部168、可挠区域142上形成层间绝缘层19。
具体地，所述层间绝缘层19的厚度范围为
Figure PCTCN2019078677-appb-000005
与沉积所述绝缘层17的方式相同，可采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式沉积形成所述层间绝缘层19,沉积温度小于或等于600℃。所述层间绝缘层19可采用单层的氧化硅材料或者氧化硅材料、氮化硅材料形成多个子层的叠层。
步骤S264:对所述层间绝缘层19进行图案化，在所述层间绝缘层19上形成与所述源极区162对应的第一凹槽192和与所述漏极区166对应的第二凹槽194。
请参阅图4h,具体地，所述图案化工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所形成的结构选择相应的构图工艺。
在本实施例中，在所述层间绝缘层19上形成一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，所述光刻胶不保留区域为所述源极区162和所述漏极区166的上方区域，通过刻蚀工艺刻蚀掉光刻胶不保留区域的层间绝缘层19，剥离剩余的光刻胶，形成所述第一凹槽192和第二凹槽194。
步骤S265:分别在第一凹槽192和第二凹槽194处分别形成源极21和漏极20，所述源极21通过所述第一凹槽192与所述源极区162电连接；所述漏极20通过所述第二凹槽194与所述漏极区166电连接。
请参阅图4i,具体地，在层间绝缘层19、第一凹槽192和第二凹槽194上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2019078677-appb-000006
的源漏金属层，在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域为第一凹槽192和第二凹槽194所在区域，光刻胶不保留区域为其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的源漏金属薄膜，剥离剩余的光刻胶，形成所述源极21和漏极20。
在一些替代的实施例中，步骤S264和S265可被以下步骤代替，即：在所述层间绝缘层19上形成分别与所述源极区162和漏极区166对应的第一过孔和第二过孔。
所述源极21通过所述第一过孔与所述源极区162电连接，所述漏极20通过所述第二过孔与所述漏极区166电连接。
具体地，在所述层间绝缘层19的上方采用光刻工艺形成掩模层，并采用干法刻蚀形成所述第一过孔和第二过孔。干法刻蚀可采用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等多种方式，刻蚀气体可采用含氟、氯的气体，如CF 4、CHF 3、SF 6、CC1 2F 2等气体或者上述气体与0 2形成的混合气体。
请参阅图5，本申请又一实施例还提供一种显示面板20，所述显示面板20包括基板21、透明薄膜层22、缓冲层23、开关阵列层24以及有机发光显示层25，所述基板21上依次形成有所述透明薄膜层22、所 述缓冲层23、所述开关阵列层24以及所述有机发光显示层25，所述开关阵列层25包括本申请上述任一实施例提供的薄膜晶体管10。有机发光显示层25包括有机发光单元，所述有机发光单元与本申请上述任一实施例提供的薄膜晶体管10的漏极20连接。
基于同一发明构思，本申请实施例还提供了一种显示装置，所述显示装置包括本申请上述实施例提供的显示面板20。
具体的，所述显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品，或者仅为将电子文件(例如，视频文件、文字文件等)显示到屏幕上的显示器。
与现有技术相比较，本申请显示装置的显示面板20中提供了一种薄膜晶体管10，所述薄膜晶体管10中的所述遮光层14、所述屏蔽层15和所述半导体层16的自对准结构，能够实现对所述遮光层14和所述半导体层16同时进行光罩，而不需要对所述遮光层14和所述半导体层16单独进行光罩，因而在制备所述薄膜晶体管10的过程中，光罩次数减少，生产成本降低，产能提升。同时上述薄膜晶体管10通过设置连接部168使所述半导体层16和所述遮光层14相连接，使源极21处的电压和所述遮光层14上的电压相等，进而屏蔽了柔性基板12和缓冲层13之间的累积电荷，提高了薄膜晶体管10的电学性能。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；在本申请的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本申请的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种薄膜晶体管的制造方法，其特征在于，包括：
    在基底上形成遮光层和屏蔽层；
    对所述屏蔽层进行处理，使所述遮光层部分显露；
    在所述屏蔽层和所述遮光层显露的部分上形成半导体层，所述半导体层的一端具有连接部，所述连接部与所述遮光层显露的部分连接；
    对所述遮光层、所述屏蔽层和所述半导体层同时进行图案化处理，使得在所述遮光层的一侧，所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层的端面和所述半导体层的端面相互齐平；
    在所述半导体层上依次形成绝缘层和栅极；以及
    设置源极和漏极，所述源极和所述漏极分别与所述半导体层电连接。
  2. 根据权利要求1所述的方法，其特征在于：
    所述对所述遮光层、所述屏蔽层和所述半导体层同时进行图案化处理，包括：
    使所述缓冲层的两侧区域显露，所述缓冲层的两侧显露区域为可挠区域。
  3. 根据权利要求2所述的方法，其特征在于：
    所述在所述半导体层上依次形成绝缘层和栅极之后，还包括：
    对所述绝缘层和所述栅极同时进行处理，使半导体层的两侧区域显露，并将所述栅极与所述半导体层正对的部分定义为沟道区，所述半导体层的两侧显露区域分别定义为源极区和漏极区。
  4. 根据权利要求3所述的方法，其特征在于：
    所述对所述绝缘层和所述栅极同时进行处理，使半导体层的两侧区域显露之后，还包括：
    对所述漏极区和所述源极区同时进行表面处理。
  5. 根据权利要求4所述的方法，其特征在于：
    所述对所述漏极区和所述源极区同时进行表面处理，包括：
    对所述源极区和漏极区的表面同时进行活化处理。
  6. 根据权利要求3至5任一项所述的方法，其特征在于：
    所述对所述漏极区和所述源极区同时进行表面处理之后，还包括：
    在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层。
  7. 根据权利要求6所述的方法，其特征在于：
    在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层之后，还包括：
    在所述层间绝缘层上形成分别与所述源极区和所述漏极区对应的第一凹槽和第二凹槽；
    分别在所述第一凹槽和所述第二凹槽处分别形成所述源极和所述漏极,所述源极通过所述第一凹槽与所述源极区电连接,所述漏极通过所述第二凹槽与所述漏极区电连接。
  8. 根据权利要求6所述的方法，其特征在于：
    在所述栅极、所述源极区、所述漏极区和所述可挠区域上形成层间绝缘层之后，还包括：
    在所述层间绝缘层上形成分别与所述源极区和所述漏极区对应的第一过孔和第二过孔；
    所述源极通过所述第一过孔与所述源极区电连接，所述漏极通过所述第二过孔与所述漏极区电连接。
  9. 一种薄膜晶体管，其特征在于，包括：基底、遮光层、屏蔽层、半导体层、绝缘层、栅极、源极和漏极；
    所述基底上依次层叠所述遮光层和所述屏蔽层，且所述遮光层部分显露；
    所述半导体层层叠于所述屏蔽层和所述遮光层显露的部分上，所述半导体层的一端具有连接部，所述连接部与所述遮光层显露的部分连接；在所述遮光层的一侧，所述连接部的端面与所述遮光层显露的部分的端面齐平,在所述遮光层的另一侧，所述遮光层的端面、所述屏蔽层 的端面和所述半导体层的端面相互齐平；
    在所述半导体层上依次层叠所述绝缘层和所述栅极；
    所述源极和所述漏极分别与所述半导体层电连接。
  10. 根据权利要求9所述的薄膜晶体管，其特征在于，
    所述缓冲层的两侧区域未被所述遮光层和所述屏蔽层遮挡，所述缓冲层未被所述遮光层和所述屏蔽层遮挡的区域为可挠区域。
  11. 根据权利要求10所述的薄膜晶体管，其特征在于，
    所述半导体层的两侧区域未被所述绝缘层和所述栅极遮挡，且所述栅极与所述半导体层正对的部分为沟道区，所述半导体层的两侧显露区域分别为源极区和漏极区。
  12. 根据权利要求11所述的薄膜晶体管，其特征在于，
    所述源极区和所述漏极区均经过表面活化处理。
  13. 根据权利要求11所述的薄膜晶体管，其特征在于，还包括层间绝缘层，所述层间绝缘层形成于所述栅极、所述漏极区、所述源极区和所述可挠区域上。
  14. 根据权利要求13所述的薄膜晶体管，其特征在于，
    所述层间绝缘层上分别开设有与所述源极区和所述漏极区对应的第一凹槽和第二凹槽；
    在所述第一凹槽和所述第二凹槽处分别层叠所述源极和所述漏极,所述源极通过所述第一凹槽与所述源极区电连接,所述漏极通过所述第二凹槽与所述漏极区电连接。
  15. 根据权利要求13所述的薄膜晶体管，其特征在于，
    在所述层间绝缘层上形成分别与所述源极区和漏极区对应的第一过孔和第二过孔；
    所述源极通过所述第一过孔与所述源极区电连接，所述漏极通过所述第二过孔与所述漏极区电连接。
  16. 一种显示面板，其特征在于，包括基板以及在所述基板上依次层叠的透明薄膜层、缓冲层、开关阵列层以及有机发光显示层，所述开关阵列层包括如权利要求9至15任一项所述的薄膜晶体管。
  17. 一种显示装置，其特征在于，包括如权利要求16所述的显示面板。
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