WO2020186450A1 - Transistor à couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage - Google Patents

Transistor à couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2020186450A1
WO2020186450A1 PCT/CN2019/078677 CN2019078677W WO2020186450A1 WO 2020186450 A1 WO2020186450 A1 WO 2020186450A1 CN 2019078677 W CN2019078677 W CN 2019078677W WO 2020186450 A1 WO2020186450 A1 WO 2020186450A1
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Prior art keywords
layer
shielding layer
semiconductor layer
region
drain
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PCT/CN2019/078677
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English (en)
Chinese (zh)
Inventor
邹灿
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深圳市柔宇科技有限公司
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Priority to CN201980073008.1A priority Critical patent/CN113261113A/zh
Priority to PCT/CN2019/078677 priority patent/WO2020186450A1/fr
Publication of WO2020186450A1 publication Critical patent/WO2020186450A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular to a thin film transistor, a method for manufacturing the thin film transistor, and a display panel and a display device using the thin film transistor.
  • Thin film transistors are a very important semiconductor device in active matrix display devices.
  • the active layer can be made of transparent oxide semiconductor materials represented by indium gallium zinc oxide. Such transparent oxide semiconductor materials have high mobility, The advantages of good uniformity and transparency can greatly improve the display effect of the active matrix display device.
  • the structures of thin film transistors that have been widely studied at present can generally be divided into two categories: bottom-gate structures and top-gate structures.
  • the embodiments of the present application aim to provide a thin film transistor, a manufacturing method thereof, a display panel, and a display device, so as to solve the technical problem of too many process masks for thin film transistors in the prior art.
  • a method for manufacturing a thin film transistor including:
  • one end of the semiconductor layer has a connecting part, and the connecting part is connected with the exposed part of the light shielding layer;
  • the light-shielding layer, the shielding layer, and the semiconductor layer are simultaneously patterned, so that on one side of the light-shielding layer, the end surface of the connecting portion is flush with the end surface of the exposed portion of the light-shielding layer, On the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer and the end surface of the semiconductor layer are flush with each other;
  • a source electrode and a drain electrode are provided, and the source electrode and the drain electrode are respectively electrically connected to the semiconductor layer.
  • the simultaneous patterning of the light shielding layer, the shielding layer and the semiconductor layer includes:
  • the areas on both sides of the buffer layer are exposed, and the exposed areas on both sides of the buffer layer are flexible areas.
  • the method further includes:
  • the insulating layer and the gate are processed at the same time to expose the areas on both sides of the semiconductor layer, and the portion of the gate and the semiconductor layer directly opposite is defined as the channel region.
  • the side exposed regions are respectively defined as the source region and the drain region.
  • the method further includes:
  • the performing surface treatment on the drain region and the source region includes:
  • the surface of the source region and the drain region are simultaneously activated.
  • the method further includes:
  • An interlayer insulating layer is formed on the gate, the source region, the drain region, and the flexible region.
  • the method further includes:
  • the source electrode and the drain electrode are respectively formed at the first groove and the second groove, the source electrode is electrically connected to the source region through the first groove, and the The drain is electrically connected to the drain region through the second groove.
  • the method further includes:
  • the source is electrically connected to the source region through the first via hole
  • the drain is electrically connected to the drain region through the second via hole.
  • a thin film transistor comprising: a substrate, a light shielding layer, a shielding layer, a semiconductor layer, an insulating layer, a gate, a source and a drain;
  • the light-shielding layer and the shielding layer are sequentially laminated on the substrate, and the light-shielding layer is partially exposed;
  • the semiconductor layer is laminated on the shielding layer and the exposed part of the light-shielding layer, one end of the semiconductor layer has a connecting part, and the connecting part is connected with the exposed part of the light-shielding layer; On one side, the end surface of the connecting portion is flush with the end surface of the exposed part of the light shielding layer, and on the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer, and the semiconductor layer The ends are flush with each other;
  • the source electrode and the drain electrode are respectively electrically connected to the semiconductor layer.
  • regions on both sides of the buffer layer are not shielded by the light shielding layer and the shielding layer, and regions of the buffer layer not shielded by the light shielding layer and the shielding layer are flexible regions.
  • regions on both sides of the semiconductor layer are not shielded by the insulating layer and the gate, and the portion directly opposite to the gate and the semiconductor layer is a channel region.
  • the side exposed areas are the source area and the drain area respectively.
  • both the source region and the drain region undergo surface activation treatment.
  • the thin film transistor further includes an interlayer insulating layer formed on the gate, the drain region, the source region, and the flexible region.
  • a first groove and a second groove corresponding to the source region and the drain region are respectively opened on the interlayer insulating layer;
  • the source electrode and the drain electrode are laminated at the first groove and the second groove respectively, and the source electrode is electrically connected to the source region through the first groove, and the drain The electrode is electrically connected to the drain region through the second groove.
  • first via hole and a second via hole respectively corresponding to the source region and the drain region on the interlayer insulating layer
  • the source is electrically connected to the source region through the first via hole
  • the drain is electrically connected to the drain region through the second via hole.
  • a display panel includes a substrate and a transparent thin film layer, a buffer layer, a switch array layer, and an organic light emitting display layer sequentially stacked on the substrate, and the switch array layer includes the thin film transistor described above.
  • a display device includes the above-mentioned display panel.
  • the connecting portion is connected to the exposed portion of the light shielding layer, and the end surface of the connecting portion is connected to the The end surface of the exposed part of the light shielding layer is flush.
  • the end surface of the light shielding layer, the end surface of the shielding layer and the end surface of the semiconductor layer are flush with each other; the light shielding can be realized
  • the layer and the semiconductor layer are simultaneously masked, and the light shielding layer and the semiconductor layer are not required to be masked separately. Therefore, in the process of preparing the thin film transistor, the number of masks is reduced, the production cost is reduced, and the productivity is reduced. Promote.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by one of the embodiments of the present application.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by one of the embodiments of the present application;
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor provided by another embodiment of the present application.
  • 4a to 4i are schematic diagrams of the manufacturing method of the thin film transistor shown in FIG. 3 at different stages;
  • FIG. 5 is a schematic structural diagram of a display panel provided by another embodiment of the application.
  • the thin film transistor 10 provided by one embodiment of the present application includes a substrate 11, a flexible substrate 12, a buffer layer 13, a light shielding layer 14, a shielding layer 15, a semiconductor layer 16, an insulating layer 17, a gate electrode 18, and an interlayer The insulating layer 19, the drain electrode 20 and the source electrode 21.
  • the base 11 serves as a substrate for carrying the thin film transistor 10, and a flexible substrate 12, a buffer layer 13, a light shielding layer 14 and a shielding layer 15 are sequentially formed on the base 11.
  • the light shielding layer 14 and the shielding layer 15 are formed in the middle of the buffer layer 13, that is, the areas on both sides of the buffer layer 13 are not shielded by the light shielding layer 14 and the shielding layer 15. 13
  • the area not blocked by the light-shielding layer 14 and the shielding layer 15 is the flexible area 142.
  • the setting of the flexible area 142 releases the thin film at the shielding layer of the current thin film transistor. The stress increases the flexibility of the thin film transistor 10.
  • One side area of the light shielding layer 14 is partially exposed, that is, it is not shielded by the shielding layer 15.
  • a semiconductor layer 16 is formed on the side of the shielding layer 15 away from the buffer layer 13, and the semiconductor layer 16 also covers an area of the light shielding layer 14 that is not shielded by the shielding layer 15. It can be understood that the semiconductor layer 16 has a connecting portion 168, and the connecting portion 168 is connected to the exposed portion of the light shielding layer 14. The semiconductor layer 16 is connected to the light shielding layer 14 through the connecting portion 168.
  • the connecting portion 168 and the exposed portion of the light shielding layer 14 are connected and aligned with each other, that is, the end surface of the connecting portion 168 is aligned with the end surface of the exposed portion of the light shielding layer 14
  • the shielding layer 15 and the semiconductor layer 16 are aligned with each other, that is, the light shielding layer 14, the shielding layer 15 and the The end faces of the semiconductor layer 16 are flush with each other, so the light-shielding layer 14, the shielding layer 15 and the semiconductor layer 16 together form a self-aligned structure, and the self-aligned structure can realize the shielding layer 14
  • the photomask is performed at the same time as the semiconductor layer 16, and the light shielding layer 14 and the semiconductor layer 16 do not need to be separately photomasked.
  • the number of photomasks is reduced and the production cost is reduced. Reduce, increase production capacity.
  • the number of etching processes is reduced, the damage caused by the excessive etching of the thin film transistor 10 is avoided, and the electrical performance of the thin film transistor 10 is improved.
  • An insulating layer 17 and a gate 18 are sequentially formed on the semiconductor layer 16, and regions on both sides of the semiconductor layer 16 are not covered by the insulating layer 17 and the gate 18, and the gate 18 and The portion facing the semiconductor layer 16 is defined as a channel region 164, and the exposed regions on both sides of the semiconductor layer 16 are defined as a source region 162 and a drain region 166, respectively.
  • the insulating layer 17 is located between the gate 18 and the channel region 164 of the semiconductor layer 16 so as to insulate the gate 18 and the channel region 164 from each other.
  • a source 21 and a drain 20 are formed on the source region 162 and the drain region 166 of the semiconductor layer 16 respectively.
  • the drain 20 is electrically connected to the drain region 166
  • the source 21 is electrically connected to the source region 162.
  • the interlayer insulating layer 19 is formed on the gate 18, the drain region 166, the source region 162, the connection portion 168 and the flexible region 142.
  • the interlayer insulating layer 19 is provided with a first groove 192 located above the source region 162, and the source electrode 21 is electrically connected to the source region 162 through the first groove 192;
  • the interlayer insulating layer 19 defines a second groove 194 above the drain region 166, and the drain electrode 20 is electrically connected to the drain region 166 through the second groove 194.
  • the self-aligned structure formed by the light-shielding layer 14, the shielding layer 15 and the semiconductor layer 16 of the thin film transistor 10 can realize the contrast between the light-shielding layer 14 and the semiconductor layer 16
  • the photomask is performed at the same time, and the light shielding layer 14 and the semiconductor layer 16 do not need to be separately photomasked. Therefore, in the process of preparing the thin film transistor 10, the number of photomasks is reduced, the production cost is reduced, and the productivity is increased.
  • the above-mentioned thin film transistor 10 connects the semiconductor layer 16 and the light shielding layer 14 by providing a connecting portion 168, so that the voltage at the source 21 is equal to the voltage on the light shielding layer 14, thereby shielding the flexible substrate 12 and The accumulated charge between the buffer layers 13 improves the electrical performance of the thin film transistor 10.
  • the substrate 11 is made of transparent materials such as glass, and is cleaned in advance.
  • the substrate 11 due to the relatively high content of metal impurities such as aluminum, barium, and sodium in the traditional alkali glass, the diffusion of metal impurities is likely to occur during the high-temperature treatment process, so the substrate 11 can also be made of alkali-free glass.
  • the base 11 can also be made of flexible materials.
  • the flexible substrate 12 is a substrate for supporting and protecting various elements that can be formed thereon, and when necessary, the flexible substrate 12 can be peeled from the base 11.
  • the flexible substrate 12 may be formed of various materials.
  • the flexible substrate 12 may be formed of a flexible insulating material.
  • flexible insulating materials may include polyimide (PI), polyetherimide (PEI), polyethylene terephthalate (PES), polycarbonate (PC), polystyrene (PS) , Styrene-acrylonitrile copolymer, and silicone acrylic resin.
  • the flexible substrate 12 may be formed of a flexible transparent insulating material.
  • the buffer layer 13 is used to prevent the impurities contained in the flexible substrate 12 from diffusing into the semiconductor layer 16 of the field effect transistor, so as to prevent the device performance of the field effect transistor from being affected. At the same time, the buffer layer 13 can enhance the adhesion between the light-shielding layer 14 and the flexible substrate 12, increase the contact firmness of the light-shielding layer 14 and the flexible substrate 12, thereby avoiding the light-shielding layer 14 from falling off, and improving the stability of the field effect transistor. Sex. Wherein, the material of the buffer layer 13 is an insulating material, such as SiOx, SiNx or any combination of the two.
  • the material of the light-shielding layer 14 is a conductive light-shielding material, which may be a common opaque metal material, such as copper, aluminum, and the like.
  • the light shielding layer 14 is made of a low-reflective material, so as to prevent the metal on the side of the thin film transistor 10 (ie, the gate 18, the source 21, and the drain 20) from reflecting light under the action of an external light source and causing poor display.
  • the shielding layer 15 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as the reaction source gas, and a series of hydrogenated amorphous silicon nitride is deposited on the light shielding layer 14 by an enhanced chemical vapor deposition (PECVD) method.
  • PECVD enhanced chemical vapor deposition
  • a-SiNx:H the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • the shielding layer 15 can prevent the phenomenon that the light shielding layer 14 is charged, thereby preventing the double-gate thin film transistor 10 (dual TFT) phenomenon.
  • the shielding layer 15 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the semiconductor layer 16 is formed by sputtering a high-mobility amorphous indium gallium zinc oxide (a-IGZO) target.
  • the amorphous indium gallium zinc oxide (a-IGZO) semiconductor has many excellent properties, a -IGZO semiconductor is superior to other amorphous semiconductors in performance.
  • the amorphous indium gallium zinc oxide thin film transistor 10 (a-IGZO-SFS) has been able to achieve a switching current ratio of ⁇ 10 10 , and the electron mobility of a-IGZO is between 2-50 cm 2 /Vs, which is a-Si 20-50 times that of the panel, and the wiring becomes thinner when it is prepared, which can achieve 4 times the resolution under the same transmittance.
  • the IGZO thin film transistor 10 has superior turn-off performance, and has the advantages of low leakage current and low power consumption.
  • the semiconductor layer 16 may be a variety of metal oxide semiconductors.
  • Quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO) based materials, such as indium gallium zinc oxide (InGaZnO) based materials, indium tin zinc oxide (InSnZnO) based materials, indium aluminum zinc oxide based Material (InAlZnO), material based on indium hafnium zinc oxide (InHfZnO), material based on tin gallium zinc oxide (SnGaZnO), material based on aluminum gallium zinc oxide (AlGaZnO), or based on tin aluminum zinc oxide (SnAlZnO) materials such as ternary metal oxides, and materials such as indium zinc oxide (InZnO)-based materials, tin-zinc oxide (SnZnO)-based materials, aluminum-zinc oxide (AlZnO)-based materials, zinc-magnesium-based materials Ox
  • the semiconductor layer 16 may also be amorphous silicon, polysilicon or organic material.
  • the insulating layer 17 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as reaction source gases, and a series of hydrogenated amorphous silicon nitride is deposited on the semiconductor layer 16 by an enhanced chemical vapor deposition (PECVD) method.
  • PECVD enhanced chemical vapor deposition
  • a-SiNx:H the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • the quality of the back interface of the active layer can be improved by adjusting the thickness of the insulating layer 17 to prevent the formation of leakage paths at the interface of the active layer.
  • the thickness of the insulating layer 17 is 100-400 nm. Because of its good interface characteristics, the prepared semiconductor device has a smaller leakage current, which improves the electrical performance of the device.
  • the insulating layer 17 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the material of the gate 18 can be selected from metals such as Al, Ti, Mo, Cu, Ni, ITO, a metal layer of a mixture, or a metal oxide.
  • the gate 18 may be a multilayer electrode.
  • the multilayer electrode includes a metal layer having Al, Ti, Mo, Cu, Ni, ITO, or a mixture thereof, and a transparent conductive oxide layer including a transparent conductive oxide material.
  • the transparent conductive oxide material may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ISZO), and the like.
  • the multilayer electrode may have a three-layer structure including a first transparent conductive oxide layer, a metal layer, and a second transparent conductive oxide layer.
  • the multilayer electrode may also have a two-layer structure including a transparent conductive oxide layer and a metal layer.
  • the interlayer insulating layer 19 can passivate the back channel of the semiconductor layer 16 and contribute to the improvement of the electrical characteristics of the thin film transistor 10.
  • the interlayer insulating layer 19 uses a silicon nitride insulating layer, which has excellent photoelectric properties, mechanical properties, and strong barriers to the diffusion of impurity particles and water vapor penetration.
  • the thinner silicon nitride gate insulating layer is not easy to block the diffusion phenomenon, and as the thickness of the interlayer insulating layer 19 increases, the concentration of contaminants at the interface of the semiconductor layer 16 decreases, but when the thickness exceeds a critical value, the contaminants The concentration will no longer decrease greatly and reach a minimum value, so the thickness of the interlayer insulating layer 19 is set to be 100-400 nm.
  • the interlayer insulating layer 19 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • one of the embodiments of the present application provides a method for manufacturing a thin film transistor 10. It should be noted that the above explanation of the embodiment of the thin film transistor 10 is also applicable to the method for manufacturing the thin film transistor 10 of this embodiment. In order to avoid redundancy, we will not expand it in detail here.
  • the manufacturing method of the thin film transistor 10 includes:
  • Step S21 forming the light shielding layer 14 and the shielding layer 15 on the substrate 11.
  • PECVD plasma-enhanced chemical vapor deposition
  • ECR-CVD electron cyclotron resonance chemical vapor deposition
  • the light shielding layer 14 is formed by a method or a sputtering method.
  • the shielding layer 15 is formed on the light-shielding layer 14.
  • the shielding layer 15 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as reaction source gases, and adopts an enhanced chemical vapor deposition (PECVD) method
  • PECVD enhanced chemical vapor deposition
  • a series of hydrogenated amorphous silicon nitride (a-SiNx:H) films are deposited on the light shielding layer 14.
  • the flexible substrate 12 and the buffer layer 13 need to be sequentially formed on the base 11 first.
  • a flexible substrate 12 is laminated on a base 11, and then on the flexible substrate 12, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor DeposiSion: PECVD in short), low pressure chemical vapor deposition Method (Low Pressure Chemical Vapor DeposiSion: LPCVD), atmospheric pressure chemical vapor deposition (ASmospheric Pressure Chemical Vapor DeposiSion: APCVD) or electronic cyclotron resonance chemical vapor deposition (ElecSron CycloSron Resonance Chemical Vapor DeposiSion: ECR-CVD)
  • the buffer layer 13 is formed by a method or a sputtering method.
  • the thickness range of the buffer layer 13 is The deposition temperature is less than or equal to 600°C.
  • the specific manufacturing method of the buffer layer 13 may be: putting copper or aluminum targets into a deposition chamber, depositing the buffer layer 13 on the flexible substrate 12 by sputtering or evaporation, and introducing nitrogen or oxygen during the deposition. According to the amount of raw materials added, the method can produce aluminum atoms with an atomic percentage of 0.05-30% of the total number of atoms in the copper alloy material, and a nitrogen or oxygen atomic percentage of 0.05--30% of the total number of atoms in the copper alloy material. 30%, the rest is copper alloy material.
  • non-copper and non-aluminum metal elements you can put the non-copper and non-aluminum metal together with copper and aluminum into the deposition chamber, and then deposit the buffer layer 13 on the flexible substrate 12 by sputtering or evaporation. In addition, nitrogen or oxygen is introduced during deposition.
  • the specific manufacturing method of the buffer layer 13 may also be: manufacturing nitrogen or oxygen, copper, and aluminum into a target in a set atomic ratio, and then depositing on the flexible substrate 12 to form the buffer layer 13.
  • nitrogen or oxygen, copper, aluminum and non-copper and non-aluminum metals can also be made into targets according to the set atomic ratio, and then deposited to form the buffer layer 13.
  • the buffer layer 13 may be a single-layer or multi-layer structure. When it is a multi-layer structure, the materials of each layer may be the same or different.
  • Step S22 Perform a patterning process on the shielding layer 15 so that the light shielding layer 14 is partially exposed.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of using photoresist, mask, exposure machine, etc., to form patterns including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present application.
  • a layer of photoresist is formed on the shielding layer 15, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and a photoresist reserved area
  • the non-reserved photoresist area is a side area of the shielding layer 15.
  • the side area of the shielding layer 15 where the photoresist is not reserved area is etched by an etching process, and the remaining photoresist is stripped to make The light shielding layer 14 is partially exposed.
  • Step S23 A semiconductor layer 16 is formed on the exposed portion of the shielding layer 15 and the light shielding layer 14. One end of the semiconductor layer 16 has a connecting portion 168, and the connecting portion 168 and the exposed portion of the light shielding layer 14 connection.
  • a semiconductor layer 16 is formed on the exposed portion of the shielding layer 15 and the light shielding layer 14 by a sputtering method.
  • the target material used for sputtering can be a variety of metal oxide semiconductors. Quaternary metal oxides such as materials based on indium tin gallium zinc oxide (InSnGaZnO), ternary metal oxides such as materials based on indium gallium zinc oxide (InGaZnO), and materials such as indium zinc oxide (InZnO) Binary metal oxides of materials, and unary metal oxides such as indium oxide (InO)-based materials, tin oxide (SnO)-based materials, or zinc oxide (ZnO)-based materials, and the like.
  • Step S24 simultaneously patterning the light-shielding layer 14, the shielding layer 15, and the semiconductor layer 16, so that on one side of the light-shielding layer 14, the connecting portion and the exposed part of the light-shielding layer Connected and the end surface of the connecting portion is flush with the end surface of the exposed part of the light shielding layer, on the other side of the light shielding layer, the end surface of the light shielding layer, the end surface of the shielding layer and the semiconductor layer The end faces are flush with each other.
  • a layer of photoresist is coated on the semiconductor layer 16, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and photolithography
  • the photoresist reserved area where the photoresist non-reserved area is the area on both sides of the semiconductor layer 16, the light shielding layer 14, the shielding layer 15 and the photoresist non-reserved area are completely etched by an etching process In the regions on both sides of the semiconductor layer 16, the remaining photoresist is stripped to expose the regions on both sides of the buffer layer 13, and the exposed regions on both sides of the buffer layer 13 are flexible regions 142.
  • the connecting portion 168 and the exposed part of the light-shielding layer 14 are connected and aligned with each other, that is, the end face of the connecting part 168 and the end face of the exposed part of the light-shielding layer 14 Flush, on the other side of the light shielding layer 14, the light shielding layer 14, the shielding layer 15 and the semiconductor layer 16 are aligned with each other, that is, the light shielding layer 14, the shielding layer 15 and The end faces of the semiconductor layer 16 are flush with each other, and the light shielding layer 14, the shielding layer 15 and the semiconductor layer 16 together form a self-aligned structure.
  • Step S25 forming an insulating layer 17 and a gate 18 on the semiconductor layer 16 in sequence.
  • the insulating layer 17 can be made of oxide, nitride or oxynitride, and the insulating layer 17 can be a single-layer, double-layer or multilayer structure. Specifically, the insulating layer 17 may be SiNx, SiOx or Si(ON)x.
  • magnetron sputtering, thermal evaporation or other film forming methods are used to deposit a layer with a thickness of about ⁇ Grid 18.
  • Step S26 setting a source electrode and a drain electrode, the source electrode and the drain electrode are electrically connected to the semiconductor layer, respectively.
  • magnetron sputtering, thermal evaporation or other film forming methods are used to deposit a layer on the semiconductor layer with a thickness of about
  • the source and drain metal layer of the source and drain metal layer is coated with a layer of photoresist, and the photoresist is exposed and developed using a mask, so that the photoresist forms a photoresist non-retained area and a photoresist reserved area , wherein the photoresist reserved areas are on both sides of the semiconductor layer, and the photoresist unreserved areas are other areas; the source and drain metal films in the photoresist unreserved areas are completely etched by the etching process, and the remaining Photoresist is used to form the source 21 and the drain 20.
  • step S26 includes:
  • Step S261 patterning the insulating layer 17 and the gate 18 at the same time to expose areas on both sides of the semiconductor layer 16, and the insulating layer 17 and the gate 18 are located in the middle of the semiconductor layer 16.
  • the portion of the gate 18 directly opposite to the semiconductor layer 16 is defined as a channel region 164, and the exposed regions on both sides of the semiconductor layer 16 are defined as a source region 162 and a drain region 166, respectively.
  • a layer of photoresist is coated on the insulating layer 17 and the gate 18, and the photoresist is exposed and developed using a mask, so that the photoresist is formed into a photoresist
  • the unreserved area and the photoresist reserved area, where the unreserved photoresist area is the area on both sides of the insulating layer 17 and the gate 18, and the photoresist unreserved area is completely etched by an etching process
  • the regions on both sides of the insulating layer 17 and the gate 18 are stripped of the remaining photoresist, so that the regions on both sides of the semiconductor layer 16 are exposed.
  • Step S262 Perform surface treatment on the source region 162 and the drain region 166.
  • the surface of the source region 162 and the drain region 166 is activated by a plasma surface treatment instrument.
  • plasma cleaning usually includes the following processes: inorganic gas is excited into a plasma state; gas phase substances are adsorbed on the solid surface; adsorbed groups react with solid surface molecules to form product molecules; product molecules resolve to form a gas phase; reaction The residue comes off the surface.
  • Step S263 forming an interlayer insulating layer 19 on the gate 18, the source region 162, the drain region 166, the connecting portion 168, and the flexible region 142.
  • the thickness range of the interlayer insulating layer 19 is The method of depositing the insulating layer 17 is the same, and the interlayer insulating layer 19 can be deposited by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
  • the deposition temperature is less than or equal to 600°C.
  • the interlayer insulating layer 19 may be a single layer of silicon oxide material, silicon oxide material, or silicon nitride material to form a stack of multiple sub-layers.
  • Step S264 Pattern the interlayer insulating layer 19, and form a first groove 192 corresponding to the source region 162 and a second groove 192 corresponding to the drain region 166 on the interlayer insulating layer 19 Two grooves 194.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of using photoresist, mask, exposure machine, etc., to form patterns including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present invention.
  • a layer of photoresist is formed on the interlayer insulating layer 19, and a mask is used to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and photoresist A reserved area, where the photoresist non-reserved area is the area above the source region 162 and the drain region 166.
  • the interlayer insulating layer 19 in the photoresist non-reserved area is etched away by an etching process, and then the The remaining photoresist forms the first groove 192 and the second groove 194.
  • Step S265 forming a source 21 and a drain 20 at the first groove 192 and the second groove 194 respectively, and the source 21 is electrically connected to the source region 162 through the first groove 192;
  • the drain 20 is electrically connected to the drain region 166 through the second groove 194.
  • magnetron sputtering, thermal evaporation, or other film forming methods are used to deposit a layer with a thickness of about 100% on the interlayer insulating layer 19, the first groove 192 and the second groove 194.
  • the source and drain metal layer of the source and drain metal layer is coated with a layer of photoresist, and the photoresist is exposed and developed using a mask, so that the photoresist forms a photoresist non-retained area and a photoresist reserved area ,
  • the photoresist reserved area is the area where the first groove 192 and the second groove 194 are located, and the photoresist unreserved area is other areas; the source and drain of the photoresist unreserved area are completely etched by the etching process
  • the metal film is peeled off the remaining photoresist to form the source 21 and the drain 20.
  • steps S264 and S265 may be replaced by the following steps: forming first via holes and corresponding to the source region 162 and the drain region 166 on the interlayer insulating layer 19, respectively.
  • the second via may be replaced by the following steps: forming first via holes and corresponding to the source region 162 and the drain region 166 on the interlayer insulating layer 19, respectively. The second via.
  • the source 21 is electrically connected to the source region 162 through the first via hole, and the drain 20 is electrically connected to the drain region 166 through the second via hole.
  • a photolithography process is used to form a mask layer above the interlayer insulating layer 19, and the first via hole and the second via hole are formed by dry etching.
  • Dry etching can use plasma etching, reactive ion etching, inductively coupled plasma etching and other methods.
  • the etching gas can be gas containing fluorine and chlorine, such as CF 4 , CHF 3 , SF 6 , CC1 2 Gas such as F 2 or a mixed gas formed by the above gas and O 2 .
  • another embodiment of the present application further provides a display panel 20, the display panel 20 includes a substrate 21, a transparent film layer 22, a buffer layer 23, a switch array layer 24, and an organic light emitting display layer 25.
  • the transparent film layer 22, the buffer layer 23, the switch array layer 24, and the organic light emitting display layer 25 are sequentially formed on the substrate 21.
  • the switch array layer 25 includes any one of the above-mentioned embodiments of the present application.
  • the organic light emitting display layer 25 includes an organic light emitting unit, and the organic light emitting unit is connected to the drain 20 of the thin film transistor 10 provided in any of the foregoing embodiments of the present application.
  • an embodiment of the present application further provides a display device, and the display device includes the display panel 20 provided in the foregoing embodiment of the present application.
  • the display device may be any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., or it may only be used to display electronic files (for example, video files, text files, etc.). ) Displayed to the on-screen display.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., or it may only be used to display electronic files (for example, video files, text files, etc.). ) Displayed to the on-screen display.
  • a thin film transistor 10 is provided in the display panel 20 of the display device of the present application.
  • the light shielding layer 14, the shielding layer 15, and the semiconductor layer 16 in the thin film transistor 10 are self-contained.
  • the alignment structure can realize the masking of the light shielding layer 14 and the semiconductor layer 16 at the same time, without the need for masking the light shielding layer 14 and the semiconductor layer 16 separately, so that the thin film transistor is prepared In the 10 process, the number of masks is reduced, the production cost is reduced, and the production capacity is increased.
  • the above-mentioned thin film transistor 10 connects the semiconductor layer 16 and the light shielding layer 14 by providing a connecting portion 168, so that the voltage at the source 21 is equal to the voltage on the light shielding layer 14, thereby shielding the flexible substrate 12 and The accumulated charge between the buffer layers 13 improves the electrical performance of the thin film transistor 10.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor à couches minces (10) et son procédé de fabrication, un panneau d'affichage (20) et un dispositif d'affichage. Le procédé de fabrication d'un transistor à couches minces consiste à : former une couche de blocage de lumière (14) et une couche de protection (15) sur un substrat (11) ; traiter la couche de protection (15) de façon à exposer partiellement la couche de blocage de lumière (14) ; et former une couche semi-conductrice (16) sur la couche de protection (15) et la partie exposée de la couche de blocage de lumière (14), la couche semi-conductrice (16) ayant une partie de connexion (168), la partie de connexion (168) étant reliée à la partie exposée de la couche de blocage de lumière (14). La couche de blocage de lumière (14), la couche de protection (15) et la couche semi-conductrice (16) forment une structure d'auto-alignement, de sorte que le masquage peut être effectué sur la couche de blocage de lumière (14) et la couche semi-conductrice (16) simultanément, sans qu'il soit nécessaire de masquer séparément la couche de blocage de lumière (14) et la couche semi-conductrice (16), réduisant le nombre de fois de masquage dans le processus de fabrication du transistor à couches minces (10), réduisant le coût de production.
PCT/CN2019/078677 2019-03-19 2019-03-19 Transistor à couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage WO2020186450A1 (fr)

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CN201980073008.1A CN113261113A (zh) 2019-03-19 2019-03-19 薄膜晶体管及其制造方法、显示面板、显示装置
PCT/CN2019/078677 WO2020186450A1 (fr) 2019-03-19 2019-03-19 Transistor à couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage

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PCT/CN2019/078677 WO2020186450A1 (fr) 2019-03-19 2019-03-19 Transistor à couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage

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