WO2020173040A1 - 一种可逆逻辑电路及其操作方法 - Google Patents

一种可逆逻辑电路及其操作方法 Download PDF

Info

Publication number
WO2020173040A1
WO2020173040A1 PCT/CN2019/096068 CN2019096068W WO2020173040A1 WO 2020173040 A1 WO2020173040 A1 WO 2020173040A1 CN 2019096068 W CN2019096068 W CN 2019096068W WO 2020173040 A1 WO2020173040 A1 WO 2020173040A1
Authority
WO
WIPO (PCT)
Prior art keywords
switching unit
voltage
resistive switching
state
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/096068
Other languages
English (en)
French (fr)
Inventor
李祎
程龙
缪向水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huazhong University of Science and Technology
Original Assignee
Huazhong University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huazhong University of Science and Technology filed Critical Huazhong University of Science and Technology
Priority to US16/965,602 priority Critical patent/US11171650B2/en
Publication of WO2020173040A1 publication Critical patent/WO2020173040A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the invention belongs to the field of digital circuits, and more specifically, relates to a reversible logic circuit and an operation method thereof.
  • Reversible logic has very important application prospects in the field of information processing technology. From the informatics point of view, the number of output information bits of traditional Boolean logic gate circuits is less than the number of input information bits, and the lost information bits will lead to energy dissipation, while the output information bits of reversible logic gates are equal to the input information bits. It reduces energy dissipation and helps to improve logic computing performance.
  • the current structure of reversible logic gate circuits based on CMOS devices is very complicated, which is not conducive to large-scale integration. One is because of the complexity of the structure of the CMOS transistor device itself, and the other is because the reversible logic gate is constructed by a complex Boolean logic gate circuit. Therefore, a simple and efficient method for implementing reversible logic functions is needed.
  • the nonvolatile resistive switching device has a simpler structure than the CMOS transistor device, and the resistance value can be changed with the current flowing through it.
  • its high-resistance state and low-resistance state can be used to represent information "0" and "1" for information storage.
  • resistive switching devices have also been proposed to implement logic operations. The logic operation based on resistive switching devices can use the resistance as a logic signal, and the result of the operation is directly stored in the resistance state of the device, that is, the calculation and storage of data are completed in the same device or circuit, which realizes the integration of information storage and calculation, and improves information processing effectiveness.
  • the purpose of the present invention is to provide a reversible logic circuit based on a multi-level resistance state resistance variable device and an operation method thereof, aiming to solve the problem of complex structure and difficult integration of CMOS reversible logic circuits.
  • the invention provides a reversible logic circuit, which includes a resistive switching unit, a word line and a bit line.
  • the word line and the bit line are perpendicular to each other, and each word line and the bit line are connected by a resistive switching unit.
  • the positive electrode of the resistive switching unit is connected to the word line
  • the negative electrode of the resistive switching unit is connected to the bit line
  • the positive electrode of the resistive switching unit can be used as the first input terminal for applying logic operation voltage or grounding
  • the negative electrode of the resistive switching unit can be used as the first input terminal.
  • the two input terminals are used for applying logic operation voltage or grounding.
  • the resistance value of the resistive switching unit When current flows from the bit line where the resistive switching unit is located to the word line, that is, from the negative electrode to the positive electrode of the resistive switching unit, the resistance value of the resistive switching unit will increase; the resistive switching unit has a highest resistance value, when it reaches the highest resistance value , Even if there is current flowing from the negative electrode to the positive electrode of the cell, the resistance of the cell cannot be further increased.
  • the highest resistance value is recorded as the first-level resistance state. When applied to single-input reversible logic, it is recorded as logic 0; when applied to two-input reversible logic, it is recorded as logic 00.
  • the resistance value of the resistive switching unit When current flows from the word line where the resistive switching unit is located to the bit line, that is, from the positive electrode to the negative electrode of the resistive switching unit, the resistance value of the resistive switching unit will become smaller; the resistive switching unit has a minimum resistance value, when it reaches the lowest resistance value , Even if current flows from the positive electrode to the negative electrode of the cell, the resistance of the cell cannot be further reduced.
  • the lowest resistance is recorded as the fourth-level resistance state. When applied to single-input reversible logic, it is recorded as logic 1; when applied to two-input reversible logic, it is recorded as logic 11.
  • the resistive switching unit reach the second-level resistance state and the third-level resistance state, denoted as 01 state and 10 state, respectively.
  • the arrangement of the resistance values of the four resistance states from high to low is 00 state, 01 state, 10 state, and 11 state.
  • the two-digit logic values represented by the four resistance states are 00, 10, 01, and 11 respectively.
  • the resistance state of the resistive switching unit When the resistance state of the resistive switching unit is in the 01 state, the 10 state, and the 11 state, the first operating voltage V1 is applied to the bit line where the cell is located, and the word line where the cell is located is grounded, so that the cell resistance is changed to the 00 state.
  • the second operating voltage V2 is applied on the word line where the cell is located, and the bit line where the cell is located is grounded, which can make the cell resistance change to the 01 state;
  • the cell The third operating voltage V3 is applied to the word line where the cell is located, and the bit line where the cell is located is grounded to make the cell resistance change to state 10;
  • the fourth operating voltage V4 is applied to the word line where the cell is located, and the cell The location of the bit line is grounded, which can make the cell resistance change to the 11 state.
  • a reversible logic operation method is provided.
  • a resistive switching unit with four-level resistance states to implement reversible logic functions
  • different logic inputs follow the same operating rule.
  • control signals are introduced. By assigning the actual logic input value to the control signal, the application of different operating voltages is realized.
  • the control signal includes a voltage direction signal C, voltage signals A and B, and a word line voltage selection signal S.
  • the operating rule is: firstly determine the voltage direction signal C, determine the application position of the voltage signal A and the voltage signal B; secondly determine the magnitude of the voltage signal A and the voltage signal B; then determine the word line voltage selection signal S according to the voltage to be applied on the word line ; Finally apply the operating voltage to complete the logic calculation.
  • the voltage signal A is applied to the word line where the cell is located, and the voltage signal B is applied to the bit line where the cell is located.
  • the voltage drop across the resistive switching unit is -V4, making the cell resistance Change to the first resistance state 00 state, it is output 0 in the single-input reversible logic function;
  • the single-input NOT reversible logic function is realized.
  • the voltage signals A and B, the voltage direction signal C, and the word line voltage selection signal S in the control signal are all used for logic operations.
  • the two-input C-NOT reversible logic function is realized.
  • Vread read voltage is not enough to change the cell resistance state.
  • the present invention realizes single-input and two-input reversible logic functions in one unit based on the multi-level resistance state characteristics of a resistive switching unit in the fork bar array of the resistive switching unit, which is compared with the traditional CMOS transistor-based reversible logic gate
  • the circuit greatly optimizes the circuit structure; a unit is used to store two-bit output information, which improves the information storage capacity; according to the one-to-one correspondence between input and output in reversible logic, only the logic output results stored in the unit need to be read,
  • the original input information can be inferred without additional processes and units for storing input information, which saves storage space; in the logic calculation process, the calculation results are directly stored in the resistive switching unit in the form of resistance state, which realizes the storage and calculation. Fusion improves computational efficiency and reduces computational power consumption.
  • Figure 1 is a schematic structural diagram of a reversible logic circuit provided by the present invention
  • FIG. 2 is a schematic diagram of the conversion relationship between the four-level resistance states of the resistive switching unit provided by the present invention
  • Fig. 3 is an I-V characteristic curve diagram of the resistive switching unit provided by the present invention.
  • Figure 5 is a logical truth table of the two-input C-NOT reversible logic operation method provided by the present invention
  • FIG. 6 is a schematic flow diagram of a single-input NOT reversible logic operation and a two-input C-NOT reversible logic operation provided by the present invention
  • FIG. 7 is a schematic diagram of the result of a single-input NOT reversible logic operation provided by Embodiment 1 of the present invention.
  • FIG. 8 is a schematic diagram of the result of a two-input C-NOT reversible logic operation provided by the second embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a cross-bar array of resistive switching units of a reversible logic circuit provided by an embodiment of the present invention.
  • the cross bar array of resistive switching units is composed of mutually perpendicular word lines, bit lines and resistive switching units, and each word line and bit line are connected by a resistive switching unit. Wherein, the positive electrode of the resistive switching unit is connected to the word line, and the negative electrode of the resistive switching unit is connected to the bit line.
  • the resistance value of the resistive switching unit When current flows from the bit line where the resistive switching unit is located to the word line, that is, from the negative electrode to the positive electrode of the resistive switching unit, the resistance value of the resistive switching unit will increase; the resistive switching unit has a highest resistance value, when it reaches the highest resistance value , Even if there is current flowing from the negative electrode to the positive electrode of the cell, the resistance of the cell cannot be further increased.
  • the resistance value of the resistive switching unit When current flows from the word line where the resistive switching unit is located to the bit line, that is, from the positive electrode to the negative electrode of the resistive switching unit, the resistance value of the resistive switching unit will become smaller; the resistive switching unit has a minimum resistance value, when it reaches the lowest resistance value , Even if current flows from the positive electrode to the negative electrode of the cell, the resistance of the cell cannot be further reduced.
  • FIG. 2 shows the conversion relationship between the four-level resistance states and the resistance states of the resistive switching unit provided by this embodiment.
  • the four resistance states are the first resistance state 00 state, the second resistance state 01 state, the third resistance state 10 state, and the fourth resistance state 11 state.
  • 00 state and 11 state can also be used for single input reversible
  • the realization of the logic function corresponds to the high resistance state 0 and the low resistance state 1 of the binary information.
  • the first operating voltage V1 is applied to the bit line where the cell is located, and the word line where the cell is located is grounded.
  • the voltage drop across the cell is -V1, which can make The cell resistance changes to the 00 state.
  • the second operating voltage V2 is applied to the word line where the cell is located, and the bit line where the cell is located is grounded.
  • the voltage drop across the cell is V2, which can make the cell resistance change to the 01 state;
  • the third operating voltage V3 is applied to the word line where the cell is located, and the bit line where the cell is located is grounded.
  • the voltage drop across the cell is V3, which can make the cell resistance change to state 10;
  • the fourth operating voltage V4 is applied on the word line where the cell is located, and the bit line where the cell is located is grounded.
  • the voltage drop across the cell is V4, which can make the cell resistance change to the 11 state.
  • FIG. 3 is a schematic diagram of the positional relationship between the I-V characteristic curve and the operating voltage of the resistive switching unit provided by this embodiment.
  • the resistance of the resistive switching unit changes with the current flowing through it.
  • the applied operating voltages of V2, V3, V4 can significantly reduce the resistance of the unit, and the corresponding operating current becomes significantly larger; the applied -V1 operating voltage can make the unit
  • the resistance value increases to the maximum value, and the corresponding operating current is the minimum.
  • the read voltage Vread is very small compared to the voltages of V1, V2, V3, and V4, and it hardly has a significant impact on the resistance of the resistive switching unit.
  • the positional relationships of the four-level resistance states reached by the operating voltages of V1, V2, V3, and V4 have also been marked.
  • Fig. 4 is a logic truth table of a single-input NOT reversible logic operation method provided by an embodiment of the present invention.
  • the logic input is 0, the logic output is 1; when the logic input is 1, the logic output is 0.
  • the input information can be inferred from the logical output result.
  • Fig. 5 is a logic truth table of a two-input C-NOT reversible logic operation method provided by an embodiment of the present invention.
  • the logic input is 00
  • the logic output is 00
  • the logic input is 01
  • the logic output is 01
  • the logic input is 10
  • the logic output is 11
  • the logic input is 11, the logic output is 10.
  • Figure 6 is a schematic diagram of the operation flow of the present invention.
  • resistive switching unit When using the resistive switching unit to realize the reversible logic function, different logic inputs follow the same operating rule. In this operation rule, control signals are introduced. By assigning the actual logic input value to the control signal, the application of different operating voltages is realized.
  • the control signal includes voltage signals A and B, a voltage direction signal C, and a word line voltage selection signal S.
  • the operating rule is: firstly determine the voltage direction signal C, determine the application position of the voltage signal A and the voltage signal B; secondly determine the magnitude of the voltage signal A and the voltage signal B; then determine the word line voltage selection signal S according to the voltage to be applied on the word line ; Finally apply the operating voltage to complete the logic calculation.
  • FIG. 7 is a schematic diagram of a single-input NOT reversible logic operation according to an embodiment of the present invention.
  • the voltage signal A is applied to the word line where the cell is located, and the voltage signal B is applied to the bit line where the cell is located.
  • the voltage drop across the resistive switching cell is -V4, regardless of the cell's Whatever the initial resistance state is, it can make the cell resistance change to the first resistance state 00 state, which is the output 0 in the single-input reversible logic function;
  • FIG. 8 is a schematic diagram of a two-input C-NOT reversible logic operation in the second embodiment of the present invention.
  • the voltage signals A and B, the voltage direction signal C, and the word line voltage selection signal S in the control signal are all used for logic operations.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

本发明公开了一种可逆逻辑电路及其操作方法，逻辑电路包括阻变单元、字线和位线，字线和位线相互垂直，阻变单元的正极与字线相连，作为第一输入端用于施加逻辑操作电压或者接地，阻变单元的负极与位线相连，作为第二输入端用于施加逻辑操作电压或者接地。进行可逆逻辑操作时，阻变单元四级电阻态作为逻辑输出，可实现单输入NOT和二输入C-NOT可逆逻辑功能。本发明仅利用一个阻变单元实现了单输入和二输入可逆逻辑功能，所需器件数少，操作简单，为可逆逻辑的实现提供了备选方案；同时逻辑运算结果直接非易失地存储在阻变单元的电阻状态中，实现了存储与计算的融合。

Description

一种可逆逻辑电路及其操作方法 [技术领域]
本发明属于数字电路领域，更具体的，涉及一种可逆逻辑电路及其操作方法。
[背景技术]
可逆逻辑在信息处理技术领域具有十分重要的应用前景。信息学的观点认为，传统布尔逻辑门电路的输出信息位数小于输入信息位数，失去的信息位将导致能量耗散，而可逆逻辑门的输出信息位数与输入信息位数相等，因此大大减少了能量耗散，有助于提升逻辑计算性能。目前基于CMOS器件的可逆逻辑门电路结构十分复杂，不利于大规模集成。其一是因为CMOS晶体管器件本身结构的复杂性，其二是因为可逆逻辑门由复杂的布尔逻辑门电路搭建而成。因此，需要一种简单高效的可逆逻辑功能实现方法。
非易失阻变器件具有比CMOS晶体管器件更为简单的结构，且电阻值能够随着流经电流的变化而改变。对于二级电阻态阻变器件，其高阻态和低阻态可以用来表示信息“0”和“1”，用于信息存储。此外，阻变器件还被提出可以实现逻辑运算。基于阻变器件的逻辑运算可以将电阻作为逻辑信号，运算结果直接存储在器件的电阻态中，即在同一器件或电路中完成数据的计算与存储，实现信息存储和计算的融合，提高信息处理效率。对于多级电阻态阻变器件，则可实现更多的逻辑功能，包括多值逻辑计算、非二进制逻辑计算、可逆逻辑等功能。对基于多级阻态阻变器件实现的可逆逻辑功能的探索，拓宽了阻变器件的应用范围，提升了信息处理的能力。
[发明内容]
针对现有技术的缺陷，本发明的目的在于提供一种基于多级电阻态阻 变器件的可逆逻辑电路及其操作方法，旨在解决CMOS可逆逻辑电路结构复杂、不易于集成的问题。
本发明提供了一种可逆逻辑电路，包括阻变单元、字线和位线，字线和位线相互垂直，每条字线和位线之间由一个阻变单元连接。其中，阻变单元的正极与字线相连，阻变单元的负极与位线相连，阻变单元的正极可以作为第一输入端用于施加逻辑操作电压或者接地，阻变单元的负极可以作为第二输入端用于施加逻辑操作电压或者接地。当有电流从阻变单元所在的位线流向字线，即从阻变单元负极流向正极时，阻变单元的阻值会变大；阻变单元具有一个最高阻值，当达到最高阻值时，即使再有电流从单元负极流向正极，也无法使单元阻值进一步升高。最高阻值记为第一级电阻态，应用于单输入可逆逻辑时，记为逻辑0；应用于二输入可逆逻辑时，记为逻辑00。当有电流从阻变单元所在的字线流向位线，即从阻变单元正极流向负极时，阻变单元的阻值会变小；阻变单元具有一个最低阻值，当达到最低阻值时，即使再有电流从单元正极流向负极，也无法使单元阻值进一步降低。最低阻值记为第四级电阻态，应用于单输入可逆逻辑时，记为逻辑1；应用于二输入可逆逻辑时，记为逻辑11。
在第一级电阻态和第四级电阻态中间，可以通过施加不同大小的操作电压，使阻变单元达到第二级电阻态和第三级电阻态，分别记为01态和10态。其中，四个电阻态的阻值从高到低的排列依次为00态、01态、10态、11态。应用于二输入可逆逻辑时，四个电阻态代表的二位逻辑值分别为00、10、01、11。
当阻变单元阻态处在01态、10态和11态时，在单元所在位线上施加第一操作电压V1，单元所在字线接地，可使单元阻变至00态。当单元阻态处在00态时，在单元所在字线上施加第二操作电压V2，单元所在位线接地，可使单元阻变至01态；当单元阻态处在00态时，在单元所在字线上施加第三操作电压V3，单元所在位线接地，可使单元阻变至10态；当 单元阻态处在00态时，在单元所在字线上施加第四操作电压V4，单元所在位线接地，可使单元阻变至11态。
优选地，四种逻辑操作电压，在数值上满足：V1＝V4，V2+V3＝V4。
按照本发明的另一方面，提供了一种可逆逻辑操作方法。使用具有四级电阻态的阻变单元实现可逆逻辑功能时，对于不同的逻辑输入，遵循同一种操作规则。在这种操作规则中，控制信号被引入。通过赋予控制信号以实际的逻辑输入值，实现不同操作电压的施加。
控制信号包括电压方向信号C、电压信号A和B和字线电压选择信号S。
对于电压信号A，A＝0时，选择0电压，即接地；A＝1时，选择非0电压V3或V4；
对于电压信号B，B＝0时，选择0电压，即接地；B＝1时，选择非0电压V3或V4；
对于电压方向信号C，C＝0时，将电压信号A施加在单元所在位线，将电压信号B施加在单元所在字线；C＝1时，将电压信号A施加在单元所在字线，将电压信号B施加在单元所在位线；
对于字线电压选择信号S，S＝0时，若字线上需要施加非0电压，则选择第三操作电压V3；S＝1时，若字线上需要施加非0电压，则选择第四操作电压V4；若字线上施加0电压，则字线电压选择信号S不会起作用。
位线上，若需要施加非0电压，则只选择第三操作电压V3；若需要施加0电压，则接地。
操作规则为，首先判断电压方向信号C，确定电压信号A和电压信号B的施加位置；其次判断电压信号A和电压信号B的大小；然后根据字线所要施加的电压判断字线电压选择信号S；最后施加操作电压，完成逻辑计算。
对于单输入NOT可逆逻辑功能，只有一个输入信号p。此时将控制信 号中的电压信号A和B、电压方向信号C用于逻辑操作。令电压信号A＝0，即电压信号A接地；令电压信号B＝1，且选择第四操作电压，即电压信号B为V4；令电压方向信号C＝p。
当输入信号p＝1时，电压方向信号C＝1，则电压信号A施加在单元所在字线，电压信号B施加在单元所在位线，阻变单元两端压降为-V4，使单元阻变至第一级电阻态00态，在单输入可逆逻辑功能中即为输出0；
当输入信号p＝0时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线，阻变单元两端压降为V4，使单元阻变至第四级电阻态11态，在单输入可逆逻辑功能中即为输出1；
根据逻辑真值表，实现了单输入NOT可逆逻辑功能。
对于二输入C-NOT可逆逻辑功能，有两个输入信号p和q。此时控制信号中的电压信号A和B、电压方向信号C以及字线电压选择信号S均用于逻辑操作。首先将单元所在字线接地，在单元所在位线上施加第四操作电压V4，将单元初始化为第一级电阻态00态；其次令电压信号A＝p，电压信号B＝q，电压方向信号C＝p，字线电压选择信号S＝p，进行逻辑操作。
当输入信号p＝0且q＝0时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线；电压信号A＝0，则位线接地；电压信号B＝0，则字线接地；字线上要施加0电压信号，则字线电压选择信号S不起作用；单元两端压降为0，不会使单元发生阻变，电阻态仍为初始化的00态，即为输出00；
当输入信号p＝0且q＝1时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线；电压信号A＝0，则位线接地；电压信号B＝1，则字线上施加非0电压信号；字线上要施加非0电压信号，且字线电压选择信号S＝0，则字线上的电压确定为第三操作电压V3；单元两端压降为V3，使单元发生阻变，电阻态变为10态，即为输出01；
当输入信号p＝1且q＝0时，电压方向信号C＝1，则电压信号A施加在单元所在字线，电压信号B施加在单元所在位线；电压信号A＝1，则字线上施加非0电压信号；电压信号B＝0，则位线接地；字线上要施加非0电压信号，且字线电压选择信号S＝1，则字线上的电压确定为第四操作电压V4；单元两端压降为V4，使单元发生阻变，电阻态变为11态，即为输出11；
当输入信号p＝1且q＝1时，电压方向信号C＝1，则电压信号A施加在单元所在字线，电压信号B施加在单元所在位线；电压信号A＝1，则字线上施加非0电压信号；电压信号B＝1，则位线上施加第三操作电压V3；字线上要施加非0电压信号，且字线电压选择信号S＝1，则字线上的电压确定为第四操作电压V4；单元两端压降为V4-V3＝V2，使单元发生阻变，电阻态变为01态，即为输出10；
根据逻辑真值表，实现了二输入C-NOT可逆逻辑功能。
如需读取逻辑输出结果，可在单元字线上施加Vread读取电压，将单元位线接地，可根据电流值大小判断单元所处的电阻态，即可获得输出结果。其中，Vread读取电压不足以使单元电阻态发生改变。
本发明根据阻变单元的叉杆阵列中的一个阻变单元多级电阻态特性，在一个单元中实现了单输入和二输入的可逆逻辑功能，相较于传统的基于CMOS晶体管的可逆逻辑门电路，极大地优化了电路结构；使用一个单元存储了二位输出信息，提高了信息存储能力；根据可逆逻辑中输入与输出一一对应的特性，只需要读取单元中存储的逻辑输出结果，即可推断出原始输入信息，无需额外的存储输入信息的过程与单元，节省了存储空间；逻辑计算过程中，计算结果直接以阻态的形式存储在阻变单元中，实现了存储与计算的融合，提高了计算效率并减少了计算功耗。
[附图说明]
图1为本发明提供的可逆逻辑电路的结构示意图；
图2为本发明提供的阻变单元四级阻态之间的转换关系示意图；
图3为本发明提供的阻变单元的I-V特性曲线图；
图4为本发明提供的单输入NOT可逆逻辑操作方法的逻辑真值表；
图5为本发明提供的二输入C-NOT可逆逻辑操作方法的逻辑真值表；
图6为本发明提供的单输入NOT可逆逻辑操作和二输入C-NOT可逆逻辑操作的流程示意图；
图7为本发明实施例一提供的单输入NOT可逆逻辑操作结果示意图；
图8为本发明实施例二提供的二输入C-NOT可逆逻辑操作结果示意图。
[具体实施方式]
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图，对本发明进行进一步详细说明。
图1为本发明实施例提供的可逆逻辑电路的阻变单元交叉杆阵列结构示意图。阻变单元交叉杆阵列由相互垂直的字线和位线以及阻变单元构成，每条字线和位线之间由一个阻变单元连接。其中，阻变单元的正极与字线相连，阻变单元的负极与位线相连。当有电流从阻变单元所在的位线流向字线，即从阻变单元负极流向正极时，阻变单元的阻值会变大；阻变单元具有一个最高阻值，当达到最高阻值时，即使再有电流从单元负极流向正极，也无法使单元阻值进一步升高。当有电流从阻变单元所在的字线流向位线，即从阻变单元正极流向负极时，阻变单元的阻值会变小；阻变单元具有一个最低阻值，当达到最低阻值时，即使再有电流从单元正极流向负极，也无法使单元阻值进一步降低。
图2为本实施例提供的阻变单元的四级电阻态以及电阻态之间的转换关系。四级电阻态分别为第一级电阻态00态、第二级电阻态01态、第三级电阻态10态、第四级电阻态11态，其中00态和11态也可用于单输入可逆逻辑功能的实现，对应二值信息高阻态0和低阻态1。
当阻变单元阻态处在01态、10态和11态时，在单元所在位线上施加第一操作电压V1，单元所在字线接地，此时单元两端压降为-V1，可使单元阻变至00态。当单元阻态处在00态时，在单元所在字线上施加第二操作电压V2，单元所在位线接地，此时单元两端压降为V2，可使单元阻变至01态；当单元阻态处在00态时，在单元所在字线上施加第三操作电压V3，单元所在位线接地，此时单元两端压降为V3，可使单元阻变至10态；当单元阻态处在00态时，在单元所在字线上施加第四操作电压V4，单元所在位线接地，此时单元两端压降为V4，可使单元阻变至11态。
所述的四种操作电压，在数学关系上满足：V1＝V4，V2+V3＝V4。
图3为本实施例提供的阻变单元的I-V特性曲线及操作电压的位置关系示意图。阻变单元的阻值随流经的电流变化而改变，施加的V2、V3、V4操作电压可以使单元的阻值显著降低，对应的操作电流显著变大；施加的-V1操作电压可以使单元的阻值升高到最大值，对应的操作电流最小。读取电压Vread相较于V1、V2、V3、V4电压非常小，几乎不会对阻变单元的阻值造成明显影响。V1、V2、V3、V4操作电压达到的四级电阻态位置关系也已标出。
图4为本发明实施例提供的单输入NOT可逆逻辑操作方法的逻辑真值表。当逻辑输入为0时，逻辑输出为1；当逻辑输入为1时，逻辑输出为0。输入与输出一一对应，由逻辑输出结果可以反向推断出输入信息。
图5为本发明实施例提供的二输入C-NOT可逆逻辑操作方法的逻辑真值表。当逻辑输入为00时，逻辑输出为00；当逻辑输入为01时，逻辑输出为01；当逻辑输入为10时，逻辑输出为11；当逻辑输入为11时，逻辑输出为10。输入与输出一一对应，由逻辑输出结果可以反向推断出输入信息。
图6为本发明的操作流程示意图。使用所述的阻变单元实现可逆逻辑功能时，对于不同的逻辑输入，遵循同一种操作规则。在这种操作规则中， 控制信号被引入。通过赋予控制信号以实际的逻辑输入值，实现不同操作电压的施加。
控制信号包括电压信号A和B、电压方向信号C和字线电压选择信号S。
对于电压信号A，A＝0时，选择0电压，即接地；A＝1时，选择非0电压V3或V4；
对于电压信号B，B＝0时，选择0电压，即接地；B＝1时，选择非0电压V3或V4；
对于电压方向信号C，C＝0时，将电压信号A施加在单元所在位线，将电压信号B施加在单元所在字线；C＝1时，将电压信号A施加在单元所在字线，将电压信号B施加在单元所在位线；
对于字线电压选择信号S，S＝0时，若字线上需要施加非0电压，则选择第三操作电压V3；S＝1时，若字线上需要施加非0电压，则选择第四操作电压V4；若字线上施加0电压，则字线电压选择信号S不会起作用。
位线上，若需要施加非0电压，则只选择第三操作电压V3；若需要施加0电压，则接地。
操作规则为，首先判断电压方向信号C，确定电压信号A和电压信号B的施加位置；其次判断电压信号A和电压信号B的大小；然后根据字线所要施加的电压判断字线电压选择信号S；最后施加操作电压，完成逻辑计算。
图7为本发明实施例一单输入NOT可逆逻辑操作示意图。对于单输入NOT可逆逻辑功能，只有一个输入信号p。此时将控制信号中的电压信号A和B、电压方向信号C用于逻辑操作。令电压信号A＝0，即电压信号A接地；令电压信号B＝1，且选择第四操作电压，即电压信号B为V4；令电压方向信号C＝p。
当输入信号p＝1时，电压方向信号C＝1，则电压信号A施加在单元所 在字线，电压信号B施加在单元所在位线，阻变单元两端压降为-V4，无论单元的初始阻态处在什么状态，都能使单元阻变至第一级电阻态00态，在单输入可逆逻辑功能中即为输出0；
当输入信号p＝0时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线，阻变单元两端压降为V4，无论单元的初始阻态处在什么状态，使单元阻变至第四级电阻态11态，在单输入可逆逻辑功能中即为输出1；
如需读取逻辑输出结果，可在单元字线上施加Vread读取电压，将单元位线接地，可根据电流值大小判断单元所处的电阻态，即可获得输出结果。根据逻辑真值表，实现了单输入NOT可逆逻辑功能。
图8为本发明实施例二二输入C-NOT可逆逻辑操作示意图。对于二输入C-NOT可逆逻辑功能，有两个输入信号p和q。此时控制信号中的电压信号A和B、电压方向信号C以及字线电压选择信号S均用于逻辑操作。首先将单元所在字线接地，在单元所在位线上施加第四操作电压V4，将单元初始化为第一级电阻态00态；其次令电压信号A＝p，电压信号B＝q，电压方向信号C＝p，字线电压选择信号S＝p，进行逻辑操作。
当输入信号p＝0且q＝0时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线；电压信号A＝0，则位线接地；电压信号B＝0，则字线接地；字线上要施加0电压信号，则字线电压选择信号S不起作用；单元两端压降为0，不会使单元发生阻变，电阻态仍为初始化的00态，即为输出00；
当输入信号p＝0且q＝1时，电压方向信号C＝0，则电压信号A施加在单元所在位线，电压信号B施加在单元所在字线；电压信号A＝0，则位线接地；电压信号B＝1，则字线上施加非0电压信号；字线上要施加非0电压信号，且字线电压选择信号S＝0，则字线上的电压确定为第三操作电压V3；单元两端压降为V3，使单元发生阻变，电阻态从初始的00态变为10 态，即为输出01；
当输入信号p＝1且q＝0时，电压方向信号C＝1，则电压信号A施加在单元所在字线，电压信号B施加在单元所在位线；电压信号A＝1，则字线上施加非0电压信号；电压信号B＝0，则位线接地；字线上要施加非0电压信号，且字线电压选择信号S＝1，则字线上的电压确定为第四操作电压V4；单元两端压降为V4，使单元发生阻变，电阻态从初始的00态变为11态，即为输出11；
当输入信号p＝1且q＝1时，电压方向信号C＝1，则电压信号A施加在单元所在字线，电压信号B施加在单元所在位线；电压信号A＝1，则字线上施加非0电压信号；电压信号B＝1，则位线上施加第三操作电压V3；字线上要施加非0电压信号，且字线电压选择信号S＝1，则字线上的电压确定为第四操作电压V4；单元两端压降为V4-V3＝V2，使单元发生阻变，电阻态从初始的00态变为01态，即为输出10；
如需读取逻辑输出结果，可在单元字线上施加Vread读取电压，将单元位线接地，可根据电流值大小判断单元所处的电阻态，即可获得输出结果。根据逻辑真值表，实现了二输入C-NOT可逆逻辑功能。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种可逆逻辑电路，其特征在于，包括：阻变单元、字线和位线；
    所述字线与所述位线相互垂直；
    所述阻变单元的正极与字线相连，所述阻变单元的负极与位线相连，每条字线和每条位线之间由一个所述阻变单元连接；
    所述阻变单元的正极作为第一输入端用于施加逻辑操作电压或者接地，所述阻变单元的负极作为第二输入端用于施加逻辑操作电压或者接地。
  2. 如权利要求1所述的可逆逻辑电路，其特征在于，工作时，施加不同逻辑操作电压所述阻变单元发生阻变行为：电流从所述阻变单元所在字线流向所述阻变单元所在位线时，所述阻变单元的电阻值降低；电流从所述阻变单元所在位线流向所述阻变单元所在字线时，所述阻变单元的电阻值升高。
  3. 如权利要求1所述的可逆逻辑电路，其特征在于，所述阻变单元具有四级电阻态；
    在所述第二输入端施加第一操作电压V1，所述第一输入端接地，所述阻变单元具有第一级电阻态，记为00态；
    当所述阻变单元处在00态时，在所述第一输入端施加第二操作电压V2，所述第二输入端接地，所述阻变单元具有第二级电阻态，记为01态；
    当所述阻变单元处在00态时，在所述第一输入端施加第三操作电压V3，所述第二输入端接地，所述阻变单元具有第三级电阻态，记为10态；
    当所述阻变单元处在00态时，在所述第一输入端施加第四操作电压V4，所述第二输入端接地，所述阻变单元具有第四级电阻态，记为11态。
  4. 如权利要求1所述的可逆逻辑电路，其特征在于，各逻辑操作电压数值上满足V1＝V4，V2+V3＝V4。
  5. 一种基于权利要求1-4所述的可逆逻辑电路实现数据读取功能的操 作方法，其特征在于，包括下述步骤：
    通过电压方向信号C施加第四操作电压V4；若C＝0，则在所述第一输入端施加第四操作电压V4，所述第二输入端接地；若C＝1，则在所述第二输入端施加第四操作电压V4，所述第一输入端接地；
    在所述第一输入端施加电压Vread，所述第二输入端接地，检测电路中的电流大小实现所述阻变单元中数据的读取；
    其中，Vread的电压幅值不超过50mV。
  6. 如权利要求5所述的操作方法，其特征在于，当检测的电流值依次从小到大，所述阻变单元分别处在00态、11态，对应读取结果分别为0、1。
  7. 一种基于权利要求1-4所述的可逆逻辑电路实现数据读取功能的操作方法，其特征在于，包括下述步骤：
    在所述第二输入端施加第一操作电压V1，所述第一输入端接地，所述阻变单元处于00态；
    通过电压方向信号C施加操作电压信号；若C＝0，则在所述第一输入端施加操作电压信号B，所述第二输入端施加操作电压信号A；若C＝1，则在所述第一输入端施加操作电压信号A，所述第二输入端施加操作电压信号B；
    若A＝1，根据电压选择信号S选择非0电压；若A＝0，接地；
    若B＝1，根据电压选择信号S选择非0电压；若B＝0，接地；
    若S＝1，施加第四操作电压V4；若S＝0，施加第三操作电压V3；
    在所述第一输入端施加电压Vread，所述第二输入端接地，检测电路中的电流大小实现所述阻变单元中数据的读取；
    其中，Vread的电压幅值不超过50mV。
  8. 如权利要求7所述的操作方法，其特征在于，当检测的电流值依次从小到大，所述阻变单元分别处在00态、01态、10态、11态，对应读取 结果分别为00、01、10、11。
  9. 一种基于权利要求1-4所述的可逆逻辑电路实现单输入NOT可逆逻辑功能的操作方法，其特征在于，包括下述步骤：
    赋予电压方向信号C以逻辑输入值p；
    若逻辑输入p＝0，则C＝0，在所述第一输入端施加第四操作电压V4，所述阻变单元所在位线接地，所述阻变单元阻变至11态，输出记为逻辑“1”；
    若逻辑输入p＝1，则C＝1，在所述第二输入端施加第四操作电压V4，所述阻变单元所在字线接地，所述阻变单元阻变至00态，输出记为逻辑“0”。
  10. 一种基于权利要求1-4所述的可逆逻辑电路实现二输入C-NOT可逆逻辑功能的操作方法，其特征在于，包括下述步骤：
    赋予电压方向信号C、操作电压信号A、操作电压信号B和电压选择信号S以逻辑输入值，即C＝p，A＝p，B＝q，S＝p；
    若逻辑输入为p＝0且q＝0，此时A＝0，B＝0，C＝0，S＝0，所述第一输入端和所述第二输入端均接地，所述阻变单元阻变至00态，输出记为逻辑“00”；
    若逻辑输入为p＝0且q＝1，此时A＝0，B＝1，C＝0，S＝0，所述第一输入端施加第三操作电压V3，所述第二输入端接地，所述阻变单元阻变至10态，输出记为逻辑“01”；
    若逻辑输入为p＝1且q＝0，此时A＝1，B＝0，C＝1，S＝1，所述第一输入端施加第四操作电压V4，所述第二输入端接地，所述阻变单元阻变至11态，输出记为逻辑“11”；
    若逻辑输入为p＝1且q＝1，此时A＝1，B＝1，C＝1，S＝1，所述第一输入端施加第四操作电压V4，所述第二输入端施加第三操作电压V3，所述阻变单元阻变至为01态，输出记为逻辑“10”。
PCT/CN2019/096068 2019-02-27 2019-07-16 一种可逆逻辑电路及其操作方法 Ceased WO2020173040A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/965,602 US11171650B2 (en) 2019-02-27 2019-07-16 Reversible logic circuit and operation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910145406.1A CN109905115B (zh) 2019-02-27 2019-02-27 一种可逆逻辑电路及其操作方法
CN201910145406.1 2019-02-27

Publications (1)

Publication Number Publication Date
WO2020173040A1 true WO2020173040A1 (zh) 2020-09-03

Family

ID=66945556

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/096068 Ceased WO2020173040A1 (zh) 2019-02-27 2019-07-16 一种可逆逻辑电路及其操作方法

Country Status (3)

Country Link
US (1) US11171650B2 (zh)
CN (1) CN109905115B (zh)
WO (1) WO2020173040A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109905115B (zh) * 2019-02-27 2020-08-04 华中科技大学 一种可逆逻辑电路及其操作方法
CN110572149B (zh) * 2019-08-09 2021-06-11 华中科技大学 一种Toffoli门电路及其操作方法
CN110827898B (zh) * 2019-10-21 2021-07-27 华中科技大学 一种基于忆阻器的电压-电阻式可逆逻辑电路及其操作方法
CN112466365B (zh) * 2020-12-09 2022-04-15 中国人民解放军国防科技大学 一种三维忆阻器状态逻辑电路及或非或逻辑实现方法
CN113376928B (zh) * 2021-06-15 2023-04-14 上海电子信息职业技术学院 一种集成光电子混合比特可逆逻辑门

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104898990A (zh) * 2015-06-05 2015-09-09 北京大学 运算存储阵列及其操作方法
US20160133836A1 (en) * 2014-11-11 2016-05-12 Sandisk 3D Llc High endurance non-volatile storage
CN106373611A (zh) * 2016-09-29 2017-02-01 华中科技大学 一种存储与计算阵列结构及其操作方法
CN109905115A (zh) * 2019-02-27 2019-06-18 华中科技大学 一种可逆逻辑电路及其操作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8541843B2 (en) * 2008-08-14 2013-09-24 Nantero Inc. Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same
KR101097435B1 (ko) * 2009-06-15 2011-12-23 주식회사 하이닉스반도체 멀티 레벨을 갖는 상변화 메모리 장치 및 그 구동방법
US9601692B1 (en) * 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8976577B2 (en) * 2011-04-07 2015-03-10 Tom A. Agan High density magnetic random access memory
US9853053B2 (en) * 2012-09-10 2017-12-26 3B Technologies, Inc. Three dimension integrated circuits employing thin film transistors
US9871077B2 (en) * 2013-12-06 2018-01-16 University Of Massachusetts Resistive memory device with semiconductor ridges
WO2015100586A1 (zh) * 2013-12-31 2015-07-09 北京大学 基于阻变器件的多位全加器及其操作方法
US9685954B2 (en) * 2014-03-09 2017-06-20 Technion Research & Development Foundation Ltd. Pure memristive logic gate
US9945727B2 (en) * 2014-12-10 2018-04-17 Robert Bosch Gmbh Resistive switching for MEMS devices
CN107112049A (zh) * 2014-12-23 2017-08-29 3B技术公司 采用薄膜晶体管的三维集成电路
US9570192B1 (en) * 2016-03-04 2017-02-14 Qualcomm Incorporated System and method for reducing programming voltage stress on memory cell devices
US9779808B2 (en) * 2016-03-07 2017-10-03 Toshiba Memory Corporation Resistance random access memory device and method for operating same
CN106158017B (zh) * 2016-06-20 2019-05-17 北京大学 阻变运算存储设备
KR102645776B1 (ko) * 2016-11-18 2024-03-11 에스케이하이닉스 주식회사 저항성 메모리 장치, 이를 위한 리드 회로 및 방법
CN208479595U (zh) * 2018-05-09 2019-02-05 福州大学 一种应用于可逆逻辑电路的dpg门电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160133836A1 (en) * 2014-11-11 2016-05-12 Sandisk 3D Llc High endurance non-volatile storage
CN104898990A (zh) * 2015-06-05 2015-09-09 北京大学 运算存储阵列及其操作方法
CN106373611A (zh) * 2016-09-29 2017-02-01 华中科技大学 一种存储与计算阵列结构及其操作方法
CN109905115A (zh) * 2019-02-27 2019-06-18 华中科技大学 一种可逆逻辑电路及其操作方法

Also Published As

Publication number Publication date
US20210218402A1 (en) 2021-07-15
CN109905115B (zh) 2020-08-04
CN109905115A (zh) 2019-06-18
US11171650B2 (en) 2021-11-09

Similar Documents

Publication Publication Date Title
WO2020173040A1 (zh) 一种可逆逻辑电路及其操作方法
CN108092658B (zh) 一种逻辑电路操作方法
CN104124960B (zh) 一种非易失性布尔逻辑运算电路及其操作方法
CN109994139B (zh) 一种基于单极性忆阻器的完备非易失逻辑实现方法及其应用
CN110569962B (zh) 一种基于1t1r存储器阵列的卷积计算加速器及其操作方法
CN116107963B (zh) 基于忆阻器的存内逻辑电路、存内逻辑计算系统及应用
CN114974337B (zh) 一种基于自旋磁随机存储器的时间域存内计算电路
CN111061454B (zh) 一种基于双极性忆阻器的逻辑实现方法
CN106374912A (zh) 一种逻辑运算电路与操作方法
CN110827898B (zh) 一种基于忆阻器的电压-电阻式可逆逻辑电路及其操作方法
CN106373611A (zh) 一种存储与计算阵列结构及其操作方法
CN110111827B (zh) 一种基于多个单值阻变存储器的多值阻变结构
CN110445489B (zh) 一种数位比较电路及其操作方法
CN113810043A (zh) 基于忆阻器的平衡三值译码器电路
CN113658625A (zh) 基于1t1r阵列的可重构状态逻辑操作电路及方法
CN113539327B (zh) 一种相变存储单元实现快速逻辑计算装置及数据检索方法
CN109524039B (zh) 一种忆阻器阻态数目扩展的结构及相关方法
CN113222131B (zh) 基于1t1r的可实现带符号权重系数的突触阵列电路
CN110768660A (zh) 一种基于忆阻器的可逆逻辑电路及操作方法
CN115035934A (zh) 存储器装置及其操作方法
CN110572149A (zh) 一种Toffoli门电路及其操作方法
CN114333944B (zh) 基于三值忆阻器交叉阵列的编码-存储-译码电路
CN112927738B (zh) 基于非易失器件的电路和电荷域存内计算方法
CN114721622B (zh) 基于忆阻器的加法器、驱动方法及电子设备
CN119513035B (zh) 一种基于dram的存内逻辑运算电路及系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19916750

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19916750

Country of ref document: EP

Kind code of ref document: A1