WO2020155411A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

Info

Publication number
WO2020155411A1
WO2020155411A1 PCT/CN2019/083133 CN2019083133W WO2020155411A1 WO 2020155411 A1 WO2020155411 A1 WO 2020155411A1 CN 2019083133 W CN2019083133 W CN 2019083133W WO 2020155411 A1 WO2020155411 A1 WO 2020155411A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
adjustment medium
array substrate
adjusting
medium layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/083133
Other languages
English (en)
French (fr)
Inventor
李迁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US16/496,421 priority Critical patent/US11307466B2/en
Publication of WO2020155411A1 publication Critical patent/WO2020155411A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
    • G02F1/133723—Polyimide, polyamide-imide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • This application relates to the field of display technology, in particular to an array substrate.
  • HVA(High Vertical Alignment (high vertical alignment) mode is mainly that negative liquid crystal rotates under the action of electric field force during the power-on process. After ultraviolet light is irradiated, a polymer film layer is formed on the alignment film, that is, the liquid crystal undergoes HVA process in A specific pretilt angle is formed on the alignment film.
  • the array substrate will have metal traces in the pixel electrode opening area.
  • a fringe electric field will be formed at this time, which will interfere with the rotation and alignment of the liquid crystal. effect. Due to the fringe electric field and the surrounding environment, dark lines will appear.
  • the purpose of the embodiments of the present application is to provide an array substrate to solve the technical problem of dark lines that are affected by the fringe electric field and the surrounding environment.
  • An embodiment of the application provides an array substrate, including:
  • An interlayer dielectric layer, the interlayer dielectric layer is disposed on the substrate and the gate metal layer;
  • An electrode layer, the electrode layer is arranged on the interlayer dielectric layer;
  • An alignment layer is disposed on the electrode layer, the alignment layer is a PI layer;
  • An adjustment medium layer is disposed in the region between the gate metal layer and the alignment layer and connected to the interlayer dielectric layer and the electrode layer, and the adjustment medium layer is used to reduce Parasitic capacitance between the gate metal layer and the electrode layer.
  • the dielectric constant of the adjustment dielectric layer is smaller than the dielectric constant of the interlayer dielectric layer; the adjustment dielectric layer is disposed on the substrate and the gate metal Layer coating, the upper surface of the adjustment medium layer is connected with the lower surface of the electrode layer and the lower surface of the alignment layer, and the periphery of the adjustment medium layer is connected with the interlayer dielectric layer.
  • the dielectric constant of the adjusting dielectric layer is 2 to 4.
  • the adjustment medium layer is a photoresist material.
  • the adjustment medium layer is coated with a photoresist material and formed by photolithography.
  • the dielectric constant of the adjusting dielectric layer is greater than the dielectric constant of the interlayer dielectric layer
  • the adjustment medium layer is opposite to the gate metal layer, the adjustment medium layer is disposed on the interlayer dielectric layer, and the periphery of the adjustment medium layer is connected to the electrode layer.
  • the upper surface is connected to the lower surface of the alignment layer.
  • the dielectric constant of the adjusting dielectric layer is greater than 10.
  • the interlayer dielectric layer is a silicon nitride layer.
  • the adjustment medium layer includes a first adjustment medium layer and a second adjustment medium layer
  • the second adjustment medium layer is disposed on the substrate and covers the gate metal layer, the upper surface of the second adjustment medium layer and the lower surface of the electrode layer, and the first adjustment medium layer
  • the lower surface of the second adjusting medium layer is connected with the interlayer dielectric layer, and the dielectric constant of the second adjusting medium layer is smaller than the dielectric constant of the interlayer dielectric layer;
  • the first adjustment medium layer is opposite to the gate metal layer, the first adjustment medium layer is disposed on the second adjustment medium layer, and the periphery of the first adjustment medium layer is connected to the electrode layer
  • the upper surface of the first adjusting medium layer is connected to the lower surface of the alignment layer; the dielectric constant of the first adjusting medium layer is greater than the dielectric constant of the interlayer dielectric layer.
  • the second adjusting dielectric layer is a silicon nitride layer with a dielectric constant of 6-8; the first adjusting dielectric layer is made of a non-metallic insulating material with a dielectric constant greater than 10. production.
  • the embodiment of the present application also provides an array substrate, including:
  • An interlayer dielectric layer, the interlayer dielectric layer is disposed on the substrate and the gate metal layer;
  • An electrode layer, the electrode layer is arranged on the interlayer dielectric layer;
  • An alignment layer is disposed on the electrode layer;
  • An adjustment medium layer is disposed in the region between the gate metal layer and the alignment layer and connected to the interlayer dielectric layer and the electrode layer, and the adjustment medium layer is used to reduce Parasitic capacitance between the gate metal layer and the electrode layer.
  • the dielectric constant of the adjustment dielectric layer is smaller than the dielectric constant of the interlayer dielectric layer; the adjustment dielectric layer is disposed on the substrate and the gate metal Layer coating, the upper surface of the adjustment medium layer is connected with the lower surface of the electrode layer and the lower surface of the alignment layer, and the periphery of the adjustment medium layer is connected with the interlayer dielectric layer.
  • the dielectric constant of the adjusting dielectric layer is 2 to 4.
  • the adjustment medium layer is a photoresist material.
  • the adjustment medium layer is coated with a photoresist material and formed by photolithography.
  • the dielectric constant of the adjusting dielectric layer is greater than the dielectric constant of the interlayer dielectric layer
  • the adjustment medium layer is opposite to the gate metal layer, the adjustment medium layer is disposed on the interlayer dielectric layer, and the periphery of the adjustment medium layer is connected to the electrode layer.
  • the upper surface is connected to the lower surface of the alignment layer.
  • the dielectric constant of the adjusting dielectric layer is greater than 10.
  • the interlayer dielectric layer is a silicon nitride layer.
  • the adjustment medium layer includes a first adjustment medium layer and a second adjustment medium layer
  • the second adjustment medium layer is disposed on the substrate and covers the gate metal layer, the upper surface of the second adjustment medium layer and the lower surface of the electrode layer, and the first adjustment medium layer
  • the lower surface of the second adjusting medium layer is connected with the interlayer dielectric layer, and the dielectric constant of the second adjusting medium layer is smaller than the dielectric constant of the interlayer dielectric layer;
  • the first adjustment medium layer is opposite to the gate metal layer, the first adjustment medium layer is disposed on the second adjustment medium layer, and the periphery of the first adjustment medium layer is connected to the electrode layer
  • the upper surface of the first adjusting medium layer is connected to the lower surface of the alignment layer; the dielectric constant of the first adjusting medium layer is greater than the dielectric constant of the interlayer dielectric layer.
  • the second adjusting dielectric layer is a silicon nitride layer with a dielectric constant of 6-8; the first adjusting dielectric layer is made of a non-metallic insulating material with a dielectric constant greater than 10. production.
  • the parasitic capacitance between the gate metal layer and the electrode layer is reduced by adopting the adjustment dielectric layer, so as to avoid the fringe electric field and the surrounding environment from causing dark lines, thereby improving the display quality.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the application.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • the embodiment of the present application provides an array substrate, including: a substrate; a gate metal layer on which the gate metal layer is arranged; an interlayer dielectric layer, which is arranged on the substrate and the gate metal layer; An electrode layer, the electrode layer is arranged on the interlayer dielectric layer; an alignment layer, the alignment layer is arranged on the electrode layer; and an adjustment medium layer, the adjustment medium layer is arranged on the gate metal layer and the area between the alignment layer and The interlayer dielectric layer and the electrode layer are connected, and the adjustment dielectric layer is used to reduce the parasitic capacitance between the gate metal layer and the electrode layer.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the application.
  • the array substrate 100 includes: a substrate 10, a gate metal layer 20, an interlayer dielectric layer 30, an electrode layer 40, an alignment layer 50, and a regulating dielectric layer 60.
  • the gate metal layer 20 is disposed on the substrate 10.
  • the interlayer dielectric layer 30 is disposed on the substrate 10 and the gate metal layer 20.
  • the electrode layer 40 is disposed on the interlayer dielectric layer 40.
  • the alignment layer 50 is disposed on the electrode layer 40.
  • the adjustment medium layer 60 is disposed on the substrate 10 and covers the gate metal layer 20. The upper surface of the adjustment medium layer 60 is connected to the lower surface of the electrode layer 40 and the lower surface of the alignment layer 50, and the surrounding and layer of the adjustment medium layer 60 The inter-dielectric layer 30 is connected.
  • the dielectric constant of the adjusting dielectric layer 60 is smaller than the dielectric constant of the interlayer dielectric layer 30.
  • the interlayer dielectric layer 30 is a silicon nitride layer, and its dielectric constant is 6-8.
  • the dielectric constant of the adjusting medium layer 60 is 2 to 4, and the adjusting medium layer 60 can be made of photoresist material.
  • the adjustment medium layer 60 is coated with a photoresist material and formed by photolithography.
  • the alignment layer 50 is a PI layer. The alignment layer 60 is used to align the liquid crystal layer.
  • the adjusting dielectric layer 60 is used to reduce the parasitic capacitance between the gate metal layer 20 and the electrode layer 40, thereby improving display quality.
  • the gate metal layer 20 is formed of a metal material and deposited by a physical vapor deposition method.
  • the interlayer dielectric layer 30 is formed by precipitation by chemical vapor deposition. Of course, in addition to silicon nitride, the interlayer dielectric layer 30 may also be made of materials such as silicon dioxide.
  • the electrode layer 40 includes a plurality of electrodes, which serve as pixel electrodes of the array substrate.
  • the electrode layer 40 can be made of ITO.
  • ITO is deposited to form an ITO layer, and then a photolithography method is used for patterning to obtain multiple pixel electrodes.
  • the parasitic capacitance between the gate metal layer and the electrode layer is reduced by adopting the adjustment dielectric layer, so as to avoid the fringe electric field and the surrounding environment from causing dark lines, thereby improving the display quality.
  • FIG. 2 is a schematic diagram of the second structure of the array substrate provided by the embodiments of the application.
  • the array substrate 200 includes: a substrate 10, a gate metal layer 20, an interlayer dielectric layer 30, an electrode layer 40, an alignment layer 50, and a regulating dielectric layer 60.
  • the gate metal layer 20 is disposed on the substrate 10.
  • the interlayer dielectric layer 30 is disposed on the substrate 10 and the gate metal layer 20.
  • the electrode layer 40 is disposed on the interlayer dielectric layer 40.
  • the alignment layer 50 is disposed on the electrode layer 40.
  • the adjusting medium layer 60 is opposite to the gate metal layer 20, the adjusting medium layer 60 is disposed on the interlayer dielectric layer 30, and the periphery of the adjusting medium layer 60 is connected with the electrode layer 40, and the upper surface of the adjusting medium layer 60 is connected to the alignment layer 50. The lower surface is connected.
  • the dielectric constant of the adjusting dielectric layer 60 is greater than the dielectric constant of the interlayer dielectric layer 30.
  • the interlayer dielectric layer 30 is a silicon nitride layer, and its dielectric constant is 6-8.
  • the dielectric constant of the adjusting dielectric layer 60 is greater than 10, and the adjusting dielectric layer 60 may be made of a non-metallic material with a dielectric constant greater than 10.
  • the alignment layer 50 is a PI layer.
  • the alignment layer 60 is used to align the liquid crystal layer.
  • the adjusting dielectric layer 60 is used to reduce the parasitic capacitance between the gate metal layer 20 and the electrode layer 40, thereby improving display quality.
  • the gate metal layer 20 is formed of a metal material and deposited by a physical vapor deposition method.
  • the interlayer dielectric layer 30 is formed by precipitation by chemical vapor deposition. Of course, in addition to silicon nitride, the interlayer dielectric layer 30 may also be made of materials such as silicon dioxide.
  • the electrode layer 40 includes a plurality of electrodes, which serve as pixel electrodes of the array substrate.
  • the electrode layer 40 can be made of ITO.
  • ITO is deposited to form an ITO layer, and then a photolithography method is used for patterning to obtain multiple pixel electrodes.
  • the parasitic capacitance between the gate metal layer and the electrode layer is reduced by adopting the adjustment dielectric layer, so as to avoid the fringe electric field and the surrounding environment from causing dark lines, thereby improving the display quality.
  • FIG. 3 is a schematic diagram of a third structure of the array substrate provided by the embodiment of the application.
  • the array substrate 300 includes: a substrate 10, a gate metal layer 20, an interlayer dielectric layer 30, an electrode layer 40, an alignment layer 50, and a regulating dielectric layer 60.
  • the gate metal layer 20 is disposed on the substrate 10.
  • the interlayer dielectric layer 30 is disposed on the substrate 10 and the gate metal layer 20.
  • the electrode layer 40 is disposed on the interlayer dielectric layer 40.
  • the alignment layer 50 is disposed on the electrode layer 40.
  • the adjusting medium layer 60 may include a first adjusting medium layer 61 and a second adjusting medium layer 62.
  • the second adjusting medium layer 62 is disposed on the substrate 10 and covers the gate metal layer 20.
  • the upper surface of the second adjusting medium layer 62 is connected to the lower surface of the electrode layer 40 and the lower surface of the first adjusting medium layer 61, and the periphery of the second adjusting medium layer 62 is connected to the interlayer dielectric layer 30.
  • the dielectric constant of the second adjusting dielectric layer 61 is smaller than the dielectric constant of the interlayer dielectric layer 30.
  • the second dielectric layer 62 is a silicon nitride layer with a dielectric constant of 6-8.
  • the first adjustment medium layer 61 is opposite to the gate metal layer 20, the first adjustment medium layer 61 is disposed on the second adjustment medium layer 62, and the periphery of the first adjustment medium layer 61 is connected to the electrode layer 40.
  • the upper surface of the layer 61 is connected to the lower surface of the alignment layer 50.
  • the dielectric constant of the first adjusting dielectric layer 61 is greater than the dielectric constant of the interlayer dielectric layer 30.
  • the first adjusting dielectric layer 61 is made of a non-metallic insulating material with a dielectric constant greater than 10.
  • the adjusting dielectric layer 60 is used to reduce the parasitic capacitance between the gate metal layer 20 and the electrode layer 40, thereby improving display quality.
  • the parasitic capacitance between the gate metal layer and the electrode layer is reduced by adopting the adjustment dielectric layer, so as to avoid the fringe electric field and the surrounding environment from causing dark lines, thereby improving the display quality.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

阵列基板(100)，通过采用调节介质层(60)来降低栅极金属层(20)与电极层(40)之间的寄生电容，从而避免边缘电场及周围环境的影响而出现暗纹现象，进而提高显示质量。

Description

阵列基板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板。
 背景技术
HVA(High Vertical Alignment，高垂直排列)模式主要是负性液晶在加电过程中，受到电场力的作用会发生转动，通过紫外光照射后在配向膜上形成一层聚合物膜层，即液晶经过HVA过程在配向膜上形成特定的预倾角。
一般阵列基板会在像素电极开口区存在金属走线，在HVA制程中，当在阵列基板和彩膜基板上同步加电固化液晶过程中，此时会形成边缘电场，从而干扰液晶的转动和配向效果。由于受边缘电场及周围环境的影响会出现暗纹现象。
 技术问题
本申请实施例的目的提供一种阵列基板，以解决受边缘电场及周围环境的影响会出现暗纹现象的技术问题。
 技术解决方案
本申请实施例提供了一种阵列基板，包括：
基板；
一栅极金属层，所述栅极金属层设置在所述基板上；
一层间介质层，所述层间介质层设置在所述基板以及所述栅极金属层上；
一电极层，所述电极层设置在所述层间介质层上；
一配向层，所述配向层设置在所述电极层上，所述配向层为PI层；以及
一调节介质层，所述调节介质层设置在所述栅极金属层以及所述配向层之间的区域并与所述层间介质层以及所述电极层相连，所述调节介质层用于降低所述栅极金属层与所述电极层之间的寄生电容。
在本申请所述的阵列基板中，所述调节介质层的介电常数小于所述层间介质层的介电常数；所述调节介质层设置于在所述基板上并将所述栅极金属层包覆，所述调节介质层的上表面与所述电极层的下表面以及所述配向层的下表面连接，所述调节介质层四周与所述层间介质层连接。
在本申请所述的阵列基板中，所述调节介质层的介电常数为2~4。
在本申请所述的阵列基板中，所述调节介质层为光刻胶材料。
在本申请所述的阵列基板中，所述调节介质层为采用光刻胶材料进行涂布并光刻形成。
在本申请所述的阵列基板中，所述调节介质层的介电常数大于所述层间介质层的介电常数；
所述调节介质层与所述栅极金属层相对，所述调节介质层设置在所述层间介质层上，且所述调节介质层的四周与所述电极层相连，所述调节介质层的上表面与所述配向层的下表面相连。
在本申请所述的阵列基板中，所述调节介质层的介电常数大于10。
在本申请所述的阵列基板中，所述层间介质层为氮化硅层。
在本申请所述的阵列基板中，所述调节介质层包括第一调节介质层以及第二调节介质层；
所述第二调节介质层设置在所述基板上并将所述栅极金属层包覆，所述第二调节介质层的上表面与所述电极层的下表面以及所述第一调节介质层的下表面连接，所述第二调节介质层四周与所述层间介质层连接，所述第二调节介质层的介电常数小于所述层间介质层的介电常数；
所述第一调节介质层与所述栅极金属层相对，所述第一调节介质层设置在所述第二调节介质层上，且所述第一调节介质层的四周与所述电极层相连，所述第一调节介质层的上表面与所述配向层的下表面相连；所述第一调节介质层的介电常数大于所述层间介质层的介电常数。
在本申请所述的阵列基板中，所述第二调节介质层为氮化硅层，其介电常数为6~8；所述第一调节介质层采用介电常数大于10的非金属绝缘材料制成。
本申请实施例还提供了一种阵列基板，包括：
基板；
一栅极金属层，所述栅极金属层设置在所述基板上；
一层间介质层，所述层间介质层设置在所述基板以及所述栅极金属层上；
一电极层，所述电极层设置在所述层间介质层上；
一配向层，所述配向层设置在所述电极层上；以及
一调节介质层，所述调节介质层设置在所述栅极金属层以及所述配向层之间的区域并与所述层间介质层以及所述电极层相连，所述调节介质层用于降低所述栅极金属层与所述电极层之间的寄生电容。
在本申请所述的阵列基板中，所述调节介质层的介电常数小于所述层间介质层的介电常数；所述调节介质层设置于在所述基板上并将所述栅极金属层包覆，所述调节介质层的上表面与所述电极层的下表面以及所述配向层的下表面连接，所述调节介质层四周与所述层间介质层连接。
在本申请所述的阵列基板中，所述调节介质层的介电常数为2~4。
在本申请所述的阵列基板中，所述调节介质层为光刻胶材料。
在本申请所述的阵列基板中，所述调节介质层为采用光刻胶材料进行涂布并光刻形成。
在本申请所述的阵列基板中，所述调节介质层的介电常数大于所述层间介质层的介电常数；
所述调节介质层与所述栅极金属层相对，所述调节介质层设置在所述层间介质层上，且所述调节介质层的四周与所述电极层相连，所述调节介质层的上表面与所述配向层的下表面相连。
在本申请所述的阵列基板中，所述调节介质层的介电常数大于10。
在本申请所述的阵列基板中，所述层间介质层为氮化硅层。
在本申请所述的阵列基板中，所述调节介质层包括第一调节介质层以及第二调节介质层；
所述第二调节介质层设置在所述基板上并将所述栅极金属层包覆，所述第二调节介质层的上表面与所述电极层的下表面以及所述第一调节介质层的下表面连接，所述第二调节介质层四周与所述层间介质层连接，所述第二调节介质层的介电常数小于所述层间介质层的介电常数；
所述第一调节介质层与所述栅极金属层相对，所述第一调节介质层设置在所述第二调节介质层上，且所述第一调节介质层的四周与所述电极层相连，所述第一调节介质层的上表面与所述配向层的下表面相连；所述第一调节介质层的介电常数大于所述层间介质层的介电常数。
在本申请所述的阵列基板中，所述第二调节介质层为氮化硅层，其介电常数为6~8；所述第一调节介质层采用介电常数大于10的非金属绝缘材料制成。
 有益效果
本申请实施例的阵列基板，通过采用调节介质层来降低栅极金属层与电极层之间的寄生电容，从而避免边缘电场及周围环境的影响而出现暗纹现象，进而提高显示质量。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的第一种结构示意图；
图2为本申请实施例提供的阵列基板的第二种结构示意图；以及
图3为本申请实施例提供的阵列基板的第三种结构示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
本申请实施例提供了一种阵列基板，包括：基板；一栅极金属层，栅极金属层设置在基板上；一层间介质层，层间介质层设置在基板以及栅极金属层上；一电极层，电极层设置在层间介质层上；一配向层，配向层设置在电极层上；以及一调节介质层，调节介质层设置在栅极金属层以及配向层之间的区域并与层间介质层以及电极层相连，调节介质层用于降低栅极金属层与电极层之间的寄生电容。
在一些实施例中，请参照图1，图1为本申请实施例提供的阵列基板的第一种结构示意图。如图1所示，该阵列基板100包括：基板10、一栅极金属层20、层间介质层30、电极层40、配向层50、调节介质层60。
其中，该栅极金属层20设置在基板10上。该层间介质层30设置在基板10以及栅极金属层20上。该电极层40设置在层间介质层40上。该配向层50设置在电极层40上。该调节介质层60设置在基板10上并将栅极金属层20包覆，调节介质层60的上表面与电极层40的下表面以及配向层50的下表面连接，调节介质层60四周与层间介质层30连接。
在本实施例中，该调节介质层60的介电常数小于该层间介质层30的介电常数。其中，该层间介质层30为氮化硅层，其介电常数为6~8。该调节介质层60的介电常数为2~4，该调节介质层60可以采用光刻胶材料。该调节介质层60为采用光刻胶材料进行涂布并光刻形成。该配向层50为PI层。该配向层60用于对液晶层进行配向。
该调节介质层60用于降低该栅极金属层20与该电极层40之间的寄生电容，从而提高显示质量。该栅极金属层20采用金属材料并采用物理气相沉淀法沉淀形成。该层间介质层30采用化学气相沉积法沉淀形成，当然，该层间介质层30除了采用氮化硅以外，还可以采用二氧化硅等材料。
其中，该电极层40包括多个电极，其作为阵列基板的像素电极。该电极层40可以采用ITO制成。制作该电极层40时，先采用ITO沉积形成一层ITO层，然后采用光刻法进行图形化处理，以得到多个像素电极。
本申请实施例的阵列基板，通过采用调节介质层来降低栅极金属层与电极层之间的寄生电容，从而避免边缘电场及周围环境的影响而出现暗纹现象，进而提高显示质量。
在另一些实施例中，请参照图2，图2为本申请实施例提供的阵列基板的第二种结构示意图。如图2所示，该阵列基板200包括：基板10、一栅极金属层20、层间介质层30、电极层40、配向层50、调节介质层60。
其中，该栅极金属层20设置在基板10上。该层间介质层30设置在基板10以及栅极金属层20上。该电极层40设置在层间介质层40上。该配向层50设置在电极层40上。该调节介质层60与栅极金属层20相对，调节介质层60设置在层间介质层30上，且调节介质层60的四周与电极层40相连，调节介质层60的上表面与配向层50的下表面相连。
在本实施例中，该调节介质层60的介电常数大于该层间介质层30的介电常数。其中，该层间介质层30为氮化硅层，其介电常数为6~8。该调节介质层60的介电常数大于10，该调节介质层60可以采用介电常数大于10的非金属材料。该配向层50为PI层。该配向层60用于对液晶层进行配向。
该调节介质层60用于降低该栅极金属层20与该电极层40之间的寄生电容，从而提高显示质量。该栅极金属层20采用金属材料并采用物理气相沉淀法沉淀形成。该层间介质层30采用化学气相沉积法沉淀形成，当然，该层间介质层30除了采用氮化硅以外，还可以采用二氧化硅等材料。
其中，电极层40包括多个电极，其作为阵列基板的像素电极。该电极层40可以采用ITO制成。制作该电极层40时，先采用ITO沉积形成一层ITO层，然后采用光刻法进行图形化处理，以得到多个像素电极。
本申请实施例的阵列基板，通过采用调节介质层来降低栅极金属层与电极层之间的寄生电容，从而避免边缘电场及周围环境的影响而出现暗纹现象，进而提高显示质量。
在另一些实施例中，请参照图3，图3为本申请实施例提供的阵列基板的第三种结构示意图。如图3所示，该阵列基板300包括：基板10、一栅极金属层20、层间介质层30、电极层40、配向层50、调节介质层60。
其中，该栅极金属层20设置在基板10上。该层间介质层30设置在基板10以及栅极金属层20上。该电极层40设置在层间介质层40上。该配向层50设置在电极层40上。
进一步的，该调节介质层60可以包括第一调节介质层61以及第二调节介质层62。该第二调节介质层62设置在基板10上并将栅极金属层20包覆。该第二调节介质层62的上表面与电极层40的下表面以及第一调节介质层61的下表面连接，第二调节介质层62四周与层间介质层30连接。该第二调节介质层61的介电常数小于该层间介质层30的介电常数。该第二介质层62为氮化硅层，其介电常数为6~8。
该第一调节介质层61与栅极金属层20相对，第一调节介质层61设置在第二调节介质层62上，且第一调节介质层61的四周与电极层40相连，第一调节介质层61的上表面与配向层50的下表面相连。该第一调节介质层61的介电常数大于该层间介质层30的介电常数。该第一调节介质层61采用介电常数大于10的非金属绝缘材料制成。
该调节介质层60用于降低该栅极金属层20与该电极层40之间的寄生电容，从而提高显示质量。
本申请实施例的阵列基板，通过采用调节介质层来降低栅极金属层与电极层之间的寄生电容，从而避免边缘电场及周围环境的影响而出现暗纹现象，进而提高显示质量。
以上对本申请实施方式提供的阵列基板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    基板；
    一栅极金属层，所述栅极金属层设置在所述基板上；
    一层间介质层，所述层间介质层设置在所述基板以及所述栅极金属层上；
    一电极层，所述电极层设置在所述层间介质层上；
    一配向层，所述配向层设置在所述电极层上，所述配向层为PI层；以及
    一调节介质层，所述调节介质层设置在所述栅极金属层以及所述配向层之间的区域并与所述层间介质层以及所述电极层相连，所述调节介质层用于降低所述栅极金属层与所述电极层之间的寄生电容。
  2. 根据权利要求1所述的阵列基板，其中，所述调节介质层的介电常数小于所述层间介质层的介电常数；所述调节介质层设置于在所述基板上并将所述栅极金属层包覆，所述调节介质层的上表面与所述电极层的下表面以及所述配向层的下表面连接，所述调节介质层四周与所述层间介质层连接。
  3. 根据权利要求2所述的阵列基板，其中，所述调节介质层的介电常数为2~4。
  4. 根据权利要求3所述的阵列基板，其中，所述调节介质层为光刻胶材料。
  5. 根据权利要求4所述的阵列基板，其中，所述调节介质层为采用光刻胶材料进行涂布并光刻形成。
  6. 根据权利要求1所述的阵列基板，其中，所述调节介质层的介电常数大于所述层间介质层的介电常数；
    所述调节介质层与所述栅极金属层相对，所述调节介质层设置在所述层间介质层上，且所述调节介质层的四周与所述电极层相连，所述调节介质层的上表面与所述配向层的下表面相连。
  7. 根据权利要求6所述的阵列基板，其中，所述调节介质层的介电常数大于10。
  8. 根据权利要求1所述的阵列基板，其中，所述层间介质层为氮化硅层。
  9. 根据权利要求1所述的阵列基板，其中，所述调节介质层包括第一调节介质层以及第二调节介质层；
    所述第二调节介质层设置在所述基板上并将所述栅极金属层包覆，所述第二调节介质层的上表面与所述电极层的下表面以及所述第一调节介质层的下表面连接，所述第二调节介质层四周与所述层间介质层连接，所述第二调节介质层的介电常数小于所述层间介质层的介电常数；
    所述第一调节介质层与所述栅极金属层相对，所述第一调节介质层设置在所述第二调节介质层上，且所述第一调节介质层的四周与所述电极层相连，所述第一调节介质层的上表面与所述配向层的下表面相连；所述第一调节介质层的介电常数大于所述层间介质层的介电常数。
  10. 根据权利要求9所述的阵列基板，其中，所述第二调节介质层为氮化硅层，其介电常数为6~8；所述第一调节介质层采用介电常数大于10的非金属绝缘材料制成。
  11. 一种阵列基板，其包括：
    基板；
    一栅极金属层，所述栅极金属层设置在所述基板上；
    一层间介质层，所述层间介质层设置在所述基板以及所述栅极金属层上；
    一电极层，所述电极层设置在所述层间介质层上；
    一配向层，所述配向层设置在所述电极层上；以及
    一调节介质层，所述调节介质层设置在所述栅极金属层以及所述配向层之间的区域并与所述层间介质层以及所述电极层相连，所述调节介质层用于降低所述栅极金属层与所述电极层之间的寄生电容。
  12. 根据权利要求11所述的阵列基板，其中，所述调节介质层的介电常数小于所述层间介质层的介电常数；所述调节介质层设置于在所述基板上并将所述栅极金属层包覆，所述调节介质层的上表面与所述电极层的下表面以及所述配向层的下表面连接，所述调节介质层四周与所述层间介质层连接。
  13. 根据权利要求12所述的阵列基板，其中，所述调节介质层的介电常数为2~4。
  14. 根据权利要求13所述的阵列基板，其中，所述调节介质层为光刻胶材料。
  15. 根据权利要求14所述的阵列基板，其中，所述调节介质层为采用光刻胶材料进行涂布并光刻形成。
  16. 根据权利要求11所述的阵列基板，其中，所述调节介质层的介电常数大于所述层间介质层的介电常数；
    所述调节介质层与所述栅极金属层相对，所述调节介质层设置在所述层间介质层上，且所述调节介质层的四周与所述电极层相连，所述调节介质层的上表面与所述配向层的下表面相连。
  17. 根据权利要求16所述的阵列基板，其中，所述调节介质层的介电常数大于10。
  18. 根据权利要求11所述的阵列基板，其中，所述层间介质层为氮化硅层。
  19. 根据权利要求11所述的阵列基板，其中，所述调节介质层包括第一调节介质层以及第二调节介质层；
    所述第二调节介质层设置在所述基板上并将所述栅极金属层包覆，所述第二调节介质层的上表面与所述电极层的下表面以及所述第一调节介质层的下表面连接，所述第二调节介质层四周与所述层间介质层连接，所述第二调节介质层的介电常数小于所述层间介质层的介电常数；
    所述第一调节介质层与所述栅极金属层相对，所述第一调节介质层设置在所述第二调节介质层上，且所述第一调节介质层的四周与所述电极层相连，所述第一调节介质层的上表面与所述配向层的下表面相连；所述第一调节介质层的介电常数大于所述层间介质层的介电常数。
  20. 根据权利要求19所述的阵列基板，其中，所述第二调节介质层为氮化硅层，其介电常数为6~8；所述第一调节介质层采用介电常数大于10的非金属绝缘材料制成。
PCT/CN2019/083133 2019-01-29 2019-04-18 阵列基板 Ceased WO2020155411A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/496,421 US11307466B2 (en) 2019-01-29 2019-04-18 Array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910086223.7A CN109683412A (zh) 2019-01-29 2019-01-29 阵列基板
CN201910086223.7 2019-01-29

Publications (1)

Publication Number Publication Date
WO2020155411A1 true WO2020155411A1 (zh) 2020-08-06

Family

ID=66194960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/083133 Ceased WO2020155411A1 (zh) 2019-01-29 2019-04-18 阵列基板

Country Status (3)

Country Link
US (1) US11307466B2 (zh)
CN (1) CN109683412A (zh)
WO (1) WO2020155411A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840121A (zh) * 2009-03-20 2010-09-22 北京京东方光电科技有限公司 阵列基板及其制造方法
CN202049316U (zh) * 2011-04-12 2011-11-23 京东方科技集团股份有限公司 薄膜晶体管阵列基板、液晶面板和显示设备
KR20120072579A (ko) * 2010-12-24 2012-07-04 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
CN102854678A (zh) * 2012-09-11 2013-01-02 友达光电股份有限公司 一种可提高画面解析度的立体显示设备及其制造方法
CN104155818A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 一种阵列基板及显示面板
US20150255029A1 (en) * 2014-03-07 2015-09-10 Semiconductor Energy Laboratory Co., Ltd. Display device, display module including the display device, and electronic device including the display device or the display module
CN107085335A (zh) * 2017-04-20 2017-08-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3362662B2 (ja) * 1998-03-11 2003-01-07 日本電気株式会社 半導体装置の製造方法
EP1361619A3 (en) * 2002-05-09 2007-08-15 Konica Corporation Organic thin-film transistor, organic thin-film transistor sheet and manufacturing method thereof
US7037767B2 (en) * 2003-03-24 2006-05-02 Konica Minolta Holdings, Inc. Thin-film transistor, thin-film transistor sheet and their manufacturing method
CN101221328B (zh) * 2007-01-11 2010-05-26 上海天马微电子有限公司 液晶显示装置及其制造方法
CN101995713B (zh) * 2009-08-21 2012-08-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102484202A (zh) * 2009-09-05 2012-05-30 默克专利股份有限公司 用于有机电子器件的可溶液加工的钝化层
TWI504981B (zh) * 2013-02-22 2015-10-21 Innolux Corp 液晶顯示面板
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN104730782B (zh) * 2015-04-01 2018-03-27 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置
US10147745B2 (en) 2015-04-01 2018-12-04 Shanghai Tianma Micro-electronics Co., Ltd. Array substrate, display panel and display device
CN105140237B (zh) * 2015-08-04 2018-06-12 武汉华星光电技术有限公司 阵列基板及其制备方法以及液晶显示器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840121A (zh) * 2009-03-20 2010-09-22 北京京东方光电科技有限公司 阵列基板及其制造方法
KR20120072579A (ko) * 2010-12-24 2012-07-04 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
CN202049316U (zh) * 2011-04-12 2011-11-23 京东方科技集团股份有限公司 薄膜晶体管阵列基板、液晶面板和显示设备
CN102854678A (zh) * 2012-09-11 2013-01-02 友达光电股份有限公司 一种可提高画面解析度的立体显示设备及其制造方法
US20150255029A1 (en) * 2014-03-07 2015-09-10 Semiconductor Energy Laboratory Co., Ltd. Display device, display module including the display device, and electronic device including the display device or the display module
CN104155818A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 一种阵列基板及显示面板
CN107085335A (zh) * 2017-04-20 2017-08-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法

Also Published As

Publication number Publication date
US11307466B2 (en) 2022-04-19
CN109683412A (zh) 2019-04-26
US20210405424A1 (en) 2021-12-30

Similar Documents

Publication Publication Date Title
CN104298040B (zh) 一种coa基板及其制作方法和显示装置
WO2017008370A1 (zh) 阵列彩膜集成式液晶显示面板的制作方法及其结构
WO2017049842A1 (zh) 阵列基板及其制作方法、显示装置
WO2017117961A1 (zh) 显示面板及其制备方法、显示装置
CN113485039B (zh) 阵列基板和显示面板
WO2020019492A1 (zh) 阵列基板及其制备方法
WO2017016014A1 (zh) Coa阵列基板及液晶面板
CN106298811B (zh) 阵列基板及其制备方法、显示装置
WO2020228168A1 (zh) 阵列基板及其制作方法
WO2021068316A1 (zh) 一种显示面板及其制作方法
CN106229318A (zh) Coa型阵列基板及其制作方法
WO2020073383A1 (zh) 一种显示面板和显示面板的制程
WO2014131238A1 (zh) 阵列基板及其制作方法、显示面板及其制作方法
WO2019056993A1 (zh) 显示面板及其制备方法和显示装置
TWI703371B (zh) 顯示面板
US9690146B2 (en) Array substrate, its manufacturing method, and display device
CN104183607A (zh) 阵列基板及其制造方法、显示装置
CN104076550A (zh) 彩膜阵列基板、显示装置及彩膜阵列基板的制作方法
CN108257976A (zh) Tft基板及其制作方法
JP2017187530A (ja) 液晶表示装置
CN106773205B (zh) 显示面板及其制作方法以及显示装置
CN103135301B (zh) 一种薄膜晶体管液晶显示器阵列基板
CN104952887A (zh) 一种阵列基板及其制备方法、显示装置
CN107170754A (zh) 显示装置、阵列基板及阵列基板制作方法
CN103996657B (zh) 一种薄膜晶体管基板及其制作方法和液晶显示器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19912568

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19912568

Country of ref document: EP

Kind code of ref document: A1