WO2020019492A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2020019492A1
WO2020019492A1 PCT/CN2018/108068 CN2018108068W WO2020019492A1 WO 2020019492 A1 WO2020019492 A1 WO 2020019492A1 CN 2018108068 W CN2018108068 W CN 2018108068W WO 2020019492 A1 WO2020019492 A1 WO 2020019492A1
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common electrode
substrate
dbs common
color
layer
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PCT/CN2018/108068
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English (en)
French (fr)
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宋利旺
李朝晖
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/321,464 priority Critical patent/US11088177B2/en
Publication of WO2020019492A1 publication Critical patent/WO2020019492A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof.
  • Liquid crystal display (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. Such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or laptop screen.
  • LCD Liquid Crystal Display
  • PDA personal digital assistant
  • digital camera computer screen or laptop screen.
  • a liquid crystal display device includes a casing, a liquid crystal panel provided in the casing, and a backlight module provided in the casing.
  • the structure of the liquid crystal panel is mainly composed of a thin film transistor array (TFT array) substrate, a color filter (CF) substrate, and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates. Its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on two glass substrates, and refracting the light of the backlight module to generate a picture.
  • TFT array thin film transistor array
  • CF color filter
  • Liquid Crystal Layer liquid crystal layer
  • COA Color Filter On Array
  • DBS Data and BM saving
  • ITO Indium Tin Oxide
  • COM common electrode
  • AMLCD active matrix liquid crystal display
  • DBS Data BM saving
  • COA color filter on array
  • the array substrate mainly includes: a substrate (not shown); a plurality of data lines 20 and a plurality of scan lines 10 disposed on one side of the substrate, which are defined by the plurality of data lines 20 and the plurality of scan lines 10.
  • a plurality of sub-pixel regions, the plurality of data lines 20 and the plurality of scanning lines 10 are insulated from each other; a color resist layer located on the same side of the substrate as the plurality of data lines 20 and the plurality of scanning lines 10
  • the color resist layer includes a plurality of color resists 30, and two adjacent color resists 30 have overlapping areas corresponding to data line areas; the overlapping areas of the color resist layers are away from the substrate by one DBS common electrode traces 40 are provided on the side to shield the data lines 20.
  • the TFT array provided on the substrate mainly includes horizontal scanning lines 10 and vertical data lines 20, and a color resist 30 and a pixel electrode (not shown) are provided in a sub-pixel area defined by the crossing scanning lines 10 and the data lines 20. ), For example, three RGB color resists 30; horizontally adjacent color resists 30 are connected and overlapped with each other in the data line area (indicated by dotted lines in FIG. 1A), and vertical adjacent color resists 30 are provided in the scan line area Black matrix 50; DBS common electrode traces 40 are arranged in parallel above the data lines 20, and the width of the DBS common electrode traces 40 is slightly wider than that of the data lines 20, and is used for light shielding in liquid crystal displays.
  • FIG. 1B it is a schematic cross-sectional view at the A-A position in FIG. 1A, and a structure not shown in FIG. 1A is added.
  • a color resistor 30 is prepared on the source 80 of the TFT array.
  • the color resistor 30 is provided with a DBS common electrode trace 40 and a pixel electrode 60.
  • the DBS common electrode trace 40 and the common electrode 70 on the opposite substrate are usually arranged at a potential of Equipotential so that the liquid crystal molecules 90 remain undeflected during operation. Because the two colors of the color resist 30 overlap, a bump is generated, so that the liquid crystal molecules 90 at the position of the DBS common electrode trace 40 at the color resist 30 overlap due to the terrain and the positive electric field or side formed by the upper and lower substrates at this position. Light leakage occurs to the electric field.
  • an object of the present invention is to provide an array substrate and a method for manufacturing the same, which can reduce light leakage at the DBS common electrode traces where the color resist overlaps.
  • an array substrate including: a substrate;
  • a DBS common electrode trace is located on the side of the overlapping area of the color resist layer facing away from the substrate to shield the data line.
  • An edge of the DBS common electrode trace is provided with a uniform slit parallel to the scanning line direction.
  • one side edge of the DBS common electrode trace is provided with the slit.
  • the two sides of the DBS common electrode wiring are provided with the slits.
  • the two sides of the DBS common electrode trace are symmetrically provided with the slits.
  • the two sides of the DBS common electrode trace are asymmetrically provided with the slits.
  • the longitudinal distribution ranges of the slits on both sides of the DBS common electrode trace are merged to cover the sub-pixel area where the DBS common electrode trace is located.
  • the sub-pixel region is provided with a pixel electrode.
  • the invention also provides a method for preparing an array substrate, including:
  • An ITO film is formed on the color resist, and the patterned ITO film forms a pixel electrode and a DBS common electrode trace.
  • the edge of the DBS common electrode trace is provided with a uniform slit parallel to the scanning line direction; the pixel electrode passes through the via hole. Connected to the drain in the TFT array.
  • the step of preparing a TFT array on the substrate side includes:
  • a passivation layer is formed on the source and drain.
  • the array substrate and the preparation method thereof of the present invention can reduce light leakage at the DBS common electrode traces at the overlapping position of color resistance, improve color gamut and contrast, and improve product quality.
  • 1A is a schematic top view of a conventional array substrate
  • FIG. 1B is a schematic cross-sectional view at the A-A position in FIG. 1A;
  • FIG. 2A is a schematic top view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2B is a schematic diagram of a DBS common electrode trace in FIG. 2A;
  • 3A is a schematic top view of another preferred embodiment of an array substrate according to the present invention.
  • Fig. 3B is a schematic cross-sectional view at the B-B position in Fig. 3A.
  • FIG. 2A is a schematic top view of a preferred embodiment of an array substrate of the present invention
  • FIG. 2B is a schematic diagram of a pattern of DBS common electrode traces in FIG. 2A
  • the array substrate of this preferred embodiment mainly includes: a substrate (not shown); a plurality of data lines 20 and a plurality of scan lines 10 arranged on one side of the substrate, and the plurality of data lines 20 and the plurality of data lines 20
  • the plurality of scanning lines 10 define a plurality of sub-pixel regions, and the plurality of data lines 20 and the plurality of scanning lines 10 are insulated from each other; they are located on the same substrate as the plurality of data lines 20 and the plurality of scanning lines 10
  • a color resist layer on the side, the color resist layer includes a plurality of color resists 30, and two adjacent color resists 30 have an overlap region corresponding to a data line region; the overlap region of the color resist layer is located
  • a DBS common electrode trace 41 is provided on a side facing away from the substrate to shield
  • the pixel structure included in the array substrate mainly includes: a TFT array provided on the substrate includes horizontal scanning lines 10 and vertical data lines 20, and is arranged in a sub-pixel area defined by the intersecting scanning lines 10 and the data lines 20. There are color resists 30 and pixel electrodes (not shown), such as three RGB color resists 30; laterally adjacent color resists 30 are connected and overlapped with each other in the data line area (indicated by dotted lines in FIG.
  • a black matrix 50 is provided in the scanning line area between the resistors 30; a DBS common electrode trace 41 is provided parallel to the data line 20 at the overlap of the color resistor 30 above the data line 20 to shield the data line 20, and the DBS common electrode trace 41
  • the width is slightly wider than the data line 20, which is used to achieve light shielding in the liquid crystal display; the edge of the DBS common electrode trace 41 is provided with a uniform slit 100 parallel to the scanning line direction.
  • the slits 100 are disposed on the edges of each side of the upper and lower positions of the DBS common electrode wiring 41; the present invention can form a slit pattern of the DBS common electrode wiring 41 through a mask definition method
  • the azimuth angles of the pattern are 0 ° and 180 °, respectively.
  • the opening direction of the slit 100 is parallel to the scanning line direction, and can be oriented in two directions on both sides.
  • FIG. 3A is a schematic top view of another preferred embodiment of an array substrate of the present invention.
  • the structure of the preferred embodiment is substantially the same as that in FIG. 2A.
  • the array substrate of the preferred embodiment mainly includes: a substrate (not shown); a plurality of data lines 20 and a plurality of data lines 20 disposed on one side of the substrate.
  • the plurality of data lines 20 and the plurality of scan lines 10 define a plurality of sub-pixel regions, the plurality of data lines 20 and the plurality of scan lines 10 are insulated from each other; and the plurality of data
  • the color resist layer on the same side of the substrate as the line 20 and the plurality of scan lines 10 includes a plurality of color resists 30, and two adjacent color resists 30 have a region corresponding to a data line
  • An overlap region of the color resist layer is provided on the side of the color resist layer facing away from the substrate, and a DBS common electrode trace 42 is provided to shield the data line 20, and an edge of the DBS common electrode trace 42 is provided in parallel to the scanning.
  • DBS common electrode traces 42 are provided parallel to the data lines 20 to shield the data lines 20 at the intersection of the color resistance 30 above the data lines 20, and the edges of the DBS common electrode traces 42 are provided with uniform slits 100 parallel to the scanning line direction.
  • the slits 100 are symmetrically disposed on both sides of the DBS common electrode wiring 42, and the slits 100 are formed on both sides to improve the liquid crystal control effect of the DBS common electrode wiring 42.
  • FIG. 3B is a schematic cross-sectional view of the position B-B in FIG. 3A of the present invention, and a structure not shown in FIG. 3A is added.
  • a color resistor 30 is prepared on the source electrode 80 of the TFT array.
  • the color resistor 30 is provided with a DBS common electrode trace 42 and a pixel electrode 60.
  • the electric field between the pixel electrode 60 and the common electrode 70 deflects the liquid crystal molecules 91 during operation, and the DBS common
  • the electrode traces 42 and the common electrode 70 on the opposite substrate are usually set to an equal potential in order to keep the liquid crystal molecules 90 at a position where the color resistance 30 overlaps during operation without deflection.
  • the slits 100 on the DBS common electrode traces 42 form azimuth angles of 0 ° and 180 °, thereby improving the liquid crystal control effect of the DBS common electrode traces 42 and eliminating the forward electric field or Light leakage due to lateral electric field.
  • the slits on the DBS common electrode traces can also adopt other designs, as long as the effect of controlling the liquid crystal by the DBS common electrode traces can be improved.
  • the DBS common electrode traces can be provided with slits on both sides, and the positions of the slits on both sides are asymmetric; or the DBS common electrode traces can be provided with slits on only one edge; DBS common electrode traces
  • the vertical distribution range of the slits on both sides is merged throughout the sub-pixel area where the DBS common electrode traces are located to meet the needs of controlling liquid crystals.
  • the invention also provides a method for preparing a corresponding array substrate, which mainly includes:
  • the TFT array can use the existing TFT array structure
  • vias in the color resist after the RGB color resist is completed, vias are formed by dry etching or wet etching to expose the passivation layer of the TFT array; the passivation layer further forms vias for connecting the pixel electrode to the TFT electrode;
  • the pattern of the DBS common electrode traces can be designed according to the previous embodiment, and a slit pattern is formed by a mask definition method.
  • An ITO film is formed by sputtering, and a pixel electrode and a DBS common electrode wiring pattern are formed by a wet etching process.
  • the TFT array can be prepared by a general TFT manufacturing process, and the preparation process is Metal1- (GI + a-Si + n + Si) -Metal 2-PV1; mainly including:
  • GI gate insulating layer
  • an ohmic contact layer (n + Si); an ohmic contact layer can be formed on the active layer by chemical vapor deposition;
  • Source / drain metal layer Metal
  • Forming a source / drain metal layer (Metal) forming a source / drain metal layer on the ohmic contact layer, and then patterning the source / drain metal layer to obtain a source / drain;
  • a passivation layer (PV1) is formed on the source and drain.
  • the array substrate and the preparation method thereof of the present invention can reduce light leakage at the DBS common electrode traces at the overlapping position of color resistance, improve color gamut and contrast, and improve product quality.

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Abstract

一种阵列基板及其制备方法。该阵列基板包括：基板；位于所述基板一侧交叉设置的多条数据线（20）和多条扫描线（10），所述多条数据线（20）和所述多条扫描线（10）限定出多个子像素区域，所述多条数据线（20）和所述多条扫描线（10）相互绝缘；与所述多条数据线（20）和所述多条扫描线（10）位于所述基板同一侧的色阻层，所述色阻层包括多个色阻（30），且相邻的两个所述色阻（30）具有对应于数据线区域的交叠区域；位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线（41、42）以遮蔽数据线（20），所述DBS公共电极走线（41、42）的边缘设有平行于扫描线（10）方向的均匀狭缝（100）。该阵列基板及其制备方法能够降低色阻交叠位置DBS公共电极走线（41、42）处漏光，提高色域及对比度，提升产品品质。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
通常液晶显示装置包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。其中，液晶面板的结构主要是由薄膜晶体管阵列(Thin Film Transistor Array，TFT Array)基板、彩色滤光片(Color Filter，CF)基板以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
COA(Color filter on Array)技术是一种将彩色滤光层即红(R)、绿(G)、蓝(B)色阻直接制作在阵列基板上的集成技术。目前在COA技术之上，DBS(Data BM saving)的像素设计也越来越多的被采用，在数据线上方覆盖ITO(氧化铟锡)走线，ITO走线的宽度略宽于数据线，这些ITO走线与公共电极(COM)在电位上通常设置成等电位，在面板正常工作时，这些ITO走线与公共电极形成的电场可以使液晶分子保持不偏转的状态，从而起到遮光的目的。
AMLCD(有源矩阵液晶显示器)曲面面板设计中通常采用DBS(Data BM saving)设计和COA(color filter on array)技术来提高开口率，降低寄生电容；但是由于地形及色阻流平性差异会使得相邻各色阻之间经常存在交叠区域，在交叠处产生凸起，形成牛角地形，平坦度变差；牛角地形会导致液晶极角发生变化，该位置处液晶非垂直排布，这样就会在色阻交叠位置发生漏光现象，影响面板色度及对比度等特性参数。
如图1A所示，其为一种现有阵列基板俯视示意图。该阵列基板主要包括：基板(图未示)；位于所述基板一侧交叉设置的多条数据线20和多条扫描线10，所述多条数据线20和所述多条扫描线10限定出多个子像素区域，所述多条数据线20和所述多条扫描线10相互绝缘；与所述多条数据线20和所述多条扫描线10位于所述基板同一侧的色阻层，所述色阻层包 括多个色阻30，且相邻的两个所述色阻30具有对应于数据线区域的交叠区域；位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线40以遮蔽数据线20。
设于基板上的TFT阵列主要包括横向的扫描线10和纵向的数据线20，在由交叉的扫描线10和数据线20所限定的子像素区域中设有色阻30以及像素电极(图未示)，例如RGB三种色阻30；横向相邻的色阻30在数据线区域互相连接交叠(图1A中以虚线部分表示)，纵向相邻的色阻30之间在扫描线区域设有黑色矩阵50；在数据线20上方平行设有DBS公共电极走线40，DBS公共电极走线40宽度略宽于数据线20，用于液晶显示中实现遮光。
如图1B所示，其为图1A中A-A位置截面示意图，并且增加了图1A中所未绘示的结构。TFT阵列的源极80上制备有色阻30，色阻30上设有DBS公共电极走线40及像素电极60，DBS公共电极走线40与对侧基板上的公共电极70在电位上通常设置成等电位，以使工作时液晶分子90保持不偏转的状态。由于两种颜色的色阻30交叠处产生凸起，从而使得色阻30交叠处DBS公共电极走线40位置的液晶分子90由于地形以及上下基板在该位置处形成的正向电场或侧向电场产生漏光。
发明内容
因此，本发明的目的在于提供一种阵列基板及其制备方法，降低色阻交叠位置DBS公共电极走线处漏光。
为实现上述目的，本发明提供了一种阵列基板，包括：基板；
位于所述基板一侧交叉设置的多条数据线和多条扫描线，所述多条数据线和所述多条扫描线限定出多个子像素区域，所述多条数据线和所述多条扫描线相互绝缘；
与所述多条数据线和所述多条扫描线位于所述基板同一侧的色阻层，所述色阻层包括多个色阻，且相邻的两个所述色阻具有对应于数据线区域的交叠区域；
位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线以遮蔽数据线，所述DBS公共电极走线的边缘设有平行于扫描线方向的均匀狭缝。
其中，所述DBS公共电极走线的一侧边缘设有所述狭缝。
其中，所述DBS公共电极走线的两侧边缘设有所述狭缝。
其中，所述DBS公共电极走线的两侧边缘对称设有所述狭缝。
其中，所述DBS公共电极走线的两侧边缘非对称设有所述狭缝。
其中，所述DBS公共电极走线两侧的所述狭缝的纵向分布范围合并后遍及所述DBS公共电极走线所处的子像素区域。
其中，所述子像素区域设有像素电极。
本发明还提供了一种阵列基板的制备方法，包括：
提供一基板，在基板一侧制备TFT阵列；
在TFT阵列的钝化层上形成色阻；
在色阻上形成过孔；
在色阻上形成ITO薄膜，图案化ITO薄膜形成像素电极以及DBS公共电极走线，DBS公共电极走线的边缘设有平行于扫描线方向的均匀狭缝；所述像素电极通过所述过孔与TFT阵列中的漏极连接。
其中，在基板一侧制备TFT阵列的步骤包括：
在基板上形成栅极金属层并图案化栅极金属层，得到栅极；
在栅极及基板上形成栅极绝缘层；
在栅极绝缘层上形成有源层；
在有源层上形成欧姆接触层；
在欧姆接触层上形成源漏极金属层并图案化源漏极金属层，得到源漏极；
在源漏极上形成钝化层。
综上，本发明的阵列基板及其制备方法能够降低色阻交叠位置DBS公共电极走线处漏光，提高色域及对比度，提升产品品质。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1A为一种现有阵列基板俯视示意图；
图1B为一种图1A中A-A位置截面示意图；
图2A为本发明阵列基板一较佳实施例的俯视示意图；
图2B为图2A中DBS公共电极走线的图案示意图；
图3A为本发明阵列基板又一较佳实施例的俯视示意图；
图3B为图3A中B-B位置截面示意图。
具体实施方式
参见图2A及图2B，图2A为本发明阵列基板一较佳实施例的俯视示意图，图2B为图2A中DBS公共电极走线的图案示意图。该较佳实施例的阵列基板主要包括：基板(图未示)；位于所述基板一侧交叉设置的多条数据线20和多条扫描线10，所述多条数据线20和所述多条扫描线10限定出多个子像素区域，所述多条数据线20和所述多条扫描线10相互绝缘；与所述多条数据线20和所述多条扫描线10位于所述基板同一侧的色阻层，所述色阻层包括多个色阻30，且相邻的两个所述色阻30具有对应于数据线区域的交叠区域；位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线41以遮蔽数据线20，所述DBS公共电极走线41的边缘设有平行于扫描线10方向的均匀狭缝。
该阵列基板所包含的像素结构主要包括：设于基板上的TFT阵列包括横向的扫描线10和纵向的数据线20，在由交叉的扫描线10和数据线20所限定的子像素区域中设有色阻30以及像素电极(图未示)，例如RGB三种色阻30；横向相邻的色阻30在数据线区域互相连接交叠(图2A中以虚线部分表示)，纵向相邻的色阻30之间在扫描线区域设有黑色矩阵50；在数据线20上方色阻30交叠处平行于数据线20设有DBS公共电极走线41以屏蔽数据线20，DBS公共电极走线41宽度略宽于数据线20，用于液晶显示中实现遮光；DBS公共电极走线41的边缘设有平行于扫描线方向的均匀狭缝100。此较佳实施例中，狭缝100设置于DBS公共电极走线41的上下位置各一侧的边缘；本发明可以将DBS公共电极走线41通过光罩定义方式形成狭缝图案(slit pattern)，该图案方位角分别为0°与180°，狭缝100开口方向平行于扫描线方向，可以朝向两侧两个方向。
图3A为本发明阵列基板又一较佳实施例的俯视示意图。该较佳实施例的结构大体上与图2A中相同，该较佳实施例的阵列基板主要包括：基板(图未示)；位于所述基板一侧交叉设置的多条数据线20和多条扫描线10，所述多条数据线20和所述多条扫描线10限定出多个子像素区域，所述多条数据线20和所述多条扫描线10相互绝缘；与所述多条数据线20和所述多条扫描线10位于所述基板同一侧的色阻层，所述色阻层包括多个色阻30，且相邻的两个所述色阻30具有对应于数据线区域的交叠区域；位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线42以遮蔽数据线20，所述DBS公共电极走线42的边缘设有平行于扫描线10方向的均匀狭缝。
在数据线20上方色阻30交叠处平行于数据线20设有DBS公共电极走线42以屏蔽数据线20，DBS公共电极走线42的边缘设有平行于扫描线方向的均匀狭缝100；此较佳实施例中，狭缝100对称设置在DBS公共电极走线42的两侧边缘，两侧均形成狭缝100可以提高DBS公共电极走线42控制液晶效果。
参见图3B，其为本发明图3A中B-B位置的截面示意图，并且增加了图3A中所未绘示的结构。TFT阵列的源极80上制备有色阻30，色阻30上设有DBS公共电极走线42及像素电极60，工作时像素电极60与公共电极70之间的电场使液晶分子91偏转，DBS公共电极走线42与对侧基板上的公共电极70在电位上通常设置成等电位，以使工作时色阻30交叠处液晶分子90保持不偏转的状态。本发明通过使DBS公共电极走线42上狭缝100形成0°与180°方位角，提高DBS公共电极走线42控制液晶效果，消除由于地形以及上下基板在该位置处形成的正向电场或侧向电场而导致的漏光。
DBS公共电极走线上的狭缝也可以采用其他设计，只要能提高DBS公共电极走线控制液晶的效果即可。例如，DBS公共电极走线的可以两侧边缘设有狭缝，并且两侧边缘的狭缝位置非对称；或者DBS公共电极走线可以仅一侧边缘设有狭缝；DBS公共电极走线上两侧(包括一侧的情况)的狭缝的纵向分布范围合并后遍及DBS公共电极走线所处的子像素区域，以满足控制液晶的需要。
本发明还提供了相应的阵列基板的制备方法，主要包括：
提供基板，在基板一侧制备TFT阵列；TFT阵列可以采用现有的TFT阵列结构；
在TFT阵列的钝化层上形成色阻；TFT阵列的钝化层(PV1)沉积后通过涂布(coating)工艺形成RGB色阻；
在色阻上形成过孔；RGB色阻完成后，通过干蚀刻或湿蚀刻工艺形成过孔以露出TFT阵列的钝化层；钝化层再形成用于使像素电极连接TFT电极的过孔；
形成ITO薄膜，图案化ITO薄膜形成像素电极以及DBS公共电极走线，DBS公共电极走线的边缘设有平行于扫描线方向的均匀狭缝；所述像素电极通过所述过孔与TFT阵列中的漏极连接；色阻上的过孔使色阻下方的TFT阵列的钝化层露出，钝化层设有用于连接漏极的过孔，像素电极通过色阻以及钝化层的过孔连接漏极。DBS公共电极走线的图案可以根据前面的实施例进行设计，通过光罩定义方式形成狭缝图案。通过溅射(Sputter) 形成ITO薄膜，通过湿蚀刻工艺形成像素电极及DBS公共电极走线图案。
制备TFT阵列可以采用一般的TFT制备工艺，制备流程为Metal1-(GI+a-Si+n+Si)-Metal 2-PV1；主要包括：
在基板上形成栅极金属层(Metal1)，图案化栅极金属层，得到栅极；
在栅极及基板上形成栅极绝缘层(GI)；
在栅极绝缘层上形成有源层(a-Si)；
形成欧姆接触层(n+Si)；可以在有源层上通过化学气相沉积等方式形成欧姆接触层；
形成源漏极金属层(Metal 2)；在欧姆接触层上形成源漏极金属层，然后图案化源漏极金属层，得到源漏极；
在源漏极上形成钝化层(PV1)。
综上，本发明的阵列基板及其制备方法能够降低色阻交叠位置DBS公共电极走线处漏光，提高色域及对比度，提升产品品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

  1. 一种阵列基板，包括：
    基板；
    位于所述基板一侧交叉设置的多条数据线和多条扫描线，所述多条数据线和所述多条扫描线限定出多个子像素区域，所述多条数据线和所述多条扫描线相互绝缘；
    与所述多条数据线和所述多条扫描线位于所述基板同一侧的色阻层，所述色阻层包括多个色阻，且相邻的两个所述色阻具有对应于数据线区域的交叠区域；
    位于所述色阻层的交叠区域背离所述基板一侧设有DBS公共电极走线以遮蔽数据线，所述DBS公共电极走线的边缘设有平行于扫描线方向的均匀狭缝。
  2. 如权利要求1所述的阵列基板，其中，所述DBS公共电极走线的一侧边缘设有所述狭缝。
  3. 如权利要求1所述的阵列基板，其中，所述DBS公共电极走线的两侧边缘设有所述狭缝。
  4. 如权利要求3所述的阵列基板，其中，所述DBS公共电极走线的两侧边缘对称设有所述狭缝。
  5. 如权利要求3所述的阵列基板，其中，所述DBS公共电极走线的两侧边缘非对称设有所述狭缝。
  6. 如权利要求1所述的阵列基板，其中，所述DBS公共电极走线两侧的所述狭缝的纵向分布范围合并后遍及所述DBS公共电极走线所处的子像素区域。
  7. 如权利要求1所述的阵列基板，其中，所述子像素区域设有像素电极。
  8. 一种阵列基板的制备方法，包括：
    提供一基板，在基板一侧制备TFT阵列；
    在TFT阵列的钝化层上形成色阻；
    在色阻上形成过孔；
    在色阻上形成ITO薄膜，图案化ITO薄膜形成像素电极以及DBS公共电极走线，DBS公共电极走线的边缘设有平行于扫描线方向的均匀狭缝；所述像素电极通过所述过孔与TFT阵列中的漏极连接。
  9. 如权利要求8所述的阵列基板的制备方法，其中，在基板一侧制备TFT阵列的步骤包括：
    在基板上形成栅极金属层并图案化栅极金属层，得到栅极；
    在栅极及基板上形成栅极绝缘层；
    在栅极绝缘层上形成有源层；
    在有源层上形成欧姆接触层；
    在欧姆接触层上形成源漏极金属层并图案化源漏极金属层，得到源漏极；
    在源漏极上形成钝化层。
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