WO2020098310A1 - 移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置 Download PDF

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Publication number
WO2020098310A1
WO2020098310A1 PCT/CN2019/098231 CN2019098231W WO2020098310A1 WO 2020098310 A1 WO2020098310 A1 WO 2020098310A1 CN 2019098231 W CN2019098231 W CN 2019098231W WO 2020098310 A1 WO2020098310 A1 WO 2020098310A1
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Prior art keywords
signal
transistor
output
terminal
coupled
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PCT/CN2019/098231
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English (en)
French (fr)
Inventor
袁志东
李永谦
李蒙
袁粲
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/642,469 priority Critical patent/US11250784B2/en
Priority to EP19850842.6A priority patent/EP3882899A4/en
Publication of WO2020098310A1 publication Critical patent/WO2020098310A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the array substrate row drive (Gate Driver Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) gate drive circuit on the array substrate of the display panel to form a scan drive for the display panel, which can be omitted
  • the general gate drive circuit is composed of multiple cascaded shift registers, and each level of shift register is correspondingly connected to a gate line, so as to sequentially input and scan each row of grid lines on the display panel through the shift registers of each level signal.
  • the gate lines of each row are correspondingly connected to a shift register, the structural design of the gate drive circuit is complicated, and the space occupied by the display panel is large, which is not conducive to the narrow bezel design.
  • An embodiment of the present disclosure provides a shift register, including:
  • Signal control circuit coupled with input signal terminal and reset signal terminal
  • a branch control circuit coupled to the first output terminal of the signal control circuit
  • the cascade signal output circuit is coupled to the cascade signal output terminal and the second output terminal of the signal control circuit;
  • At least two scan signal output circuits one of the at least two scan signal output circuits, the second output terminal of the scan signal output circuit and the signal control circuit, the corresponding at least one scan signal output terminal, and the branch An output terminal corresponding to the control circuit is coupled.
  • the cascade signal output circuit is coupled to an output terminal of the branch control circuit.
  • there are two scan signal output circuits including a first scan signal output circuit and a second scan signal output circuit;
  • the first scan signal output circuit is coupled to the first output terminal of the branch control circuit; the second scan signal output circuit is coupled to the second output terminal of the branch control circuit.
  • the branch control circuit includes: a first transistor and a second transistor;
  • the first transistor is connected to the first output terminal of the signal control circuit and the first output terminal of the branch control circuit under the control of the effective level
  • the second transistor is connected to the The first output terminal of the signal control circuit and the second output terminal of the branch control circuit.
  • both the gate and the first pole of the first transistor are coupled to the first output terminal of the signal control circuit, and the second pole of the first transistor is the branch The first output of the control circuit;
  • the gate and the first pole of the second transistor are coupled to the first output of the signal control circuit, and the second pole of the second transistor is the second output of the branch control circuit.
  • the gate of the first transistor is coupled to the first reference signal terminal, and the first electrode of the first transistor is coupled to the first output terminal of the signal control circuit ,
  • the second pole of the first transistor is the first output of the branch control circuit;
  • the gate of the second transistor is coupled to the first reference signal terminal, the first electrode of the second transistor is coupled to the first output terminal of the signal control circuit, and the second of the second transistor The second output terminal of the branch control circuit.
  • the first scan signal output circuit includes: at least one first sub-scan signal output circuit; wherein, one of the first sub-scan signal output circuit and the second reference signal terminal , A corresponding first clock signal terminal and a corresponding first sub-scanning signal output terminal are coupled.
  • the first sub-scanning signal output circuit includes: a third transistor, a fourth transistor, and a first capacitor;
  • the gate of the third transistor is coupled to the first output of the branch control circuit, the first pole of the third transistor is coupled to the first clock signal, and the second of the third transistor The pole is coupled to the corresponding output terminal of the first sub-scan signal;
  • the gate of the fourth transistor is coupled to the second output of the signal control circuit, the first pole of the fourth transistor is coupled to the second reference signal, and the second of the fourth transistor The pole is coupled to the corresponding output terminal of the first sub-scan signal;
  • the first capacitor is coupled between the gate of the third transistor and the first sub-scanning signal output terminal.
  • the second scan signal output circuit includes: at least one second sub-scan signal output circuit; wherein, one of the second sub-scan signal output circuits is respectively connected to the second reference signal Terminal, a corresponding second clock signal terminal and a corresponding second sub-scanning signal output terminal are coupled.
  • the second sub-scanning signal output circuit includes: a fifth transistor, a sixth transistor, and a second capacitor;
  • the gate of the fifth transistor is coupled to the second output terminal of the branch control circuit, the first electrode of the fifth transistor is coupled to the second clock signal terminal, and the second of the fifth transistor The pole is coupled to the corresponding output terminal of the second sub-scanning signal;
  • the gate of the sixth transistor is coupled to the second output of the signal control circuit, the first pole of the sixth transistor is coupled to the second reference signal, and the second of the sixth transistor The pole is coupled to the corresponding output terminal of the second sub-scanning signal;
  • the second capacitor is coupled between the gate of the fifth transistor and the second sub-scanning signal output terminal.
  • the cascade signal output circuit includes: a seventh transistor and an eighth transistor;
  • the gate of the seventh transistor is coupled to the first output terminal of the branch control circuit, the first electrode of the seventh transistor is coupled to the third clock signal terminal, and the second electrode of the seventh transistor is The cascade signal output terminal is coupled;
  • the gate of the eighth transistor is coupled to the second output of the signal control circuit, the first pole of the eighth transistor is coupled to the third reference signal, and the second of the eighth transistor The pole is coupled to the cascade signal output terminal.
  • the signal control circuit includes: an input circuit, a reset circuit, and a node control circuit;
  • the input circuit is respectively coupled to the input signal terminal, the first reference signal terminal and the first output terminal of the signal control circuit;
  • the reset circuit is respectively coupled to the reset signal terminal, the third reference signal terminal, and the first output terminal and the second output terminal of the branch control circuit;
  • the node control circuit is connected to the first reference signal terminal, the third reference signal terminal, the first output terminal and the second output terminal of the signal control circuit, and the first output terminal of the branch control circuit and The second output terminal is coupled.
  • the input circuit includes: a ninth transistor; wherein, the gate of the ninth transistor is coupled to the input signal terminal, and the first pole of the ninth transistor is The first reference signal is coupled, and the second electrode of the ninth transistor is coupled to the first output terminal of the signal control circuit;
  • the reset circuit includes: a tenth transistor and an eleventh transistor; wherein the gate of the tenth transistor is coupled to the reset signal terminal, the first electrode of the tenth transistor and the third reference signal Terminal coupling, the second electrode of the tenth transistor is coupled to the first output terminal of the branch control circuit; the gate of the eleventh transistor is coupled to the reset signal terminal, the eleventh The first electrode of the transistor is coupled to the third reference signal terminal, and the second electrode of the eleventh transistor is coupled to the second output terminal of the branch control circuit;
  • the node control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; wherein the gate of the twelfth transistor is coupled to the second output terminal of the signal control circuit Connected, the first electrode of the twelfth transistor is coupled to the third reference signal terminal, the second electrode of the twelfth transistor is coupled to the first output terminal of the branch control circuit;
  • the gate of the thirteenth transistor is coupled to the second output of the signal control circuit, the first pole of the thirteenth transistor is coupled to the third reference signal, and the second of the thirteenth transistor Is coupled to the second output terminal of the branch control circuit;
  • the gate and the first pole of the fourteenth transistor are coupled to the first reference signal terminal, and the second pole of the fourteenth transistor Is coupled to the second output terminal of the signal control circuit;
  • the gate of the fifteenth transistor is coupled to the first output terminal of the signal control circuit, and the first pole of the fifteenth transistor is connected to the The third reference signal terminal is coupled, and
  • the reset circuit further includes: a sixteenth transistor; wherein, the first pole of the tenth transistor and the first pole of the eleventh transistor respectively pass through the Sixteen transistors are coupled to the third reference signal terminal; the gate of the sixteenth transistor is coupled to the reset signal terminal;
  • the node control circuit further includes: a seventeenth transistor; wherein the first pole of the twelfth transistor and the first pole of the thirteenth transistor pass through the seventeenth transistor and the third reference respectively The signal terminal is coupled; the gate of the seventeenth transistor is coupled to the second output terminal of the signal control circuit.
  • the shift register further includes: a detection circuit; the detection circuit includes: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a 22 transistors and the third capacitor;
  • the gate of the eighteenth transistor is coupled to the first detection control signal terminal, the first pole of the eighteenth transistor is coupled to the input signal terminal, and the second pole of the eighteenth transistor is coupled to all The first pole of the twentieth transistor is coupled;
  • the gate of the nineteenth transistor is coupled to the first detection control signal terminal, the first pole of the nineteenth transistor is coupled to the gate of the twenty-first transistor, the nineteenth The second pole of the transistor is coupled to the first pole of the twentieth transistor;
  • the gate of the twentieth transistor is coupled to the gate of the twenty-first transistor, and the second pole of the twentieth transistor is used to couple with the fourth reference signal terminal;
  • the first pole of the twenty-first transistor is coupled to the fourth reference signal terminal, and the second pole of the twenty-first transistor is coupled to the first pole of the twenty-second transistor;
  • the gate of the twenty-second transistor is coupled to the second detection control signal terminal, and the second electrode of the twenty-second transistor is coupled to the first output terminal of the signal control circuit;
  • the third capacitor is coupled between the first electrode of the twenty-first transistor and the gate of the twenty-first transistor.
  • an embodiment of the present disclosure also provides a gate driving circuit, including a plurality of cascaded shift registers provided by the embodiments of the present disclosure;
  • the input signal terminal of the first-stage shift register is coupled to the frame start signal terminal;
  • the input signal terminal of the fourth-stage shift register is coupled to the cascade signal input terminal of the first-stage shift register;
  • the reset signal terminal of the first-stage shift register is coupled to the cascade signal input terminal of the fifth-stage shift register.
  • an embodiment of the present disclosure also provides an array substrate including the gate driving circuit provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a display device, including the array substrate provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a method for driving a shift register provided by an embodiment of the present disclosure, including: a display scanning stage; wherein the display scanning stage includes: an input stage, an output stage, and a reset stage;
  • the signal control circuit controls the signal of the first output terminal of the signal control circuit and the signal of the second output terminal of the signal control circuit in response to the signal of the input signal terminal;
  • the branch control circuit In response to the signal at the first output terminal of the signal control circuit, the output signals of each output terminal of the branch control circuit are controlled;
  • the cascade signal output circuit responds to the output signal of one output terminal of the branch control circuit to control The cascade signal output terminal outputs a cascade signal; each of the scan signal output circuits controls at least one scan signal output terminal to output different scan signals in response to a signal of an output terminal corresponding to the branch control circuit;
  • the branch control circuit controls the output signal of each output terminal of the branch control circuit in response to the signal of the first output terminal of the signal control circuit;
  • the cascade signal output circuit responds to the branch The output signal of one output terminal of the control circuit controls the cascade signal output terminal to output a cascade signal;
  • each of the scan signal output circuits controls at least one scan signal corresponding to the signal of one output terminal corresponding to the branch control circuit The output terminal outputs different scanning signals;
  • the signal control circuit controls the signals of the first output terminal and the second output terminal of the signal control circuit in response to the signal of the reset signal terminal; the cascade signal output circuit responds to the branch The output signal of one output end of the control circuit controls the cascade signal output end to output the cascade signal; each of the scan signal output circuits outputs different scan signals in response to the signal of the corresponding output control node.
  • the first scan signal output circuit includes: a plurality of first A sub-scanning signal output circuit
  • the second scanning signal output circuit includes: a plurality of second sub-scanning signal output circuits
  • each of the first sub-scanning signal output circuits provides the corresponding signal of the first clock signal terminal to the corresponding signal in response to the signal of the first output terminal of the branch control circuit A first sub-scanning signal output terminal; each of the second sub-scanning signal output circuits provides the corresponding signal of the second clock signal terminal to the corresponding second sub-channel in response to the signal of the second output terminal of the branch control circuit Scanning signal output terminal; the cascade signal output circuit responds to the signal of the first output terminal of the branch control circuit, and provides the signal of the third clock signal terminal to the cascade signal output terminal;
  • each of the first sub-scanning signal output circuits provides the signal of the second reference signal terminal to the corresponding first sub-scanning signal output terminal in response to the signal of the second output terminal of the signal control circuit;
  • the second sub-scanning signal output circuit provides the signal of the second reference signal terminal to the corresponding second sub-scanning signal output terminal in response to the signal of the second output terminal of the signal control circuit;
  • the cascade signal output The circuit provides the signal of the third reference signal terminal to the cascade signal output terminal in response to the signal of the second output terminal of the signal control circuit.
  • the signal timing of each first clock signal terminal is the same, the signal timing of each second clock signal terminal is the same, and the first clock signal terminal and The signal timing of the second clock signal terminal is different.
  • FIG. 1 is a schematic structural diagram of a shift register in the related art
  • FIG. 2 is a signal simulation simulation diagram of the shift register shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of a shift register provided by an embodiment of the present disclosure.
  • FIG. 6 is a simulation timing diagram after the simulation of the shift register shown in FIG. 4;
  • FIG. 7 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure.
  • FIG. 8 is another circuit timing diagram provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is another circuit timing diagram provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a driving method provided by an embodiment of the present disclosure.
  • 14a is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • 14b is another schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the shift register may be provided with multiple scan signal output circuits 01, for example, two scan signal output circuits 01 are provided in FIG. 1; one of the scan signal output circuits 01 outputs scans The signal G1, the other scan signal output circuit 01 outputs the scan signal G2.
  • the signal of the pull-up node A and the signal of the pull-down node B are controlled by a signal control circuit.
  • the scan signal output circuit 01 that outputs the scan signal G1 includes: transistors M01 and M02 and a capacitor C01; wherein, the gate of the transistor M01 is coupled to the pull-up node A, the first electrode of the transistor M01 is used to receive the clock signal CK1, and the transistor M01 Is used to output the scan signal G1.
  • the gate of the transistor M02 is coupled to the pull-down node B, the first electrode of the transistor M02 is used to receive the signal VGL, and the second electrode of the transistor M02 is coupled to the second electrode of the transistor 01.
  • the capacitor C01 is coupled between the pull-up node A and the second electrode of the transistor 01.
  • the scan signal output circuit 01 that outputs the scan signal G2 includes: transistors M03 and M04 and a capacitor C02; wherein, the gate of the transistor M03 is coupled to the pull-up node A, the first pole of the transistor M03 is used to receive the clock signal CK2, and the transistor M03 Is used to output the scan signal G2.
  • the gate of the transistor M04 is coupled to the pull-down node B, the first electrode of the transistor M04 is used to receive the signal VGL, and the second electrode of the transistor M04 is coupled to the second electrode of the transistor 03.
  • the capacitor C02 is coupled between the pull-up node A and the second electrode of the transistor 03.
  • the transistor M01 can provide the signal of the clock signal CK1 to its second end under the control of the signal of the pull-up node A to output as the scan signal G1.
  • the transistor 03 can provide the signal of the clock signal CK2 to its second terminal to be output as the scan signal G2.
  • the simulation timing diagram can be obtained by simulating the clock signals CK1, CK2, the signal a of the pull-up node A, the signal b of the pull-down node B, and the scan signals G1 and G2, as shown in FIG. 2.
  • the transistor 01 Since the high level of the clock signal CK1 occurs earlier than the high level of the clock signal CK2, when the transistor 01 is turned on under the control of the signal of the pull-up node A to output the high level signal of the clock signal CK1 as the scan signal G1, Will pull up the level of node A.
  • the transistor 02 When the transistor 02 is turned on under the control of the signal of the pull-up node A to output the high-level signal of the clock signal CK2 as the scan signal G2, the level of the pull-up node A is further raised.
  • the scan signal G1 is restored from a high level to a low level.
  • the time (Fall Time) RFT (12us) is less than the fall time RFT (14us) of the scan signal G2 returning from the high level to the low level, resulting in a difference in the waveforms of the output scan signals G1 and G2.
  • the signal control circuit 10 is coupled to the input signal terminal INPUT and the reset signal terminal RE, that is, the signal control circuit 10 is configured to control the first output of the signal control circuit 10 in response to the signal of the input signal terminal INPUT and the signal of the reset signal terminal RE And the second output terminal; for convenience of description, the first output terminal of the signal control circuit 10 is referred to as a first node PU, and the first output terminal of the signal control circuit 10 is referred to as a second node PD;
  • the branch control circuit 20 is coupled to the first output of the signal control circuit 10, that is, the branch control circuit 20 is configured to control the output control node PO_m corresponding to each scan signal output circuit 40_m in response to the signal of the first node PU Signal; for convenience of description, each output terminal of the branch control circuit 20 is recorded as an output control node PO_m;
  • the cascade signal output circuit 30 is respectively coupled to the cascade signal output terminal CROUT, one output terminal of the branch control circuit 20 and the second output terminal of the signal control circuit 10, that is, the cascade signal output circuit 30 is configured to respond to multiple The signal of the output control node PO_1 and the signal of the second node PD corresponding to the first scan output circuit in the scan signal output circuit output a cascade signal CR;
  • Each scan signal output circuit 40_m is coupled to the second output terminal of the signal control circuit 10, the corresponding at least one scan signal output terminal goutm, and an output terminal corresponding to the branch control circuit 20, that is, each scan signal output circuit 40_m is configured In response to the signal of the corresponding output control node PO_m and the signal of the second node PD, different scan signals goutm are output.
  • the shift register provided by the embodiment of the present disclosure controls the signal of the first node and the signal of the second node through the signal control circuit in response to the signals of the input signal terminal and the reset signal terminal.
  • the branch control circuit is configured to control the signal of the output control node corresponding to each scan signal output circuit in response to the signal of the first node, and the different output control nodes can be divided so that the signal at the output control node changes The time may not affect the signals of other output control nodes.
  • the cascade signal output circuit outputs the cascade signal in response to the output control node signal and the second node signal corresponding to the first scan output circuit of the plurality of scan signal output circuits, and provides an input signal for the next stage shift register .
  • each scan signal output circuit outputs different scan signals in response to the corresponding output control node signal and the second node signal.
  • each shift register can output multiple scan signals to correspond to different gate lines in the display panel.
  • the number of shift registers in the gate drive circuit can be reduced, the occupied space of the gate drive circuit can be reduced, and an ultra-narrow bezel design can be realized.
  • the signals of different output control nodes have no influence on each other, the output stability can also be improved.
  • the signal control circuit 10 may include: an input circuit 11, a reset circuit 12, and a node control circuit 13, so that the input circuit 11, the reset circuit 12, and the node The control circuits 13 cooperate with each other to control the levels of the signals of the first node PU, the output control node PO_m, and the second node PD.
  • the input circuit 11 is coupled to the input signal terminal INPUT, the first reference signal terminal VREF1 and the first output terminal of the signal control circuit, the input circuit 11 is configured to respond to the signal of the input signal terminal INPUT, the first reference signal The signal at terminal VREF1 is provided to the first node PU.
  • the reset circuit 12 is coupled to the reset signal terminal RE, the third reference signal terminal VREF3, and the first and second output terminals of the branch control circuit 20.
  • the reset circuit 12 is configured to respond to the signal of the reset signal terminal RE
  • the signal of the third reference signal terminal VREF3 is provided to the output control node PO_m corresponding to each scan signal output circuit 40_m.
  • the node control circuit 13 is respectively coupled to the first reference signal terminal VREF1, the third reference signal terminal VREF3, the first output terminal and the second output terminal of the signal control circuit 10, and the first output terminal and the second output terminal of the branch control circuit 20 Then, the node control circuit 13 is configured to control the signal of the first node PU and the signal of each output control node PO_m to be opposite in level to the signal of the second node PD, respectively.
  • the cascade signal output circuit 30 is configured to respond to the output control node PO_1 corresponding to the first scan signal output circuit 40_1 among the plurality of scan signal output circuits Signal, the signal of the third clock signal terminal CLK3 is provided to the cascade signal output terminal CROUT; and in response to the signal of the second node PD, the signal of the third reference signal terminal VREF3 is provided to the cascade signal output terminal CROUT.
  • the number of scan signal output circuits 40_m may be configured to be two.
  • the number of scan signal output circuits 40_m may be three, four, five, etc.
  • the number of scan signal output circuits 40_m can be designed and determined according to the actual application environment, which is not limited herein. In the following, the number of scanning signal output circuits 40_m is set to two as an example for description.
  • the first scan signal output circuit 40_1 of the two scan signal output circuits may include: at least one first sub-scan signal output circuit 41_n (1 ⁇ n ⁇ N, N represents the total number of first sub-scanning signal output circuits, and FIG.
  • N 1 as an example); wherein, a first sub-scanning signal output circuit 41_n and the second reference signal terminal VREF2 respectively correspond to a first A clock signal terminal CLK1_n is coupled to a corresponding first sub-scanning signal output terminal GOUT1_n; each first sub-scanning signal output circuit 41_n corresponds to a first clock signal terminal CLK1_n, and each first sub-scanning signal output circuit 41_n-1 One corresponds to a first sub-scanning signal output terminal GOUT1_n.
  • the first sub-scanning signal output circuit 41_n is configured to respond to the signal of the same output control node, that is, the first sub-scanning signal output circuit 41_n is configured to respond to the signal of the output control node PO_1, the corresponding first clock signal
  • the signal of the terminal CLK1_n is provided to the corresponding first sub-scanning signal output terminal GOUT1_n; and in response to the signal of the second node PD, the signal of the second reference signal terminal VREF2 is provided to the corresponding first sub-scanning signal output terminal GOUT1_n.
  • the first sub-scanning signal output terminal GOUT1_n respectively outputs the scanning signal gout1_n.
  • one first sub-scanning signal output circuit may be provided; or two first sub-scanning signal output circuits may also be provided.
  • the specific number of the first sub-scanning signal output circuit can be designed and determined according to the actual application environment, which is not limited herein. In the following, an example of providing a first sub-scanning signal output circuit will be described.
  • the second scan signal output circuit 40_2 of the two scan signal output circuits may include: at least one second sub-scan signal output circuit 42_k (1 ⁇ k ⁇ K, K represents the total number of second sub-scanning signal output circuits, and FIG.
  • a second sub-scanning signal output circuit 42_k respectively corresponds to the second reference signal terminal VREF2 and a corresponding first
  • the two clock signal terminals CLK2_k are coupled to a corresponding second sub-scanning signal output terminal; each second sub-scanning signal output circuit 42_k corresponds to a second clock signal terminal CLK2_k, and each second sub-scanning signal output circuit 42_k one to one Corresponds to a second sub-scanning signal output terminal GOUT2_k.
  • the second sub-scanning signal output circuit 42_k is configured to respond to the signal of the same output control node, that is, the second sub-scanning signal output circuit 42_k is configured to respond to the signal of the output control node PO_2, and the corresponding second clock
  • the signal of the signal terminal CLK2_k is provided to the corresponding second sub-scanning signal output terminal GOUT2_k; and in response to the signal of the second node PD, the signal of the second reference signal terminal VREF2 is provided to the corresponding second sub-scanning signal output terminal GOUT2_k.
  • the second sub-scanning signal output terminal GOUT2_k respectively outputs the scanning signal gout2_k.
  • one second sub-scanning signal output circuit may be provided; or two second sub-scanning signal output circuits may also be provided.
  • the specific number of the second sub-scanning signal output circuit can be designed and determined according to the actual application environment, which is not limited herein. In the following, an example of setting a second sub-scanning signal output circuit will be described.
  • the branch control circuit 20 may include: a first transistor M1 and a second transistor M2; the first transistor M1 communicates with the signal control circuit under the control of the effective level
  • the first output terminal of 10 is connected to the first output terminal of the branch control circuit 20, and the second transistor M2 connects the first output terminal of the signal control circuit 20 and the second output terminal of the branch control circuit 20 under the control of the effective level .
  • both the gate of the first transistor M1 and its first pole are coupled to the first node PU, and the second pole of the first transistor M1 corresponds to the output of the first scan signal output circuit 40_1 of the two scan signal output circuits
  • the control node PO_1 is coupled; the gate of the second transistor M2 and its first pole are coupled to the first node PU, the second pole of the second transistor M2 and the second scan signal output circuit 40_2 of the two scan signal output circuits
  • the corresponding output control node PO_2 is coupled.
  • the first transistor M1 since the gate of the first transistor M1 is coupled to the first electrode, the first transistor M1 forms a diode connection, so that when the voltage of the gate of the first transistor M1 is greater than the voltage of its second electrode, The first transistor M1 may form a path to turn on the first node PU and the output control node PO_1; when the voltage of the gate of the first transistor M1 is not greater than the voltage of its second electrode, the first transistor M1 may form an open circuit, In order to disconnect the first node PU from the output control node PO_1.
  • the second transistor M2 when the voltage of the gate of the second transistor M2 is greater than the voltage of its second electrode, the second transistor M2 can form a path to make the first node PU and the output control node PO_2 conduct; the second transistor M2 When the voltage of the gate is not greater than the voltage of the second electrode, the second transistor M2 may form an open circuit to disconnect the first node PU from the output control node PO_2.
  • the first sub-scanning signal output circuit 41_n may include: a third transistor M3, a fourth transistor M4, and a first capacitor C1; wherein, the third transistor M3 Is coupled to the corresponding output control node PO_1, the first electrode of the third transistor M3 is used to receive the signal of the corresponding first clock signal terminal CLK1_n, and the second electrode of the third transistor M3 is connected to the corresponding first sub-scan The signal output terminal GOUT1_n is coupled.
  • the gate of the fourth transistor M4 is coupled to the second node PD, the first electrode of the fourth transistor M4 is used to receive the signal of the second reference signal terminal VREF2, the second electrode of the fourth transistor M4 and the corresponding first sub-scan
  • the signal output terminal GOUT1_n is coupled.
  • the first capacitor C1 is coupled between the gate of the third transistor M3, that is, the corresponding output control node PO_1 and the first sub-scanning signal output terminal GOUT1_n.
  • the third transistor M3 in each first sub-scanning signal output circuit 41_n may be in a conducting state under the control of the signal outputting the control node PO_1, so that the corresponding first clock The signal of the signal terminal CLK1_n is provided to the corresponding first sub-scanning signal output terminal GOUT1_n.
  • the fourth transistor M4 in each first sub-scanning signal output circuit 41_n may be turned on under the control of the signal of the second node PD to provide the signal of the second reference signal terminal VREF2 to the corresponding first sub-scanning signal Output GOUT1_n.
  • the first capacitor C1 can maintain the level of the connected output control node PO_1 and the level of the first sub-scanning signal output terminal GOUT1_n, and can maintain the output control node PO_1 and the first sub-scanning signal when the output control node PO_1 is floating The voltage difference between the output terminals GOUT1_n is stable.
  • the second sub-scanning signal output circuit 42_k may include: a fifth transistor M5, a sixth transistor M6, and a second capacitor C2; wherein, the fifth transistor M5 Is coupled to the corresponding output control node PO_2, the first electrode of the fifth transistor M5 is used to receive the signal of the corresponding second clock signal terminal CLK2_k, and the second electrode of the fifth transistor M5 is connected to the corresponding second sub-scan The signal output terminal GOUT2_k is coupled.
  • the gate of the sixth transistor M6 is coupled to the second node PD, the first electrode of the sixth transistor M6 is used to receive the signal of the second reference signal terminal VREF2, the second electrode of the sixth transistor M6 and the corresponding second sub-scan
  • the signal output terminal GOUT2_k is coupled.
  • the second capacitor C2 is coupled between the corresponding output control node PO_2 and the second sub-scanning signal output terminal GOUT2_k.
  • the fifth transistor M5 in each second sub-scanning signal output circuit 42_k may be in a conducting state under the control of the signal outputting the control node PO_2, so that the corresponding second clock The signal of the signal terminal CLK2_k is provided to the corresponding second sub-scanning signal output terminal GOUT2_k.
  • the sixth transistor M6 in each second sub-scanning signal output circuit 42_k may be turned on under the control of the signal of the second node PD to provide the signal of the second reference signal terminal VREF2 to the corresponding second sub-scanning signal Output GOUT2_k.
  • the second capacitor C2 can maintain the level of the connected output control node PO_2 and the level of the second sub-scanning signal output terminal GOUT2_k, and can maintain the output control node PO_2 and the second sub-scanning signal when the output control node PO_2 is floating The voltage difference between the output terminals GOUT2_k is stable.
  • the input circuit 11 may include: a ninth transistor M9; wherein, the gate of the ninth transistor M9 is used to receive the signal of the input signal terminal INPUT, ninth The first electrode of the transistor M9 is used to receive the signal of the first reference signal terminal VREF1, and the second electrode of the ninth transistor M9 is coupled to the first node PU.
  • the ninth transistor M9 may be in a conducting state under the control of the input signal terminal INPUT to provide the signal of the first reference signal terminal VREF1 to the first node PU.
  • the reset circuit 12 may include: a tenth transistor M10 and an eleventh transistor M11; wherein, the gate of the tenth transistor M10 is used to receive a reset signal terminal For the signal of RE, the first electrode of the tenth transistor M10 is used to receive the signal of the third reference signal terminal VREF3, and the second electrode of the tenth transistor M10 is coupled to an output control node, that is, the output control node PO_1.
  • the gate of the eleventh transistor M11 is used to receive the signal of the reset signal terminal RE, the first pole of the eleventh transistor M11 is used to receive the signal of the third reference signal terminal VREF3, and the second pole of the eleventh transistor M11 is connected to another An output control node, namely the output control node PO_2 is coupled.
  • the tenth transistor M10 may be in a conducting state under the control of the effective pulse signal of the reset signal terminal RE to provide the signal of the third reference signal terminal VREF3 to the output control node PO_1.
  • the eleventh transistor M11 may be in an on state under the control of the reset signal terminal RE to provide the signal of the third reference signal terminal VREF3 to the output control node PO_2.
  • the node control circuit 13 may include: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15; wherein , The gate of the twelfth transistor M12 is coupled to the second node PD, the first electrode of the twelfth transistor M12 is used to receive the signal of the third reference signal terminal VREF3, the second electrode of the twelfth transistor M12 and an output The control node, namely the output control node PO_1 is coupled; the gate of the thirteenth transistor M3 is coupled to the second node PD, the first pole of the thirteenth transistor M13 is used to receive the signal of the third reference signal terminal VREF3, the tenth The second electrode of the three transistor M13 is coupled to another output control node, namely the output control node PO_2.
  • the gate of the fourteenth transistor M14 and its first pole are used to receive the signal of the first reference signal terminal VREF1, the second pole of the fourteenth transistor M14 is coupled to the second node PD; the gate of the fifteenth transistor M15 It is coupled to the first node PU, the first electrode of the fifteenth transistor M15 is used to receive the signal of the third reference signal terminal VREF3, and the second electrode of the fifteenth transistor M15 is coupled to the second node PD.
  • the twelfth transistor M12 may be in a conducting state under the control of the signal of the second node PD, so as to provide the signal of the third reference signal terminal VREF3 to the output control node PO_1.
  • the thirteenth transistor M13 may be in an on state under the control of the signal of the second node PD to provide the signal of the third reference signal terminal VREF3 to the output control node PO_2.
  • the fourteenth transistor M14 and the fifteenth transistor M15 may form an inverter so that the level of the second node PD and the level of the first node PU are opposite.
  • the cascade signal output circuit 30 may include: a seventh transistor M7 and an eighth transistor M8; wherein, the gate of the seventh transistor M7 and the first scan The output control node PO_1 corresponding to the signal output circuit is coupled, the first electrode of the seventh transistor M7 is used to receive the signal of the third clock signal terminal CLK3, and the second electrode of the seventh transistor M7 is coupled to the cascade signal output terminal CROUT.
  • the gate of the eighth transistor M8 is coupled to the second node PD, the first electrode of the eighth transistor M8 is used to receive the signal of the third reference signal terminal VREF3, and the second electrode of the eighth transistor M8 and the cascade signal output terminal CROUT Coupling.
  • the third capacitor C3 is coupled between the first node PU and the cascade signal output terminal CROUT.
  • the seventh transistor M7 may be in a conducting state under the control of the output signal of the control node PO_1 to provide the third clock signal CLK3 to the cascade signal output terminal CROUT.
  • the eighth transistor M8 may be in a conducting state under the control of the signal of the second node PD to provide the signal of the third reference signal terminal VREF3 to the cascade signal output terminal CROUT.
  • all switching transistors may be N-type transistors. It should be noted that the embodiments of the present disclosure are only described by taking the transistors in the shift register as N-type transistors. For the case where the transistors are P-type transistors, the design principles are the same as the present disclosure and are also protected by the present disclosure range.
  • the signal at the first reference signal terminal is a high-level signal
  • the signal at the second reference signal terminal and the signal at the third reference signal terminal are both low Level signal.
  • the signal at the first reference signal terminal is a low-level signal
  • the signal at the second reference signal terminal and the signal at the third reference signal terminal are high-level signals.
  • the levels of the signals mentioned in the embodiments of the present disclosure only represent their logic levels, and not the actual voltage values applied by the signals during specific implementation.
  • one frame time during display driving may include a display scanning stage and a blanking time stage.
  • the timing of the signals of the first clock signal terminals is the same, the timing of the signals of the second clock signal terminals is the same, and the timing of the signals of the first clock signal terminal and the signals of the third clock signal terminal are the same.
  • the timing of the signal at the first clock signal terminal and the signal at the second clock signal terminal are different. For example, as shown in FIG. 5, the signal timing of the first clock signal terminal CLK1_1 and the second clock signal terminal CLK2_1 are different, and the signal timing of the first clock signal terminal CLK1_1 and the third clock signal terminal CLK3 are the same.
  • the voltage values of the high-level signals mentioned in the embodiments of the present disclosure are the same, for example, the high-level voltage value of the input signal terminal INPUT, the high-level voltage value of the first clock signal terminal CLK1_1, the first The voltage value of the high level of the two clock signal terminals CLK2_1 and the voltage value of the first reference signal terminal VREF1 are the same.
  • the voltage value of the low-level signal mentioned in the embodiment of the present disclosure may also be the same, for example, the low-level voltage value of the input signal terminal INPUT, the low-level voltage value of the first clock signal terminal CLK1_1, the first The low-level voltage values of the two clock signal terminals CLK2_1, the second reference signal terminal VREF2 and the third reference signal terminal VREF3 are the same.
  • the second reference signal terminal VREF2 and the third reference signal terminal VREF3 can be set to the same signal, that is, the same reference signal terminal is used to provide the second reference signal terminal VREF2 and the third reference signal The signal at terminal VREF3.
  • the voltage values of the second reference signal terminal VREF2 and the third reference signal terminal VREF3 may also be different, which is not limited herein.
  • the cycles of the first clock signal terminal CLK1_n, the second clock signal terminal CLK2_k, and the third clock signal terminal CLK3 are the same.
  • the duration of the high-level signal of the first clock signal terminal CLK1_n may be 4a, and the duration of the low-level signal may be 6a, then the duration of the signal of the first clock signal terminal CLK1_n for one cycle is 10a.
  • the duration of the high-level signal of the second clock signal terminal CLK2_n may be 4a, and the duration of the low-level signal may be 6a, then the duration of the signal of the second clock signal terminal CLK2_n is 10a.
  • the duration of the high-level signal of the third clock signal terminal CLK3 may be 4a, and the duration of the low-level signal may be 6a, and the duration of the signal of the third clock signal terminal CLK3 in one cycle is also 10a.
  • the N-type transistor is turned on under the action of the high-level signal and is turned off under the action of the low-level signal; the P-type transistor is under the low-level signal Turn on under the action, and cut off under the action of high-level signal.
  • the first electrode of the transistor may be used as the source and the second electrode as the drain, or the first electrode of the transistor may be used as the drain and the second electrode is used as the source, which is not specifically distinguished here.
  • the input stage T1, the output stage T2, and the reset stage T3 in the circuit timing diagram shown in FIG. 5 are selected.
  • the ninth transistor M9 is turned on to provide the high level of the first reference signal terminal VREF1 to the first node PU, so that the signal of the first node PU is a high level signal. Since the signal of the first node PU is a high-level signal, the fifteenth transistor M15 is turned on to provide the low level of the third reference signal terminal VREF3 to the second node PD, so that the signal of the second node PD is low Level signal.
  • the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all turned off.
  • the signals output to the control nodes PO_1 and PO_2 are also high-level signals. Since the signal of the output control node PO_1 is a high-level signal, the third transistor M3 and the seventh transistor M7 are turned on, and the turned-on seventh transistor M7 provides the low level of the third clock signal terminal CLK3 to the cascade signal output Terminal CROUT to output low-level cascade signal CR. The turned-on third transistor M3 provides the low level of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1 to output the low-level scanning signal gout1_1, and the first capacitor C1 is charged.
  • the fifth transistor M5 Since the signal of the output control node PO_2 is a high-level signal, the fifth transistor M5 is turned on to provide the low level of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level signal
  • the scan signal gout2_1 and the second capacitor C2 are charged.
  • RE 0, both the tenth transistor M10 and the eleventh transistor M11 are turned off.
  • the ninth transistor M9 is turned off, and the first node PU is floating. Due to the function of the first capacitor C1, the output control node PO_1 remains at a high level signal to control the third transistor M3 and the seventh transistor M7 to be turned on.
  • the turned-on seventh transistor M7 turns the third clock signal terminal CLK3 high The level is provided to the cascade signal output terminal CROUT, and the turned-on third transistor M3 provides the high level of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1, so that the output control node PO_1 is further pulled High, so that the third transistor M3 provides the high level of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1, and outputs the high-level scanning signal gout1_1. And make the seventh transistor M7 supply the high level of the third clock signal terminal CLK3 to the cascade signal output terminal CROUT, and output the cascade signal CR of high level.
  • the output control node PO_2 remains at a high level signal to control the fifth transistor M5 to be turned on to provide the low level of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 outputs the low-level scan signal gout2_1. Since the signal of the first node PU is a high-level signal, the signal of the second node PD is a low-level signal, thereby controlling the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, the first The thirteen transistors M13 are all turned off.
  • the fifth transistor M5 provides the high level of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1, the level of the output control node PO_2 can be pulled high due to the function of the second capacitor C2
  • the high-level scanning signal gout2_1 is output.
  • the third transistor M3 provides the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1 to output the low-level scanning signal gout1_1.
  • the turned-on tenth transistor M10 provides the low level of the third reference signal terminal VREF3 to the output control node PO_1, so that the signal of the output control node PO_1 is a low-level signal, and the turned-on eleventh transistor M11 turns the third The low level of the reference signal terminal VREF3 is provided to the output control node PO_2, so that the signal of the output control node PO_2 is a low level signal, so that the first node PU can be discharged as a low level signal.
  • the function of the fourteenth transistor M14 and the fifteenth transistor M15 can make the second node PD a high-level signal. Since the signal of the second node PD is a high-level signal, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all turned on.
  • the turned-on fourth transistor M4 provides the low level of the second reference signal terminal VREF2 to the first sub-scanning signal output terminal GOUT1_1 to output the low-level scanning signal gout1_1.
  • the turned-on sixth transistor M6 provides the low level of the second reference signal terminal VREF2 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level scanning signal gout2_1.
  • the turned-on eighth transistor M8 provides the low level of the third reference signal terminal VREF3 to the cascade signal output terminal CROUT to output the low-level cascade signal CR.
  • the turned-on twelfth transistor M12 supplies the low level of the third reference signal terminal VREF3 to the output control node PO_1, and further outputs the signal of the control node PO_1 to low level.
  • the turned-on thirteenth transistor M13 provides the low level of the third reference signal terminal VREF3 to the output control node PO_2, and further makes the signal of the output control node PO_2 low.
  • the signal of the output control node PO_1 is kept low by the first capacitor C1
  • the signal of the output control node PO_2 is kept low by the second capacitor C2
  • the signal and the signal of the second node PD are high-level signals, so that the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all turned on.
  • the turned-on fourth transistor M4 provides the low level of the second reference signal terminal VREF2 to the first sub-scanning signal output terminal GOUT1_1 to output the low-level scanning signal gout1_1.
  • the turned-on sixth transistor M6 provides the low level of the second reference signal terminal VREF2 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level scanning signal gout2_1.
  • the turned-on eighth transistor M8 provides the low level of the third reference signal terminal VREF3 to the cascade signal output terminal CROUT to output the low-level cascade signal CR.
  • the turned-on twelfth transistor M12 provides the low level of the third reference signal terminal VREF3 to the output control node PO_1, and further outputs the signal of the control node PO_1 to low level.
  • the turned-on thirteenth transistor M13 provides the low level of the third reference signal terminal VREF3 to the output control node PO_2, and further makes the signal of the output control node PO_2 low.
  • the shift register provided by the present disclosure can make the signals of different output control nodes not affect each other, the stability of the waveform of the output scan signal can be improved, and the difference in the waveform of the scan signal can be avoided.
  • the simulation simulation diagram shown in FIG. 6 is obtained. It can be seen from FIG. 6 that the scan signal gout1_1 and the scan signal gout2_1 are converted from the high-level signal to the low-level signal in 12us, so that the waveforms of the scan signal gout1_1 and the scan signal gout2_1 have a higher similarity and difference Sexuality is small.
  • the display device may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display device or a liquid crystal display device (Liquid Crystal Display, LCD), which is not limited herein.
  • OLED Organic Light-Emitting Diode
  • LCD Liquid Crystal Display
  • two first sub-scanning signal output circuits 41_1 and 41_2 and two second sub-scanning signal output circuits 42_1 are provided in the shift register And 42_2.
  • the first sub-scanning signal output circuit 41_1 corresponds to the first clock signal terminal CLK1_1 and the first sub-scanning signal output terminal GOUT1_1.
  • the first sub-scanning signal output circuit 41_2 corresponds to the first clock signal terminal CLK1_2 and the first sub-scanning signal output terminal GOUT1_2.
  • the second sub-scanning signal output circuit 42_1 corresponds to the second clock signal terminal CLK2_1 and the second sub-scanning signal output terminal GOUT2_1.
  • the second sub-scanning signal output circuit 42_2 corresponds to the second clock signal terminal CLK2_2 and the second sub-scanning signal output terminal GOUT2_2.
  • the third transistor M3, the fourth transistor M4 and the first capacitor C1 in the first sub-scanning signal output circuit 41_2, and the fifth transistor M5, the sixth transistor M6 and the first transistor in the second sub-scanning signal output circuit 42_2 Two capacitors C2 will be described.
  • the rest of the working process at this stage may be basically the same as the working process of the input stage T1 in the first embodiment, which will not be repeated here.
  • the third transistor M3 is turned on to provide the low level of the first clock signal terminal CLK1_2 to the first sub-scanning signal output terminal GOUT1_2 to output low Level scan signal gout1_2, and the first capacitor C1 is charged.
  • the fifth transistor M5 is turned on to provide the low level of the second clock signal terminal CLK2_2 to the second sub-scanning signal output terminal GOUT2_2 to output the low-level signal
  • the signal gout2_2 is scanned, and the second capacitor C2 is charged.
  • the high-level scanning signal gout1_2 is output.
  • the second clock signal terminal CLK2_2 is converted from a low-level signal to a high-level signal. Since the level of the output control node PO_2 is pulled high, the high level of the second clock signal terminal CLK2_2 is provided to the fifth transistor M5
  • the second sub-scanning signal output terminal GOUT2_2 outputs a high-level scanning signal gout2_2.
  • the third transistor M3 provides the low level of the first clock signal terminal CLK1_2 to the first sub-scanning signal output terminal GOUT1_2 to output the low-level scanning signal gout1_2.
  • the turned-on fourth transistor M4 provides the low level of the second reference signal terminal VREF2 to the first sub-scanning signal output terminal GOUT1_2 to output the low-level scanning signal gout1_2.
  • the turned-on sixth transistor M6 provides the low level of the second reference signal terminal VREF2 to the second sub-scanning signal output terminal GOUT2_2 to output the low-level scanning signal gout2_2.
  • the first sub-scanning signal output circuit 41_1 and the first sub-scanning signal output circuit 41_2 can output scan signals with the same timing and waveform, and these two scan signals can be input into the same gate line of a row to improve the driving ability .
  • the second sub-scanning signal output circuit 42_1 and the second sub-scanning signal output circuit 42_2 can output scanning signals with the same timing and waveform, and these two scanning signals can be input to the same gate line in the next row to Improve driving ability.
  • the reset circuit 12 may further include: an eighteenth transistor M18; wherein, the first pole of the tenth transistor M10 is The first electrode of the eleventh transistor M11 receives the signal of the third reference signal terminal VREF3 through the eighteenth transistor M18, respectively.
  • the gate of the eighteenth transistor M18 is used to receive the signal of the reset signal terminal RE
  • the first pole of the eighteenth transistor M18 is used to receive the signal of the third reference signal terminal VREF3
  • the second poles of the eighteenth transistor M18 are respectively The first electrode of the tenth transistor M10 and the first electrode of the eleventh transistor M11 are coupled.
  • the signal of the third reference signal terminal VREF3 can be provided to the first and tenth electrodes of the tenth transistor M10, respectively The first pole of a transistor M11. In this way, the influence of the signal change of the third reference signal terminal VREF3 on the tenth transistor M10 and the eleventh transistor M11 can be avoided, and the circuit stability can be improved.
  • the node control circuit 13 further includes: a seventeenth transistor M17; wherein, the first electrode of the twelfth transistor M12 and the third electrode of the thirteenth transistor M13 One pole receives the signal of the third reference signal terminal VREF3 through the nineteenth transistor M19, respectively.
  • the gate of the nineteenth transistor M19 is coupled to the second node PD.
  • the first pole of the nineteenth transistor M19 is used to receive the signal of the third reference signal terminal VREF3.
  • the second pole of the nineteenth transistor M19 is respectively connected to the tenth
  • the first electrode of the second transistor M12 and the first electrode of the thirteenth transistor M13 are coupled.
  • the signal of the third reference signal terminal VREF3 can be provided to the first electrode and the first electrode of the twelfth transistor M12, respectively.
  • the first pole of the thirteen transistor M13 In this way, the influence of the signal change of the third reference signal terminal VREF3 on the twelfth transistor M12 and the thirteenth transistor M13 can be avoided, and the circuit stability can be improved.
  • a pixel circuit in the form of 3T1C shown in FIG. 10 is used to drive the OLED to emit light and perform external threshold compensation on the OLED.
  • the pixel circuit includes: a driving transistor T01, transistors T02 to T03, and a storage capacitor Cst.
  • the pixel circuit turns on the control transistor T02 to write the data voltage of the data signal terminal Data to the gate of the driving transistor T01, and controls the driving transistor T01 to generate an operating current to drive the organic light emitting diode L to emit light.
  • the signal carrying the threshold voltage information of the driving transistor T01 is output through the detection line SL through the transistor T03. In this way, a row of pixel circuits needs to correspond to two gate lines to input signals G01 and G02, respectively.
  • the shift register may further include: a detection circuit 50.
  • the detection circuit 50 may include: an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, and a third capacitor C3; wherein, the eighteenth transistor The gate of M18 is used to receive the signal of the first detection control signal terminal VC1, the first pole of the eighteenth transistor M18 is used to receive the signal of the input signal terminal INPUT, the second pole of the eighteenth transistor M18 and the twentieth transistor The first pole of M20 is coupled.
  • the gate of the nineteenth transistor M19 is used to receive the signal of the first detection control signal terminal VC1.
  • the first pole of the nineteenth transistor M19 is coupled to the gate of the twenty-first transistor M21.
  • the second electrode is coupled to the first electrode of the twentieth transistor M20.
  • the gate of the twentieth transistor M20 is coupled to the gate of the twenty-first transistor M21, and the second electrode of the twentieth transistor M20 is used to receive the signal of the fourth reference signal terminal VREF4.
  • the first pole of the twenty-first transistor M21 is used to receive the signal of the fourth reference signal terminal VREF4.
  • the second pole of the twenty-first transistor M21 is coupled to the first pole of the twenty-second transistor M22.
  • the gate of the twenty-second transistor M22 is used to receive the signal of the second detection control signal terminal VC2, and the second electrode of the twenty-second transistor M22 is coupled to the first node PU.
  • the third capacitor C3 is coupled between the first electrode of the twenty-first transistor M21 and the gate of the twenty-first transistor M21.
  • the eighteenth transistor M18 may be in an on state under the control of the first detection control signal terminal VC1 to provide the signal of the input signal terminal INPUT to the first pole of the twentieth transistor M20 and the nineteenth transistor M19 The second pole.
  • the nineteenth transistor M19 may be in an on state under the control of the first detection control signal terminal VC1 to provide the signal of its second pole to the gate of the twenty-first transistor M21 and the gate of the twentieth transistor M20 .
  • the twentieth transistor M20 may be turned on under the control of the signal of its gate.
  • the twenty-first transistor M21 may be in an on-state under the control of the signal of its gate to provide the signal of the fourth reference signal terminal VREF4 to the first pole of the twenty-second transistor M22.
  • the twenty-second transistor M22 may be in a conducting state under the control of the second detection control signal terminal VC2 to provide the signal of the first pole thereof to the first node PU.
  • the fourth reference signal terminal may be loaded with a high-level signal. Further, the voltage value of the fourth reference signal terminal may be the same as the voltage value of the first reference signal terminal. In order to reduce the number of signal terminals and the space occupied by the signal lines, the fourth reference signal terminal and the first reference signal terminal can be set to the same signal terminal, that is, the same reference signal terminal is used to provide the signals of the fourth reference signal terminal and the first reference signal terminal .
  • one frame time is divided into a display scan phase DP and a blank time phase BT.
  • the signal timing of each first clock signal terminal CLK1_n in the display scan phase DP is the same, and the signal timing of each first clock signal terminal CLK1_n in the blank time phase BT is different.
  • the signal timing of each second clock signal terminal CLK2_n in the display scan phase DP is the same, and the signal timing of each second clock signal terminal CLK2_n in the blank time phase BT is different.
  • the display scan phase DP includes: an input phase T1, an output phase T2, and a reset phase T3.
  • both the eighteenth transistor M18 and the nineteenth transistor M19 are turned on to provide the high-level signal of the input signal terminal INPUT to the gate of the twenty-first transistor M21 and pass through the third capacitor C3
  • the 21st transistor M21 is maintained and controlled to be turned on to provide the high level of the fourth reference signal terminal VREF4 to the 22nd transistor M22.
  • the twenty-second transistor M22 is turned off, so that it does not affect the signal of the first node PU.
  • the remaining working process at this stage may be basically the same as the working process at the input stage T1 in the second embodiment, which will not be repeated here.
  • the working processes of the output stage T2 and the reset stage T3 in the third embodiment may be basically the same as the working processes of the output stage T2 and the reset stage T3 in the second embodiment, which will not be repeated here.
  • the blank time phase BT may include: a detection input phase T4, a detection output phase T5, and a detection reset phase T6.
  • the input signal terminal INPUT, the reset signal terminal RE, the second clock signal terminals CLK2_1 to CLK2_2, the third clock signal terminal CLK3, and the first to fourth reference signal terminals VREF4 are all loaded with low-level signals.
  • the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all turned off. Since the signal of the first node PU is a high-level signal, and the first transistor M1 and the second transistor M2 form a diode connection structure, the signals outputting the control nodes PO_1 and PO_2 are also high-level signals. Since the signal of the output control node PO_1 is a high-level signal, both the seventh transistor M7 and the two third transistors M3 are turned on. The turned-on seventh transistor M7 provides the low level of the third clock signal terminal CLK3 to the cascade signal output terminal CROUT to output the low-level cascade signal CR.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_1 provides the signal of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1 to output a low-level scanning signal gout1_1.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_2 provides the signal of the first clock signal terminal CLK1_2 to the first sub-scanning signal output terminal GOUT1_2 to output a low-level scanning signal gout1_2. Since the signal of the output control node PO_2 is a high-level signal, the two fifth transistors M5 are turned on.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the signal of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level scanning signal gout2_1.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_2 supplies the signal of the second clock signal terminal CLK2_2 to the second sub-scanning signal output terminal GOUT2_2 to output a low-level scanning signal gout2_2.
  • the first clock signal terminal CLK1_1 has two high-level pulses
  • the first clock signal terminal CLK1_2 has a high-level pulse.
  • the signal at the output control node PO_1 is kept at a high level signal, so both the seventh transistor M7 and the two third transistors M3 are turned on.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_1 provides the signal of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1 to output the scan signal gout1_1 with two high-level pulses.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_2 supplies the signal of the first clock signal terminal CLK1_2 to the first sub-scanning signal output terminal GOUT1_2 to output the scanning signal gout1_2 with a high-level pulse.
  • the turned-on seventh transistor M7 supplies the high level of the third clock signal terminal CLK3 to the cascade signal output terminal CROUT to output the high-level cascade signal CR. Due to the function of the second capacitor C2, the signal at the output control node PO_2 is kept at a high level signal, so the two fifth transistors M5 are turned on.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the signal of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level scanning signal gout2_1.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_2 supplies the signal of the second clock signal terminal CLK2_2 to the second sub-scanning signal output terminal GOUT2_2 to output a low-level scanning signal gout2_2.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_1 provides the low level of the first clock signal terminal CLK1_1 to the first sub-scanning signal output terminal GOUT1_1 to output the low-level scanning signal gout1_1.
  • the third transistor M3 in the first sub-scanning signal output circuit 41_2 provides the low level of the first clock signal terminal CLK1_2 to the first sub-scanning signal output terminal GOUT1_2 to output the low-level scanning signal gout1_2.
  • the turned-on seventh transistor M7 provides the low level of the third clock signal terminal CLK3 to the cascade signal output terminal CROUT to output the low-level cascade signal CR.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the signal of the second clock signal terminal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the low-level scanning signal gout2_1.
  • the fifth transistor M5 in the second sub-scanning signal output circuit 42_2 supplies the signal of the second clock signal terminal CLK2_2 to the second sub-scanning signal output terminal GOUT2_2 to output a low-level scanning signal gout2_2.
  • the external compensation of the OLED is detected in the blank time period, so that the scan signals gout1_1 and gout1_2 output through the shift register in the third embodiment input signals G01 and G02 to two gate lines in a row, respectively, to
  • the OLED in the row is controlled to realize the display function
  • the OLED in the row is controlled to realize the detection function of external compensation.
  • the scan signals gout2_1 and gout2_2 are used to input signals G01 and G02 to the two gate lines in the next row, respectively, to meet the needs of OLED display.
  • the branch control circuit 20 may include: a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is used to receive the signal of the first reference signal terminal VREF1, the first electrode of the first transistor M1 is coupled to the first node PU, and the second electrode of the first transistor M1 is coupled to the first scan signal
  • the output control node PO_1 corresponding to the output circuit is coupled.
  • the gate of the second transistor M2 is used to receive the signal of the first reference signal terminal VREF1, the first pole of the second transistor M2 is coupled to the first node PU, and the second pole of the second transistor M2 and the second scan signal are output
  • the output control node PO_2 corresponding to the circuit is coupled.
  • the first reference signal terminal is a high-level signal during the display scan phase DP and the blank time phase BT.
  • the voltage value of the first reference signal terminal is the same as the voltage value of the first clock signal terminal and the voltage value of the second clock signal terminal.
  • the voltage value of the gate of the first transistor M1 and its first electrode is the same, which is equivalent to forming a diode connection structure
  • the gate of the second transistor M2 is The voltage value of the first pole is the same, which is equivalent to forming a diode connection structure.
  • the rest of the working process at this stage may be basically the same as the working process of the input stage T1 in the third embodiment, which will not be repeated here.
  • the output stage T2 since the output control signals PO_1 to PO_1 are pulled high, the gate-source voltages of the first transistor M1 and the second transistor M2 are large, causing the first transistor M1 and the second transistor M2 to be turned off, so that the pull The signals of the high output control signals PO_1 to PO_1 will not affect each other through the first node PU, thereby improving circuit stability.
  • the rest of the working process at this stage may be basically the same as the working process at the output stage T2 in Embodiment 3, which will not be repeated here.
  • the first transistor M1 and the second transistor M2 are always on.
  • the rest of the working process at this stage may be basically the same as the working process at the reset stage T3 in Embodiment 3, and will not be repeated here.
  • the detection input stage T4 In the detection input stage T4, the detection output stage T5, and the detection reset stage T6.
  • the first transistor M1 and the second transistor M2 are always on.
  • the remaining working processes of these three stages may be basically the same as the working processes of the detection input stage T4, the detection output stage T5, and the detection reset stage T6 in Embodiment 3, which will not be repeated here.
  • an embodiment of the present disclosure also provides a method for driving a shift register provided by an embodiment of the present disclosure, by which the shift register provided by the embodiment of the present disclosure can be driven to output multiple shift registers Different scanning signals.
  • the driving method reference may be made to the implementation of the aforementioned shift register, and the repetition is not repeated here.
  • the display scanning stage may include: an input stage, an output stage, and a reset stage. Specifically, as shown in FIG. 13, the following steps may be included:
  • the signal control circuit controls the signal of the first node and the signal of the second node in response to the signal of the input signal terminal;
  • the branch control circuit controls the one-to-one correspondence with each scan signal output circuit in response to the signal of the first node
  • the output signal of the output control node the cascade signal output circuit responds to the signal of an output control node, controls the cascade signal output terminal to output the cascade signal;
  • each scan signal output circuit responds to the signal of the corresponding output control node, and outputs different Scan signal
  • the branch control circuit controls the signal of the output control node corresponding to each scan signal output circuit in response to the signal of the first node; the cascade signal output circuit responds to the signal of an output control node The cascade signal is output from the cascade signal output terminal; each scan signal output circuit outputs different scan signals in response to the signal of the corresponding output control node;
  • the signal control circuit controls the signal of the first node and the signal of the second node in response to the reset signal;
  • the cascade signal output circuit controls the output of the cascade signal output terminal in response to a signal output from the control node Signal;
  • each scan signal output circuit outputs different scan signals in response to the signal of the corresponding output control node.
  • the first scan signal output circuit of the two scan signal output circuits includes: a plurality of first sub-scan signal output circuits; the second scan signal output circuit includes: a plurality of Two sub-scanning signal output circuit.
  • each first sub-scanning signal output circuit provides the corresponding first clock signal to the corresponding first sub-scanning signal output terminal in response to the signal of the corresponding output control node ;
  • Each second sub-scanning signal output circuit responds to the signal of the corresponding output control node, provides the corresponding second clock signal to the corresponding second sub-scanning signal output terminal;
  • the cascade signal output circuit responds to the branch control circuit A signal from an output terminal, providing a third clock signal to the cascade signal output terminal;
  • each first sub-scanning signal output circuit responds to the signal of the second node, and provides a second reference signal to the corresponding first sub-scanning signal output terminal; each second sub-scanning signal output circuit responds to the second node Signal, the second reference signal is provided to the corresponding second sub-scanning signal output terminal; the cascade signal output circuit responds to the signal of the first output terminal of the branch control circuit, and provides the third reference signal to the cascade signal output terminal.
  • the signal timing of each first clock signal terminal is the same, the signal timing of each second clock signal terminal is the same, and the signal timing of the first clock signal terminal and the second clock signal terminal are different.
  • the shift register further includes a detection circuit, so that the shift register can be applied to the OLED display device.
  • the driving method may further include: a blank time phase; wherein, the blank time phase may include: a detection input phase, a detection output phase, and a detection reset phase.
  • the blank time phase may include: a detection input phase, a detection output phase, and a detection reset phase.
  • an embodiment of the present disclosure also provides a gate drive circuit, as shown in FIGS. 14a and 14b, including a plurality of cascaded shift registers provided by the embodiments of the present disclosure: SR (n-2) , SR (n-1), SR (n), SR (n + 1), SR (n + 2); (N shift registers in total, 1 ⁇ n ⁇ N and n is an integer);
  • the input signal of the first-stage shift register is input from the frame start signal end;
  • the input signal terminal INPUT of the fourth-stage shift register SR (n + 1) is input by the cascade signal CR of the first-stage shift register SR (n-2);
  • the reset signal terminal RE of the first-stage shift register SR (n-2) is input by the cascade signal CR of the fifth-stage shift register SR (n + 2).
  • FIG. 14a is an example in which the structure of the shift register adopts the structure shown in FIG. 4 as an example.
  • FIG. 14b is an example in which the structure of the shift register adopts the structure shown in FIG. 9 as an example.
  • the first clock signal terminal CLK1_1 of the 5y-4th stage shift register is provided by the same clock signal line clk1_1, and the second clock signal terminal CLK2_1 is provided by The same clock signal line clk2_1 is provided, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_1.
  • the first clock signal terminal CLK1_1 of the 5y-3 stage shift register is provided by the same clock signal line clk1_2, the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_2, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_2 .
  • the first clock signal terminal CLK1_1 of the 5y-2 stage shift register is provided by the same clock signal line clk1_3, the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_3, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_3 .
  • the first clock signal terminal CLK1_1 of the shift register of the 5y-1 stage is provided by the same clock signal line clk1_4, the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_4, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_4 .
  • the first clock signal terminal CLK1_1 of the shift register in the 5y stage is provided by the same clock signal line clk1_5, the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_5, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_5.
  • k is a positive integer.
  • the first clock signal terminal CLK1_1 of the 5y-4th stage shift register is provided by the same clock signal line clk1_11, and the first clock signal terminal CLK1_2 is The same clock signal line clk1_21 is provided, the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_11, the second clock signal terminal CLK2_2 is provided by the same clock signal line clk2_21, and the third clock signal terminal CLK3 is provided by the same clock signal line clk3_1.
  • the first clock signal terminal CLK1_1 of the 5y-3 stage shift register is provided by the same clock signal line clk1_12
  • the first clock signal terminal CLK1_2 is provided by the same clock signal line clk1_22
  • the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_12
  • the second clock signal terminal CLK2_2 is provided by the same clock signal line clk2_22
  • the third clock signal terminal CLK3 is provided by the same clock signal line clk3_2.
  • the first clock signal terminal CLK1_1 of the 5y-2 stage shift register is provided by the same clock signal line clk1_13
  • the first clock signal terminal CLK1_2 is provided by the same clock signal line clk1_23
  • the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_13
  • the second clock signal terminal CLK2_2 is provided by the same clock signal line clk2_23
  • the third clock signal terminal CLK3 is provided by the same clock signal line clk3_3.
  • the first clock signal terminal CLK1_1 of the 5y-1 stage shift register is provided by the same clock signal line clk1_14
  • the first clock signal terminal CLK1_2 is provided by the same clock signal line clk1_24
  • the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_14
  • the second clock signal terminal CLK2_2 is provided by the same clock signal line clk2_24
  • the third clock signal terminal CLK3 is provided by the same clock signal line clk3_4.
  • the first clock signal terminal CLK1_1 of the shift register in the 5y stage is provided by the same clock signal line clk1_15
  • the first clock signal terminal CLK1_2 is provided by the same clock signal line clk1_25
  • the second clock signal terminal CLK2_1 is provided by the same clock signal line clk2_15
  • the second clock signal terminal CLK2_2 is provided by the same clock signal line clk2_25
  • the third clock signal terminal CLK3 is provided by the same clock signal line clk3_5.
  • k is a positive integer.
  • the first detection control signals of the shift registers at all levels are the same signal to control the shift registers at all levels within a frame time.
  • the second detection control signal of each stage of the shift register is different. In a frame time, only the second detection control signal terminal corresponding to the first stage of the shift register has a high-level pulse signal, so that the stage of the shift register is in During the blank time period, the scan signals gout1_1, gout1_2, gout2_1, and gout2_2 shown in FIG. 11 are output. The remaining shift registers output low-level signals during the blank time period.
  • each shift register in the above-mentioned gate drive circuit is the same in function and structure as the above-mentioned shift register of the present disclosure, and the repetition is not repeated.
  • an embodiment of the present disclosure also provides an array substrate including the gate driving circuit provided by the embodiment of the present disclosure.
  • the principle of the array substrate to solve the problem is similar to that of the aforementioned gate drive circuit, so the implementation of the array substrate can refer to the implementation of the aforementioned gate drive circuit, and the repetition is not repeated here.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure includes the above-mentioned gate driving circuit, and provides a scanning signal for each gate line on the array substrate through the shift registers at all levels in the gate driving circuit. The description of the registers will not be repeated here.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned array substrate provided by the embodiment of the present disclosure.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the other indispensable components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • the shift register, the driving method thereof, the gate driving circuit, the array substrate and the display device respond to the input signal and the reset signal through the signal control circuit to control the signal of the first node and the signal of the second node .
  • the branch control circuit is configured to control the signal of the output control node corresponding to each scan signal output circuit in response to the signal of the first node, and the different output control nodes can be divided so that the signal at the output control node changes The time may not affect the signals of other output control nodes.
  • the cascade signal output circuit outputs the cascade signal in response to the output control node signal and the second node signal corresponding to the first scan output circuit of the plurality of scan signal output circuits, and provides an input signal for the next stage shift register .
  • each scan signal output circuit outputs different scan signals in response to the corresponding output control node signal and the second node signal.
  • each shift register can output multiple scan signals to correspond to different gate lines in the display panel.
  • the number of shift registers in the gate drive circuit can be reduced, the occupied space of the gate drive circuit can be reduced, and an ultra-narrow bezel design can be realized.
  • the signals of different output control nodes have no influence on each other, the output stability can also be improved.

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Abstract

本公开公开了一种移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置，通过信号控制电路、分支控制电路、级联信号输出电路以及至少两个扫描信号输出电路，可以使每个移位寄存器输出至少两个扫描信号，以对应显示面板中的不同栅线。与现有的移位寄存器仅能输出一个扫描信号相比，可以使栅极驱动电路中移位寄存器的数量减少，降低栅极驱动电路的占用空间，实现超窄边框设计。并且，由于不同输出控制节点的信号相互无影响，从而还可以提高输出稳定性。

Description

移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置
相关申请的交叉引用
本公开要求在2018年11月13日提交中国专利局、申请号为201811345139.4、申请名称为“移位寄存器单元及其驱动方法、栅极驱动电路及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。其中，阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)栅极驱动电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省去栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间。一般的栅极驱动电路均是由多个级联的移位寄存器组成，各级移位寄存器分别对应连接一条栅线，以通过各级移位寄存器实现依次向显示面板上的各行栅线输入扫描信号。然而，由于每行的栅线均对应连接一个移位寄存器，使得栅极驱动电路的结构设计复杂，并且所占显示面板的空间较大，不利于窄边框设计。
发明内容
本公开实施例提供了一种移位寄存器，包括：
信号控制电路，与输入信号端和复位信号端耦接；
分支控制电路，与所述信号控制电路的第一输出端耦接；
级联信号输出电路，与级联信号输出端和所述信号控制电路的第二输出端耦接；
至少两个扫描信号输出电路，所述至少两个扫描信号输出电路中的一个所述扫描信号输出电路与所述信号控制电路的第二输出端、对应的至少一个扫描信号输出端以及所述分支控制电路对应的一个输出端耦接。
可选地，在本公开实施例中，所述级联信号输出电路与所述分支控制电路的一个输出端耦接。
可选地，在本公开实施例中，所述扫描信号输出电路为两个，包括第一扫描信号输出电路和第二扫描信号输出电路；
所述第一扫描信号输出电路与所述分支控制电路的第一输出端耦接；所述第二扫描信号输出电路与所述分支控制电路的第二输出端耦接。
可选地，在本公开实施例中，所述分支控制电路包括：第一晶体管和第二晶体管；
所述第一晶体管在有效电平的控制下连通所述信号控制电路的第一输出端与所述分支控制电路的第一输出端，所述第二晶体管在有效电平的控制下连通所述信号控制电路的第一输出端与所述分支控制电路的第二输出端。
可选地，在本公开实施例中，所述第一晶体管的栅极与其第一极均与所述信号控制电路的第一输出端耦接，所述第一晶体管的第二极为所述分支控制电路的第一输出端；
所述第二晶体管的栅极与其第一极均与所述信号控制电路的第一输出端耦接，所述第二晶体管的第二极为所述分支控制电路的第二输出端。
可选地，在本公开实施例中，所述第一晶体管的栅极与第一参考信号端耦接，所述第一晶体管的第一极与所述信号控制电路的第一输出端耦接，所述第一晶体管的第二极为所述分支控制电路的第一输出端；
所述第二晶体管的栅极与所述第一参考信号端耦接，所述第二晶体管的第一极与所述信号控制电路的第一输出端耦接，所述第二晶体管的第二极为所述分支控制电路的第二输出端。
可选地，在本公开实施例中，所述第一扫描信号输出电路包括：至少1个第一子扫描信号输出电路；其中，一个所述第一子扫描信号输出电路与第二参考信号端、对应的一个第一时钟信号端和对应的一个第一子扫描信号输出端耦接。
可选地，在本公开实施例中，所述第一子扫描信号输出电路包括：第三晶体管、第四晶体管以及第一电容；
所述第三晶体管的栅极与所述分支控制电路的第一输出端耦接，所述第三晶体管的第一极与所述第一时钟信号端耦接，所述第三晶体管的第二极与对应的所述第一子扫描信号输出端耦接；
所述第四晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第四晶体管的第一极与所述第二参考信号端耦接，所述第四晶体管的第二极与对应的所述第一子扫描信号输出端耦接；
所述第一电容耦接于所述第三晶体管的栅极与所述第一子扫描信号输出端之间。
可选地，在本公开实施例中，所述第二扫描信号输出电路包括：至少1个第二子扫描信号输出电路；其中，一个所述第二子扫描信号输出电路分别与第二参考信号端、对应的一个第二时钟信号端和对应的一个第二子扫描信号输出端耦接。
可选地，在本公开实施例中，所述第二子扫描信号输出电路包括：第五晶体管、第六晶体管以及第二电容；
所述第五晶体管的栅极与所述分支控制电路的第二输出端耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与对应的所述第二子扫描信号输出端耦接；
所述第六晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第六晶体管的第一极与所述第二参考信号端耦接，所述第六晶体管的第二极与对应的所述第二子扫描信号输出端耦接；
所述第二电容耦接于所述第五晶体管的栅极与所述第二子扫描信号输出 端之间。
可选地，在本公开实施例中，所述级联信号输出电路包括：第七晶体管和第八晶体管；
所述第七晶体管的栅极与所述分支控制电路的第一输出端耦接，所述第七晶体管的第一极与第三时钟信号端耦接，所述第七晶体管的第二极与所述级联信号输出端耦接；
所述第八晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第八晶体管的第一极与所述第三参考信号端耦接，所述第八晶体管的第二极与所述级联信号输出端耦接。
可选地，在本公开实施例中，所述信号控制电路包括：输入电路、复位电路、节点控制电路；
所述输入电路分别与所述输入信号端，第一参考信号端和所述信号控制电路的第一输出端耦接；
所述复位电路分别与所述复位信号端，第三参考信号端以及所述分支控制电路的第一输出端和第二输出端耦接；
所述节点控制电路分别与所述第一参考信号端、所述第三参考信号端、所述信号控制电路的第一输出端和第二输出端、所述分支控制电路的第一输出端和第二输出端耦接。
可选地，在本公开实施例中，所述输入电路包括：第九晶体管；其中，所述第九晶体管的栅极与所述输入信号端耦接，所述第九晶体管的第一极与所述第一参考信号耦接，所述第九晶体管的第二极与所述信号控制电路的第一输出端耦接；
所述复位电路包括：第十晶体管与第十一晶体管；其中，所述第十晶体管的栅极与所述复位信号端耦接，所述第十晶体管的第一极与所述第三参考信号端耦接，所述第十晶体管的第二极与所述分支控制电路的第一输出端耦接；所述第十一晶体管的栅极与所述复位信号端耦接，所述第十一晶体管的第一极与所述第三参考信号端耦接，所述第十一晶体管的第二极与所述分支 控制电路的第二输出端耦接；
所述节点控制电路包括：第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管；其中，所述第十二晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第十二晶体管的第一极与所述第三参考信号端耦接，所述第十二晶体管的第二极与所述分支控制电路的第一输出端耦接；所述第十三晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第十三晶体管的第一极与所述第三参考信号端耦接，所述第十三晶体管的第二极与所述分支控制电路的第二输出端耦接；所述第十四晶体管的栅极与其第一极均与所述第一参考信号端耦接，所述第十四晶体管的第二极与所述信号控制电路的第二输出端耦接；所述第十五晶体管的栅极与所述信号控制电路的第一输出端耦接，所述第十五晶体管的第一极与所述第三参考信号端耦接，所述第十五晶体管的第二极与所述信号控制电路的第二输出端耦接。
可选地，在本公开实施例中，所述复位电路还包括：第十六晶体管；其中，所述第十晶体管的第一极与所述第十一晶体管的第一极分别通过所述第十六晶体管与所述第三参考信号端耦接；所述第十六晶体管的栅极与所述复位信号端耦接；
所述节点控制电路还包括：第十七晶体管；其中，所述第十二晶体管的第一极和所述第十三晶体管的第一极分别通过所述第十七晶体管与所述第三参考信号端耦接；所述第十七晶体管的栅极与所述信号控制电路的第二输出端耦接。
可选地，在本公开实施例中，所述移位寄存器还包括：检测电路；所述检测电路包括：第十八晶体管、第十九晶体管、第二十晶体管、第二十一晶体管、第二十二晶体管以及第三电容；
所述第十八晶体管的栅极与第一检测控制信号端耦接，所述第十八晶体管的第一极与所述输入信号端耦接，所述第十八晶体管的第二极与所述第二十晶体管的第一极耦接；
所述第十九晶体管的栅极与所述第一检测控制信号端耦接，所述第十九 晶体管的第一极与所述第二十一晶体管的栅极耦接，所述第十九晶体管的第二极与所述第二十晶体管的第一极耦接；
所述第二十晶体管的栅极与所述第二十一晶体管的栅极耦接，所述第二十晶体管的第二极用于与第四参考信号端耦接；
所述第二十一晶体管的第一极与所述第四参考信号端耦接，所述第二十一晶体管的第二极与所述第二十二晶体管的第一极耦接；
所述第二十二晶体管的栅极与第二检测控制信号端耦接，所述第二十二晶体管的第二极与所述信号控制电路的第一输出端耦接；
所述第三电容耦接于所述第二十一晶体管的第一极与第二十一晶体管的栅极之间。
相应地，本公开实施例还提供了一种栅极驱动电路，包括级联的多个本公开实施例提供的上述移位寄存器；
第一级移位寄存器的输入信号端与帧起始信号端耦接；
每相邻四级移位寄存器中，第四级移位寄存器的输入信号端与第一级移位寄存器的级联信号输入端耦接；
每相邻五级移位寄存器中，第一级移位寄存器的复位信号端与第五级移位寄存器的级联信号输入端耦接。
相应地，本公开实施例还提供了一种阵列基板，包括本公开实施例提供的栅极驱动电路。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的阵列基板。
相应地，本公开实施例还提供了一种本公开实施例提供的移位寄存器的驱动方法，包括：显示扫描阶段；其中，所述显示扫描阶段包括：输入阶段、输出阶段以及复位阶段；
在所述输入阶段，所述信号控制电路响应于所述输入信号端的信号，控制所述信号控制电路的第一输出端的信号和所述信号控制电路的第二输出端的信号；所述分支控制电路响应于所述信号控制电路的第一输出端的信号， 控制与所述分支控制电路的各输出端的输出信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于所述分支控制电路对应的一个输出端的信号，控制对应的至少一个扫描信号输出端输出不同的扫描信号；
在所述输出阶段，所述分支控制电路响应于所述信号控制电路的第一输出端的信号，控制所述分支控制电路的各输出端的输出信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于所述分支控制电路对应的一个输出端的信号，控制对应的至少一个扫描信号输出端输出不同的扫描信号；
在所述复位阶段，所述信号控制电路响应于所述复位信号端的信号，控制所述信号控制电路的第一输出端和第二输出端的信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于对应的输出控制节点的信号，输出不同的扫描信号。
可选地，在本公开实施例中，所述扫描信号输出电路为两个，包括第一扫描信号输出电路和第二扫描信号输出电路；所述第一扫描信号输出电路包括：多个第一子扫描信号输出电路；所述第二扫描信号输出电路包括：多个第二子扫描信号输出电路；
在所述输入阶段和所述输出阶段，各所述第一子扫描信号输出电路响应于所述分支控制电路的第一输出端的信号，将对应的所述第一时钟信号端的信号提供给对应的第一子扫描信号输出端；各所述第二子扫描信号输出电路响应于所述分支控制电路的第二输出端的信号，将对应的所述第二时钟信号端的信号提供给对应的第二子扫描信号输出端；所述级联信号输出电路响应于所述分支控制电路的第一输出端的信号，将第三时钟信号端的信号提供给级联信号输出端；
在所述复位阶段，各所述第一子扫描信号输出电路响应于所述信号控制 电路的第二输出端的信号，将第二参考信号端的信号提供给对应的第一子扫描信号输出端；各所述第二子扫描信号输出电路响应于所述信号控制电路的第二输出端的信号，将所述第二参考信号端的信号提供给对应的第二子扫描信号输出端；所述级联信号输出电路响应于所述信号控制电路的第二输出端的信号，将第三参考信号端的信号提供给所述级联信号输出端。
可选地，在本公开实施例中，在所述显示扫描阶段，各所述第一时钟信号端的信号时序相同，各所述第二时钟信号端的信号时序相同，所述第一时钟信号端和所述第二时钟信号端的信号时序不同。
附图说明
图1为相关技术中的移位寄存器的结构示意图；
图2为图1所示的移位寄存器的信号仿真模拟图；
图3为本公开实施例提供的移位寄存器的结构示意图；
图4为本公开实施例提供的移位寄存器的一种具体结构示意图；
图5为本公开实施例提供的一种电路时序图；
图6为对图4所示的移位寄存器进行仿真模拟后的模拟时序图；
图7为本公开实施例提供的移位寄存器的另一种具体结构示意图；
图8为本公开实施例提供的另一种电路时序图；
图9为本公开实施例提供的移位寄存器的另一种具体结构示意图；
图10为本公开实施例提供的像素电路的结构示意图；
图11为本公开实施例提供的另一种电路时序图；
图12为本公开实施例提供的移位寄存器的另一种具体结构示意图；
图13为本公开实施例提供的驱动方法的流程图；
图14a为本公开实施例提供的栅极驱动电路的一种结构示意图；
图14b为本公开实施例提供的栅极驱动电路的另一种结构示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的移位寄存器及其驱动方法、栅极驱动电路及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。需要注意的是，附图中各形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，为了实现输出多个扫描信号，移位寄存器可以设置多个扫描信号输出电路01，例如图1中设置了两个扫描信号输出电路01；其中一个扫描信号输出电路01输出扫描信号G1，另一个扫描信号输出电路01输出扫描信号G2。具体地，通过信号控制电路控制上拉节点A的信号和下拉节点B的信号。输出扫描信号G1的扫描信号输出电路01包括：晶体管M01和M02以及电容C01；其中，晶体管M01的栅极与上拉节点A耦接，晶体管M01的第一极用于接收时钟信号CK1，晶体管M01的第二极用于输出扫描信号G1。晶体管M02的栅极与下拉节点B耦接，晶体管M02的第一极用于接收信号VGL，晶体管M02的第二极与晶体管01的第二极耦接。电容C01耦接于上拉节点A与晶体管01的第二极之间。输出扫描信号G2的扫描信号输出电路01包括：晶体管M03和M04以及电容C02；其中，晶体管M03的栅极与上拉节点A耦接，晶体管M03的第一极用于接收时钟信号CK2，晶体管M03的第二极用于输出扫描信号G2。晶体管M04的栅极与下拉节点B耦接，晶体管M04的第一极用于接收信号VGL，晶体管M04的第二极与晶体管03的第二极耦接。电容C02耦接于上拉节点A与晶体管03的第二极之间。其中，晶体管M01在上拉节点A的信号控制下可以将时钟信号CK1的信号提供给其第二端，以作为扫描信号G1输出。晶体管03在上拉节点A的信号控制下可以将时钟信号CK2的信号提供给其第二端，以作为扫描信号G2输出。通过对时钟信号CK1、CK2、上拉节点A的信号a、下拉节点B的信号b以及扫描信号G1和G2进行仿真模拟可以得到模拟时序图，如图2所示。由于时 钟信号CK1的高电平早于时钟信号CK2的高电平出现，晶体管01在上拉节点A的信号控制下导通以将时钟信号CK1的高电平的信号作为扫描信号G1输出时，会拉高上拉节点A的电平。在晶体管02在上拉节点A的信号控制下导通以将时钟信号CK2的高电平的信号作为扫描信号G2输出时，会进一步拉高上拉节点A的电平。由于晶体管01与晶体管03均受相同的上拉节点A的信号a的控制，且时钟信号CK1的高电平优先转换为低电平，导致扫描信号G1由高电平恢复为低电平的下降时间(Fall Time)RFT(12us)小于扫描信号G2由高电平恢复为低电平的下降时间RFT(14us)，从而导致输出的扫描信号G1和G2的波形有差异。
基于此，本公开实施例提供一种移位寄存器，如图3所示，可以包括：信号控制电路10、分支控制电路20、级联信号输出电路30以及至少两个扫描信号输出电路40_m(1≤m≤M，M代表扫描信号输出电路的总数，图3以M＝2为例)；其中，
信号控制电路10与输入信号端INPUT和复位信号端RE耦接，即信号控制电路10被配置为响应于输入信号端INPUT的信号和复位信号端RE的信号，控制信号控制电路10的第一输出端和第二输出端的信号；为了方便描述，将信号控制电路10的第一输出端记为第一节点PU，将信号控制电路10的第一输出端记为第二节点PD；
分支控制电路20与信号控制电路10的第一输出端耦接，即分支控制电路20被配置为响应于第一节点PU的信号，控制与各扫描信号输出电路40_m一一对应的输出控制节点PO_m的信号；为了方便描述，将分支控制电路20的各输出端记为输出控制节点PO_m；
级联信号输出电路30分别与级联信号输出端CROUT，分支控制电路20的一个输出端和信号控制电路10的第二输出端耦接，即级联信号输出电路30被配置为响应于多个扫描信号输出电路中的第一扫描输出电路对应的输出控制节点PO_1的信号和第二节点PD的信号，输出级联信号CR；
每一个扫描信号输出电路40_m分别与信号控制电路10的第二输出端、 对应的至少一个扫描信号输出端goutm以及分支控制电路20对应的一个输出端耦接，即各扫描信号输出电路40_m被配置为响应于对应的输出控制节点PO_m的信号和第二节点PD的信号，输出不同的扫描信号goutm。
本公开实施例提供的移位寄存器，通过信号控制电路响应于输入信号端和复位信号端的信号，以控制第一节点的信号和第二节点的信号。通过分支控制电路被配置为响应于第一节点的信号，控制与各扫描信号输出电路一一对应的输出控制节点的信号，可以将不同的输出控制节点分割开，从而在输出控制节点的信号变化时可以不会影响其他输出控制节点的信号。通过级联信号输出电路响应于多个扫描信号输出电路中的第一扫描输出电路对应的输出控制节点的信号和第二节点的信号，输出级联信号，为下一级移位寄存器提供输入信号。通过设置多个扫描信号输出电路，以通过各扫描信号输出电路响应于对应的输出控制节点的信号和第二节点的信号，输出不同的扫描信号。这样可以使每个移位寄存器输出多个扫描信号，以对应显示面板中的不同栅线。与现有的移位寄存器仅能输出一个扫描信号相比，可以使栅极驱动电路中移位寄存器的数量减少，降低栅极驱动电路的占用空间，实现超窄边框设计。并且，由于不同输出控制节点的信号相互无影响，从而还可以提高输出稳定性。
在具体实施时，在本公开实施例中，如图4所示，信号控制电路10可以包括：输入电路11、复位电路12、节点控制电路13，这样可以通过输入电路11、复位电路12以及节点控制电路13的相互配合，控制第一节点PU、输出控制节点PO_m以及第二节点PD的信号的电平。其中，输入电路11分别与输入信号端INPUT，第一参考信号端VREF1和信号控制电路的第一输出端耦接，输入电路11被配置为响应于输入信号端INPUT的信号，将第一参考信号端VREF1的信号提供给第一节点PU。复位电路12分别与复位信号端RE，第三参考信号端VREF3以及分支控制电路20的第一输出端和第二输出端耦接，复位电路12被配置为响应于复位信号端RE的信号，将第三参考信号端VREF3的信号提供给各扫描信号输出电路40_m对应的输出控制节点PO_m。 节点控制电路13分别与第一参考信号端VREF1、第三参考信号端VREF3、信号控制电路10的第一输出端和第二输出端、分支控制电路20的第一输出端和第二输出端耦接，节点控制电路13被配置为控制第一节点PU的信号和各输出控制节点PO_m的信号分别与第二节点PD的信号的电平相反。
在具体实施时，在本公开实施例中，如图4所示，级联信号输出电路30被配置为响应于多个扫描信号输出电路中的第一扫描信号输出电路40_1对应的输出控制节点PO_1的信号，将第三时钟信号端CLK3的信号提供给级联信号输出端CROUT；以及响应于第二节点PD的信号，将第三参考信号端VREF3的信号提供给级联信号输出端CROUT。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例是为了更好的解释本公开，但不限制本公开。
实施例一、
在具体实施时，在本公开实施例中，如图3与图4所示，可以配置扫描信号输出电路40_m的数量为两个。或者，也可以配置扫描信号输出电路40_m的数量为三个、四个、五个等。当然，在实际应用中，扫描信号输出电路40_m的数量可以根据实际应用环境来设计确定，在此不作限定。下面均以扫描信号输出电路40_m的数量设置为两个为例进行说明。
在具体实施时，在本公开实施例中，如图4所示，两个扫描信号输出电路中的第一扫描信号输出电路40_1可以包括：至少1个第一子扫描信号输出电路41_n(1≤n≤N，N代表第一子扫描信号输出电路的总数，图4以N＝1为例)；其中，一个第一子扫描信号输出电路41_n分别与第二参考信号端VREF2、对应的一个第一时钟信号端CLK1_n和对应的一个第一子扫描信号输出端GOUT1_n耦接；各第一子扫描信号输出电路41_n一一对应一个第一时钟信号端CLK1_n，各第一子扫描信号输出电路41_n一一对应一个第一子扫描信号输出端GOUT1_n。并且，第一子扫描信号输出电路41_n被配置为响应于同一输出控制节点的信号，即第一子扫描信号输出电路41_n被配置为响应于输出控制节点PO_1的信号，将对应的第一时钟信号端CLK1_n的信号 提供给对应的第一子扫描信号输出端GOUT1_n；以及响应于第二节点PD的信号，将第二参考信号端VREF2的信号提供给对应的第一子扫描信号输出端GOUT1_n。并且，第一子扫描信号输出端GOUT1_n分别输出扫描信号gout1_n。
进一步地，在具体实施时，如图4所示，可以设置1个第一子扫描信号输出电路；或者也可以设置2个第一子扫描信号输出电路。在实际应用中，第一子扫描信号输出电路的具体数量可以根据实际应用环境来设计确定，在此不作限定。下面以设置1个第一子扫描信号输出电路为例进行说明。
在具体实施时，在本公开实施例中，如图4所示，两个扫描信号输出电路中的第二扫描信号输出电路40_2可以包括：至少1个第二子扫描信号输出电路42_k(1≤k≤K，K代表第二子扫描信号输出电路的总数，图4以K＝1为例)；其中，一个第二子扫描信号输出电路42_k分别与第二参考信号端VREF2、对应的一个第二时钟信号端CLK2_k和对应的一个第二子扫描信号输出端耦接；各第二子扫描信号输出电路42_k一一对应一个第二时钟信号端CLK2_k，各第二子扫描信号输出电路42_k一一对应一个第二子扫描信号输出端GOUT2_k。并且，第二子扫描信号输出电路42_k被配置为响应于同一的输出控制节点的信号，即第二子扫描信号输出电路42_k被配置为响应于输出控制节点PO_2的信号，将对应的第二时钟信号端CLK2_k的信号提供给对应的第二子扫描信号输出端GOUT2_k；以及响应于第二节点PD的信号，将第二参考信号端VREF2的信号提供给对应的第二子扫描信号输出端GOUT2_k。并且，第二子扫描信号输出端GOUT2_k分别输出扫描信号gout2_k。
进一步地，在具体实施时，如图4所示，可以设置1个第二子扫描信号输出电路；或者也可以设置2个第二子扫描信号输出电路。在实际应用中，第二子扫描信号输出电路的具体数量可以根据实际应用环境来设计确定，在此不作限定。下面以设置1个第二子扫描信号输出电路为例进行说明。
进一步地在具体实施时，在本公开实施例中，可以使N＝K，n＝k。
在具体实施时，在本公开实施例中，如图4所示，分支控制电路20可以包括：第一晶体管M1和第二晶体管M2；第一晶体管M1在有效电平的控制 下连通信号控制电路10的第一输出端与分支控制电路20的第一输出端，所述第二晶体管M2在有效电平的控制下连通信号控制电路20的第一输出端与分支控制电路20的第二输出端。
具体地，第一晶体管M1的栅极与其第一极均与第一节点PU耦接，第一晶体管M1的第二极与两个扫描信号输出电路中的第一扫描信号输出电路40_1对应的输出控制节点PO_1耦接；第二晶体管M2的栅极与其第一极均与第一节点PU耦接，第二晶体管M2的第二极与两个扫描信号输出电路中的第二扫描信号输出电路40_2对应的输出控制节点PO_2耦接。
在具体实施时，由于第一晶体管M1的栅极和第一极耦接，因此第一晶体管M1形成二极管连接方式，这样在第一晶体管M1的栅极的电压大于其第二极的电压时，第一晶体管M1可以形成通路，以使第一节点PU与输出控制节点PO_1导通；在第一晶体管M1的栅极的电压不大于其第二极的电压时，第一晶体管M1可以形成断路，以使第一节点PU与输出控制节点PO_1断开。同理，在第二晶体管M2的栅极的电压大于其第二极的电压时，第二晶体管M2可以形成通路，以使第一节点PU与输出控制节点PO_2导通；在第二晶体管M2的栅极的电压不大于其第二极的电压时，第二晶体管M2可以形成断路，以使第一节点PU与输出控制节点PO_2断开。
在具体实施时，在本公开实施例中，如图4所示，第一子扫描信号输出电路41_n可以包括：第三晶体管M3、第四晶体管M4以及第一电容C1；其中，第三晶体管M3的栅极与对应的输出控制节点PO_1耦接，第三晶体管M3的第一极用于接收对应的第一时钟信号端CLK1_n的信号，第三晶体管M3的第二极与对应的第一子扫描信号输出端GOUT1_n耦接。第四晶体管M4的栅极与第二节点PD耦接，第四晶体管M4的第一极用于接收第二参考信号端VREF2的信号，第四晶体管M4的第二极与对应的第一子扫描信号输出端GOUT1_n耦接。第一电容C1耦接于第三晶体管M3的栅极即对应的输出控制节点PO_1与第一子扫描信号输出端GOUT1_n之间。
在具体实施时，在本公开实施例中，各第一子扫描信号输出电路41_n中 的第三晶体管M3在输出控制节点PO_1的信号的控制下可以处于导通状态，以将对应的第一时钟信号端CLK1_n的信号提供给对应的第一子扫描信号输出端GOUT1_n。各第一子扫描信号输出电路41_n中的第四晶体管M4在第二节点PD的信号的控制下可以处于导通状态，以将第二参考信号端VREF2的信号提供给对应的第一子扫描信号输出端GOUT1_n。第一电容C1可以保持连接的输出控制节点PO_1的电平与第一子扫描信号输出端GOUT1_n的电平，以及在输出控制节点PO_1浮接时，可以保持输出控制节点PO_1与第一子扫描信号输出端GOUT1_n之间的电压差稳定。
在具体实施时，在本公开实施例中，如图4所示，第二子扫描信号输出电路42_k可以包括：第五晶体管M5、第六晶体管M6以及第二电容C2；其中，第五晶体管M5的栅极与对应的输出控制节点PO_2耦接，第五晶体管M5的第一极用于接收对应的第二时钟信号端CLK2_k的信号，第五晶体管M5的第二极与对应的第二子扫描信号输出端GOUT2_k耦接。第六晶体管M6的栅极与第二节点PD耦接，第六晶体管M6的第一极用于接收第二参考信号端VREF2的信号，第六晶体管M6的第二极与对应的第二子扫描信号输出端GOUT2_k耦接。第二电容C2耦接于对应的输出控制节点PO_2与第二子扫描信号输出端GOUT2_k之间。
在具体实施时，在本公开实施例中，各第二子扫描信号输出电路42_k中的第五晶体管M5在输出控制节点PO_2的信号的控制下可以处于导通状态，以将对应的第二时钟信号端CLK2_k的信号提供给对应的第二子扫描信号输出端GOUT2_k。各第二子扫描信号输出电路42_k中的第六晶体管M6在第二节点PD的信号的控制下可以处于导通状态，以将第二参考信号端VREF2的信号提供给对应的第二子扫描信号输出端GOUT2_k。第二电容C2可以保持连接的输出控制节点PO_2的电平与第二子扫描信号输出端GOUT2_k的电平，以及在输出控制节点PO_2浮接时，可以保持输出控制节点PO_2与第二子扫描信号输出端GOUT2_k之间的电压差稳定。
在具体实施时，在本公开实施例中，如图4所示，输入电路11可以包括： 第九晶体管M9；其中，第九晶体管M9的栅极用于接收输入信号端INPUT的信号，第九晶体管M9的第一极用于接收第一参考信号端VREF1的信号，第九晶体管M9的第二极与第一节点PU耦接。其中，第九晶体管M9在输入信号端INPUT的控制下可以处于导通状态，以将第一参考信号端VREF1的信号提供给第一节点PU。
在具体实施时，在本公开实施例中，如图4所示，复位电路12可以包括：第十晶体管M10与第十一晶体管M11；其中，第十晶体管M10的栅极用于接收复位信号端RE的信号，第十晶体管M10的第一极用于接收第三参考信号端VREF3的信号，第十晶体管M10的第二极与一个输出控制节点，即输出控制节点PO_1耦接。第十一晶体管M11的栅极用于接收复位信号端RE的信号，第十一晶体管M11的第一极用于接收第三参考信号端VREF3的信号，第十一晶体管M11的第二极与另一个输出控制节点，即输出控制节点PO_2耦接。其中，第十晶体管M10在复位信号端RE的有效脉冲信号的控制下可以处于导通状态，以将第三参考信号端VREF3的信号提供给输出控制节点PO_1。第十一晶体管M11在复位信号端RE的控制下可以处于导通状态，以将第三参考信号端VREF3的信号提供给输出控制节点PO_2。
在具体实施时，在本公开实施例中，如图4所示，节点控制电路13可以包括：第十二晶体管M12、第十三晶体管M13、第十四晶体管M14以及第十五晶体管M15；其中，第十二晶体管M12的栅极与第二节点PD耦接，第十二晶体管M12的第一极用于接收第三参考信号端VREF3的信号，第十二晶体管M12的第二极与一个输出控制节点，即输出控制节点PO_1耦接；第十三晶体管M3的栅极与第二节点PD耦接，第十三晶体管M13的第一极用于接收第三参考信号端VREF3的信号，第十三晶体管M13的第二极与另一个输出控制节点，即输出控制节点PO_2耦接。第十四晶体管M14的栅极与其第一极均用于接收第一参考信号端VREF1的信号，第十四晶体管M14的第二极与第二节点PD耦接；第十五晶体管M15的栅极与第一节点PU耦接，第十五晶体管M15的第一极用于接收第三参考信号端VREF3的信号，第十 五晶体管M15的第二极与第二节点PD耦接。其中，第十二晶体管M12在第二节点PD的信号的控制下可以处于导通状态，以将第三参考信号端VREF3的信号提供给输出控制节点PO_1。第十三晶体管M13在第二节点PD的信号的控制下可以处于导通状态，以将第三参考信号端VREF3的信号提供给输出控制节点PO_2。第十四晶体管M14和第十五晶体管M15可以形成反相器，以使第二节点PD的电平和第一节点PU的电平相反。
在具体实施时，在本公开实施例中，如图4所示，级联信号输出电路30可以包括：第七晶体管M7、第八晶体管M8；其中，第七晶体管M7的栅极与第一扫描信号输出电路对应的输出控制节点PO_1耦接，第七晶体管M7的第一极用于接收第三时钟信号端CLK3的信号，第七晶体管M7的第二极与级联信号输出端CROUT耦接。第八晶体管M8的栅极与第二节点PD耦接，第八晶体管M8的第一极用于接收第三参考信号端VREF3的信号，第八晶体管M8的第二极与级联信号输出端CROUT耦接。第三电容C3耦接于第一节点PU与级联信号输出端CROUT之间。其中，第七晶体管M7在输出控制节点PO_1的信号的控制下可以处于导通状态，以将第三时钟信号CLK3提供给级联信号输出端CROUT。第八晶体管M8在第二节点PD的信号的控制下可以处于导通状态，以将第三参考信号端VREF3的信号提供给级联信号输出端CROUT。
以上仅是举例说明移位寄存器中各电路的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其它结构，在此不做限定。
在具体实施时，为了制作工艺统一，在本公开实施例中，如图4所示，所有开关晶体管可以均为N型晶体管。需要说明的是，本公开实施例仅是以移位寄存器中的晶体管为N型晶体管为例进行说明的，对于晶体管为P型晶体管的情况，设计原理与本公开相同，也属于本公开保护的范围。
需要说明的是，在本公开实施例中，当所有晶体管均为N型晶体管时，第一参考信号端的信号为高电平信号，第二参考信号端的信号和第三参考信 号端的信号均为低电平信号。当所有晶体管均为P型晶体管时，第一参考信号端的信号为低电平信号，第二参考信号端的信号和第三参考信号端的信号均为高电平信号。需要说明的是，本公开实施例中提到的信号的电平仅代表其逻辑电平，而不是在具体实施时各信号实际所施加的电压值。
一般在显示驱动时的一帧时间可以包括显示扫描阶段和空白时间(blanking time)阶段。在具体实施时，在显示扫描阶段，各第一时钟信号端的信号的时序相同，各第二时钟信号端的信号的时序相同，第一时钟信号端的信号与第三时钟信号端的信号的时序相同。第一时钟信号端的信号和第二时钟信号端的信号的时序不同。例如图5所示，第一时钟信号端CLK1_1与第二时钟信号端CLK2_1的信号时序不同，第一时钟信号端CLK1_1与第三时钟信号端CLK3的信号时序相同。需要说明的是，本公开实施例中提到的高电平信号的电压值相同，例如输入信号端INPUT的高电平的电压值、第一时钟信号端CLK1_1的高电平的电压值、第二时钟信号端CLK2_1的高电平的电压值以及第一参考信号端VREF1的电压值相同。进一步地，本公开实施例中提到的低电平信号的电压值也可以相同，例如输入信号端INPUT的低电平的电压值、第一时钟信号端CLK1_1的低电平的电压值、第二时钟信号端CLK2_1的低电平的电压值、第二参考信号端VREF2以及第三参考信号端VREF3的电压值相同。为了降低信号端的数量，减少信号线占用空间，可以将第二参考信号端VREF2与第三参考信号端VREF3设置为同一信号，即采用同一参考信号端提供第二参考信号端VREF2与第三参考信号端VREF3的信号。或者，第二参考信号端VREF2和第三参考信号端VREF3的电压值也可以不同，在此不做限定。
在具体实施时，如图5所示，第一时钟信号端CLK1_n、第二时钟信号端CLK2_k以及第三时钟信号端CLK3的周期相同。例如，在一个周期内，第一时钟信号端CLK1_n的高电平信号的时长可以为4a，低电平信号的时长可以为6a，则第一时钟信号端CLK1_n的信号一个周期的时长为10a。在一个周期内，第二时钟信号端CLK2_n的高电平信号的时长可以为4a，低电平信号的 时长可以为6a，则第二时钟信号端CLK2_n的信号一个周期的时长为10a。在一个周期内，第三时钟信号端CLK3的高电平信号的时长可以为4a，低电平信号的时长可以为6a，则第三时钟信号端CLK3的信号一个周期的时长也为10a。
进一步地，在具体实施时，在本公开实施例提供的移位寄存器中，N型晶体管在高电平信号作用下导通，在低电平信号作用下截止；P型晶体管在低电平信号作用下导通，在高电平信号作用下截止。在具体实施时，晶体管的第一极可以作为源极，第二极作为漏极，或者晶体管的第一极可以作为漏极，第二极作为源极，在此不作具体区分。
下面以图4所示的移位寄存器的结构为例，结合电路时序图，即图5对本公开实施例提供的上述移位寄存器的工作过程作以描述。其中，下述描述中以1表示高电平信号，0表示低电平信号，其中，1和0代表其逻辑电平，仅是为了更好的解释本公开实施例提供的上述移位寄存器的工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压值。
具体地，选取如图5所示的电路时序图中的输入阶段T1、输出阶段T2、复位阶段T3。
在输入阶段T1，INPUT＝1、CLK1_1＝0、CLK2_1＝0、CLK3＝0、RE＝0。
由于INPUT＝1，因此第九晶体管M9导通，以将第一参考信号端VREF1的高电平提供给第一节点PU，使第一节点PU的信号为高电平信号。由于第一节点PU的信号为高电平信号，因此第十五晶体管M15导通，以将第三参考信号端VREF3的低电平提供给第二节点PD，使第二节点PD的信号为低电平信号。从而控制第四晶体管M4、第六晶体管M6、第八晶体管M8、第十二晶体管M12、第十三晶体管M13均截止。由于第一晶体管M1和第二晶体管M2形成二极管连接结构，因此输出控制节点PO_1和PO_2的信号也为高电平信号。由于输出控制节点PO_1的信号为高电平信号，因此第三晶体管M3与第七晶体管M7导通，导通的第七晶体管M7将第三时钟信号端CLK3的低电平提供给级联信号输出端CROUT，以输出低电平的级联信号CR。导 通的第三晶体管M3将第一时钟信号端CLK1_1的低电平提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1，并且第一电容C1充电。由于输出控制节点PO_2的信号为高电平信号，因此第五晶体管M5导通，以将第二时钟信号端CLK2_1的低电平提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1，并且第二电容C2充电。并且，由于RE＝0，因此第十晶体管M10与第十一晶体管M11均截止。
在输出阶段T2，INPUT＝0、CLK1_1＝1、CLK2_1＝0、CLK3＝1、RE＝0。
由于INPUT＝1，因此第九晶体管M9截止，则第一节点PU浮接。由于第一电容C1的作用，因此输出控制节点PO_1保持为高电平信号，以控制第三晶体管M3与第七晶体管M7导通，导通的第七晶体管M7将第三时钟信号端CLK3的高电平提供给级联信号输出端CROUT，以及导通的第三晶体管M3将第一时钟信号端CLK1_1的高电平提供给第一子扫描信号输出端GOUT1_1，从而使输出控制节点PO_1被进一步拉高，以使第三晶体管M3将第一时钟信号端CLK1_1的高电平提供给第一子扫描信号输出端GOUT1_1，输出高电平的扫描信号gout1_1。以及使第七晶体管M7将第三时钟信号端CLK3的高电平提供给级联信号输出端CROUT，输出高电平的级联信号CR。由于第二电容C2的作用，因此输出控制节点PO_2保持为高电平信号，以控制第五晶体管M5导通，以将第二时钟信号端CLK2_1的低电平提供给第二子扫描信号输出端GOUT2_1，输出低电平的扫描信号gout2_1。由于第一节点PU的信号为高电平信号，使得第二节点PD的信号为低电平信号，从而控制第四晶体管M4、第六晶体管M6、第八晶体管M8、第十二晶体管M12、第十三晶体管M13均截止。在输出控制节点PO_1的电平被进一步拉高时，由于第一晶体管M1形成二极管连接方式，因此可以将第一节点PU和输出控制节点PO_1断开，从而避免输出控制节点PO_1被进一步拉高时，影响输出控制节点PO_2的信号。
之后，第二时钟信号端CLK2_1由低电平信号转换为高电平信号，即由CLK2_1＝0转换为CLK2_1＝1，而其余信号未变化。此时，由于第五晶体管 M5将第二时钟信号端CLK2_1的高电平提供给第二子扫描信号输出端GOUT2_1，由于第二电容C2的作用，可以使输出控制节点PO_2的电平被拉高，以通过第五晶体管M5将第二时钟信号端CLK2_1的高电平提供给第二子扫描信号输出端GOUT2_1，输出高电平的扫描信号gout2_1。在输出控制节点PO_2的电平被拉高时，由于第二晶体管M2形成二极管连接方式，因此可以将第一节点PU和输出控制节点PO_2断开，从而避免输出控制节点PO_2被拉高时，影响输出控制节点PO_1的信号。
之后，第一时钟信号端CLK1_1由高电平信号转换为低电平信号，即由CLK1_1＝1转换为CLK1_1＝0，而其余信号未变化。这样第三晶体管M3将第一时钟信号端CLK1_1的提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1。
在复位阶段T3，INPUT＝0、RE＝1。
由于INPUT＝0，因此第九晶体管M9截止，由于RE＝1，因此第十晶体管M10与第十一晶体管M11均导通。导通的第十晶体管M10将第三参考信号端VREF3的低电平提供给输出控制节点PO_1，以使输出控制节点PO_1的信号为低电平信号，导通的第十一晶体管M11将第三参考信号端VREF3的低电平提供给输出控制节点PO_2，以使输出控制节点PO_2的信号为低电平信号，从而可以使第一节点PU放电为低电平信号。这样通过第十四晶体管M14和第十五晶体管M15的作用，可以使第二节点PD为高电平信号。由于第二节点PD的信号为高电平信号，从而控制第四晶体管M4、第六晶体管M6、第八晶体管M8、第十二晶体管M12、第十三晶体管M13均导通。导通的第四晶体管M4将第二参考信号端VREF2的低电平提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1。导通的第六晶体管M6将第二参考信号端VREF2的低电平提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1。导通的第八晶体管M8将第三参考信号端VREF3的低电平提供给级联信号输出端CROUT，以输出低电平的级联信号CR。导通的第十二晶体管M12将第三参考信号端VREF3的低电平提供给输 出控制节点PO_1，进一步地输出控制节点PO_1的信号为低电平。导通的第十三晶体管M13将第三参考信号端VREF3的低电平提供给输出控制节点PO_2，进一步使输出控制节点PO_2的信号为低电平。
在复位阶段T3之后，由于INPUT＝0、RE＝0，从而通过第一电容C1保持输出控制节点PO_1的信号为低电平信号，通过第二电容C2保持输出控制节点PO_2的信号为低电平信号，以及第二节点PD的信号为高电平信号，从而控制第四晶体管M4、第六晶体管M6、第八晶体管M8、第十二晶体管M12、第十三晶体管M13均导通。导通的第四晶体管M4将第二参考信号端VREF2的低电平提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1。导通的第六晶体管M6将第二参考信号端VREF2的低电平提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1。导通的第八晶体管M8将第三参考信号端VREF3的低电平提供给级联信号输出端CROUT，以输出低电平的级联信号CR。导通的第十二晶体管M12将第三参考信号端VREF3的低电平提供给输出控制节点PO_1，进一步地输出控制节点PO_1的信号为低电平。导通的第十三晶体管M13将第三参考信号端VREF3的低电平提供给输出控制节点PO_2，进一步使输出控制节点PO_2的信号为低电平。
并且，由于本公开提供的移位寄存器可以使不同输出控制节点的信号相互无影响，从而可以提高输出的扫描信号的波形的稳定性，避免扫描信号波形有差异。通过对实施例一中的移位寄存器进行仿真模拟，得到如图6所示的仿真模拟图。从图6中可以看出，扫描信号gout1_1和扫描信号gout2_1由高电平信号转换为低电平信号所用时长均为12us，从而可以使扫描信号gout1_1和扫描信号gout2_1的波形相似度较高，差异性较小。
在实际应用中，将实施例一中的移位寄存器应用于显示装置的阵列基板中时，由于阵列基板中包括多条栅线，这样通过实施例一中的移位寄存器向两条栅线输出具有相位差的扫描信号。其中，该显示装置可以为有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置或者也可以为液晶显示 装置(Liquid Crystal Display，LCD)，在此不作限定。
实施例二、
本公开实施例二提供的移位寄存器与实施例一提供的移位寄存器相同的部分在此不再赘述，下面只说明不同的部分。
在具体实施时，在本公开实施例中，如图7所示，移位寄存器中设置了2个第一子扫描信号输出电路41_1和41_2，以及设置了2个第二子扫描信号输出电路42_1和42_2。其中，第一子扫描信号输出电路41_1对应第一时钟信号端CLK1_1以及对应第一子扫描信号输出端GOUT1_1。第一子扫描信号输出电路41_2对应第一时钟信号端CLK1_2以及对应第一子扫描信号输出端GOUT1_2。第二子扫描信号输出电路42_1对应第二时钟信号端CLK2_1以及对应第二子扫描信号输出端GOUT2_1。第二子扫描信号输出电路42_2对应第二时钟信号端CLK2_2以及对应第二子扫描信号输出端GOUT2_2。
下面结合图8所示的电路时序图，对本实施例提供的上述移位寄存器的工作过程作以描述。具体地，选取如图8所示的电路时序图中的输入阶段T1、输出阶段T2、复位阶段T3。
在输入阶段T1，INPUT＝1、CLK1_1＝0、CLK1_2＝0、CLK2_1＝0、CLK2_2＝0、CLK3＝0、RE＝0。下面仅针对第一子扫描信号输出电路41_2中的第三晶体管M3、第四晶体管M4以及第一电容C1，和第二子扫描信号输出电路42_2中的第五晶体管M5、第六晶体管M6以及第二电容C2进行说明。该阶段的其余工作过程可以与实施例一中的输入阶段T1的工作过程基本相同，在此不作赘述。具体地，由于输出控制节点PO_1的信号为高电平信号，因此第三晶体管M3导通，以将第一时钟信号端CLK1_2的低电平提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2，并且第一电容C1充电。由于输出控制节点PO_2的信号为高电平信号，因此第五晶体管M5导通，以将第二时钟信号端CLK2_2的低电平提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2，并且第二电容C2充电。
在输出阶段T2，INPUT＝0、CLK1_1＝1、CLK1_2＝1、CLK2_1＝0、CLK2_2＝0、 CLK3＝1、RE＝0。下面仅针对第一子扫描信号输出电路41_2中的第三晶体管M3、第四晶体管M4以及第一电容C1，和第二子扫描信号输出电路42_2中的第五晶体管M5、第六晶体管M6以及第二电容C2进行说明。该阶段的其余工作过程可以与实施例一中的输出阶段T2的工作过程基本相同，在此不作赘述。由于输出控制节点PO_1的电平被进一步拉高，以通过第三晶体管M3将第一时钟信号端CLK1_2的高电平提供给第一子扫描信号输出端GOUT1_2，输出高电平的扫描信号gout1_2。之后，第二时钟信号端CLK2_2由低电平信号转换为高电平信号，由于输出控制节点PO_2的电平被拉高，通过第五晶体管M5将第二时钟信号端CLK2_2的高电平提供给第二子扫描信号输出端GOUT2_2，输出高电平的扫描信号gout2_2。之后，第一时钟信号端CLK1_2由高电平信号转换为低电平信号，即由CLK1_2＝1转换为CLK1_2＝0，而其余信号未变化。这样第三晶体管M3将第一时钟信号端CLK1_2的低电平提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2。
在复位阶段T3，INPUT＝0、RE＝1。下面仅针对第一子扫描信号输出电路41_2中的第三晶体管M3、第四晶体管M4以及第一电容C1，和第二子扫描信号输出电路42_2中的第五晶体管M5、第六晶体管M6以及第二电容C2进行说明。该阶段的其余工作过程可以与实施例一中的复位阶段T3的工作过程基本相同，在此不作赘述。第三晶体管M3和第五晶体管M5均截止，第四晶体管M4和第六晶体管M6均导通。导通的第四晶体管M4将第二参考信号端VREF2的低电平提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2。导通的第六晶体管M6将第二参考信号端VREF2的低电平提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2。
在复位阶段T3之后，由于INPUT＝0、RE＝0。下面仅针对第一子扫描信号输出电路41_2中的第三晶体管M3、第四晶体管M4以及第一电容C1，和第二子扫描信号输出电路42_2中的第五晶体管M5、第六晶体管M6以及第二电容C2进行说明。第三晶体管M3和第五晶体管M5均截止，第四晶体管M4和第六晶体管M6均导通。导通的第四晶体管M4将第二参考信号端 VREF2的低电平提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2。导通的第六晶体管M6将第二参考信号端VREF2的低电平提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2。
这样通过第一子扫描信号输出电路41_1和第一子扫描信号输出电路41_2可以输出相同时序和波形的扫描信号，可以将这两个扫描信号输入到一行的同一条栅线中，以提高驱动能力。同理，通过第二子扫描信号输出电路42_1和第二子扫描信号输出电路42_2可以输出相同时序和波形的扫描信号，可以将这两个扫描信号输入到下一行的同一条栅线中，以提高驱动能力。
实施例三、
本公开实施例三提供的移位寄存器与实施例二提供的移位寄存器相同的部分在此不再赘述，下面只说明不同的部分。
在具体实施时，扫描信号输出电路为两个，在本公开实施例中，如图9所示，复位电路12还可以包括：第十八晶体管M18；其中，第十晶体管M10的第一极与第十一晶体管M11的第一极分别通过第十八晶体管M18接收第三参考信号端VREF3的信号。第十八晶体管M18的栅极用于接收复位信号端RE的信号，第十八晶体管M18的第一极用于接收第三参考信号端VREF3的信号，第十八晶体管M18的第二极分别与第十晶体管M10的第一极和第十一晶体管M11的第一极耦接。其中，第十八晶体管M18在复位信号端RE的高电平信号的控制下处于导通状态时，可以将第三参考信号端VREF3的信号分别提供给第十晶体管M10的第一极和第十一晶体管M11的第一极。这样可以避免第三参考信号端VREF3的信号变化对第十晶体管M10和第十一晶体管M11的影响，提高电路稳定性。
在具体实施时，在本公开实施例中，如图9所示，节点控制电路13还包括：第十七晶体管M17；其中，第十二晶体管M12的第一极和第十三晶体管M13的第一极分别通过第十九晶体管M19接收第三参考信号端VREF3的信号。第十九晶体管M19的栅极与第二节点PD耦接，第十九晶体管M19的第一极用于接收第三参考信号端VREF3的信号，第十九晶体管M19的第二极 分别与第十二晶体管M12的第一极和第十三晶体管M13的第一极耦接。其中，第十九晶体管M19在第二节点PD的高电平信号的控制下处于导通状态时，可以将第三参考信号端VREF3的信号分别提供给第十二晶体管M12的第一极和第十三晶体管M13的第一极。这样可以避免第三参考信号端VREF3的信号变化对第十二晶体管M12和第十三晶体管M13的影响，提高电路稳定性。
一般OLED显示装置中采用图10所示的3T1C形式的像素电路驱动OLED发光以及对OLED进行外部阈值补偿。该像素电路包括：驱动晶体管T01、晶体管T02～T03以及存储电容Cst。该像素电路通过控制晶体管T02打开以将数据信号端Data的数据电压写入驱动晶体管T01的栅极，控制驱动晶体管T01产生工作电流以驱动有机发光二极管L发光。通过晶体管T03将携带有驱动晶体管T01的阈值电压信息的信号通过检测线SL输出。这样使得一行像素电路需要对应两条栅线，以分别输入信号G01和G02。为了实现控制上述像素电路，在具体实施时，在本公开实施例中，如图9所示，移位寄存器还可以包括：检测电路50。该检测电路50可以包括：第十八晶体管M18、第十九晶体管M19、第二十晶体管M20、第二十一晶体管M21、第二十二晶体管M22以及第三电容C3；其中，第十八晶体管M18的栅极用于接收第一检测控制信号端VC1的信号，第十八晶体管M18的第一极用于接收输入信号端INPUT的信号，第十八晶体管M18的第二极与第二十晶体管M20的第一极耦接。第十九晶体管M19的栅极用于接收第一检测控制信号端VC1的信号，第十九晶体管M19的第一极与第二十一晶体管M21的栅极耦接，第十九晶体管M19的第二极与第二十晶体管M20的第一极耦接。第二十晶体管M20的栅极与第二十一晶体管M21的栅极耦接，第二十晶体管M20的第二极用于接收第四参考信号端VREF4的信号。第二十一晶体管M21的第一极用于接收第四参考信号端VREF4的信号，第二十一晶体管M21的第二极与第二十二晶体管M22的第一极耦接。第二十二晶体管M22的栅极用于接收第二检测控制信号端VC2的信号，第二十二晶体管M22的第二极与第一节点PU耦接。第三电容C3耦接于第二十一晶体管M21的第一极与第二十一晶体管M21的 栅极之间。具体地，第十八晶体管M18在第一检测控制信号端VC1的控制下可以处于导通状态，以将输入信号端INPUT的信号提供给第二十晶体管M20的第一极和第十九晶体管M19的第二极。第十九晶体管M19在第一检测控制信号端VC1的控制下可以处于导通状态，以将其第二极的信号提供给第二十一晶体管M21的栅极和第二十晶体管M20的栅极。第二十晶体管M20在其栅极的信号的控制下可以处于导通状态。第二十一晶体管M21在其栅极的信号的控制下可以处于导通状态，以将第四参考信号端VREF4的信号提供给第二十二晶体管M22的第一极。第二十二晶体管M22在第二检测控制信号端VC2的控制下可以处于导通状态，以将其第一极的信号提供给第一节点PU。
在具体实施时，第四参考信号端可以加载高电平信号。进一步地，第四参考信号端的电压值可以与第一参考信号端的电压值相同。为了降低信号端的数量，减少信号线占用空间，可以将第四参考信号端与第一参考信号端设置为同一信号端，即采用同一参考信号端提供第四参考信号端与第一参考信号端的信号。
下面结合图11所示的电路时序图，对本实施例提供的上述移位寄存器的工作过程作以描述。具体地，将一帧时间分为显示扫描阶段DP和空白时间阶段BT。各第一时钟信号端CLK1_n在显示扫描阶段DP中的信号时序相同，各第一时钟信号端CLK1_n在空白时间阶段BT中的信号时序不同。同理，各第二时钟信号端CLK2_n在显示扫描阶段DP中的信号时序相同，各第二时钟信号端CLK2_n在空白时间阶段BT中的信号时序不同。
具体地，显示扫描阶段DP包括：输入阶段T1、输出阶段T2、复位阶段T3。其中，在输入阶段T1，INPUT＝1、CLK1_1＝0、CLK1_2＝0、CLK2_1＝0、CLK2_2＝0、CLK3＝0、RE＝0、VC1＝1、VC2＝0。由于RE＝0，因此第十六晶体管M16截止。由于第二节点PD的信号为低电平信号，因此第十七晶体管M17截止。由于VC1＝1，因此第十八晶体管M18和第十九晶体管M19均导通，以将输入信号端INPUT的高电平信号提供给第二十一晶体管M21的栅极，并通过第三电容C3保持，以及控制第二十一晶体管M21导通，以将第四参 考信号端VREF4的高电平提供给第二十二晶体管M22。但是由于VC2＝0，因此第二十二晶体管M22截止，从而不会影响第一节点PU的信号。该阶段的其余工作过程可以与实施例二中的输入阶段T1的工作过程基本相同，在此不作赘述。并且，实施例三中的输出阶段T2和复位阶段T3的工作过程可以与实施例二中的输出阶段T2和复位阶段T3的工作过程基本相同，在此不作赘述。
空白时间阶段BT可以包括：检测输入阶段T4、检测输出阶段T5、检测复位阶段T6。在空白时间阶段BT，输入信号端INPUT、复位信号端RE，第二时钟信号端CLK2_1～CLK2_2、第三时钟信号端CLK3、第一至第四参考信号端VREF4均加载低电平信号。
在检测输入阶段T4，VC1＝0、VC2＝1、CLK1_1＝0、CLK1_2＝0。由于VC1＝0，因此第十八晶体管M18和第十九晶体管M19均截止。由于第三电容C3的作用使第二十一晶体管M21的栅极为高电平信号，以控制第二十一晶体管M21导通，以及由于VC2＝1，第二十二晶体管M22导通，以将第四参考信号端VREF4的高电平提供给第一节点PU。由于第一节点PU的信号为高电平信号，第十五晶体管M15导通，使第二节点PD的信号为低电平信号。从而控制第四晶体管M4、第六晶体管M6、第八晶体管M8、第十二晶体管M12、第十三晶体管M13均截止。由于第一节点PU的信号为高电平信号，第一晶体管M1和第二晶体管M2形成二极管连接结构，因此输出控制节点PO_1和PO_2的信号也为高电平信号。由于输出控制节点PO_1的信号为高电平信号，因此第七晶体管M7以及两个第三晶体管M3均导通。导通的第七晶体管M7将第三时钟信号端CLK3的低电平提供给级联信号输出端CROUT，以输出低电平的级联信号CR。第一子扫描信号输出电路41_1中的第三晶体管M3将第一时钟信号端CLK1_1的信号提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1。第一子扫描信号输出电路41_2中的第三晶体管M3将第一时钟信号端CLK1_2的信号提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2。由于输出控制节点PO_2的信 号为高电平信号，因此两个第五晶体管M5导通。其中，第二子扫描信号输出电路42_1中的第五晶体管M5将第二时钟信号端CLK2_1的信号提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1。第二子扫描信号输出电路42_2中的第五晶体管M5将第二时钟信号端CLK2_2的信号提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2。
在检测输出阶段T5，VC1＝0、VC2＝0，第一时钟信号端CLK1_1具有两个高电平脉冲，第一时钟信号端CLK1_2具有一个高电平脉冲。具体地，由于第一电容C1的作用，保持输出控制节点PO_1的信号为高电平信号，因此第七晶体管M7以及两个第三晶体管M3均导通。其中，第一子扫描信号输出电路41_1中的第三晶体管M3将第一时钟信号端CLK1_1的信号提供给第一子扫描信号输出端GOUT1_1，以输出具有两个高电平脉冲的扫描信号gout1_1。第一子扫描信号输出电路41_2中的第三晶体管M3将第一时钟信号端CLK1_2的信号提供给第一子扫描信号输出端GOUT1_2，以输出具有一个高电平脉冲的扫描信号gout1_2。导通的第七晶体管M7将第三时钟信号端CLK3的高电平提供给级联信号输出端CROUT，以输出高电平的级联信号CR。由于第二电容C2的作用，保持输出控制节点PO_2的信号为高电平信号，因此两个第五晶体管M5导通。其中，第二子扫描信号输出电路42_1中的第五晶体管M5将第二时钟信号端CLK2_1的信号提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1。第二子扫描信号输出电路42_2中的第五晶体管M5将第二时钟信号端CLK2_2的信号提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2。
在检测复位阶段T6，VC1＝1、VC2＝0、CLK1_1＝0、CLK1_2＝0。
由于VC2＝0，因此第二十二晶体管M22截止。由于VC1＝1，因此第十八晶体管M18与第十九晶体管M19导通，以将输入信号端INPUT的低电平提供给第二十一晶体管M21的栅极，控制第二十一晶体管M21截止。由于第一电容C1的作用，保持输出控制节点PO_1的信号为高电平信号，因此第七晶体管M7以及两个第三晶体管M3均导通。其中，第一子扫描信号输出电路 41_1中的第三晶体管M3将第一时钟信号端CLK1_1的低电平提供给第一子扫描信号输出端GOUT1_1，以输出低电平的扫描信号gout1_1。第一子扫描信号输出电路41_2中的第三晶体管M3将第一时钟信号端CLK1_2的低电平提供给第一子扫描信号输出端GOUT1_2，以输出低电平的扫描信号gout1_2。导通的第七晶体管M7将第三时钟信号端CLK3的低电平提供给级联信号输出端CROUT，以输出低电平的级联信号CR。由于第二电容C2的作用，保持输出控制节点PO_2的信号为高电平信号，因此两个第五晶体管M5导通。其中，第二子扫描信号输出电路42_1中的第五晶体管M5将第二时钟信号端CLK2_1的信号提供给第二子扫描信号输出端GOUT2_1，以输出低电平的扫描信号gout2_1。第二子扫描信号输出电路42_2中的第五晶体管M5将第二时钟信号端CLK2_2的信号提供给第二子扫描信号输出端GOUT2_2，以输出低电平的扫描信号gout2_2。
一般在空白时间阶段中对OLED进行外部补偿的检测，这样通过实施例三中的移位寄存器输出的扫描信号gout1_1和gout1_2分别对一行中的两条栅线输入信号G01和G02，以在一帧内的显示扫描阶段DP中控制该行中的OLED实现显示功能，在空白时间阶段BT中控制该行中的OLED实现外部补偿的检测功能。以及，通过扫描信号gout2_1和gout2_2分别对下一行中的两条栅线输入信号G01和G02，以满足OLED显示的需要。
实施例四、
本公开实施例四提供的移位寄存器与实施例三提供的移位寄存器相同的部分在此不再赘述，下面只说明不同的部分。
在具体实施时，扫描信号输出电路为两个，在本公开实施例中，如图12所示，分支控制电路20可以包括：第一晶体管M1和第二晶体管M2。其中，第一晶体管M1的栅极用于接收第一参考信号端VREF1的信号，第一晶体管M1的第一极与第一节点PU耦接，第一晶体管M1的第二极与第一扫描信号输出电路对应的输出控制节点PO_1耦接。第二晶体管M2的栅极用于接收第一参考信号端VREF1的信号，第二晶体管M2的第一极均与第一节点PU耦 接，第二晶体管M2的第二极与第二扫描信号输出电路对应的输出控制节点PO_2耦接。
在具体实施时，第一参考信号端在显示扫描阶段DP和空白时间阶段BT为高电平信号。并且，第一参考信号端的电压值与第一时钟信号端的电压值以及第二时钟信号端的电压值相同。这样在输入阶段T1中，在第一节点PU为高电平信号时，第一晶体管M1的栅极与其第一极的电压值相同，相当于形成二极管连接结构，第二晶体管M2的栅极与其第一极的电压值相同，相当于形成二极管连接结构。该阶段其余工作过程可以与实施例三中的输入阶段T1的工作过程基本相同，在此不作赘述。
在输出阶段T2中，由于输出控制信号PO_1～PO_1被拉高，因此第一晶体管M1和第二晶体管M2的栅源电压较大，导致第一晶体管M1和第二晶体管M2截止，从而可以使拉高的输出控制信号PO_1～PO_1的信号不会通过第一节点PU相互影响，进而提高电路稳定性。该阶段其余工作过程可以与实施例三中的输出阶段T2的工作过程基本相同，在此不作赘述。
在复位阶段T3中，第一晶体管M1和第二晶体管M2一直导通。该阶段其余工作过程可以与实施例三中的复位阶段T3的工作过程基本相同，在此不作赘述。
在检测输入阶段T4、检测输出阶段T5、检测复位阶段T6。第一晶体管M1和第二晶体管M2一直导通。这三个阶段其余工作过程可以与实施例三中的检测输入阶段T4、检测输出阶段T5、检测复位阶段T6的工作过程基本相同，在此不作赘述。
基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的移位寄存器的驱动方法，通过该驱动方法驱动本公开实施例提供的移位寄存器，可以使移位寄存器输出多个不同的扫描信号。并且，该驱动方法的实施可以参见前述移位寄存器的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示扫描阶段可以包括：输入阶段、输出阶段以及复位阶段。具体地，如图13所示，可以包括如下步骤：
S1301、在输入阶段，信号控制电路响应于输入信号端的信号，控制第一节点的信号和第二节点的信号；分支控制电路响应于第一节点的信号，控制与各扫描信号输出电路一一对应的输出控制节点的信号；级联信号输出电路响应于一个输出控制节点的信号，控制级联信号输出端输出级联信号；各扫描信号输出电路响应于对应的输出控制节点的信号，输出不同的扫描信号；
S1302、在输出阶段，分支控制电路响应于第一节点的信号，控制与各扫描信号输出电路一一对应的输出控制节点的信号；级联信号输出电路响应于一个输出控制节点的信号，控制级联信号输出端输出级联信号；各扫描信号输出电路响应于对应的输出控制节点的信号，输出不同的扫描信号；
S1303、在复位阶段，信号控制电路响应于复位信号，控制第一节点的信号和第二节点的信号；级联信号输出电路响应于一个输出控制节点的信号，控制级联信号输出端输出级联信号；各扫描信号输出电路响应于对应的输出控制节点的信号，输出不同的扫描信号。
在具体实施时，扫描信号输出电路为两个，两个扫描信号输出电路中的第一扫描信号输出电路包括：多个第一子扫描信号输出电路；第二扫描信号输出电路包括：多个第二子扫描信号输出电路。需要说明的是，该部分具体描述参考实施例一，在此不作赘述。
在本公开实施例中，在输入阶段和输出阶段，各第一子扫描信号输出电路响应于对应的输出控制节点的信号，将对应的第一时钟信号提供给对应的第一子扫描信号输出端；各第二子扫描信号输出电路响应于对应的输出控制节点的信号，将对应的第二时钟信号提供给对应的第二子扫描信号输出端；级联信号输出电路响应于分支控制电路的第一输出端的信号，将第三时钟信号提供给级联信号输出端；
在复位阶段，各第一子扫描信号输出电路响应于第二节点的信号，将第二参考信号提供给对应的第一子扫描信号输出端；各第二子扫描信号输出电路响应于第二节点的信号，将第二参考信号提供给对应的第二子扫描信号输出端；级联信号输出电路响应于分支控制电路的第一输出端的信号，将第三 参考信号提供给级联信号输出端。
在本公开实施例中，在显示扫描阶段，各第一时钟信号端的信号时序相同，各第二时钟信号端的信号时序相同，第一时钟信号端和第二时钟信号端的信号时序不同。
进一步地，在具体实施时，移位寄存器还包括检测电路，这样可以将移位寄存器应用于OLED显示装置中。在本公开实施例中，驱动方法还可以包括：空白时间阶段；其中，空白时间阶段可以包括：检测输入阶段、检测输出阶段以及检测复位阶段。检测电路在这些阶段中的工作过程参见实施例三，在此不作赘述。
基于同一发明构思，本公开实施例还提供了一种栅极驱动电路，如图14a与图14b所示，包括级联的多个本公开实施例提供的移位寄存器：SR(n-2)、SR(n-1)、SR(n)、SR(n+1)、SR(n+2)；(共N个移位寄存器，1≤n≤N且n为整数)；
第一级移位寄存器的输入信号由帧起始信号端输入；
每相邻四级移位寄存器中，第四级移位寄存器SR(n+1)的输入信号端INPUT由第一级移位寄存器SR(n-2)的级联信号CR输入；
每相邻五级移位寄存器中，第一级移位寄存器SR(n-2)的复位信号端RE由第五级移位寄存器SR(n+2)的级联信号CR输入。
需要说明的是，图14a是以移位寄存器的结构采用图4所示的结构为例进行说明。图14b是以移位寄存器的结构采用图9所示的结构为例进行说明。
在具体实施时，在移位寄存器的结构采用图4所示的结构时，第5y-4级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_1提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_1提供，第三时钟信号端CLK3由同一时钟信号线clk3_1提供。第5y-3级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_2提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_2提供，第三时钟信号端CLK3由同一时钟信号线clk3_2提供。第5y-2级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_3提 供，第二时钟信号端CLK2_1由同一时钟信号线clk2_3提供，第三时钟信号端CLK3由同一时钟信号线clk3_3提供。第5y-1级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_4提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_4提供，第三时钟信号端CLK3由同一时钟信号线clk3_4提供。第5y级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_5提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_5提供，第三时钟信号端CLK3由同一时钟信号线clk3_5提供。其中，k为正整数。
在具体实施时，在移位寄存器的结构采用图9所示的结构时，第5y-4级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_11提供，第一时钟信号端CLK1_2由同一时钟信号线clk1_21提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_11提供，第二时钟信号端CLK2_2由同一时钟信号线clk2_21提供，第三时钟信号端CLK3由同一时钟信号线clk3_1提供。第5y-3级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_12提供，第一时钟信号端CLK1_2由同一时钟信号线clk1_22提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_12提供，第二时钟信号端CLK2_2由同一时钟信号线clk2_22提供，第三时钟信号端CLK3由同一时钟信号线clk3_2提供。第5y-2级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_13提供，第一时钟信号端CLK1_2由同一时钟信号线clk1_23提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_13提供，第二时钟信号端CLK2_2由同一时钟信号线clk2_23提供，第三时钟信号端CLK3由同一时钟信号线clk3_3提供。第5y-1级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_14提供，第一时钟信号端CLK1_2由同一时钟信号线clk1_24提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_14提供，第二时钟信号端CLK2_2由同一时钟信号线clk2_24提供，第三时钟信号端CLK3由同一时钟信号线clk3_4提供。第5y级移位寄存器的第一时钟信号端CLK1_1由同一时钟信号线clk1_15提供，第一时钟信号端CLK1_2由同一时钟信号线clk1_25提供，第二时钟信号端CLK2_1由同一时钟信号线clk2_15提供，第 二时钟信号端CLK2_2由同一时钟信号线clk2_25提供，第三时钟信号端CLK3由同一时钟信号线clk3_5提供。其中，k为正整数。
在具体实施时，各级移位寄存器的第一检测控制信号均为同一信号，以在一帧时间内对各级移位寄存器进行控制。而每一级移位寄存器的第二检测控制信号不同，在一帧时间内，只有一级移位寄存器对应的第二检测控制信号端具有高电平脉冲信号，以使该级移位寄存器在空白时间阶段输出图11所示的扫描信号gout1_1、gout1_2、gout2_1、gout2_2。其余移位寄存器在空白时间阶段均输出低电平信号。
具体地，上述栅极驱动电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种阵列基板，包括本公开实施例提供的栅极驱动电路。该阵列基板解决问题的原理与前述栅极驱动电路相似，因此该阵列基板的实施可以参见前述栅极驱动电路的实施，重复之处在此不再赘述。
本公开实施例提供的上述阵列基板，包括上述栅极驱动电路，并通过该栅极驱动电路中各级移位寄存器为阵列基板上的各栅线提供扫描信号，其具体实施可参见上述移位寄存器的描述，相同之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
本公开实施例提供的移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置，通过信号控制电路响应于输入信号和复位信号，以控制第一节点的信号和第二节点的信号。通过分支控制电路被配置为响应于第一节点的信号，控制与各扫描信号输出电路一一对应的输出控制节点的信号，可以 将不同的输出控制节点分割开，从而在输出控制节点的信号变化时可以不会影响其他输出控制节点的信号。通过级联信号输出电路响应于多个扫描信号输出电路中的第一扫描输出电路对应的输出控制节点的信号和第二节点的信号，输出级联信号，为下一级移位寄存器提供输入信号。通过设置多个扫描信号输出电路，以通过各扫描信号输出电路响应于对应的输出控制节点的信号和第二节点的信号，输出不同的扫描信号。这样可以使每个移位寄存器输出多个扫描信号，以对应显示面板中的不同栅线。与现有的移位寄存器仅能输出一个扫描信号相比，可以使栅极驱动电路中移位寄存器的数量减少，降低栅极驱动电路的占用空间，实现超窄边框设计。并且，由于不同输出控制节点的信号相互无影响，从而还可以提高输出稳定性。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (21)

  1. 一种移位寄存器，包括：
    信号控制电路，与输入信号端和复位信号端耦接；
    分支控制电路，与所述信号控制电路的第一输出端耦接；
    级联信号输出电路，与级联信号输出端和所述信号控制电路的第二输出端耦接；
    至少两个扫描信号输出电路，所述至少两个扫描信号输出电路中的一个扫描信号输出电路与所述信号控制电路的第二输出端、对应的至少一个扫描信号输出端以及所述分支控制电路对应的一个输出端耦接。
  2. 如权利要求1所述的移位寄存器，其中，所述级联信号输出电路与所述分支控制电路的一个输出端耦接。
  3. 如权利要求2所述的移位寄存器，其中，所述扫描信号输出电路为两个，包括第一扫描信号输出电路和第二扫描信号输出电路；
    所述第一扫描信号输出电路与所述分支控制电路的第一输出端耦接；所述第二扫描信号输出电路与所述分支控制电路的第二输出端耦接。
  4. 如权利要求3所述的移位寄存器，其中，所述分支控制电路包括：第一晶体管和第二晶体管；
    所述第一晶体管在有效电平的控制下连通所述信号控制电路的第一输出端与所述分支控制电路的第一输出端，所述第二晶体管在有效电平的控制下连通所述信号控制电路的第一输出端与所述分支控制电路的第二输出端。
  5. 如权利要求4所述的移位寄存器，其中，所述第一晶体管的栅极与其第一极均与所述信号控制电路的第一输出端耦接，所述第一晶体管的第二极为所述分支控制电路的第一输出端；
    所述第二晶体管的栅极与其第一极均与所述信号控制电路的第一输出端耦接，所述第二晶体管的第二极为所述分支控制电路的第二输出端。
  6. 如权利要求4所述的移位寄存器，其中，所述第一晶体管的栅极与第 一参考信号端耦接，所述第一晶体管的第一极与所述信号控制电路的第一输出端耦接，所述第一晶体管的第二极为所述分支控制电路的第一输出端；
    所述第二晶体管的栅极与所述第一参考信号端耦接，所述第二晶体管的第一极与所述信号控制电路的第一输出端耦接，所述第二晶体管的第二极为所述分支控制电路的第二输出端。
  7. 如权利要求3所述的移位寄存器，其中，所述第一扫描信号输出电路包括：至少1个第一子扫描信号输出电路；其中，一个所述第一子扫描信号输出电路分别与第二参考信号端、对应的一个第一时钟信号端和对应的一个第一子扫描信号输出端耦接。
  8. 如权利要求7所述的移位寄存器，其中，所述第一子扫描信号输出电路包括：第三晶体管、第四晶体管以及第一电容；
    所述第三晶体管的栅极与所述分支控制电路的第一输出端耦接，所述第三晶体管的第一极与所述第一时钟信号端耦接，所述第三晶体管的第二极与对应的所述第一子扫描信号输出端耦接；
    所述第四晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第四晶体管的第一极与所述第二参考信号端耦接，所述第四晶体管的第二极与对应的所述第一子扫描信号输出端耦接；
    所述第一电容耦接于所述第三晶体管的栅极与所述第一子扫描信号输出端之间。
  9. 如权利要求3所述的移位寄存器，其中，所述第二扫描信号输出电路包括：至少1个第二子扫描信号输出电路；其中，一个所述第二子扫描信号输出电路分别与第二参考信号端、对应的一个第二时钟信号端和对应的一个第二子扫描信号输出端耦接。
  10. 如权利要求9所述的移位寄存器，其中，所述第二子扫描信号输出电路包括：第五晶体管、第六晶体管以及第二电容；
    所述第五晶体管的栅极与所述分支控制电路的第二输出端耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与 对应的所述第二子扫描信号输出端耦接；
    所述第六晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第六晶体管的第一极与所述第二参考信号端耦接，所述第六晶体管的第二极与对应的所述第二子扫描信号输出端耦接；
    所述第二电容耦接于所述第五晶体管的栅极与所述第二子扫描信号输出端之间。
  11. 如权利要求3所述的移位寄存器，其中，所述级联信号输出电路包括：第七晶体管和第八晶体管；
    所述第七晶体管的栅极与所述分支控制电路的第一输出端耦接，所述第七晶体管的第一极与第三时钟信号端耦接，所述第七晶体管的第二极与所述级联信号输出端耦接；
    所述第八晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第八晶体管的第一极与所述第三参考信号端耦接，所述第八晶体管的第二极与所述级联信号输出端耦接。
  12. 如权利要求3所述的移位寄存器，其中，所述信号控制电路包括：输入电路、复位电路、节点控制电路；
    所述输入电路分别与所述输入信号端，第一参考信号端和所述信号控制电路的第一输出端耦接；
    所述复位电路分别与所述复位信号端，第三参考信号端以及所述分支控制电路的第一输出端和第二输出端耦接；
    所述节点控制电路分别与所述第一参考信号端、所述第三参考信号端、所述信号控制电路的第一输出端和第二输出端、所述分支控制电路的第一输出端和第二输出端耦接。
  13. 如权利要求12所述的移位寄存器，其中，所述输入电路包括：第九晶体管；其中，所述第九晶体管的栅极与所述输入信号端耦接，所述第九晶体管的第一极与所述第一参考信号耦接，所述第九晶体管的第二极与所述信号控制电路的第一输出端耦接；
    所述复位电路包括：第十晶体管与第十一晶体管；其中，所述第十晶体管的栅极与所述复位信号端耦接，所述第十晶体管的第一极与所述第三参考信号端耦接，所述第十晶体管的第二极与所述分支控制电路的第一输出端耦接；所述第十一晶体管的栅极与所述复位信号端耦接，所述第十一晶体管的第一极与所述第三参考信号端耦接，所述第十一晶体管的第二极与所述分支控制电路的第二输出端耦接；
    所述节点控制电路包括：第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管；其中，所述第十二晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第十二晶体管的第一极与所述第三参考信号端耦接，所述第十二晶体管的第二极与所述分支控制电路的第一输出端耦接；所述第十三晶体管的栅极与所述信号控制电路的第二输出端耦接，所述第十三晶体管的第一极与所述第三参考信号端耦接，所述第十三晶体管的第二极与所述分支控制电路的第二输出端耦接；所述第十四晶体管的栅极与其第一极均与所述第一参考信号端耦接，所述第十四晶体管的第二极与所述信号控制电路的第二输出端耦接；所述第十五晶体管的栅极与所述信号控制电路的第一输出端耦接，所述第十五晶体管的第一极与所述第三参考信号端耦接，所述第十五晶体管的第二极与所述信号控制电路的第二输出端耦接。
  14. 如权利要求13所述的移位寄存器，其中，所述复位电路还包括：第十六晶体管；其中，所述第十晶体管的第一极与所述第十一晶体管的第一极分别通过所述第十六晶体管与所述第三参考信号端耦接；所述第十六晶体管的栅极与所述复位信号端耦接；
    所述节点控制电路还包括：第十七晶体管；其中，所述第十二晶体管的第一极和所述第十三晶体管的第一极分别通过所述第十七晶体管与所述第三参考信号端耦接；所述第十七晶体管的栅极与所述信号控制电路的第二输出端耦接。
  15. 如权利要求1-14任一项所述的移位寄存器，其中，所述移位寄存器还包括：检测电路；所述检测电路包括：第十八晶体管、第十九晶体管、第 二十晶体管、第二十一晶体管、第二十二晶体管以及第三电容；
    所述第十八晶体管的栅极与第一检测控制信号端耦接，所述第十八晶体管的第一极与所述输入信号端耦接，所述第十八晶体管的第二极与所述第二十晶体管的第一极耦接；
    所述第十九晶体管的栅极与所述第一检测控制信号端耦接，所述第十九晶体管的第一极与所述第二十一晶体管的栅极耦接，所述第十九晶体管的第二极与所述第二十晶体管的第一极耦接；
    所述第二十晶体管的栅极与所述第二十一晶体管的栅极耦接，所述第二十晶体管的第二极用于与第四参考信号端耦接；
    所述第二十一晶体管的第一极与所述第四参考信号端耦接，所述第二十一晶体管的第二极与所述第二十二晶体管的第一极耦接；
    所述第二十二晶体管的栅极与第二检测控制信号端耦接，所述第二十二晶体管的第二极与所述信号控制电路的第一输出端耦接；
    所述第三电容耦接于所述第二十一晶体管的第一极与第二十一晶体管的栅极之间。
  16. 一种栅极驱动电路，其中，包括级联的多个如权利要求1-15任一项所述的移位寄存器；
    第一级移位寄存器的输入信号端与帧起始信号端耦接；
    每相邻四级移位寄存器中，第四级移位寄存器的输入信号端与第一级移位寄存器的级联信号输入端耦接；
    每相邻五级移位寄存器中，第一级移位寄存器的复位信号端与第五级移位寄存器的级联信号输入端耦接。
  17. 一种阵列基板，其中，包括如权利要求16所述的栅极驱动电路。
  18. 一种显示装置，其中，包括如权利要求17所述的阵列基板。
  19. 一种如权利要求1-15任一项所述的移位寄存器的驱动方法，其中，包括：显示扫描阶段；其中，所述显示扫描阶段包括：输入阶段、输出阶段以及复位阶段；
    在所述输入阶段，所述信号控制电路响应于所述输入信号端的信号，控制所述信号控制电路的第一输出端的信号和所述信号控制电路的第二输出端的信号；所述分支控制电路响应于所述信号控制电路的第一输出端的信号，控制与所述分支控制电路的各输出端的输出信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于所述分支控制电路对应的一个输出端的信号，控制对应的至少一个扫描信号输出端输出不同的扫描信号；
    在所述输出阶段，所述分支控制电路响应于所述信号控制电路的第一输出端的信号，控制所述分支控制电路的各输出端的输出信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于所述分支控制电路对应的一个输出端的信号，控制对应的至少一个扫描信号输出端输出不同的扫描信号；
    在所述复位阶段，所述信号控制电路响应于所述复位信号端的信号，控制所述信号控制电路的第一输出端和第二输出端的信号；所述级联信号输出电路响应于所述分支控制电路的一个输出端的输出信号，控制所述级联信号输出端输出级联信号；各所述扫描信号输出电路响应于对应的输出控制节点的信号，输出不同的扫描信号。
  20. 如权利要求19所述的驱动方法，其中，所述扫描信号输出电路为两个，包括第一扫描信号输出电路和第二扫描信号输出电路；所述第一扫描信号输出电路包括：多个第一子扫描信号输出电路；所述第二扫描信号输出电路包括：多个第二子扫描信号输出电路；
    在所述输入阶段和所述输出阶段，各所述第一子扫描信号输出电路响应于所述分支控制电路的第一输出端的信号，将对应的所述第一时钟信号端的信号提供给对应的第一子扫描信号输出端；各所述第二子扫描信号输出电路响应于所述分支控制电路的第二输出端的信号，将对应的所述第二时钟信号端的信号提供给对应的第二子扫描信号输出端；所述级联信号输出电路响应 于所述分支控制电路的第一输出端的信号，将第三时钟信号端的信号提供给级联信号输出端；
    在所述复位阶段，各所述第一子扫描信号输出电路响应于所述信号控制电路的第二输出端的信号，将第二参考信号端的信号提供给对应的第一子扫描信号输出端；各所述第二子扫描信号输出电路响应于所述信号控制电路的第二输出端的信号，将所述第二参考信号端的信号提供给对应的第二子扫描信号输出端；所述级联信号输出电路响应于所述信号控制电路的第二输出端的信号，将第三参考信号端的信号提供给所述级联信号输出端。
  21. 如权利要求20所述的驱动方法，其中，在所述显示扫描阶段，各所述第一时钟信号端的信号时序相同，各所述第二时钟信号端的信号时序相同，所述第一时钟信号端和所述第二时钟信号端的信号时序不同。
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