WO2020077737A1 - 有机自发光二极管显示面板及其制作方法 - Google Patents

有机自发光二极管显示面板及其制作方法 Download PDF

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WO2020077737A1
WO2020077737A1 PCT/CN2018/116985 CN2018116985W WO2020077737A1 WO 2020077737 A1 WO2020077737 A1 WO 2020077737A1 CN 2018116985 W CN2018116985 W CN 2018116985W WO 2020077737 A1 WO2020077737 A1 WO 2020077737A1
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layer
gate
dielectric layer
display panel
located above
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PCT/CN2018/116985
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French (fr)
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丁武
李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US16/467,994 priority Critical patent/US11088231B2/en
Publication of WO2020077737A1 publication Critical patent/WO2020077737A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30—Doping active layers, e.g. electron transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention relates to the field of electronic display, in particular to an organic self-luminous diode display panel and a manufacturing method thereof.
  • the gate metal is usually made of metal molybdenum (Mo)
  • the interlayer dielectric layer is usually made of a stack of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the invention provides an organic self-luminous diode display panel and a manufacturing method thereof to solve the technical problem of film peeling caused by the stress between the interlayer dielectric layer and the gate metal in the prior art.
  • the present invention provides an organic self-emitting diode display panel, wherein the display panel includes: a substrate; a thin film transistor layer above the substrate; and a thin film transistor layer above the thin film transistor layer, and the thin film A light-emitting structure connected to a wiring layer of a source-drain region in a transistor layer; wherein,
  • the thin film transistor layer includes:
  • An interlayer dielectric layer covering the gate dielectric layer, the gate metal layer and the gate buffer layer;
  • the material constituting the gate buffer layer is the oxide of the gate metal layer. By oxidizing the gate metal layer, a corresponding oxide is formed on the top of the gate buffer layer to form the gate buffer layer.
  • the material constituting the gate metal layer is molybdenum
  • the material constituting the gate buffer layer is molybdenum oxide
  • the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer is silicon oxide, and the second dielectric layer is located in the first dielectric Above the layer, its material is silicon nitride.
  • the present invention provides an organic self-emitting diode display panel, wherein the display panel includes: a substrate; a thin film transistor layer above the substrate; and a thin film transistor layer above the thin film transistor layer, and the thin film A light-emitting structure connected to a wiring layer of a source-drain region in a transistor layer; wherein,
  • the thin film transistor layer includes:
  • An interlayer dielectric layer covering the gate dielectric layer, the gate metal layer and the gate buffer layer;
  • the material constituting the gate buffer layer is an oxide of the gate metal layer, and by oxidizing the gate metal layer, a corresponding oxide is formed on top of the gate buffer layer to form the gate buffer layer .
  • the material constituting the gate metal layer is molybdenum
  • the material constituting the gate buffer layer is molybdenum oxide
  • the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer is silicon oxide, and the second dielectric layer is located in the first dielectric Above the layer, its material is silicon nitride.
  • the thickness of the gate buffer layer is 2-5 nm.
  • the present invention also provides a method for manufacturing an organic self-luminous diode display panel, wherein the method includes the following steps:
  • a polysilicon layer located above the substrate Forming a polysilicon layer located above the substrate, forming a source-drain region composed of spaced heavily doped regions and a channel region not heavily doped between the source-drain regions in the polysilicon layer;
  • a light emitting structure connected to the source and drain region wiring layer is formed.
  • the material constituting the gate buffer layer is an oxide of the gate metal layer, and by oxidizing the gate metal layer, a corresponding oxide is formed on top of the gate buffer layer to form the gate buffer layer .
  • the material constituting the gate metal layer is molybdenum
  • the material constituting the gate buffer layer is molybdenum oxide
  • the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer is silicon oxide, and the second dielectric layer is located in the first dielectric Above the layer, its material is silicon nitride.
  • the thickness of the gate buffer layer is 2-5 nm.
  • the invention improves the existing thin film transistor of the organic self-luminous diode display panel and the manufacturing method thereof.
  • a thin layer of about 2 ⁇ 5 is formed on the gate dielectric layer by oxidation
  • the dense molybdenum oxide around nm is used as the gate buffer layer, and then the interlayer dielectric layer is deposited. Since the stress of molybdenum oxide is between molybdenum and the interlayer dielectric layer, the stress between the two can be well balanced to prevent the interlayer dielectric layer from falling off after deposition, which can improve the characteristics of the thin film transistor. Can greatly improve the yield of the device.
  • FIG. 1 is a schematic structural diagram of a thin film transistor in an organic self-luminous diode display panel in the prior art
  • FIGS. 2 to 4 are schematic structural diagrams of thin film transistors in various steps of the method for manufacturing an organic self-luminous diode display panel in a specific embodiment of the present invention.
  • the thin film transistor layer of the organic self-luminous diode display panel includes: a substrate 110, a silicon nitride layer 120, a silicon oxide layer 130, a polysilicon layer 140, a gate metal 210, The interlayer dielectric layer 150, the second interlayer dielectric layer 160, the source-drain metal trace 220, the first insulating layer 170, the second insulating layer 180, the anode metal 240, and the pixel definition layer 190.
  • the substrate 110 is usually a hard substrate, such as glass, or a flexible substrate, such as a polyimide substrate.
  • the silicon nitride layer 120 is located above the substrate 110, and the silicon oxide layer 130 is located above the silicon nitride layer 120.
  • the polysilicon layer 140 is located above the silicon oxide layer 130.
  • the polysilicon layer 140 includes a source-drain region 230 in a heavily doped region and a channel region between the source-drain regions 230.
  • the gate metal 210 is located on the polysilicon layer 140, and the gate metal 210 covers the polysilicon layer 140 above the channel region.
  • the first interlayer dielectric layer 150 is located above the polysilicon layer 140, the first interlayer dielectric layer 150 covers the gate metal 210 and the polysilicon layer 140 not covered by the gate metal 210 .
  • the second interlayer dielectric layer 160 is located above the first interlayer dielectric layer 150.
  • the source-drain metal trace 220 penetrates the first interlayer dielectric layer 150 and the second interlayer dielectric layer 160.
  • the first insulating layer 170 covers the source-drain metal trace 220 and the second interlayer dielectric layer 160.
  • the second insulating layer 180 is located above the first insulating layer 170.
  • the anode metal 240 penetrates the first insulating layer 170 and the second insulating layer 180.
  • the pixel definition layer 190 is located above the anode metal 240, and has a communication hole connected to the anode metal 240.
  • the gate metal is usually made of metal molybdenum (Mo)
  • the interlayer dielectric layer is usually made of a stack of silicon oxide (SiO x ) and silicon nitride (SiN x ). Due to the large difference in material properties between the metal molybdenum and silicon oxide, there is often a large stress at the interface, which cannot be tightly combined. Even the stress between the two will cause the interlayer dielectric layer to fall off, forming a gap between the gate metal and the interlayer dielectric layer, thereby seriously affecting the characteristics of the thin film transistor and the yield of the device.
  • Mo metal molybdenum
  • SiN x silicon nitride
  • the present invention provides an organic self-luminous diode display panel and a manufacturing method thereof to solve the technical problem of the film layer falling off due to the stress between the interlayer dielectric layer and the gate metal in the prior art.
  • the present invention provides an organic self-emitting diode display panel, wherein the display panel includes:
  • the polysilicon layer 140, the gate metal 210, the first interlayer dielectric layer 150, the second interlayer dielectric layer 160, and the source-drain metal trace 220 constitute a thin film transistor layer.
  • the substrate 110 is usually a hard substrate, such as glass, or a flexible substrate, such as a polyimide substrate.
  • the silicon nitride layer 120 is located above the substrate 110, and the silicon oxide layer 130 is located above the silicon nitride layer 120.
  • the polysilicon layer 140 is located above the silicon oxide layer 130.
  • the polysilicon layer 140 includes a source-drain region 230 in a heavily doped region and a channel region between the source-drain regions 230.
  • the gate metal 210 is located on the polysilicon layer 140, and the gate metal 210 covers the polysilicon layer 140 above the channel region.
  • the gate buffer layer 210a is located above the gate metal 210, and the material constituting the gate buffer layer 210a is the oxide of the gate metal layer 210.
  • the material constituting the gate buffer layer 210a is the oxide of the gate metal layer 210.
  • a corresponding oxide is formed on the top to form a gate buffer layer.
  • the material constituting the gate metal layer is molybdenum
  • the material constituting the gate buffer layer is molybdenum oxide.
  • the thickness of the gate buffer layer is 2-5 nm.
  • the first interlayer dielectric layer 150 is located above the polysilicon layer 140 and is made of silicon oxide.
  • the first interlayer dielectric layer 150 covers the gate metal 210 and is not covered by the gate metal 210 The polysilicon layer 140.
  • the second interlayer dielectric layer 160 is located above the first interlayer dielectric layer 150, and its material is silicon nitride.
  • the source-drain metal trace 220 penetrates the first interlayer dielectric layer 150 and the second interlayer dielectric layer 160.
  • the first insulating layer 170 covers the source-drain metal trace 220 and the second interlayer dielectric layer 160.
  • the second insulating layer 180 is located above the first insulating layer 170.
  • the anode metal 240 penetrates the first insulating layer 170 and the second insulating layer 180.
  • the pixel definition layer 190 is located above the anode metal 240, and has a communication hole connected to the anode metal 240.
  • a thin layer of dense molybdenum oxide of about 2 to 5 nm is formed as a gate buffer layer above the gate dielectric layer by oxidation, and then the interlayer is deposited Medium layer. Since the stress of molybdenum oxide is between molybdenum and the interlayer dielectric layer, the stress between the two can be well balanced to prevent the interlayer dielectric layer from falling off after deposition, which can improve the characteristics of the thin film transistor Can greatly improve the yield of the device.
  • the present invention also provides a method for manufacturing an organic self-luminous diode display panel, wherein the method includes the following steps:
  • a polysilicon layer located above the substrate Forming a polysilicon layer located above the substrate, forming a source-drain region composed of spaced heavily doped regions and a channel region not heavily doped between the source-drain regions in the polysilicon layer;
  • a light emitting structure connected to the source and drain region wiring layer is formed.
  • a substrate 110 is provided, and a silicon nitride layer 120, a silicon oxide layer 130, a polysilicon layer 140, a gate metal 210, and a gate are sequentially formed on the substrate 110 ⁇ Buffer layer 210a.
  • the substrate 110 is usually a hard substrate, such as glass, or a flexible substrate, such as a polyimide substrate.
  • the silicon nitride layer 120 is located above the substrate 110, and the silicon oxide layer 130 is located above the silicon nitride layer 120.
  • the polysilicon layer 140 is located above the silicon oxide layer 130.
  • the polysilicon layer 140 includes a source-drain region 230 in a heavily doped region and a channel region between the source-drain regions 230.
  • the gate metal 210 is located on the polysilicon layer 140, and the gate metal 210 covers the polysilicon layer 140 above the channel region.
  • the gate buffer layer 210a is located above the gate metal 210, and the material constituting the gate buffer layer 210a is the oxide of the gate metal layer 210.
  • the material constituting the gate buffer layer 210a is the oxide of the gate metal layer 210.
  • a corresponding oxide is formed on the top to form a gate buffer layer.
  • the material constituting the gate metal layer is molybdenum
  • the material constituting the gate buffer layer is molybdenum oxide.
  • the thickness of the gate buffer layer is 2-5 nm.
  • a first interlayer dielectric layer 150, a second interlayer dielectric layer 160, and source-drain metal traces 220 are sequentially formed thereon.
  • the first interlayer dielectric layer 150 is located above the polysilicon layer 140 and is made of silicon oxide.
  • the first interlayer dielectric layer 150 covers the gate metal 210 and is not covered by the gate metal 210 The polysilicon layer 140.
  • the second interlayer dielectric layer 160 is located above the first interlayer dielectric layer 150, and its material is silicon nitride.
  • the source-drain metal trace 220 penetrates the first interlayer dielectric layer 150 and the second interlayer dielectric layer 160.
  • a first insulating layer 170 After that, referring to FIG. 4, after the source-drain metal trace 220 is formed, a first insulating layer 170, a second insulating layer 180, an anode metal 240, a pixel definition layer 190, and Light emitting structure.
  • the first insulating layer 170 covers the source-drain metal trace 220 and the second interlayer dielectric layer 160.
  • the second insulating layer 180 is located above the first insulating layer 170.
  • the anode metal 240 penetrates the first insulating layer 170 and the second insulating layer 180.
  • the pixel definition layer 190 is located above the anode metal 240, and has a communication hole connected to the anode metal 240.
  • a substrate 110, a silicon nitride layer 120, a silicon oxide layer 130, a polysilicon layer 140, a gate metal 210, a gate buffer layer 210a, a first interlayer dielectric layer 150, and a second interlayer dielectric layer 160 are formed ,
  • the source-drain metal trace 220, the first insulating layer 170, the second insulating layer 180, the anode metal 240, the pixel definition layer 190, and the technology of the light emitting structure above the pixel definition layer 190 are mature processes in the art, No more detailed explanation here.
  • the invention improves the existing thin film transistor of the organic self-luminous diode display panel and the manufacturing method thereof.
  • a thin layer of about 2 ⁇ 5 is formed on the gate dielectric layer by oxidation
  • the dense molybdenum oxide around nm is used as the gate buffer layer, and then the interlayer dielectric layer is deposited. Since the stress of molybdenum oxide is between molybdenum and the interlayer dielectric layer, the stress between the two can be well balanced to prevent the interlayer dielectric layer from falling off after deposition, which can improve the characteristics of the thin film transistor. Can greatly improve the yield of the device.

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Abstract

一种有机自发光二极管显示面板及其制作方法。所述显示面板包括：基板(110)；薄膜晶体管层；发光结构；其中，所述薄膜晶体管层包括：多晶硅层(140)；位于所述多晶硅层(140)上方的栅极介质层；位于所述栅极介质层上方的栅极金属层(210)；位于所述栅极介质层上方的栅极缓冲层(210a)；覆盖所述栅极介质层、栅极金属层(210)和栅极缓冲层(210a)的层间介质层(150/160)。

Description

有机自发光二极管显示面板及其制作方法 技术领域
本发明涉及电子显示领域，尤其涉及一种有机自发光二极管显示面板及其制作方法。
 背景技术
在传统的有机自发光二极管显示面板薄膜晶体管的制作过程中，在制作完成栅极金属后，会利用PECVD沉积层间介质层。目前，栅极金属通常采用金属钼（Mo）制成，而层间介质层则通常采用氧化硅（SiO x）和氮化硅（SiN x）的叠层制成。
技术问题
由于金属钼和氧化硅之间的材料特性差异较大，其界面处往往存在较大的应力，无法紧密的结合。甚至二者之间的应力会导致层间介质层脱落，在栅极金属和层间介质层之间形成缝隙，从而严重影响薄膜晶体管的特性，进行严重影响器件的良率。
 技术解决方案
本发明提供一种有机自发光二极管显示面板及其制作方法，以解决现有技术中由于层间介质层和栅极金属之间的应力导致的膜层脱落的技术问题。
为解决上述问题，本发明提供了一种有机自发光二极管显示面板，其中，所述显示面板包括：基板；位于所述基板上方的薄膜晶体管层；位于所述薄膜晶体管层上方，与所述薄膜晶体管层中的源漏区走线层相连接的发光结构；其中，
所述薄膜晶体管层包括：
位于基板上方的多晶硅层，所述多晶硅层中具有由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
位于所述多晶硅层上方的栅极介质层；
位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
位于所述栅极介质层上方的栅极缓冲层；
覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；以及
贯穿所述栅极介质层和层间介质层的源漏区走线层；其中，
构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
根据本发明的其中一个方面，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
根据本发明的其中一个方面，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
为解决上述问题，本发明提供了一种有机自发光二极管显示面板，其中，所述显示面板包括：基板；位于所述基板上方的薄膜晶体管层；位于所述薄膜晶体管层上方，与所述薄膜晶体管层中的源漏区走线层相连接的发光结构；其中，
所述薄膜晶体管层包括：
位于基板上方的多晶硅层，所述多晶硅层中具有由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
位于所述多晶硅层上方的栅极介质层；
位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
位于所述栅极介质层上方的栅极缓冲层；
覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；以及
贯穿所述栅极介质层和层间介质层的源漏区走线层。
根据本发明的其中一个方面，构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
根据本发明的其中一个方面，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
根据本发明的其中一个方面，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
根据本发明的其中一个方面，所述栅极缓冲层的厚度为2~5nm。
相应的，本发明还提供了一种有机自发光二极管显示面板的制作方法，其中，该方法包括以下步骤：
提供基板；
形成位于基板上方的多晶硅层，在所述多晶硅层中形成由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
形成位于所述多晶硅层上方的栅极介质层；
形成位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
形成位于所述栅极介质层上方的栅极缓冲层；
形成覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；
形成贯穿所述栅极介质层和层间介质层的源漏区走线层；
形成与所述源漏区走线层相连接的发光结构。
根据本发明的其中一个方面，构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
根据本发明的其中一个方面，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
根据本发明的其中一个方面，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
根据本发明的其中一个方面，所述栅极缓冲层的厚度为2~5nm。
 有益效果
本发明改善了现有的有机自发光二极管显示面板的薄膜晶体管及其制作方法。通过在制作完成栅极金属钼后，利用氧化作用在所述栅极介质层上方形成一层很薄的约2~5 nm左右的致密的氧化钼作为栅极缓冲层，再沉积层间介质层。由于氧化钼的应力介于钼和层间介质层之间，能很好地平衡二者之间的应力，防止在层间介质层沉积后出现脱落的状况，从而可以改善薄膜晶体管的特性，进行可以大幅度提升器件的良率。
 附图说明
图1为现有技术中的有机自发光二极管显示面板中的薄膜晶体管的结构示意图；
图2至图4为本发明具体实施方式中的有机自发光二极管显示面板的制作方法的各个步骤中的薄膜晶体管的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明，参见图1，有机自发光二极管显示面板的薄膜晶体管层包括：基板110、氮化硅层120、氧化硅层130、多晶硅层140、栅极金属210、第一层间介质层150、第二层间介质层160、所述源漏金属走线220、第一绝缘层170、第二绝缘层180、阳极金属240以及像素定义层190。
具体的，所述基板110通常为硬质基板，如玻璃；也可以是柔性基板，如聚酰亚胺基板。
具体的，所述氮化硅层120位于所述基板110上方，所述氧化硅层130位于所述氮化硅层120上方。
具体的，所述多晶硅层140位于所述氧化硅层130上方，所述多晶硅层140包括重掺杂区的源漏区230以及位于所述源漏区230之间的沟道区。
具体的，所述栅极金属210位于所述多晶硅层140上的，所述栅极金属210覆盖沟道区上方的多晶硅层140。
具体的，所述第一层间介质层150位于所述多晶硅层140上方，所述第一层间介质层150覆盖所述栅极金属210和未被栅极金属210覆盖的所述多晶硅层140。
具体的，所述第二层间介质层160位于第一层间介质层150上方。
具体的，所述源漏金属走线220贯穿所述第一层间介质层150和所述第二层间介质层160。
具体的，所述第一绝缘层170覆盖所述源漏金属走线220和第二层间介质层160。
具体的，所述第二绝缘层180位于所述第一绝缘层170上方。
具体的，所述阳极金属240贯穿所述第一绝缘层170和所述第二绝缘层180。
具体的，所述像素定义层190以及位于所述阳极金属240上方，并具有与所述阳极金属240相连接的连通孔。
现有技术中，栅极金属通常采用金属钼（Mo）制成，而层间介质层则通常采用氧化硅（SiO x）和氮化硅（SiN x）的叠层制成。由于金属钼和氧化硅之间的材料特性差异较大，其界面处往往存在较大的应力，无法紧密的结合。甚至二者之间的应力会导致层间介质层脱落，在栅极金属和层间介质层之间形成缝隙，从而严重影响薄膜晶体管的特性，进行严重影响器件的良率。
因此，本发明提供了一种有机自发光二极管显示面板及其制作方法，以解决现有技术中由于层间介质层和栅极金属之间的应力导致的膜层脱落的技术问题。
具体的，本发明提供了一种有机自发光二极管显示面板，其中，所述显示面板包括：
基板110、氮化硅层120、氧化硅层130、多晶硅层140、栅极金属210、栅极缓冲层210a、第一层间介质层150、第二层间介质层160、源漏金属走线220、第一绝缘层170、第二绝缘层180、阳极金属240、像素定义层190、以及位于所述像素定义层190上方的发光结构。其中，所述多晶硅层140、栅极金属210、第一层间介质层150、第二层间介质层160和所述源漏金属走线220构成薄膜晶体管层。
具体的，所述基板110通常为硬质基板，如玻璃；也可以是柔性基板，如聚酰亚胺基板。
具体的，所述氮化硅层120位于所述基板110上方，所述氧化硅层130位于所述氮化硅层120上方。
具体的，所述多晶硅层140位于所述氧化硅层130上方，所述多晶硅层140包括重掺杂区的源漏区230以及位于所述源漏区230之间的沟道区。
具体的，所述栅极金属210位于所述多晶硅层140上的，所述栅极金属210覆盖沟道区上方的多晶硅层140。
具体的，所述栅极缓冲层210a位于所述栅极金属210上方，构成所述栅极缓冲层210a的材料为栅极金属层210的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。优选的，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。优选的，所述栅极缓冲层的厚度为2~5nm。
具体的，所述第一层间介质层150位于所述多晶硅层140上方，其材料为氧化硅，所述第一层间介质层150覆盖所述栅极金属210和未被栅极金属210覆盖的所述多晶硅层140。
具体的，所述第二层间介质层160位于第一层间介质层150上方，其材料为氮化硅。
具体的，所述源漏金属走线220贯穿所述第一层间介质层150和所述第二层间介质层160。
具体的，所述第一绝缘层170覆盖所述源漏金属走线220和第二层间介质层160。
具体的，所述第二绝缘层180位于所述第一绝缘层170上方。
具体的，所述阳极金属240贯穿所述第一绝缘层170和所述第二绝缘层180。
具体的，所述像素定义层190以及位于所述阳极金属240上方，并具有与所述阳极金属240相连接的连通孔。
本发通过在制作完成栅极金属钼后，利用氧化作用在所述栅极介质层上方形成一层很薄的约2~5 nm左右的致密的氧化钼作为栅极缓冲层，再沉积层间介质层。由于氧化钼的应力介于钼和层间介质层之间，能很好地平衡二者之间的应力，防止在层间介质层沉积后出现脱落的状况，从而可以改善薄膜晶体管的特性，进行可以大幅度提升器件的良率。
相应的，本发明还提供了一种有机自发光二极管显示面板的制作方法，其中，该方法包括以下步骤：
提供基板；
形成位于基板上方的多晶硅层，在所述多晶硅层中形成由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
形成位于所述多晶硅层上方的栅极介质层；
形成位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
形成位于所述栅极介质层上方的栅极缓冲层；
形成覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；
形成贯穿所述栅极介质层和层间介质层的源漏区走线层；
形成与所述源漏区走线层相连接的发光结构。
下面将结合附图对上述方法进行详细说明，首先，参见图2，提供基板110，并依次在基板110上形成氮化硅层120、氧化硅层130、多晶硅层140、栅极金属210以及栅极缓冲层210a。
具体的，所述基板110通常为硬质基板，如玻璃；也可以是柔性基板，如聚酰亚胺基板。
具体的，所述氮化硅层120位于所述基板110上方，所述氧化硅层130位于所述氮化硅层120上方。
具体的，所述多晶硅层140位于所述氧化硅层130上方，所述多晶硅层140包括重掺杂区的源漏区230以及位于所述源漏区230之间的沟道区。
具体的，所述栅极金属210位于所述多晶硅层140上的，所述栅极金属210覆盖沟道区上方的多晶硅层140。
具体的，所述栅极缓冲层210a位于所述栅极金属210上方，构成所述栅极缓冲层210a的材料为栅极金属层210的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。优选的，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。优选的，所述栅极缓冲层的厚度为2~5nm。
之后，参见图3，形成栅极缓冲层210a之后，在其上方依次形成第一层间介质层150、第二层间介质层160和源漏金属走线220。
具体的，所述第一层间介质层150位于所述多晶硅层140上方，其材料为氧化硅，所述第一层间介质层150覆盖所述栅极金属210和未被栅极金属210覆盖的所述多晶硅层140。
具体的，所述第二层间介质层160位于第一层间介质层150上方，其材料为氮化硅。
具体的，所述源漏金属走线220贯穿所述第一层间介质层150和所述第二层间介质层160。
之后，参见图4，在所述源漏金属走线220形成之后依次形成第一绝缘层170、第二绝缘层180、阳极金属240、像素定义层190、以及位于所述像素定义层190上方的发光结构。
具体的，所述第一绝缘层170覆盖所述源漏金属走线220和第二层间介质层160。
具体的，所述第二绝缘层180位于所述第一绝缘层170上方。
具体的，所述阳极金属240贯穿所述第一绝缘层170和所述第二绝缘层180。
具体的，所述像素定义层190以及位于所述阳极金属240上方，并具有与所述阳极金属240相连接的连通孔。
在本发明中，形成基板110、氮化硅层120、氧化硅层130、多晶硅层140、栅极金属210、栅极缓冲层210a、第一层间介质层150、第二层间介质层160、源漏金属走线220、第一绝缘层170、第二绝缘层180、阳极金属240、像素定义层190、以及位于所述像素定义层190上方的发光结构的技术为本领域的成熟工艺，在此不再详细说明。
本发明改善了现有的有机自发光二极管显示面板的薄膜晶体管及其制作方法。通过在制作完成栅极金属钼后，利用氧化作用在所述栅极介质层上方形成一层很薄的约2~5 nm左右的致密的氧化钼作为栅极缓冲层，再沉积层间介质层。由于氧化钼的应力介于钼和层间介质层之间，能很好地平衡二者之间的应力，防止在层间介质层沉积后出现脱落的状况，从而可以改善薄膜晶体管的特性，进行可以大幅度提升器件的良率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种有机自发光二极管显示面板，其中，所述显示面板包括：基板；位于所述基板上方的薄膜晶体管层；位于所述薄膜晶体管层上方，与所述薄膜晶体管层中的源漏区走线层相连接的发光结构；其中，
    所述薄膜晶体管层包括：
    位于基板上方的多晶硅层，所述多晶硅层中具有由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
    位于所述多晶硅层上方的栅极介质层；
    位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
    位于所述栅极介质层上方的栅极缓冲层；
    覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；以及
    贯穿所述栅极介质层和层间介质层的源漏区走线层；其中，
    构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
  2. 根据权利要求1所述的有机自发光二极管显示面板，其中，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
  3. 根据权利要求1所述的有机自发光二极管显示面板，其中，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
  4. 一种有机自发光二极管显示面板，其中，所述显示面板包括：基板；位于所述基板上方的薄膜晶体管层；位于所述薄膜晶体管层上方，与所述薄膜晶体管层中的源漏区走线层相连接的发光结构；其中，
    所述薄膜晶体管层包括：
    位于基板上方的多晶硅层，所述多晶硅层中具有由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
    位于所述多晶硅层上方的栅极介质层；
    位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
    位于所述栅极介质层上方的栅极缓冲层；
    覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；以及
    贯穿所述栅极介质层和层间介质层的源漏区走线层。
  5. 根据权利要求4所述的有机自发光二极管显示面板，其中，构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
  6. 根据权利要求4所述的有机自发光二极管显示面板，其中，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
  7. 根据权利要求4所述的有机自发光二极管显示面板，其中，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
  8. 根据权利要求5所述的有机自发光二极管显示面板，其中，所述栅极缓冲层的厚度为2~5nm。
  9. 一种有机自发光二极管显示面板的制作方法，其中，该方法包括以下步骤：
    提供基板；
    形成位于基板上方的多晶硅层，在所述多晶硅层中形成由间隔设置的重掺杂区构成的源漏区和位于所述源漏区之间未被重掺杂的沟道区；
    形成位于所述多晶硅层上方的栅极介质层；
    形成位于所述栅极介质层上方的栅极金属层，所述栅极金属层覆盖且仅覆盖位于所述沟道区上方的栅极介质层；
    形成位于所述栅极介质层上方的栅极缓冲层；
    形成覆盖所述栅极介质层、栅极金属层和栅极缓冲层的层间介质层；
    形成贯穿所述栅极介质层和层间介质层的源漏区走线层；
    形成与所述源漏区走线层相连接的发光结构。
  10. 根据权利要求9所述的有机自发光二极管显示面板的制作方法，其中，构成所述栅极缓冲层的材料为栅极金属层的氧化物，通过对所述栅极金属层进行氧化，在其顶部形成对应的氧化物构成栅极缓冲层。
  11. 根据权利要求9所述的有机自发光二极管显示面板的制作方法，其中，构成所述栅极金属层的材料为钼，构成所述栅极缓冲层的材料为氧化钼。
  12. 根据权利要求9所述的有机自发光二极管显示面板的制作方法，其中，所述层间介质层包括第一介质层和第二介质层，其中所述第一介质层的材料为氧化硅，所述第二介质层位于所述第一介质层上方，其材料为氮化硅。
  13. 根据权利要求9所述的有机自发光二极管显示面板的制作方法，其中，所述栅极缓冲层的厚度为2~5nm。
PCT/CN2018/116985 2018-10-18 2018-11-22 有机自发光二极管显示面板及其制作方法 WO2020077737A1 (zh)

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