WO2020073823A1 - 电路板、设备及过孔结构的形成方法 - Google Patents

电路板、设备及过孔结构的形成方法 Download PDF

Info

Publication number
WO2020073823A1
WO2020073823A1 PCT/CN2019/108411 CN2019108411W WO2020073823A1 WO 2020073823 A1 WO2020073823 A1 WO 2020073823A1 CN 2019108411 W CN2019108411 W CN 2019108411W WO 2020073823 A1 WO2020073823 A1 WO 2020073823A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
hole
layer
board body
target signal
Prior art date
Application number
PCT/CN2019/108411
Other languages
English (en)
French (fr)
Inventor
尹昌刚
王迎新
易毕
曹化章
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to JP2021517629A priority Critical patent/JP7178764B2/ja
Priority to US17/282,410 priority patent/US11457529B2/en
Priority to EP19871140.0A priority patent/EP3866571A4/en
Publication of WO2020073823A1 publication Critical patent/WO2020073823A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material

Definitions

  • Embodiments of the present invention relate to, but are not limited to, the field of circuit boards. Specifically, it relates to but not limited to a circuit board, equipment, and a method for forming a via structure.
  • Via is a kind of structure that must be used in high-speed and high-density design, its performance directly affects the performance of high-speed and high-density products.
  • One of the important indicators to measure the performance of vias is impedance continuity. The impedance of vias is generally much lower than the characteristic impedance of the PCB transmission line connected to it, resulting in poor impedance continuity of the entire link and causing signal integrity problems.
  • the impedance of the via is related to the parasitic capacitance and parasitic inductance of the via.
  • the relevant approach is to expand the hollowing of the anti-pad of the via to a certain extent, but the actual hollowing size cannot be unlimited, otherwise it will affect the integrity of the signal reference plane and cause other signals. Integrity problem, and after the hollowing size reaches a certain level, it has reached a bottleneck in enhancing the impedance of the via.
  • Another approach in related practices is to reduce the via hole diameter, because the smaller the via hole diameter, the smaller the parasitic capacitance, the greater the via impedance, and the better the impedance continuity of the system link.
  • the thickness-to-diameter ratio that is, the ratio of the thickness of the board to the diameter of the via. Therefore, it is difficult to process the small hole design, which affects the PCB yield and ultimately affects the cost and reliability of the product. Even because the thickness-to-diameter ratio is too large, the PCB processing fails and is scrapped. Therefore, how to effectively increase the via impedance is a technical problem that needs to be solved urgently.
  • the circuit board, equipment, and method for forming a via structure provided in the embodiments of the present invention mainly solve the technical problem of how to increase the impedance of the via.
  • an embodiment of the present invention provides a circuit board including a circuit board body with a multilayer structure, and a via structure provided on the circuit board body, the via structure included in the circuit board A hole formed by a conductive layer surrounding the main body, the conductive layer constituting a hole wall of the hole; the via structure further includes a dielectric filling layer, at least part of the hole wall and the circuit board body are provided between The dielectric filling layer, the dielectric constant of the dielectric filling layer is smaller than the dielectric constant of the circuit board body.
  • an embodiment of the present invention further provides a device, including a device body and the above-mentioned circuit board, the circuit board being disposed on the device body.
  • embodiments of the present invention also provide a method for forming a via structure, including:
  • the dielectric constant of the medium is smaller than the dielectric constant of the circuit board body
  • a second hole penetrating the medium is opened in the medium area of the first hole, the second hole has a smaller diameter than the first hole, and the medium with the second hole is formed as a medium filling Floor;
  • a conductive layer is formed on the hole wall of the second hole to obtain a via structure, wherein the conductive layer surrounds to form a hole, and the conductive layer constitutes the hole wall of the hole.
  • the via structure formed on the circuit board body of the circuit board includes a hole surrounded by a conductive layer in the circuit board body, the conductive layer A hole wall constituting a hole, and a dielectric filling layer having a dielectric constant lower than that of the circuit board body is provided between at least a part of the hole wall and the circuit board body, that is, in some implementation processes, a via hole can be made
  • the dielectric constant of the surrounding medium is less than the dielectric constant of the main body of the circuit board, thereby reducing the parasitic capacitance of the via, increasing the impedance of the via, making it closer to the impedance of the transmission line, and effectively improving the impedance continuity of the system link.
  • FIG. 1 is a schematic diagram 1 of a circuit board according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram 2 of a circuit board according to the first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram 3 of a circuit board according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram 4 of a circuit board according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram 5 of a circuit board according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic flow chart of a via forming method according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic view of the cross-sectional structure of the first opening of the second embodiment of the present invention.
  • FIG. 8 is a schematic top view of the first opening of the second embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a cross-sectional structure after being filled with a medium according to Embodiment 2 of the present invention.
  • FIG. 10 is a schematic top view of the second embodiment of the present invention after filling with a medium
  • FIG. 11 is a schematic diagram of a cross-sectional structure of the second opening of the second embodiment of the present invention.
  • FIG. 12 is a schematic top view of the second opening of the second embodiment of the present invention.
  • FIG. 13 is a schematic diagram of another cross-sectional structure of the second opening according to Embodiment 2 of the present invention.
  • FIG. 14 is a schematic top view of another second opening of the second embodiment of the present invention.
  • 15 is a schematic cross-sectional structure diagram of a second embodiment of the present invention after forming a conductive layer
  • 16 is a schematic top view of the second embodiment of the present invention after forming a conductive layer.
  • this embodiment provides a circuit board, which is provided with Hole structure, the via structure includes a hole surrounded by a conductive layer in the circuit board body, the conductive layer constitutes the hole wall of the hole (the hole and the hole wall forming process), and at least part of the hole wall and the hole A dielectric filling layer with a dielectric constant lower than that of the circuit board body is provided between the circuit board bodies, that is, between the vias formed on the circuit board body and the circuit board body, a dielectric constant less than the circuit board body is provided A dielectric filling layer with its own dielectric constant, so that the dielectric constant of the dielectric around the via is smaller than the dielectric constant of the circuit board body, thereby reducing the parasitic capacitance of the via.
  • a way to calculate the parasitic capacitance of the via is shown in the following
  • C represents the parasitic capacitance of the via
  • T represents the thickness of the circuit board body
  • D 2 represents the diameter of the reverse pad of the via
  • D 1 represents the diameter of the pad
  • ⁇ r represents the Dielectric constant.
  • the parasitic capacitance of the via is proportional to the dielectric constant of the board material of the circuit board. Therefore, in this embodiment, the dielectric constant between the via and the circuit board body is smaller than the dielectric of the circuit board body itself.
  • the constant dielectric filling layer is made of the main material of the circuit board around the existing vias, which can reduce the dielectric constant of the dielectric around the vias, that is, reduce the ⁇ r value, and thereby reduce the parasitic capacitance C of the vias To increase the impedance of the vias and improve the impedance continuity of the system link.
  • FIG. 1 An exemplary circuit board structure provided in this embodiment is shown in FIG. 1, which includes a multilayer circuit board body 10, and it is assumed that the uppermost layer in FIG. 1 is the top layer of the circuit board body 10, and the lowermost one The layer is the bottom layer of the circuit board body 10; a via structure is formed on the circuit board body 10, the via structure includes a hole 12 surrounded by a conductive layer in the circuit board body 10, and the conductive layer at this time constitutes the hole 12 Of the hole wall 11 (the hole 12 and the hole wall 11 constitute a via in this embodiment), the via structure further includes a dielectric filling layer 13, and at least a portion of the hole wall 11 and the circuit board body 10 are provided with a medium The filling layer 13 and the dielectric constant of the dielectric filling layer 13 are smaller than the dielectric constant of the circuit board body 10.
  • the dielectric filling layer 13 in this embodiment may be composed of a single material medium having a dielectric constant smaller than that of the circuit board body 10; it may also be composed of a dielectric constant lower than that of the circuit board body 10 Small, multi-material media.
  • the dielectric constant of the specific medium and the material of the specific medium can be flexibly selected according to the system.
  • the medium includes but is not limited to resin, and when the medium is resin, the medium includes but is not limited to polyethylene, benzo ring At least one of butene and polytetrafluoroethylene (or Teflon).
  • the dielectric constant of the medium can also be flexibly selected, as long as it is smaller than the dielectric constant of the circuit board body 10 or as long as it meets the current requirements for via impedance.
  • the conductive layer surrounds the conductive layer forming the hole 12, that is, the conductive material used for the hole wall 11 of the hole 12.
  • the specific process of forming the hole wall 11 can also be flexibly selected, for example, including but not limited to forming a hole wall 11 through various metal plating processes (for example, including but not limited to electroplating).
  • the shape of the cross section of the hole 12 in this embodiment includes but is not limited to a circle, which can be flexibly set according to specific application requirements, for example, in some application scenarios, the cross section of the hole 12 is set to an ellipse Other shapes can meet the needs.
  • a dielectric filling layer 13 is provided between at least part of the area of the hole wall 11 and the circuit board body 10. Including in some examples (for example, see FIG. 3), a dielectric filling layer 13 is provided between the entire hole wall 11 and the circuit board body 10. As shown in FIGS. 1 and 2, a dielectric filling layer 13 may be provided only between a partial area of the hole wall 11 and the circuit board body 10. You can flexibly choose which setting method to use according to your needs and specific implementation process.
  • the multilayer structure of the circuit board body 10 includes a target signal layer 101 corresponding to the via structure.
  • the lower end of the hole 12 extends in the circuit board body 10 along the thickness direction of the circuit board body 10 and extends to the corresponding target signal layer 101 in the circuit board body 10; the hole wall 11 of the hole 12 is located in the corresponding target signal layer 101 At least a part of the part is in direct contact with the target signal layer 101, that is, the hole wall 11 of the hole 12 is in the part 101 of the target signal layer, and at least a part of the target signal layer 101 has no dielectric filling layer 13 between the target signal layer 101 to achieve the corresponding target signal Electrical connection between layers 101.
  • the portion of the hole wall 11 of the hole 12 in the corresponding target signal layer 101 is completely free of the dielectric filling layer 13 between the corresponding target signal layer 101, that is, directly connected to the corresponding target signal layer 101 contacts.
  • a dielectric filling layer 13 is provided on the hole wall of the hole 12 between the portion outside the target signal layer 101 and the circuit board body 10.
  • a dielectric filling layer 13 is provided between the upper part of the portion within the corresponding target signal layer 101 and the target signal layer 101, the hole On the hole wall 11 of 12, there is no dielectric filling layer 13 between the lower part of the portion within the corresponding target signal layer 101 and the target signal layer 101, and the hole wall 11 of the hole 12 is located outside the corresponding target signal layer 101
  • a dielectric filling layer 13 is provided between the portion and the circuit board body 10.
  • the hole to be opened is larger than the general via hole diameter, so the opening is not Extend to the target signal layer 101 or only to a part of the target signal layer 101 without penetrating the target signal layer 101, for example, extend into the target signal layer 101 and above the corresponding target line in the target signal layer 101 to avoid The destruction of the line or pad on the target signal layer 101, thereby ensuring the reliability of the circuit board.
  • the upper end of the hole 12 is opposite to the lower end of the hole 12, and the upper end of the hole 12 may extend in the direction of the top layer or the bottom layer of the circuit board body 10 in the reverse direction of the thickness of the circuit board body 10. That is, the via in this embodiment may be opened from the top layer of the circuit board body 10 (ie, the TOP layer) to the corresponding target signal layer in the circuit board body, or from the bottom layer of the circuit board body 10 (ie, the BOT layer).
  • the corresponding target signal layer in the circuit board body 10 is opened, for example, as shown in FIG. 4, it is opened from the bottom layer (ie, the BOT layer) of the circuit board body 10 to the corresponding target signal layer in the circuit board body 10, and the upper end of the hole 12 is located The bottom layer of the circuit board body 10.
  • the lower end of the hole refers to the end extending toward the inside of the circuit board body 10 when the hole is opened in the circuit board body 10, and the upper end of the hole is the other end opposite to the lower end.
  • the lower end of the obtained hole is the end located inside the circuit board body 10.
  • the upper end is the end located on the top layer of the circuit board body 10.
  • the lower end of the obtained hole is the end located inside the circuit board body 10, and the upper end of the hole It is the end located on the bottom layer of the circuit board body 10.
  • the upper and lower ends of the hole 12 may be located in two signal layers in the circuit board body 10 that need to be connected, for connecting corresponding lines in the two signal layers.
  • the two signal layers may be located inside the circuit board body 10, or one layer may be located inside the circuit body 10, and the other layer may be a top layer or a bottom layer of the circuit board body 10.
  • the via structure shown in FIG. 5 can be called For buried vias.
  • the number of via structures to be provided on the circuit board body 10 and the distance between each via and the size relationship can be flexibly set according to specific system requirements, for example, it can be set One via structure, two or more via structures can also be set according to specific requirements, for example, two via structures for differential device application scenarios, or three or more vias
  • the hole structure is suitable for the requirements of corresponding application scenarios.
  • some of the via structures may use the via structures provided in this embodiment, and the remaining vias may use other via structures.
  • the anti-pad structure of each via in this embodiment may adopt various anti-pad structures, and no limitation is imposed on it in this embodiment.
  • the above-mentioned via structure formed on the circuit board body 10 in this embodiment can be applied to single-ended signal vias or differential signal vias.
  • the application scenarios of vias used include but are not limited to BGA (Ball Grid Array, solder ball array package) vias, crimp connector vias, AC coupling capacitor fan-out vias, chip rectangular pad fan-out vias, Solder connector pads fan out vias, etc.
  • the via structure provided in this embodiment is applicable not only to through holes, but also to but not limited to laser blind holes, mechanical blind holes, buried holes, POFV (Plating Over Filled Via) Wait.
  • This embodiment also provides a device, which may be various devices that require a circuit board with a via structure.
  • the device includes a device body and a circuit board as illustrated above, and the circuit board is disposed on the device body.
  • the via structure provided in this embodiment can fill the dielectric between the via and the circuit board body with a dielectric constant lower than that of the circuit board body, thereby reducing the dielectric constant of the dielectric around the via hole, thereby reducing the parasitic capacitance of the via hole and improving the The impedance of the hole makes it closer to the impedance of the transmission line, which effectively improves the impedance continuity of the system link.
  • the via structure provided in this embodiment can be used in combination with other structures that can increase the via impedance and can be combined to enhance the effect of increasing the via impedance, including but not limited to The anti-pad of the via hole is enlarged to a certain extent, or the aperture diameter of the via hole is reduced to a certain extent.
  • FIG. 6 An example process of a method for forming a via structure is shown in FIG. 6 and includes:
  • a first hole is formed in the circuit board body of the multilayer structure.
  • the first hole formed in the main body of the circuit board in this step is for setting a medium having a dielectric constant lower than that of the main body of the circuit board to form a dielectric filling layer.
  • the specific opening depth and aperture size of the first hole can be flexibly set, and the specific opening method of the first hole can also adopt various opening methods, including, but not limited to, drilling.
  • the method of filling the medium in the first hole can also be flexibly set according to specific application scenarios, including but not limited to the use of injection molding, precipitation, molding and other processes to achieve the filling of the medium.
  • the process supporting dielectric filling layer is integrally formed with each layer of the circuit board body, this integrated forming process may also be used to form the dielectric filling layer in the corresponding region of the corresponding layer of the circuit board main board.
  • the dielectric filling layer may be composed of a single material medium whose dielectric constant is smaller than that of the circuit board body; or may be composed of a variety of material mediums whose dielectric constant is smaller than that of the circuit board body .
  • a medium with a dielectric constant less than or equal to any one of 2.6, 2.5, and 2.4 is used.
  • the medium includes but is not limited to resin
  • S603 A second hole penetrating the medium is opened in the medium area in the first hole, and the medium with the second via hole is formed as a medium filling layer.
  • the second hole and the first hole may or may not be concentric holes, and the opening depth of the second hole is greater than or equal to the first hole, and the diameter of the second hole is smaller than the diameter of the first hole.
  • S604 Form a conductive layer on the hole wall of the second hole to obtain a via structure, wherein the conductive layer surrounds to form a hole, and the conductive layer constitutes the hole wall of the hole.
  • the conductive layer formed in this step and the hole surrounded by the conductive layer constitute the via hole in this embodiment, and the formation process of the conductive layer can also be flexibly selected. Through the conductive layer, the corresponding lines on each signal layer that needs to be connected through vias can be connected.
  • a dielectric filling layer having a dielectric constant smaller than that of the circuit board body is formed between the via hole and the circuit board body, thereby reducing the dielectric of the dielectric around the via hole Constant, thereby reducing the parasitic capacitance of the via, increasing the impedance of the via, making it closer to the impedance of the transmission line, and effectively improving the impedance continuity of the system link.
  • the method for forming a via structure provided in this embodiment further has at least the following advantages:
  • circuit boards such as, but not limited to, PCB
  • circuit boards such as, but not limited to, PCB
  • circuit boards relatively related to the practice of increasing the via impedance by reducing the via hole diameter, as the thickness-to-diameter ratio of the PCB becomes larger, the processing difficulty becomes more and more difficult
  • the via impedance is increased by reducing the dielectric constant around the via. There is no need to increase the via impedance by reducing the via diameter, which greatly reduces the via impedance. Processing difficulty, reducing processing costs and improving yield.
  • the dielectric constant around the via is reduced, thereby reducing the parasitic capacitance of the via, thereby increasing the impedance of the via and making it closer to the impedance of the target line, which can effectively improve the system The impedance continuity of the link.
  • the opening depth of the second hole in this embodiment may be greater than or equal to the first hole.
  • the lower end of the first hole extends into the circuit board body along the thickness direction of the circuit board body, and extends to a layer above the corresponding target signal layer in the circuit board body (of course, it can also be the target signal layer)
  • the other layers above can be flexibly set according to the requirements), or extend into the target signal layer and above the corresponding target line.
  • the lower end of the second hole extends into the main body of the circuit board and extends to the target signal layer.
  • the first hole or the second hole is formed by drilling.
  • the target signal layer 101 is on the Lm2 layer.
  • the first hole is drilled from the top TOP layer of the circuit board body 10 to the m1 (1 ⁇ m1 ⁇ n) layer (that is, the Lm1 layer) to obtain the first hole 14 having a diameter Ds1.
  • a medium is provided in the first hole, for example, a first hole 14 of a low dielectric constant dielectric plug is used, where low dielectric constant means that the dielectric constant is lower than the dielectric constant of the circuit board body 10 .
  • the dielectric filling layer uses a material with a dielectric constant lower than that of the glass fiber, such as, but not limited to, resin.
  • a second drilling is performed, the second drilling is located inside the first hole, and the second hole 15 is obtained from the top layer of the circuit board body 10 to the m2 (m1 ⁇ m2 ⁇ n) layer, The diameter of the second hole 15 is Ds2, and Ds2 is smaller than Ds1.
  • a medium filled layer 13 is formed.
  • the second drilling hole is located inside the first via hole. It is not limited to drilling the second hole 15 concentrically with the first hole from the center of the first hole, but may be any position. For example, referring to FIGS. 13 and 14, the second hole 15 may also be located at any eccentric position within the first hole 14 relative to the first hole 14.
  • a conductive layer 11 is formed in the second hole 15 by a process such as electroplating, and the conductive layer 11 surrounds to form the hole 12.
  • the related design generally guarantees that the impedance of the crimped via is between 80 and 85 ohms. If it is discontinuous for a 100 ohm system, it will increase the chain. The discontinuity of the road. Especially for 400G and other application scenarios, the signal rate is higher and the signal edge is steeper, so the via impedance is higher.
  • the hole diameter of the differential via is 0.4mm, and the diameter of the counter pad is 1.2mm. Assuming that the number of PCB layers in this application scenario is 24, M6G plate is used, the dielectric constant is 3.5, and the target signal The layer is on the L10 layer.
  • the formation process of a via structure in this application scenario includes:
  • the medium from the TOP layer to the L9 layer in the order of pp (pre-pregnant, semi-cured board) / core (inner core board) / pp to form the first daughter board (that is, part of the circuit board body).
  • the first drilling is performed on the daughter board, the diameter Ds1 is 1.0mm, and the high-speed connector uses differential signals, so the number of holes drilled on the first daughter board is 2, and the hole center distance is 1.2mm;
  • a low dielectric constant medium for example, a dielectric with a dielectric constant of 2.6
  • a dielectric filling layer for example, a dielectric with a dielectric constant of 2.6
  • a low dielectric constant medium for example, a dielectric with a dielectric constant of 2.6
  • a dielectric filling layer for example, a dielectric with a dielectric constant of 2.6
  • the holes obtained by the second drilling are electroplated to obtain corresponding via holes;
  • the dielectric constant around the differential via of the high-speed connector is reduced from 3.5 to 2.6 after adopting the above-mentioned embodiment, the parasitic capacitance of the differential via is effectively reduced, which can increase the impedance of the differential via and improve the system link Impedance continuity.
  • the thickness of the circuit board body is 3 mm
  • the diameter of the BGA differential via hole is 0.2 mm
  • the medium of the circuit board body is M6G
  • the dielectric constant is 3.5
  • the target signal layer is on the L10 layer.
  • the diameter of the drill hole Ds1 is 0.7mm, and the high-speed chip uses differential signals, so the number of drill holes is 2, assuming that the hole center distance is 1mm;
  • a low dielectric constant medium for example, a dielectric with a dielectric constant of 2.4
  • a dielectric constant of 2.4 is used to plug the hole to obtain a dielectric filling layer
  • a low dielectric constant medium for example, a dielectric with a dielectric constant of 2.4
  • a dielectric filling layer for example, a dielectric with a dielectric constant of 2.4
  • the holes obtained by the second drilling are electroplated to obtain corresponding via holes;
  • the dielectric constant around the BGA differential via is reduced from 3.6 to 2.4, and the parasitic capacitance of the differential via is effectively reduced, which can increase the impedance of the differential via and improve the continuous impedance of the system link. Sex.
  • a laser blind hole can be used, and the via structure provided in this embodiment can effectively improve the laser blind hole drilling performance.
  • the via structure provided in this embodiment can effectively improve the laser blind hole drilling performance. For example, suppose the thickness of the circuit board body is 3mm, the BGA differential via hole diameter is 0.25mm, the medium of the circuit board body is the medium M4S, the dielectric constant is 3.6, and the signal is changed from the TOP layer to the L3 layer.
  • the formation process of a via structure includes:
  • a low dielectric constant medium eg, a dielectric with a dielectric constant of 2.0
  • a dielectric filling layer e.g, a dielectric with a dielectric constant of 2.0
  • laser drilling is performed from the TOP downward (that is, the second drilling) to the L3 layer, and then the holes obtained by the laser drilling are electroplated to form a hole wall as a conductive layer.
  • the dielectric constant around the laser blind hole of the high-density plate is reduced from 3.6 to 2.0 in the above embodiment, and the parasitic capacitance of the via is effectively reduced, which can increase the via impedance and improve the link impedance continuity.
  • the via structure provided in this embodiment is not limited to the application scenarios of the above examples. And it can be flexibly combined with other structures that can increase the resistance of the via and can be combined, such as, but not limited to, a certain degree of expansion and hollowing of the anti-pad of the via, or a reduction of the via to a certain extent Aperture, to further increase the impedance of the via, to make it closer to the impedance of the transmission line, and effectively improve the impedance continuity of the system link.
  • communication media generally contains computer readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium. Therefore, the present invention is not limited to any specific combination of hardware and software.

Abstract

一种电路板、设备及过孔结构的形成方法，在电路板的电路板主体(10)上所形成的过孔结构包括在电路板主体(10)内由导电层围合形成的孔(12)，导电层构成孔(12)的孔壁(11)，且在该孔(12)的孔壁(11)的至少一部分与电路板主体(10)之间设置有介电常数小于电路板主体(10)的介电常数的介质填充层(13)，从而降低过孔的寄生电容，提升过孔的阻抗，使其与传输线的阻抗更为接近，提升了系统链路的阻抗连续性。

Description

电路板、设备及过孔结构的形成方法 技术领域
本发明实施例涉及但不限于电路板领域，具体的，涉及但不限于一种电路板、设备及一种过孔结构的形成方法。
背景技术
目前系统容量以及信号速率越来越高，并且PCB(Printed Circuit Board，印制电路板)设计的密度随之增加，PCB的板厚和层数也增加，对信号完整性的要求也比以前更加严格。过孔作为高速、高密设计中必然会采用的一种结构，其性能直接影响高速、高密产品的性能。衡量过孔性能的其中一个重要指标就是阻抗连续性，过孔的阻抗一般都要比与之相连的PCB传输线特性阻抗要小很多，造成整个链路阻抗连续性较差，引起信号完整性问题。
过孔的阻抗与过孔的寄生电容和寄生电感有关系，寄生电容越大，过孔阻抗越小，寄生电感越大，过孔阻抗越大。为了提升过孔的阻抗，相关做法是对过孔的反焊盘进行一定程度的扩大挖空，但是实际的挖空大小不能无限制，否则会影响信号参考平面的完整性，引起其他方面的信号完整性问题，而且挖空尺寸到一定程度后，对于提升过孔的阻抗作用已达到一个瓶颈。相关做法中的另一种做法则是减小过孔的孔径，因为过孔孔径越小，寄生电容也会减小，过孔阻抗越大，进而系统链路的阻抗连续性就越好。
但是随着系统容量的增加，PCB板会越来越厚，而影响PCB加工难度的关键指标之一厚径比(即板厚和过孔直径的比值)会随着孔径的减小而变大。所以小孔设计的加工难度较大，影响PCB成品率，最终影响产品成本和可靠性，甚至因为厚径比太大导致PCB加工失败而报废。因此如何有效的提升过孔阻抗是目前急需解决的一个技术问题。
发明内容
本发明实施例提供的一种电路板、设备及过孔结构的形成方法，主要解决的技术问题是：如何提升过孔的阻抗。
为解决上述技术问题，本发明实施例提供一种电路板，包括多层结构的电路板主体，以及设置于所述电路板主体上的过孔结构，所述过孔结构包括在所述电路板主体内由导电层围合形成的孔，所述导电层构成所述孔的孔壁；所述过孔结构还包括介质填充层，至少部分所述孔壁与所述电路板主体之间设置有所述介质填充层，所述介质填充层的介电常数小于所述电路板主体的介电常数。
为解决上述技术问题，本发明实施例还提供一种设备，包括设备主体和上所述的电路板，所述电路板设置于所述设备主体上。
为解决上述技术问题，本发明实施例还提供一种过孔结构的形成方法，包括：
在多层结构的电路板主体上形成第一孔；
在所述第一孔内填充介质形成介质，所述介质的介电常数小于所述电路板主体的介电常数；
在所述第一孔内的介质区域内开设贯穿所述介质的第二孔，所述第二孔的孔径小于所述第一孔的孔径，开设了所述第二孔的介质形成为介质填充层；
在所述第二孔的孔壁上形成导电层，以获得过孔结构，其中，所述导电层围合形成孔，所述导电层构成所述孔的孔壁。
本发明的有益效果是：
根据本发明实施例提供的电路板、设备及过孔结构的形成方法，在电路板的电路板主体上所形成的过孔结构包括在电路板主体内由导电层围合形成的孔，导电层构成孔的孔壁，且在该孔的至少部分孔壁与电路板主体之间设置有介电常数小于电路板主体介电常数的介质填充层，也即在某些实施过程中可使得过孔周围介质的介电常数小于电路板主体的介电常数，从而降低过孔的寄生电容，提升过孔的阻抗，使其与传输线的阻抗更为接近，有效提升了系统链路的阻抗连续性。
本发明其他特征和相应的有益效果在说明书的后面部分进行阐 述说明，且应当理解，至少部分有益效果从本发明说明书中的记载变的显而易见。
附图说明
图1为本发明实施例一的电路板结构示意图一；
图2为本发明实施例一的电路板结构示意图二；
图3为本发明实施例一的电路板结构示意图三；
图4为本发明实施例一的电路板结构示意图四；
图5为本发明实施例一的电路板结构示意图五；
图6为本发明实施例二的过孔形成方法流程示意图；
图7为本发明实施例二的第一次开孔剖面结构示意图；
图8为本发明实施例二的第一次开孔俯视示意图；
图9为本发明实施例二的填充介质后的剖面结构示意图；
图10为本发明实施例二的填充介质后的俯视示意图；
图11为本发明实施例二的第二次开孔剖面结构示意图；
图12为本发明实施例二的第二次开孔俯视示意图；
图13为本发明实施例二的另一第二次开孔剖面结构示意图；
图14为本发明实施例二的另一第二次开孔俯视示意图；
图15为本发明实施例二的形成导电层后的剖面结构示意图；
图16为本发明实施例二的形成导电层后的俯视示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本发明实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
至少为了提升电路板上过孔的阻抗，使其与电路板上传输线的阻抗更为接近，以提升系统链路的阻抗连续性；本实施例提供一种电路板，该电路板上设置有过孔结构，该过孔结构包括在电路板主体内 由导电层围合形成的孔，导电层构成该孔的孔壁(该孔和孔壁构成过程)，且在该孔的至少部分孔壁与电路板主体之间设置有介电常数小于电路板主体介电常数的介质填充层，也即在电路板主体上所形成的过孔与电路板主体之间，设置有介电常数小于电路板主体自身介电常数的介质填充层，以使得过孔周围介质的介电常数小于电路板主体的介电常数，从而降低过孔的寄生电容。其中，过孔的寄生电容的一种计算方式如下面的公式(1)所示：
Figure PCTCN2019108411-appb-000001
上述公式(1)中，其中C表示过孔的寄生电容，T表示电路板主体的厚度，D 2表示过孔的反焊盘直径，D 1代表焊盘直径，ε r代表电路板主体板材的介电常数。从公式(1)可知，过孔的寄生电容与电路板主体板材的介电常数成正比，因此本实施例通过在过孔与电路板主体之间设置介电常数小于电路板主体自身的介电常数的介质填充层，相对现有过孔周围都为电路板主体材质的结构，可以减小过孔周围介质的介电常数，也即减小ε r值，进而减小过孔的寄生电容C，增大过孔的阻抗，提升系统链路的阻抗连续性。
本实施例提供的一种示例的电路板结构参见图1所示，其包括多层结构的电路板主体10，且假设图1中最上面的一层为电路板主体10的顶层，最下面一层为电路板主体10的底层；在电路板主体10上形成有过孔结构，该过孔结构包括在电路板主体10内由导电层围合形成的孔12，此时的导电层构成孔12的孔壁11(孔12和孔壁11构成本实施例中的过孔)，所述过孔结构还包括介质填充层13，孔壁11的至少部分区域与电路板主体10之间设置有介质填充层13，介质填充层13的介电常数小于电路板主体10的介电常数。
应当理解的是，本实施例中介质填充层13可以由介电常数比电路板主体10介电常数小的单种材质的介质构成；也可以由介电常数比电路板主体10的介电常数小的多种材质的介质构成。且具体采用的介质的介电常数的大小以及具体介质的材质可根据系统灵活选择，例如该介质包括但不限于树脂，且当介质为树脂时，该介质包括但不 限于聚乙烯、苯并环丁烯、聚四氟乙烯(或称特氟纶)中的至少一种。介质的介电常数也可灵活选择，只要比电路板主体10的介电常数小或只要满足当前对过孔阻抗的需求即可。
在本实施例中，导电层围合形成孔12的导电层，也即孔12的孔壁11所采用的导电材质。形成孔壁11的具体的工艺也可以灵活选择，例如包括但不限于通各种镀金属的工艺(例如包括但不限于电镀)形成孔壁11。
应当理解的是，本实施例中孔12的横截面的形状包括但不限于圆形，根据具体应用需求可以灵活设定，例如在某些应用场景下将孔12的横截面设置为椭圆形或其他可满足需求的形状。
本实施例中，孔壁11的至少部分区域与电路板主体10之间设置介质填充层13。包括在一些示例(例如，参见图3)中，在整个孔壁11与电路板主体10之间设置介质填充层13。也可如图1和图2中所示，仅在孔壁11的部分区域与电路板主体10之间设置介质填充层13。可根据需求和具体实施工艺灵活选择具体采用哪种设置方式。
例如，参见图1所示，在一种示例中，电路板主体10的多层结构包括与所述过孔结构相应的目标信号层101。孔12的下端沿电路板主体10的厚度方向在电路板主体10内延伸，并延伸至电路板主体10内相应的目标信号层101；孔12的孔壁11上位于相应目标信号层内101的部分的至少一部分与目标信号层101直接接触，也即孔12的孔壁11在目标信号层内101部分中，至少部分与目标信号层101之间无介质填充层13，以实现与对应目标信号层101之间的电连接。在图1所示的示例中，孔12的孔壁11在相应的目标信号层101内的部分全部与相应的目标信号层101之间无介质填充层13，也即直接与相应的目标信号层101接触。孔12的孔壁上在目标信号层101之外部分与电路板主体10之间则设置有介质填充层13。
又例如，在一种示例中，参见图2所示，孔12的孔壁11上，位于相应的目标信号层101内的部分的上部与目标信号层101之间设置有介质填充层13，孔12的孔壁11上，位于相应的目标信号层101内的部分的下部与目标信号层101之间无介质填充层13，且孔12的 孔壁11上，位于相应的目标信号层101之外的部分与电路板主体10之间则设置有介质填充层13。
图1和图2中示例的介质填充层13的设置方式，在电路板主体10上开孔设置介质填充层13时，由于所需开的孔比一般的过孔孔径大，因此开孔时不延伸至目标信号层101或仅延伸至目标信号层101的一部分而不贯穿目标信号层101，例如延伸至目标信号层101内并位于该目标信号层101内的对应目标线路之上，以避免对目标信号层101上的线路或焊盘的破坏，从而保证电路板的可靠性。
在本实施例中，孔12的上端与孔12的下端相对，孔12的上端可沿电路板主体10的厚度反向朝向电路板主体10的顶层方向或底层方向延伸。也即本实施例中的过孔可为从电路板主体10的顶层(即TOP层)向电路板主体内相应的目标信号层开设，也可从电路板主体10的底层(即BOT层)向电路板主体10内相应的目标信号层开设，例如图4所示则为从电路板主体10的底层(即BOT层)向电路板主体10内相应的目标信号层开设，孔12的上端则位于电路板主体10的底层。
应当理解的是，本实施例中，孔的下端是指在电路板主体10上开孔时，向电路板主体10内部延伸的一端，孔的上端则是与该下端相对的另一端。例如，在一种示例中，当从电路板主体10的顶层向下(即向电路板主体10内部)开孔时，则得到的孔的下端则是位于电路板主体10内部的一端，孔的上端则是位于电路板主体10顶层上的一端。又例如，在一种示例中，当从电路板主体10的底层向上(即向电路板主体10内部)开孔时，则得到的孔的下端是位于电路板主体10内部的一端，孔的上端则是位于电路板主体10底层上的一端。
另外，应当理解的是，在一些示例中，孔12的上端和下端可位于电路板主体10中需要连接的两层信号层中，用于将这两层信号层中相应的线路进行连接。这两层信号层有可能都位于电路板主体10内部，也可能一层位于电路主体10的内部，另一层为电路板主体10的顶层或底层等。例如参见图5所示，当两层信号层都位于电路板主体10的内部时，可在电路板主体10的内部形成本实施例提供的过孔 结构，图5所示的过孔结构可称为掩埋式过孔。
应当理解的是，本实施例中在电路板主体10上所需设置的过孔结构的个数以及各过孔之间的距离、尺寸大小关系可根据具体的系统需求灵活设定，例如可以设置1个过孔结构，也可根据具体需求设置两个及两个以上的过孔结构，例如可设置两个用于差分器件应用场景的过孔结构，也可设置3个或3个以上的过孔结构以适用于相应的应用场景需求。且在本实施例中，在电路板主体10上设置有至少两个过孔结构时，可以其中一部分过过孔结构用本实施例提供的过孔结构，剩余过孔则采用其他的过孔结构。且应当理解的是，本实施例中各过孔的反焊盘结构则可以采用各种反焊盘结构，在本实施例中对其不做任何限制。因此，本实施例中在电路板主体10上所形成的上述过孔结构可适用于单端信号过孔，也可适用于差分信号过孔的情况。且所使用的过孔应用场景包括但不限于BGA(Ball Grid Array，焊球阵列封装)过孔、压接连接器过孔、交流耦合电容扇出过孔、芯片矩形焊盘扇出过孔、焊接连接器焊盘扇出过孔等。
另外，应当理解的是，本实施例提供的过孔结构不仅适用于通孔，也适用于包括但不限于激光盲孔、机械盲孔、埋孔、POFV(Plating Over Filled Via，盘中孔)等。
本实施例还提供了一种设备，该设备可以是各种需采用具有过孔结构的电路板的设备，该设备包括设备主体和如上所示例的电路板，该电路板设置于设备主体上。
本实施例提供的过孔结构可在孔与电路板主体之间填充介电常数小于电路板主体的介质，进而减小过孔周围介质的介电常数，从而降低过孔的寄生电容，提升过孔的阻抗，使其与传输线的阻抗更为接近，有效提升了系统链路的阻抗连续性。且应当理解的是，可选地，本实施例提供的过孔结构可与其他能提升过孔阻抗且能结合的结构组合使用，以提升增大过孔阻抗的效果，例如包括但不限于对过孔的反焊盘进行一定程度的扩大挖空，或在一定程度上减小过孔的孔径。
实施例二：
为了便于理解，本实施例结合一种过孔结构的形成方法进行示 例说明。通过本实施例所提供的过孔结构的形成方法可得到但不限于上述实施例一种所示例的过孔结构。其中一种过孔结构的形成方法的示例过程参见图6所示，包括：
S601：在多层结构的电路板主体上形成第一孔。
本步骤中在电路板主体上形成的第一孔是为了设置介电常数小于电路板主体介电常数的介质，以形成介质填充层。第一孔的具体开孔深度和孔径大小可灵活设定，第一孔的具体开设方式也可采用各种开孔方式，例如包括但不限于通过钻孔的方式实现。
S602：在第一孔内填充介质。
本步骤中在第一孔内填充介质的方式也可根据具体应用场景灵活设定，例如包括但不限于采用注塑、沉淀、模压等工艺实现介质的填充。
另外，应当理解的是，在工艺支持介质填充层与电路板主体的各层一体成形时，也可采用这种一体成形工艺在电路板主板相应层的相应区域形成介质填充层。本实施例中介质填充层可以由介电常数比电路板主体介电常数小的单种材质的介质构成；也可以由介电常数比电路板主体的介电常数小的多种材质的介质构成。例如采用介电常数小于或等于2.6、2.5、2.4中任意一者的介质。又例如该介质包括但不限于树脂
S603：在第一孔内的介质区域内开设贯穿介质的第二孔，开设了第二过孔的介质形成为介质填充层。
本实施例中第二孔与第一孔可为同心孔，也可不为同心孔，且第二孔的开孔深度大于等于第一孔，第二孔的孔径小于第一孔的孔径。
S604：在第二孔的孔壁上形成导电层，以获得过孔结构，其中，所述导电层围合形成孔，所述导电层构成孔的孔壁。
该步骤中的导电层以及导电层所围合成的孔(导电层构成该孔的孔壁)即构成本实施例中的过孔，且该导电层的形成工艺也可灵活选用。通过该导电层可将需要利用过孔实现连接的各信号层上相应的线路进行连接。
通过图6所示的过孔形成方法所得到的过孔结构，在过孔与电路板主体之间形成有介电常数小于电路板主体的介质填充层，进而减小过孔周围介质的介电常数，从而降低过孔的寄生电容，提升过孔的阻抗，使其与传输线的阻抗更为接近，有效提升了系统链路的阻抗连续性。且本实施例提供的过孔结构的形成方法还至少具备以下优点：
更利于电路板(例如包括但不限于PCB)的设计和加工：相对相关通过减小过孔孔径来提升过孔阻抗的做法，由于PCB的厚径比越来越大，加工难度也越来越大，成本和成品率难以得到保证的问题，本实施例通过减小过孔周围介质介电常数的方法来增加过孔阻抗，不需要通过减小过孔孔径来提升过孔阻抗，大大降低了加工难度，降低加工成本和提升了成品率。
利于提升阻抗的连续性：过孔周围介质介电常数减小，以此降低过孔的寄生电容，从而使得过孔的阻抗增大，使其与目标线路的阻抗更为接近，可以有效提升系统链路的阻抗连续性。
如上所示，本实施例中第二孔的开孔深度可大于或等于第一孔。例如在一种示例中，第一孔的下端沿电路板主体的厚度方向向电路板主体内延伸，并延伸至电路板主体内相应的目标信号层的上一层(当然也可是目标信号层之上的其它层，具体可根据需求灵活设定)，或延伸至目标信号层内并位于对应目标线路之上。
第二孔的下端向电路板主体内延伸，并延伸至目标信号层。
为了便于理解，本实施例下面结合一个完成的制作过程进行示例说明。
参见图7和图8，假设电路板主体10包括n层，通过钻孔的方式形成第一孔或第二孔。假设目标信号层101在Lm2层。在本示例中，第一次钻孔从电路板主体10的顶层TOP层钻至第m1(1<m1<n)层(即Lm1层)得到第一孔14，第一孔14直径为Ds1。
参见图9和10，在第一孔内设置介质，例如采用低介电常数的介质塞第一孔14，此处的低介电常数是指介电常数低于电路板主体10的介电常数。例如当电路板主体10为玻璃纤维材质时，则介质填充层采用介电常数低于玻璃纤维介电常数的材质，例如包括但不限于 树脂。
参见图11和12，进行第二次钻孔，第二次钻孔位于第一孔内部，从电路板主体10的顶层TOP层钻至m2(m1<m2<n)层得到第二孔15，第二孔15的直径为Ds2，且Ds2小于Ds1。第一孔内填充的介质被钻出第二空15后，形成为介质填充层13。
本示例中，第二次钻孔位于一次过孔内部，不限于从第一孔的中心钻得到与第一孔同心的第二孔15，还可以是任意位置。例如参见图13和14，第二孔15也可位于第一孔14内相对第一孔14的任意偏心位置。
参见图15和16，在第二孔15内通过电镀等工艺形成导电层11，导电层11围合形成孔12。
为了便于理解，本实施例下面以几种具体的应用场景，对过孔结构的形成过程进行示例说明。
场景一：高速板连接器差分压接孔
很多设备都会用到高速连接器，在一些应用示例中，相关设计一般保证压接过孔的阻抗在80～85欧姆之间，若对于100欧姆的系统来讲其是不连续的，会增加链路的不连续性。尤其是对于400G等应用场景，信号速率更高，信号沿更陡，那么对过孔阻抗要求更高。对于一些示例型号的连接器，差分过孔的钻孔直径为0.4mm，反焊盘直径1.2mm，假设本应用场景中PCB层数为24层，采用M6G板材，介电常数为3.5，目标信号层在L10层。该应用场景的一种过孔结构的形成过程包括：
将TOP层至L9层的介质按pp(pre-pregnant，半固化板)/core(内芯板)/pp的顺序压合为第一子板(也即电路板主体的一部分)，在第一子板上进行第一次钻孔，钻孔直径Ds1为1.0mm，高速连接器采用差分信号，所以在第一子板上钻孔数量为2个，设孔中心距1.2mm；
第一子板钻孔完后采用低介电常数介质(例如介电常数为2.6的介质)塞孔得到介质填充层；
将BOTTOM层至L12层的介质按pp/core/pp的顺序压合为第二 子板，在第二子板上进行一次钻孔，钻孔直径Ds1＝1.0mm，钻孔数量为2个，设孔中心距1.2mm；
第二子板钻孔完后采用低介电常数介质(例如介电常数为2.6的介质)塞孔得到介质填充层；
将第一子板、L10-L11层芯板和第二子板进行压合后，分别前面得到的孔内的介质填充层区域的钻孔中心进行二次钻孔，钻孔直径Ds2＝0.4mm；
然后对第二次钻孔得到的孔进行电镀得到相应的过孔；
在本应用场景中，采用上述实施方式后高速连接器差分过孔周围介质介电常数由3.5降低为2.6，差分过孔的寄生电容得到有效降低，从而可以提升差分过孔阻抗，改善系统链路阻抗连续性。
场景二：高速板BGA差分扇出过孔
高速芯片可以采用BGA封装方式，而BGA扇出过孔的阻抗连续性是影响系统链路阻抗连续性的重要因素。
记载在本应用场景中，电路板主体的厚度为3mm，BGA差分过孔钻孔直径0.2mm，电路板主体的介质为M6G，介电常数为3.5，目标信号层在L10层，该应用场景的一种过孔结构的形成过程包括：
将TOP层至L9层的介质按pp(pre-pregnant，半固化板)/core(内芯板)/pp的顺序压合为第一子板，在第一子板上进行第一次钻孔，钻孔的直径Ds1为0.7mm，高速芯片采用差分信号，所以钻孔数量为2个，假设孔中心距1mm；
第一子板钻孔完后采用低介电常数介质(例如介电常数为2.4的介质)塞孔得到介质填充层；
将BOTTOM层至L12层的介质按pp/core/pp的顺序压合为第二子板，在第二子板上进行一次钻孔，钻孔直径Ds1＝0.7mm，钻孔数量为2个，设孔中心距1mm；
第二子板钻孔完后采用低介电常数介质(例如介电常数为2.4的介质)塞孔得到介质填充层；
将第一子板、L10-L11层芯板和第二子板进行压合后，分别前面得到的孔内的介质填充层区域的钻孔中心进行二次钻孔，钻孔直径 Ds2＝0.2mm；
然后对第二次钻孔得到的孔进行电镀得到相应的过孔；
在本应用场景中，采用上述实施方式后BGA差分过孔周围介质介电常数由3.6降低为2.4，差分过孔的寄生电容得到有效降低，从而可以提升差分过孔阻抗，改善系统链路阻抗连续性。
场景三：高密板激光盲孔
在高密板上为了不占用内层走线空间，可以采用激光盲孔，利用本实施例提供而定过孔结构则可以有效提升激光盲孔钻孔性能。例如，假设电路板主体的厚度为3mm，BGA差分过孔钻孔直径0.25mm，电路板主体的介质为介质M4S，介电常数为3.6，信号由TOP层换至L3层情况，该应用场景的一种过孔结构的形成过程包括：
将TOP层至L3层的介质按pp/core的顺序压合为第一子板，压合后可进行机械钻孔(即第一次钻孔)，此次钻孔钻破L2层不钻破L3层；
第一子板钻孔完后采用低介电常数介质(例如介电常数为2.0的介质)塞孔得到介质填充层；
将L4层至BOTTOM层的介质按pp/core/pp的顺序压合为第二子板；
将第一子板和第二子板进行二次压合；
在介质填充层区域内从TOP向下进行激光钻孔(即第二次钻孔)，钻至L3层，然后对激光钻孔得到孔进行电镀形成作为导电层的孔壁。
在本应用场景中，采用上述实施方式高密板激光盲孔周围介质介电常数由3.6降低为2.0，过孔的寄生电容得到有效降低，从而可以提升过孔阻抗，改善链路阻抗连续性。
应当理解的是，本实施例提供的过孔结构并不限于应用于上述示例的几种应用场景。且其可灵活的结合其他可提升过孔阻抗且能结合的结构组合使用，例如包括但不限于对过孔的反焊盘进行一定程度的扩大挖空，或在一定程度上减小过孔的孔径，以进一步增大过孔阻抗，使其与传输线的阻抗更为接近，有效提升了系统链路的阻抗连续 性。
可见，本领域的技术人员应该明白，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件(可以用计算装置可执行的计算机程序代码来实现)、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、计算机程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。所以，本发明不限制于任何特定的硬件和软件结合。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (11)

  1. 一种电路板，包括多层结构的电路板主体(10)，以及设置于所述电路板主体(10)上的过孔结构，所述过孔结构包括在所述电路板主体(10)内由导电层围合形成的孔(12)，所述导电层构成所述孔(12)的孔壁(11)；所述过孔结构还包括介质填充层(13)，至少部分所述孔壁(11)与所述电路板主体(10)之间设置有所述介质填充层(13)，所述介质填充层(13)的介电常数小于所述电路板主体(10)的介电常数。
  2. 如权利要求1所述的电路板，其中，所述电路板主体(10)的多层结构包括与所述过孔结构相应的目标信号层(101)，所述孔(12)位于所述电路板主体(10)内的一端为下端，所述孔(12)的下端沿所述电路板主体(10)的厚度方向在所述电路板主体(10)内延伸，并延伸至所述电路板主体(10)内相应的目标信号层(101)；所述孔(12)的孔壁(11)上位于相应的目标信号层(101)内的部分的至少一部分与所述目标信号层(101)直接接触。
  3. 如权利要求2所述的电路板，其中，所述孔(12)的孔壁(11)上位于相应的目标信号层(101)之外的部分与所述电路板主体(10)之间设置有所述介质填充层(13)。
  4. 如权利要求2或3所述的电路板，其中，所述孔(12)的孔壁(11)上位于相应的目标信号层(101)内的部分全部与相应的目标信号层(101)直接接触。
  5. 如权利要求2或3所述的电路板，其中，所述孔(12)的上端沿所述电路板的厚度方向朝向所述电路本主体的顶层或底层延伸。
  6. 如权利要求1-3任一项所述的电路板，其中，所述电路板主 体(10)上设置有至少两个所述过孔结构。
  7. 如权利要求1至3任一项所述的电路板，其中，所述介质填充层(13)由树脂制成。
  8. 一种设备，包括设备主体和如权利要求1-7任一项所述的电路板，所述电路板设置于所述设备主体上。
  9. 一种过孔结构的形成方法，包括：
    在多层结构的电路板主体(10)上形成第一孔；
    在所述第一孔内填充介质，所述介质的介电常数小于所述电路板主体(10)的介电常数；
    在所述第一孔内的介质区域内开设贯穿所述介质的第二孔，所述第二孔的孔径小于所述第一孔的孔径，开设了所述第二孔的介质形成为介质填充层(13)；
    在所述第二孔的孔壁上形成导电层，以获得过孔结构，其中，所述导电层围合形成孔(12)，所述导电层构成所述孔(12)的孔壁(11)。
  10. 如权利要求8所述的过孔结构的形成方法，其中，所述电路板主体(10)的多层结构包括与所述过孔结构相应的目标信号层(101)，所述第一孔的下端沿所述电路板主体(10)的厚度方向向所述电路板主体(10)内延伸，并延伸至所述电路板主体(10)内相应的目标信号层(101)的上一层，或延伸至所述目标信号层(101)内并位于对应目标线路之上；
    所述第二孔的下端向所述电路板主体(10)内延伸，并延伸至所述目标信号层(101)。
  11. 如权利要求8或9所述的过孔结构的形成方法，其中，所述介质包括树脂。
PCT/CN2019/108411 2018-10-08 2019-09-27 电路板、设备及过孔结构的形成方法 WO2020073823A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2021517629A JP7178764B2 (ja) 2018-10-08 2019-09-27 回路基板、デバイスおよびバイアホール構造の形成方法
US17/282,410 US11457529B2 (en) 2018-10-08 2019-09-27 Circuit board, apparatus and method for forming via hole structure
EP19871140.0A EP3866571A4 (en) 2018-10-08 2019-09-27 PRINTED CIRCUIT BOARD, DEVICE AND METHOD FOR FORMING A THROUGH-HOLE STRUCTURE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811169550.0A CN111010797A (zh) 2018-10-08 2018-10-08 电路板、设备及过孔形成方法
CN201811169550.0 2018-10-08

Publications (1)

Publication Number Publication Date
WO2020073823A1 true WO2020073823A1 (zh) 2020-04-16

Family

ID=70111640

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/108411 WO2020073823A1 (zh) 2018-10-08 2019-09-27 电路板、设备及过孔结构的形成方法

Country Status (5)

Country Link
US (1) US11457529B2 (zh)
EP (1) EP3866571A4 (zh)
JP (1) JP7178764B2 (zh)
CN (1) CN111010797A (zh)
WO (1) WO2020073823A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113325526A (zh) * 2021-05-26 2021-08-31 青岛海信宽带多媒体技术有限公司 一种光模块
CN114269071A (zh) * 2021-12-08 2022-04-01 江苏普诺威电子股份有限公司 多层板的通孔填孔制作工艺
CN114269071B (zh) * 2021-12-08 2024-04-26 江苏普诺威电子股份有限公司 多层板的通孔填孔制作工艺

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114501771A (zh) * 2020-10-27 2022-05-13 南京中兴软件有限责任公司 一种印制电路板及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064869A (ja) * 2007-09-05 2009-03-26 Toppan Printing Co Ltd 多層配線板及びその製造方法
US20100326716A1 (en) * 2009-06-26 2010-12-30 Zhichao Zhang Core via for chip package and interconnect
CN102291929A (zh) * 2011-06-24 2011-12-21 福建星网锐捷网络有限公司 印刷电路板及控制印刷电路板上通孔结构的阻抗的方法
CN105764235A (zh) * 2014-12-15 2016-07-13 财团法人工业技术研究院 信号传输板及其制作方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335163A (en) * 1976-09-14 1978-04-01 Hitachi Chemical Co Ltd Method of producing printed circuit board substrate having through hole from metallic material
GB8320086D0 (en) * 1983-07-26 1983-08-24 Ciba Geigy Ag Spherical fused silica
US6204453B1 (en) * 1998-12-02 2001-03-20 International Business Machines Corporation Two signal one power plane circuit board
US5847327A (en) * 1996-11-08 1998-12-08 W.L. Gore & Associates, Inc. Dimensionally stable core for use in high density chip packages
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers
TW411737B (en) 1999-03-09 2000-11-11 Unimicron Technology Corp A 2-stage process to form micro via
KR101384035B1 (ko) * 1999-09-02 2014-04-09 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
KR100823767B1 (ko) * 1999-09-02 2008-04-21 이비덴 가부시키가이샤 프린트배선판 및 프린트배선판의 제조방법
US6541712B1 (en) * 2001-12-04 2003-04-01 Teradyhe, Inc. High speed multi-layer printed circuit board via
DE502004007114D1 (de) * 2003-09-29 2008-06-26 Bosch Gmbh Robert Härtbares Reaktionsharzsystem
TWI261046B (en) * 2004-10-08 2006-09-01 Ind Tech Res Inst Resin composition with low dielectric constant filler for high frequency substrate
US7470863B2 (en) * 2006-01-24 2008-12-30 International Business Machines Corporation Microelectronic device with mixed dielectric
TWI272886B (en) 2006-02-27 2007-02-01 Advanced Semiconductor Eng Substrate with multi-layer PTH and method for forming the multi-layer PTH
JP5125166B2 (ja) * 2007-03-27 2013-01-23 日本電気株式会社 多層配線基板及びその製造方法
US20080245555A1 (en) * 2007-04-04 2008-10-09 Ati Technologies Ulc Circuit substrate with plated through hole structure and method
US8440917B2 (en) * 2007-11-19 2013-05-14 International Business Machines Corporation Method and apparatus to reduce impedance discontinuity in packages
US20110163348A1 (en) * 2008-03-25 2011-07-07 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump
US8273995B2 (en) 2008-06-27 2012-09-25 Qualcomm Incorporated Concentric vias in electronic substrate
JP5170253B2 (ja) * 2008-11-20 2013-03-27 富士通株式会社 配線基板及び配線基板の製造方法
US8107254B2 (en) * 2008-11-20 2012-01-31 International Business Machines Corporation Integrating capacitors into vias of printed circuit boards
WO2010074121A1 (ja) * 2008-12-25 2010-07-01 三菱電機株式会社 プリント配線板の製造方法
US20110232953A1 (en) * 2010-03-29 2011-09-29 Kyocera Corporation Circuit board and structure using the same
JP5482546B2 (ja) * 2010-07-28 2014-05-07 富士通株式会社 プリント配線板、プリント配線板の製造方法及び電子機器
JP5606268B2 (ja) * 2010-10-27 2014-10-15 日本特殊陶業株式会社 多層配線基板の製造方法
JP2012195389A (ja) * 2011-03-15 2012-10-11 Fujitsu Ltd 配線基板、配線基板ユニット、電子装置、及び配線基板の製造方法
JP5895635B2 (ja) * 2012-03-16 2016-03-30 富士通株式会社 配線板の製造方法、配線板およびビアの構造
DE112013002916T5 (de) * 2013-06-27 2015-03-05 Intel IP Corporation Hochleitende, hochfrequente Durchkontaktierung für elektronische Anlagen
TWI488553B (zh) * 2013-07-08 2015-06-11 Boardtek Electronics Corp 電路板及其製造方法
TWI484876B (zh) * 2013-12-20 2015-05-11 Ind Tech Res Inst 具傳輸孔之電路板及其製造方法
JP6165640B2 (ja) 2014-01-10 2017-07-19 株式会社東芝 配線基板およびその製造方法
US9596768B2 (en) * 2014-03-04 2017-03-14 Qualcomm Incorporated Substrate with conductive vias
US10249943B2 (en) * 2014-06-18 2019-04-02 Massachusetts Institute Of Technology Printed circuit board assembly with foam dielectric material
MY191331A (en) 2016-12-30 2022-06-16 Intel Corp Substrate with gradiated dielectric for reducing impedance mismatch
WO2018175660A1 (en) 2017-03-21 2018-09-27 Sanmina Corporation Methods of forming blind vias for printed circuit boards

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064869A (ja) * 2007-09-05 2009-03-26 Toppan Printing Co Ltd 多層配線板及びその製造方法
US20100326716A1 (en) * 2009-06-26 2010-12-30 Zhichao Zhang Core via for chip package and interconnect
CN102291929A (zh) * 2011-06-24 2011-12-21 福建星网锐捷网络有限公司 印刷电路板及控制印刷电路板上通孔结构的阻抗的方法
CN105764235A (zh) * 2014-12-15 2016-07-13 财团法人工业技术研究院 信号传输板及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3866571A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113325526A (zh) * 2021-05-26 2021-08-31 青岛海信宽带多媒体技术有限公司 一种光模块
CN114269071A (zh) * 2021-12-08 2022-04-01 江苏普诺威电子股份有限公司 多层板的通孔填孔制作工艺
CN114269071B (zh) * 2021-12-08 2024-04-26 江苏普诺威电子股份有限公司 多层板的通孔填孔制作工艺

Also Published As

Publication number Publication date
JP7178764B2 (ja) 2022-11-28
EP3866571A4 (en) 2022-06-22
US11457529B2 (en) 2022-09-27
US20210392744A1 (en) 2021-12-16
CN111010797A (zh) 2020-04-14
JP2022502862A (ja) 2022-01-11
EP3866571A1 (en) 2021-08-18

Similar Documents

Publication Publication Date Title
US11800636B2 (en) Electronic substrate having differential coaxial vias
WO2020073823A1 (zh) 电路板、设备及过孔结构的形成方法
US8508947B2 (en) Flex cable and method for making the same
US20020017397A1 (en) Vialess printed circuit board
WO2019024813A1 (zh) 一种嵌入式基板
US20210227685A1 (en) Structure for circuit interconnects
US8723293B1 (en) Compensation network using an on-die compensation inductor
US20160066415A1 (en) Multilayer wiring board
US10743405B2 (en) Printed circuit board and display apparatus
CN109936912B (zh) 具有旁路电容的电子模块卡结构
US9949381B2 (en) Electronic device with at least one impedance-compensating inductor and related methods
TWI619302B (zh) 傳輸線的阻抗匹配架構
CN107734833A (zh) 一种优化高速信号过孔处回流路径的方法
CN208094898U (zh) 盘中孔式多层柔性pcb板
CN206260140U (zh) 软式印刷电路板与硬式印刷电路板焊接结构
US11690173B2 (en) Circuit board structure
US10332826B2 (en) Semiconductor device and method of manufacturing semiconductor device
CN206585832U (zh) Pcb板
CN105188254B (zh) Hdi十层板迭构
CN103730446A (zh) 基于刚柔结合印刷电路板三维封装结构的互连结构和制作方法
WO2021052327A1 (zh) 一种电路板
US20050168913A1 (en) Capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode
TWM553914U (zh) 用於高速傳輸之印刷電路板
US20230007778A1 (en) Adapter board, method for manufacturing the same and circuit board assembly using the same
US20240008177A1 (en) Vertical interconnect design for improved electrical performance

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19871140

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021517629

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019871140

Country of ref document: EP

Effective date: 20210510