JP5125166B2 - 多層配線基板及びその製造方法 - Google Patents
多層配線基板及びその製造方法 Download PDFInfo
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- JP5125166B2 JP5125166B2 JP2007081544A JP2007081544A JP5125166B2 JP 5125166 B2 JP5125166 B2 JP 5125166B2 JP 2007081544 A JP2007081544 A JP 2007081544A JP 2007081544 A JP2007081544 A JP 2007081544A JP 5125166 B2 JP5125166 B2 JP 5125166B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 238000000034 method Methods 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 18
- 230000000149 penetrating effect Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 229920001187 thermosetting polymer Polymers 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09809—Coaxial layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10545—Related components mounted on both sides of the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
多層配線基板の製造方法であって、
第1の絶縁層と、該第1の絶縁層の双方の面上に形成された一対の第2の絶縁層と、前記第1の絶縁層と前記第2の絶縁層との間に形成された内層配線パターンと、を有する積層体を形成する工程と、
前記積層体を貫通する第1のスルーホールを形成する工程と、
少なくとも前記第1のスルーホールの壁面に第1の導電層を形成する工程と、
前記第1のスルーホールよりも外径が大きく、内部に樹脂材料を充填するための一対の溝孔を、前記一対の第2の絶縁層の内部に前記第1のスルーホールにそれぞれ連通するように形成する工程と、
前記第1の導電層の内側と前記一対の溝孔の内部とに前記樹脂材料を充填し、絶縁プラグを形成する工程と、
前記第1の導電層の内径よりも外径が小さな第2のスルーホールを、前記絶縁プラグに形成する工程と、
前記第2のスルーホールの内部に第2の導電層を形成する工程と、を有することを特徴とする。
第1の絶縁層と、該第1の絶縁層の双方の面上に形成された一対の第2の絶縁層と、前記第1の絶縁層と前記第2の絶縁層との間に形成された内層配線パターンと、前記一対の第2の絶縁層上に形成された外層配線パターンとを有する積層体を備える多層配線基板であって、
前記第1の絶縁層及び内層配線パターンを貫通する第1のスルーホールの壁面に形成され、前記内層配線パターンを相互に接続する第1の貫通ビアと、
前記第1の貫通ビアの内部に形成され前記積層体を貫通する第2のスルーホール内に形成され、前記外層配線パターンを相互に接続する第2の貫通ビアと、
前記第1の貫通ビアと前記第2の貫通ビアとを絶縁する絶縁プラグであって、前記第1の絶縁層を貫通する部分が前記第1の貫通ビアの内側に形成され、前記一対の第2の絶縁層を貫通する部分が前記第1のスルーホールよりも直径が大きな一対の溝孔の内部に形成された絶縁プラグと、を備えることを特徴とする。
11:第1の絶縁層
12:第2の絶縁層
13:内層配線パターン
13a:導電層
14:外層配線パターン
14a:導電層
15:第1のスルーホール
16:第1の貫通ビア
16a:めっき導電層
17:溝孔
18:絶縁プラグ
19:第2のスルーホール
20:第2の貫通ビア
20a:めっき導電層
21:配線材料
22:積層体
31:ドリル
32:ルーティングドリル
33:ドリル
34:ドリル
40:パッケージ
41:多層配線基板
42〜45:電子部品
46:ビアホール
47:ビア
47a:めっき導電層
Claims (8)
- 多層配線基板の製造方法であって、
第1の絶縁層と、該第1の絶縁層の双方の面上に形成された一対の第2の絶縁層と、前記第1の絶縁層と前記第2の絶縁層との間に形成された内層配線パターンと、を有する積層体を形成する工程と、
前記積層体を貫通する第1のスルーホールを形成する工程と、
少なくとも前記第1のスルーホールの壁面に第1の導電層を形成する工程と、
前記第1のスルーホールよりも外径が大きく、内部に樹脂材料を充填するための一対の溝孔を、前記一対の第2の絶縁層の内部に前記第1のスルーホールにそれぞれ連通するように形成する工程と、
前記第1の導電層の内側と前記一対の溝孔の内部とに前記樹脂材料を充填し、絶縁プラグを形成する工程と、
前記第1の導電層の内径よりも外径が小さな第2のスルーホールを、前記絶縁プラグに形成する工程と、
前記第2のスルーホールの内部に第2の導電層を形成する工程と、を有することを特徴とする多層配線基板の製造方法。 - 前記積層体の形成工程が、前記第2の絶縁層を貫通するビアホールを形成する工程と、少なくとも前記ビアホールの壁面に前記内層配線パターンと前記第2の絶縁層上に形成された第3の導電層とを接続するビアを形成する工程とを有する、請求項1に記載の多層配線基板の製造方法。
- 前記絶縁プラグを熱硬化性樹脂で形成する、請求項1又は2に記載の多層配線基板の製造方法。
- 前記第1の導電層及び第2の導電層の少なくとも一方をめっき工法で形成する、請求項1〜3の何れか一に記載の多層配線基板の製造方法。
- 第1の絶縁層と、該第1の絶縁層の双方の面上に形成された一対の第2の絶縁層と、前記第1の絶縁層と前記第2の絶縁層との間に形成された内層配線パターンと、前記一対の第2の絶縁層上に形成された外層配線パターンとを有する積層体を備える多層配線基板であって、
前記第1の絶縁層及び内層配線パターンを貫通する第1のスルーホールの壁面に形成され、前記内層配線パターンを相互に接続する第1の貫通ビアと、
前記第1の貫通ビアの内部に形成され前記積層体を貫通する第2のスルーホール内に形成され、前記外層配線パターンを相互に接続する第2の貫通ビアと、
前記第1の貫通ビアと前記第2の貫通ビアとを絶縁する絶縁プラグであって、前記第1の絶縁層を貫通する部分が前記第1の貫通ビアの内側に形成され、前記一対の第2の絶縁層を貫通する部分が前記第1のスルーホールよりも直径が大きな一対の溝孔の内部に形成された絶縁プラグと、を備えることを特徴とする多層配線基板。 - 前記第2の絶縁層を貫通し、前記外層配線パターンと前記内層配線パターンとを接続する第3のスルーホールを更に有する、請求項5に記載の多層配線基板。
- 前記絶縁プラグが、熱硬化性樹脂からなる、請求項5又は6に記載の多層配線基板。
- 前記第1の貫通ビア及び第2の貫通ビアの少なくとも一方がめっき層で形成されている、請求項5〜7の何れか一に記載の多層配線基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007081544A JP5125166B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板及びその製造方法 |
US12/056,705 US20080236881A1 (en) | 2007-03-27 | 2008-03-27 | Multilayer printed wiring board and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007081544A JP5125166B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008244083A JP2008244083A (ja) | 2008-10-09 |
JP5125166B2 true JP5125166B2 (ja) | 2013-01-23 |
Family
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JP2007081544A Expired - Fee Related JP5125166B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板及びその製造方法 |
Country Status (2)
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US (1) | US20080236881A1 (ja) |
JP (1) | JP5125166B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8729176B2 (en) | 2006-09-06 | 2014-05-20 | Keio University | Polyricinoleate composition and process for producing the same |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5895635B2 (ja) * | 2012-03-16 | 2016-03-30 | 富士通株式会社 | 配線板の製造方法、配線板およびビアの構造 |
CN103857207B (zh) * | 2012-11-30 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | 电路板及其制作方法 |
WO2015116093A1 (en) * | 2014-01-30 | 2015-08-06 | Hewlett-Packard Development Company, L.P. | Printed circuit board with co-axial vias |
US9426891B2 (en) * | 2014-11-21 | 2016-08-23 | Advanced Semiconductor Engineering, Inc. | Circuit board with embedded passive component and manufacturing method thereof |
JP6634696B2 (ja) * | 2015-04-20 | 2020-01-22 | 富士通株式会社 | コンデンサを有するプリント基板の製造方法 |
CN106793534A (zh) * | 2015-11-20 | 2017-05-31 | 富泰华工业(深圳)有限公司 | 电路板钢网印刷方法 |
US9807867B2 (en) * | 2016-02-04 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method of manufacturing the same |
US10446356B2 (en) | 2016-10-13 | 2019-10-15 | Sanmina Corporation | Multilayer printed circuit board via hole registration and accuracy |
CN106653318B (zh) * | 2017-02-28 | 2019-06-18 | 华为技术有限公司 | 电感器件和交错并联直流变换器 |
CN111010797A (zh) * | 2018-10-08 | 2020-04-14 | 中兴通讯股份有限公司 | 电路板、设备及过孔形成方法 |
CN109661107B (zh) * | 2018-11-29 | 2022-05-17 | 广东骏亚电子科技股份有限公司 | Pcb树脂塞孔工艺 |
CN111182743B (zh) * | 2020-01-06 | 2021-06-04 | 江门崇达电路技术有限公司 | 一种陶瓷基线路板的制作方法 |
CN115116855A (zh) * | 2021-03-18 | 2022-09-27 | 澜起科技股份有限公司 | 封装基板结构及其制作方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53100464A (en) * | 1977-02-15 | 1978-09-01 | Matsushita Electric Works Ltd | Multilayer printed circuit board and method of producing same |
US4706167A (en) * | 1983-11-10 | 1987-11-10 | Telemark Co., Inc. | Circuit wiring disposed on solder mask coating |
JPH0828581B2 (ja) * | 1993-05-31 | 1996-03-21 | 日本電気株式会社 | 多層印刷配線板およびその製造方法 |
US5421083A (en) * | 1994-04-01 | 1995-06-06 | Motorola, Inc. | Method of manufacturing a circuit carrying substrate having coaxial via holes |
US5949030A (en) * | 1997-11-14 | 1999-09-07 | International Business Machines Corporation | Vias and method for making the same in organic board and chip carriers |
TW411737B (en) * | 1999-03-09 | 2000-11-11 | Unimicron Technology Corp | A 2-stage process to form micro via |
-
2007
- 2007-03-27 JP JP2007081544A patent/JP5125166B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-27 US US12/056,705 patent/US20080236881A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8729176B2 (en) | 2006-09-06 | 2014-05-20 | Keio University | Polyricinoleate composition and process for producing the same |
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US20080236881A1 (en) | 2008-10-02 |
JP2008244083A (ja) | 2008-10-09 |
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