WO2019024813A1 - 一种嵌入式基板 - Google Patents

一种嵌入式基板 Download PDF

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Publication number
WO2019024813A1
WO2019024813A1 PCT/CN2018/097605 CN2018097605W WO2019024813A1 WO 2019024813 A1 WO2019024813 A1 WO 2019024813A1 CN 2018097605 W CN2018097605 W CN 2018097605W WO 2019024813 A1 WO2019024813 A1 WO 2019024813A1
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Prior art keywords
substrate
chamber
electronic device
chambers
embedded
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PCT/CN2018/097605
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English (en)
French (fr)
Inventor
彭浩
廖小景
王军鹤
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华为技术有限公司
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Publication of WO2019024813A1 publication Critical patent/WO2019024813A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular, to an embedded substrate.
  • FIG. 1 is a schematic cross-sectional view of a conventional embedded substrate, which includes a substrate 10 and a first chip packaged in the substrate 10. 20 and a second chip 30, wherein a plurality of chambers 11 are formed on the substrate 10, and each of the chambers 11 is filled with a first chip 20 or a second chip 30 by a resin 40, and pads of the first chip 20 21.
  • the front pad 31 and the back pad 32 of the second chip 30 are both connected to the conductive layer 50 to achieve connection with the outer layer circuit.
  • the front pad 31 and the back pad 32 of the second chip 30 may also be electrically conductive.
  • Layer 50 implements a two-sided interconnect.
  • the conventional embedded substrate shown in FIG. 1 is generally manufactured by forming one or more chambers 11 by etching on the substrate, and inserting a corresponding first chip 20 or second chip 30 in each of the chambers 11, and then The first chip 20 and the second chip 30 are sealed and double-sided pressed using a resin 40, and then the conductive layer 50 is formed by laser drilling and hole-filling copper plating.
  • the embedded substrate shown in FIG. 1 saves the chip mounting space reserved on the surface of the substrate, thereby reducing the package volume of all the chips and improving the package integration degree of the chip.
  • the embedding of the structure is In the substrate, each chip needs to occupy one chamber, which results in a larger area occupied by all the chips.
  • the second chip is caused.
  • the pad blind hole height of 30 is greater than the pad blind hole height of the first chip 20.
  • the pad blind hole of the second chip 30 cannot be completely filled, so that the embedded substrate
  • the final product produces the bubble 01 and the pad recess 02 shown in FIG. 1, which reduces the reliability of the embedded substrate. Because the embedded substrate in the prior art has the problems of large chip occupation area and low product reliability, the package integration degree of the embedded substrate is further improved.
  • the present invention provides an embedded substrate for solving the problem that the embedded substrate in the prior art has a larger footprint of the entire chip and lower reliability of the product, which limits the further improvement of the package integration degree of the embedded substrate.
  • an embedded substrate including:
  • a substrate wherein at least one first chamber is respectively disposed on two sides in a thickness direction of the substrate, and a depth of each of the first chambers in a thickness direction of the substrate is smaller than a thickness of the substrate;
  • At least two first electronic devices each of the first electronic devices corresponding to a first chamber and located in the corresponding first chamber;
  • An encapsulation layer is filled in each of the first chambers and covers the first electronic device in each of the first chambers, and the encapsulation layer is provided with a plurality of first connection holes, each of the first connection holes and A pin of a first electronic device is correspondingly disposed and electrically connected to a corresponding pin;
  • a conductive circuit layer a part of the conductive circuit layer is filled in the plurality of first connection holes and connected to pins corresponding to each of the first connection holes.
  • the embedded substrate In the embedded substrate, at least one first chamber is respectively disposed on two sides in the thickness direction of the substrate, and each of the first chambers is packaged with a first electronic device through the encapsulation layer, and both sides of the substrate can be performed.
  • the packaging of the first electronic device reduces the occupied area of all the first electronic devices on the substrate, thereby improving the integration degree of the embedded substrate; and, when the thickness of the first electronic device is thin, due to each The depth of a chamber in the thickness direction of the substrate is smaller than the thickness of the substrate, which can reduce the distance between the lead of the first electronic device and the encapsulation layer, thereby reducing the depth of each of the first connection holes and making the conductive layer It is difficult to form bubble and pit defects at the first connection hole, which improves the product reliability of the embedded substrate. Therefore, the embedded substrate provided by the present application can reduce the occupied area of all electronic devices and can improve the reliability of the product, thereby further improving the package integration degree of the embedded substrate.
  • each of the first chambers on the other side of the substrate covers at least a portion of the at least one first chamber on the other side.
  • the projection of a portion of the first chamber on one side of the substrate on the other side of the substrate covers at least a portion of a portion of the first chamber on the other side, which can further reduce the occupied area of all the first electronic devices.
  • each of the first chambers on one side of the substrate and the first chamber on the other side of the substrate Corresponding to the arrangement, and the projection on the other side of the substrate covers the corresponding first chamber.
  • each of the first chambers on one side of the substrate is disposed corresponding to a first chamber on the other side of the substrate, and the projection on the other side of the substrate covers the corresponding first chamber, The footprint of all of the first electronic devices can be further reduced.
  • the depths of the two first chambers on the two sides of the substrate and corresponding to each other in the thickness direction of the substrate The sum is smaller than the thickness of the substrate.
  • the sum of the depths of the two corresponding first chambers on the two sides of the substrate in the thickness direction of the substrate is smaller than the thickness of the substrate, so that the two first chambers corresponding to each other can be overlapped.
  • the substrate is a substrate prepared by using a conductive material, and two first and second corresponding to each other on the two sides of the substrate In the chamber, the pins of the two first electronic devices in the two first chambers are connected by a substrate between the two first chambers.
  • the substrate is a conductive material
  • the two first electronic devices in the two first chambers respectively located on the two sides of the substrate and corresponding to each other can be connected through the substrate, and the two first electrons are shortened.
  • the connection path of the device reduces line loss.
  • the method further includes at least one second electronic device;
  • the substrate is provided with at least one second chamber penetrating the substrate along the thickness direction of the substrate, and each second electronic device is disposed corresponding to a second chamber and located in the corresponding second chamber;
  • the encapsulation layer is filled in each of the second chambers and covers the second electronic device in each of the second chambers, and the encapsulation layer is provided with a plurality of second connection holes, each of the second connection holes and a second One pin of the electronic device is correspondingly set and is electrically connected to the corresponding pin;
  • a portion of the conductive circuit layer is filled in the plurality of second connection holes and connected to pins corresponding to each of the second connection holes.
  • the substrate is further provided with a second chamber penetrating the substrate, and the second chamber is packaged with the second electronic device, which can further improve the package integration degree of the embedded substrate.
  • a thickness of each second electronic device is greater than a thickness of each first electronic device in a thickness direction of the substrate.
  • the first electronic device and the second electronic device having different thicknesses can be packaged on the substrate, and the applicable range of the embedded substrate can be improved.
  • a difference between a thickness of each second electronic device and each of the first electronic devices in a thickness direction of the substrate is 200 ⁇ m.
  • the maximum difference between the thickness of each of the second electronic devices and each of the first electronic devices is 200 ⁇ m, which can improve the applicable range of the embedded substrate.
  • the first electronic device is an active device or a passive device
  • the second electronic device is an active device or Passive components
  • the active device or the passive device can be packaged, and the applicable range of the embedded substrate is further improved.
  • the substrate is further provided with at least one via hole, and each via hole penetrates through the thickness direction of the substrate A substrate, a portion of the conductive circuit layer is disposed on an inner wall of each via.
  • the substrate is provided with a via hole, and the inner wall of the via hole is provided with a conductive circuit layer, and the first electronic device or the second electronic device located on both sides of the substrate can be connected.
  • the pin of the at least one first electronic device on one side of the substrate and the other side of the substrate are connected by a layer of conductive circuitry within at least one via.
  • the first electronic devices respectively located on both sides of the substrate may be connected to each other through the conductive circuit layer in the via.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional embedded substrate in the prior art
  • FIG. 2 is a schematic cross-sectional structural view of an embedded substrate according to an embodiment of the present application.
  • FIG. 3 is a schematic partial structural view of a substrate according to an embodiment of the present application.
  • FIG. 4 is a flow chart of a method for preparing an embedded substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic structural view of a substrate
  • FIG. 6 is a schematic structural view of a substrate after processing
  • FIG. 7 is a schematic structural view of a substrate after the first electronic device and the second electronic device are fixed;
  • FIG. 8 is a schematic structural view of a substrate after forming a partial encapsulation layer
  • FIG. 9 is a schematic structural view of a substrate after fixing another first electronic device
  • FIG. 10 is a schematic structural view of a substrate after forming another partial encapsulation layer
  • FIG. 11 is a schematic structural view of a substrate after forming a first connection hole and a second connection hole;
  • Fig. 12 is a schematic view showing the structure of a substrate after forming a conductive wiring layer.
  • the present invention provides an embedded substrate for solving the problem that the embedded substrate in the prior art has a larger footprint of the entire chip and lower reliability of the product, thereby further improving the package integration degree of the embedded substrate.
  • FIG. 2 is a cross-sectional structural diagram of an embedded substrate according to an embodiment of the present application.
  • the embedded substrate includes:
  • the direction indicated by the arrow A in FIG. 2 is the thickness direction of the substrate 100
  • the first chambers 110 are respectively disposed on both sides in the thickness direction of the substrate 100
  • each of the first chambers 110 is in the thickness direction of the substrate 100.
  • the depth is smaller than the thickness of the substrate 100.
  • each of the second chambers 120 has an opening disposed on the substrate 100.
  • the size and thickness of the substrate 100 should be set according to the number and thickness of the electronic components required for packaging, and the second chamber 120 disposed on either side of the substrate 100 according to the number of electronic components required for packaging. The number can be multiple.
  • each of the first electronic devices 200 is disposed corresponding to a first chamber 110 and located in the corresponding first chamber 110.
  • each first electronic device 200 has a plurality of pins 210, each of which faces an opening of the first chamber 110 in which it is located.
  • the first electronic device 200 can be an active device, such as a triode, an operational amplifier, etc., and the first electrical device can also be a passive device, such as a capacitor, a resistor, or the like.
  • an encapsulation layer 300 is also included.
  • the encapsulation layer 300 is filled in each of the first chambers 110 and covers the first electronic device 200 in each of the first chambers 110.
  • the encapsulation layer 300 is provided.
  • a plurality of first connection holes 310 each of which is disposed corresponding to one pin 210 of a first electronic device 200 and is electrically connected to the corresponding pin 210.
  • Each of the first electronic devices 200 is fixed in the corresponding first chamber 110 by the encapsulation layer 300.
  • the encapsulation layer 300 may be made of a material having thermoplasticity and insulation, such as a resin material, and in particular, hot pressing may be employed. According to the method, the first connection hole 310 on the encapsulation layer 300 can be processed by a laser drilling process.
  • a conductive circuit layer 400 is further included.
  • a portion of the conductive circuit layer 400 is filled in the plurality of first connection holes 310 and connected to the pins 210 corresponding to each of the first connection holes 310.
  • the conductive circuit layer 400 is disposed on the surface of the encapsulation layer 300 and is respectively located on two sides of the encapsulation layer 300.
  • the conductive circuit layer 400 is formed with a line pattern, and each of the first electronic devices 200 is filled in the first connection hole 310.
  • the inner conductive wiring layer 400 is connected to an external circuit.
  • the conductive circuit layer 400 can be prepared by using a copper material, and can be formed by a hole-filling copper plating process.
  • At least one first chamber 110 is disposed on each side of the substrate 100 in the thickness direction, and each of the first chambers 110 is encapsulated with a first electronic device through the encapsulation layer 300.
  • the first electronic device 200 since the first electronic device 200 can be packaged on both sides of the substrate 100, the occupied area of all the first electronic devices 200 on the substrate 100 is reduced, thereby improving the integration degree of the embedded substrate;
  • the thickness of the first electronic device 200 is thin, since the depth of each of the first chambers 110 in the thickness direction of the substrate 100 is smaller than the thickness of the substrate 100, the pins 210 and the encapsulation layer 300 of the first electronic device 200 can be reduced.
  • the distance between the first connection holes 310 can be reduced, so that the conductive circuit layer 400 is less likely to form bubbles and pit defects at the first connection holes 310, which improves the product reliability of the embedded substrate. Therefore, the embedded substrate provided by the present application can reduce the occupied area of all electronic devices and can improve the reliability of the product, thereby further improving the package integration degree of the embedded substrate.
  • a portion of the first chambers 110 respectively located on both sides of the substrate 100 may be overlapped such that the first chambers 110 are on the substrate 100.
  • the distribution is more concentrated.
  • at least a portion of the first chamber 110 on one side of the substrate 100, the projection of each of the first chambers 110 on the other side of the substrate 100 covers at least one first chamber 110 on the other side. At least part of it.
  • the projection of one first chamber on one side of the substrate on the other side of the substrate may completely cover one or more first chambers on the other side, or may cover only one or more first chambers on the other side. Part of the room.
  • FIG. 3 is a partial schematic structural diagram of a substrate 100 according to the embodiment.
  • the projection of one first chamber 110 on the other side of the substrate 100 on the other side of the substrate 100 covers the other side.
  • a portion of the two first chambers 110 can reduce the footprint of the three first chambers 110 on the substrate 100. Therefore, the projection of a portion of the first chamber 110 on one side of the substrate 100 on the other side of the substrate 100 covers a portion of the first chamber 110 on the other side, and the occupied area of all of the first electronic devices 200 can be further reduced.
  • each of the first chambers 110 on one side of the substrate 100 is disposed corresponding to one first chamber 110 on the other side of the substrate 100, and is another in the substrate 100.
  • the projection of the side covers the corresponding first chamber 110.
  • the arrangement manner can further reduce the occupied area of all the first electronic devices 200.
  • the depths of the two first chambers 110 respectively located on the two sides of the substrate 100 and corresponding to each other may be the same or different, a specific In the embodiment, as shown in FIG. 2, the sum of the depths of the two first chambers 110 respectively located on the two sides of the substrate 100 and corresponding to each other in the thickness direction of the substrate 100 is smaller than the thickness of the substrate 100, which can facilitate two corresponding to each other.
  • the first chambers 110 are arranged in an overlapping manner.
  • the substrate is a substrate prepared by using a conductive material.
  • the substrate provided by the embodiment of the present application may be made of a conductive material such as copper or aluminum.
  • FIG. 2 in the two first chambers 110 respectively located on opposite sides of the substrate 100 and corresponding to each other, two The pins 220 of the two first electronic devices 200 within one chamber 110 are connected by a substrate 100 between the two first chambers 110.
  • each of the first electronic devices 200 is provided with pins on both sides thereof, and the respective pins 220 of the two first electronic devices 200 shown in FIG. 2 are oppositely disposed and can pass between the first chambers 110.
  • the substrate 100 is connected, and the respective pins 210 of the two first electronic devices 200 are disposed opposite to each other and respectively connected to the conductive circuit layer 400, so that connection with an external line can be realized.
  • the respective pins 220 of the two first electronic devices 200 are connected through the substrate 100, no additional conductive lines are required between the two first electronic devices 200, shortening the connection path, thereby reducing line loss.
  • the embedded substrate provided by the embodiment further includes a second electronic device 500, as shown in FIG.
  • the thickness of each of the second electronic devices 500 is greater than the thickness of each of the first electronic devices 200;
  • the substrate 100 is provided with a second chamber 120 penetrating the substrate 100 in the thickness direction of the substrate 100, and second The electronic device 500 is disposed corresponding to the second chamber 120 and located in the corresponding second chamber 120.
  • a plurality of second chambers 120 and a plurality of second electronic devices 500 may be disposed on the substrate 100.
  • the second electronic device 500 can be an active device, such as a triode, an operational amplifier, etc., and the second electrical device can also be a passive device, such as a capacitor, a resistor, etc., each of the second electrical devices having a plurality of pins 510, pins 510 can be located on one or both sides of the second electrical device.
  • the encapsulation layer 300 is filled in each of the second chambers 120 and covers the second electronic device 500 in each of the second chambers 120.
  • the encapsulation layer 300 is provided with a plurality of second connection holes 320.
  • Each of the second connection holes 320 is disposed corresponding to one pin 510 of the second electronic device 500 and is electrically connected to the corresponding pin 510.
  • Each of the second electronic devices 500 is also fixed to the corresponding portion by using the encapsulation layer 300.
  • the second layer of the second electronic device 500 is provided with a second connecting hole 320 on both sides of the second electronic device 500.
  • a portion of the conductive wiring layer 400 is filled in the plurality of second connection holes 320 and connected to the pins 510 corresponding to each of the second connection holes 320.
  • the conductive circuit layer 400 is connected to the pins 510 on both sides of the second electronic device 500, so that the two-sided interconnection of the second electronic device 500 can be realized.
  • the second substrate 120 and the second electronic device 500 are disposed on the substrate 100, and the package integration degree of the embedded substrate can be further improved, and the first electronic device 200 and the second electronic device 500 having different thicknesses can be packaged on the substrate 100, It can improve the application range of embedded substrates.
  • the first electronic device 200 and the second electronic device 500 Since the height difference between the first electronic device 200 and the second electronic device 500 can be compensated by setting the depth of the first chamber 110, the first electronic device 200 and the second electronic device 500 having different thicknesses can be used.
  • the embedded substrate provided by the embodiment is packaged, and the difference in depth between the first connection hole 310 and the second connection hole 320 on the package layer 300 can be reduced, so that bubbles and pit defects are less likely to be formed when the conductive wiring layer 400 is formed.
  • the maximum difference between the thickness of each of the second electronic device 500 and each of the first electronic devices 200 is 200 ⁇ m in the thickness direction of the substrate 100, which can improve the applicable range of the embedded substrate. .
  • a via hole is further disposed on the substrate 100.
  • each of the via holes 130 penetrates the substrate 100 in the thickness direction of the substrate 100, and a portion of the conductive circuit layer 400 is disposed on the inner wall of each of the via holes 130.
  • the number of vias 130 may be multiple, and should be set according to the number of the first electronic device 200 or the second electronic device 500 to be connected.
  • the first electronic device 200 or the second electronic device 500 located on both sides of the substrate 100 may be connected through the conductive circuit layer 400 in the via 130, specifically, at least one of the sides of the substrate 100.
  • the pin 210 of an electronic device 200 is connected to the pin 210 of at least one first electronic device 200 on the other side of the substrate 100 through the conductive circuit layer 400 in the at least one via 130, or at least one second electronic device 500
  • the side pins 510 are connected through the conductive circuit layer 400 in the at least one via 130, which can shorten the connection path of the first electronic device 200 or the second electronic device 500 on both sides of the substrate 100, thereby reducing line loss.
  • the embedded substrate provided by the embodiment of the present application further includes the solder resist layer 600 shown in FIG. 2 .
  • the embedded substrate provided in this embodiment can be applied to electronic products such as mobile phones, tablet computers, notebook computers or smart wearable devices, and can reduce the volume of electronic products.
  • FIG. 4 is a flowchart of a method for preparing an embedded substrate according to an embodiment of the present application, including the following steps:
  • a first chamber and a second chamber are formed on the substrate.
  • FIG. 5 is a schematic structural view of a substrate
  • FIG. 6 is a schematic structural view of the processed substrate.
  • the substrate is made of a conductive material such as copper or aluminum.
  • the first chamber 110 and the second chamber 120 may be formed on the substrate 100 by etching, and the via holes 130 may be formed on the substrate at the same time.
  • step S20 the first electronic device is fixed in the first chamber on one side of the substrate, and the second electronic device is fixed in the second chamber.
  • FIG. 7 is a schematic structural diagram of a substrate after the first electronic device and the second electronic device are fixed.
  • the second electronic device 500 can be fixed in the second chamber 120 by using a tape 01 mounting method.
  • the first electronic device 200 is fixed in the first chamber 110 by a silver sintering method.
  • a partial encapsulation layer is formed in the first chamber on the second chamber and the substrate side.
  • FIG. 8 is a schematic structural view of a substrate after forming a partial encapsulation layer.
  • the resin may be filled into the first chamber 110 , the second chamber 120 , and the via 130 by thermal compression bonding.
  • a partial encapsulation layer 300 is formed.
  • step S40 the first electronic device is fixed in the first chamber on the other side of the substrate.
  • FIG. 9 is a schematic structural view of a substrate after fixing another first electronic device.
  • another first electronic device 200 may be fixed by a silver sintering method.
  • step S50 another partial encapsulation layer is formed in the first chamber on the other side of the substrate.
  • FIG. 10 is a schematic structural view of a substrate after another portion of the encapsulation layer is formed.
  • the resin may be filled into the first chamber 110 on the other side of the substrate 100 by thermocompression bonding to form another A portion of the encapsulation layer 300.
  • Step S60 forming a first connection hole and a second connection hole on the encapsulation layer.
  • FIG. 11 is a schematic structural view of a substrate after forming a first connection hole and a second connection hole.
  • a first connection hole 310 and a second connection may be formed on the package layer 300 by using a laser drilling process.
  • the hole 320 can also drill through the encapsulation layer 300 in the via 130.
  • Step S70 forming a conductive circuit layer on the encapsulation layer.
  • FIG. 12 is a schematic structural view of a substrate after forming a conductive circuit layer.
  • the conductive circuit layer 400 may be formed by a hole-fill copper plating process.
  • a process step of patterning the conductive wiring layer 400 and forming the solder resist layer 600 is further required.

Abstract

本申请涉及集成电路技术领域，公开一种嵌入式基板。用以解决现有技术中的嵌入式基板由于其全部芯片占用面积较大和产品可靠性较低，限制了嵌入式基板的封装集成度的进一步提高的问题。该嵌入式基板包括：基板，基板厚度方向上的两侧分别设有至少一个第一腔室，至少两个第一电子器件，每个第一电子器件与一个第一腔室对应设置；封装层，封装层填充于每个第一腔室内并包覆每个第一腔室内的第一电子器件，封装层设有多个第一连接孔，每个第一连接孔与一个第一电子器件的一个引脚对应设置、并与对应的引脚导通；导电线路层，导电线路层的一部分填充于多个第一连接孔内并与每个第一连接孔对应的引脚连接。

Description

一种嵌入式基板
本申请要求在2017年7月31日提交中国专利局、申请号为201710643126.4、发明名称为“一种嵌入式基板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种嵌入式基板。
背景技术
随着电子产品的设计趋势朝向小型化和轻薄化的方向发展，产品模块的封装集成度也随之提高，目前在业界出现了将芯片嵌入基板内的高密度互连集成技术。采用该技术制成的嵌入式基板的结构如图1所示，图1为目前一种常见的嵌入式基板的剖面结构示意图，该嵌入式基板包括基板10和封装于基板10内的第一芯片20和第二芯片30，其中，基板10上形成有多个腔室11，每个腔室11内通过树脂40封装有一个第一芯片20或一个第二芯片30，第一芯片20的焊盘21、第二芯片30的正面焊盘31以及背面焊盘32均与导电层50连接，以实现与外层电路的连接，第二芯片30的正面焊盘31和背面焊盘32还可通过导电层50实现双面互连。图1所示的嵌入式基板目前常用的制造方法为：在基板上通过蚀刻形成一个或多个腔室11，在每个腔室11内置入对应的第一芯片20或第二芯片30，再使用树脂40将第一芯片20和第二芯片30密封并双面压合，然后通过激光钻孔和填孔镀铜形成导电层50。
图1所示的嵌入式基板与传统基板相比，省去了基板表面预留的芯片安装空间，从而可减少全部芯片的封装体积，提升了芯片的封装集成度，然而，在此结构的嵌入式基板中，每个芯片需占用一个腔室，导致全部芯片所占用的面积较大，而且，参见图1所示，在第一芯片20的厚度大于第二芯片30时，会导致第二芯片30的焊盘盲孔高度大于第一芯片20的焊盘盲孔高度，在对第二芯片30进行填孔镀铜时，第二芯片30的焊盘盲孔无法完全填满，使得嵌入式基板的最终产品产生图1所示的气泡01及焊盘凹坑02，降低了嵌入式基板的可靠性。由于现有技术中的嵌入式基板存在全部芯片占用面积较大和产品可靠性较低的问题，限制了嵌入式基板的封装集成度的进一步提高。
发明内容
本申请提供一种嵌入式基板，用以解决现有技术中的嵌入式基板由于其全部芯片占用面积较大和产品可靠性较低，限制了嵌入式基板的封装集成度的进一步提高的问题。
第一方面，本申请提供了一种嵌入式基板，包括：
基板，所述基板厚度方向上的两侧分别设有至少一个第一腔室，每个第一腔室在所述基板厚度方向上的深度小于所述基板的厚度；
至少两个第一电子器件，每个第一电子器件与一个第一腔室对应设置、并位于对应的第一腔室内；
封装层，所述封装层填充于每个第一腔室内并包覆每个第一腔室内的第一电子器件，所述封装层设有多个第一连接孔，每个第一连接孔与一个第一电子器件的一个引脚对应设置、并与对应的引脚导通；
导电线路层，所述导电线路层的一部分填充于所述多个第一连接孔内并与每个第一连接孔对应的引脚连接。
上述嵌入式基板中，在基板的厚度方向上的两侧分别设有至少一个第一腔室，每个第一腔室内通过封装层封装有一个第一电子器件，由于基板的两侧均可进行第一电子器件的封装，减小了全部的第一电子器件在基板上的占用面积，进而提高了嵌入式基板的集成度；而且，在第一电子器件的厚度较薄时，由于每个第一腔室在基板厚度方向上的深度小于基板的厚度，可减小第一电子器件的引脚与封装层之间的距离，进而可减小每个第一连接孔的深度，使导电线路层不易在第一连接孔处形成气泡和凹坑缺陷，提高了嵌入式基板的产品可靠性。因此本申请提供的嵌入式基板可减小全部电子器件的占用面积、并且可提高产品的可靠性，从而可进一步提高嵌入式基板的封装集成度。
结合上述第一方面，在第一方面的第一种可能的实现方式中，位于所述基板一侧的至少一部分第一腔室中，每个第一腔室在所述基板的另一侧的投影覆盖另一侧的至少一个第一腔室的至少一部分。
上述嵌入式基板中，基板一侧的一部分第一腔室在基板的另一侧的投影覆盖另一侧的一部分第一腔室的至少一部分，可进一步减小全部的第一电子器件的占用面积。
结合上述第一种可能的实现方式，在第一方面的第二种可能的实现方式中，位于所述基板一侧的每个第一腔室与所述基板另一侧的一个第一腔室对应设置，且在所述基板的另一侧的投影覆盖对应的第一腔室。
上述嵌入式基板中，位于所述基板一侧的每个第一腔室与基板另一侧的一个第一腔室对应设置，且在基板的另一侧的投影覆盖对应的第一腔室，可进一步减小全部的第一电子器件的占用面积。
结合上述第二种可能的实现方式，在第一方面的第三种可能的实现方式中，分别位于所述基板两侧且互相对应的两个第一腔室在所述基板厚度方向上的深度之和小于所述基板的厚度。
上述嵌入式基板中，分别位于基板两侧的互相对应的两个第一腔室在基板厚度方向上的深度之和小于基板的厚度，可便于互相对应的两个第一腔室进行交叠设置。
结合上述第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述基板为导电材料制备的基板，在分别位于所述基板两侧且互相对应的两个第一腔室中，所述两个第一腔室内的两个第一电子器件的引脚通过所述两个第一腔室之间的基板连接。
上述嵌入式基板中，基板为导电材料，在分别位于所述基板两侧且互相对应的两个第一腔室中的两个第一电子器件可通过基板进行连接，缩短了两个第一电子器件的连接路径，减小了线路损耗。
结合上述第一方面、第一方面的第一种可能的实现方式、第一方面的第二种可能 的实现方式、第一方面的第三种可能的实现方式、第一方面的第四种可能的实现方式，在第一方面的第五种可能的实现方式中，还包括至少一个第二电子器件；
所述基板上设有至少一个沿所述基板厚度方向贯穿所述基板的第二腔室，每个第二电子器件与一个第二腔室对应设置、并位于对应的第二腔室内；
所述封装层填充于每个第二腔室内并包覆每个第二腔室内的第二电子器件，所述封装层设有多个第二连接孔，每个第二连接孔与一个第二电子器件的一个引脚对应设置、并与对应的引脚导通；
所述导电线路层的一部分填充于所述多个第二连接孔内并与每个第二连接孔对应的引脚连接。
上述嵌入式基板中，基板上还设有贯穿基板的第二腔室，第二腔室内封装有第二电子器件，可进一步提高嵌入式基板的封装集成度。
结合上述第五种可能的实现方式，在第一方面的第六种可能的实现方式中，在所述基板厚度方向上，每个第二电子器件的厚度大于每个第一电子器件的厚度。
上述嵌入式基板中，可在基板上封装厚度不同的第一电子器件和第二电子器件，可提高嵌入式基板的适用范围。
结合上述第六种可能的实现方式，在第一方面的第七种可能的实现方式中，在所述基板厚度方向上，每个第二电子器件与每个第一电子器件的厚度的差值最大值为200μm。
上述嵌入式基板中，每个第二电子器件与每个第一电子器件的厚度的差值最大值为200μm，可提高嵌入式基板的适用范围。
结合上述第五种可能的实现方式，在第一方面的第八种可能的实现方式中，所述第一电子器件为有源器件或无源器件，所述第二电子器件为有源器件或无源器件。
上述嵌入式基板中，可进行有源器件或无源器件的封装，进一步提高了嵌入式基板的适用范围。
结合上述第五种可能的实现方式，在第一方面的第九种可能的实现方式中，所述基板上还设有至少一个过孔，每个过孔沿所述基板的厚度方向贯穿所述基板，所述导电线路层的一部分设置于每个过孔的内壁。
上述嵌入式基板中，基板上设有过孔，过孔内壁设有导电线路层，可将位于基板两侧的第一电子器件或第二电子器件进行连接。
结合上述第九种可能的实现方式，在第一方面的第十种可能的实现方式中，位于所述基板一侧的至少一个第一电子器件的引脚与所述基板另一侧的至少一个第一电子器件的引脚通过至少一个过孔内的导电线路层连接。
上述嵌入式基板中，分别位于基板两侧的第一电子器件可通过过孔内导电线路层互相连接。
附图说明
图1为现有技术中一种常见的嵌入式基板的剖面结构示意图；
图2为本申请实施例提供的一种嵌入式基板的剖面结构示意图；
图3为本申请实施例提供的一种基板的局部结构示意图；
图4为本申请实施例提供的嵌入式基板的制备方法流程图；
图5为基板的结构示意图；
图6为加工后的基板结构示意图；
图7是固定第一电子器件和第二电子器件后的基板结构示意图；
图8是形成部分封装层后的基板结构示意图；
图9为固定另一个第一电子器件后的基板结构示意图；
图10是形成另一部分封装层后的基板结构示意图；
图11是形成第一连接孔和第二连接孔后的基板结构示意图；
图12是形成导电线路层后的基板结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
本申请提供一种嵌入式基板，用以解决现有技术中的嵌入式基板由于全部芯片占用面积较大和产品可靠性较低，进而限制了嵌入式基板的封装集成度的进一步提高的问题。
参见图2所示，图2是本申请实施例提供的一种嵌入式基板的剖面结构示意图，该嵌入式基板包括：
基板100，图2中箭头A所示方向为基板100的厚度方向，在基板100厚度方向上的两侧分别设有一个第一腔室110，每个第一腔室110在基板100厚度方向上的深度小于基板100的厚度。具体地，每个第二腔室120具有一个设置于基板100上的开口。具体实施中，基板100的大小和厚度应根据所需封装的电子器件的数量和厚度进行设置，且根据所需封装的电子器件的数量，在基板100的任一侧设置的第二腔室120的数量可为多个。
继续参见图2所示，还包括两个第一电子器件200，每个第一电子器件200与一个第一腔室110对应设置、并位于对应的第一腔室110内。具体地，每个第一电子器件200具有多个引脚210，每个引脚210朝向其所在的第一腔室110的开口。具体实施中，第一电子器件200可为有源器件，例如三极管、运算放大器等，第一电气器件也可为无源器件，例如电容、电阻等。
继续参见图2所示，还包括封装层300，封装层300填充于每个第一腔室110内，并包覆每个第一腔室110内的第一电子器件200，封装层300设有多个第一连接孔310，每个第一连接孔310与一个第一电子器件200的一个引脚210对应设置、并与对应的引脚210导通。每个第一电子器件200通过封装层300固定在对应的第一腔室110内，具体实施中，封装层300可采用具有热塑性和绝缘性的材料制成，例如树脂材料，具体可采用热压合方法制备，封装层300上的第一连接孔310可采用激光钻孔工艺进行加工。
继续参见图2所示，还包括导电线路层400，导电线路层400的一部分填充于多个第一连接孔310内并与每个第一连接孔310对应的引脚210连接。具体地，导电线路层400设置于封装层300的表面，并分别位于封装层300的两侧，导电线路层400上形成有线路图案，每个第一电子器件200通过填充于第一连接孔310内的导电线路 层400与外部电路进行连接。具体实施中，导电线路层400可采用铜材料制备，具体可采用填孔镀铜工艺形成。
本实施例提供的嵌入式基板中，在基板100的厚度方向上的两侧分别设有至少一个第一腔室110，每个第一腔室110内通过封装层300封装有一个第一电子器件200，由于基板100的两侧均可进行第一电子器件200的封装，减小了全部的第一电子器件200在基板100上的占用面积，进而提高了嵌入式基板的集成度；而且，在第一电子器件200的厚度较薄时，由于每个第一腔室110在基板100厚度方向上的深度小于基板100的厚度，可减小第一电子器件200的引脚210与封装层300之间的距离，进而可减小每个第一连接孔310的深度，使导电线路层400不易在第一连接孔310处形成气泡和凹坑缺陷，提高了嵌入式基板的产品可靠性。因此本申请提供的嵌入式基板可减小全部电子器件的占用面积、并且可提高产品的可靠性，从而可进一步提高嵌入式基板的封装集成度。
为进一步减小嵌入式基板上的全部的第一电子器件200的占用面积，可将分别位于基板100两侧的一部分第一腔室110交叠设置，以使第一腔室110在基板100上的分布更加集中。一种具体实施方式中，位于基板100一侧的至少一部分第一腔室110中，每个第一腔室110在基板100的另一侧的投影覆盖另一侧的至少一个第一腔室110的至少一部分。具体地，基板一侧的一个第一腔室在基板另一侧的投影可完全覆盖另一侧的一个或多个第一腔室，也可只覆盖另一侧的一个或多个第一腔室的一部分。
具体参见图3所示，图3是本实施例提供的一种基板100的局部结构示意图，在该基板100一侧的一个第一腔室110在基板100另一侧的投影覆盖另一侧的两个第一腔室110的一部分，可减小三个第一腔室110在基板100上的占用面积。因此，基板100一侧的一部分第一腔室110在基板100的另一侧的投影覆盖另一侧的一部分第一腔室110，可进一步减小全部的第一电子器件200的占用面积。
另一种具体实施方式中，参见图2所示，位于基板100一侧的每个第一腔室110与基板100另一侧的一个第一腔室110对应设置，且在基板100的另一侧的投影覆盖对应的第一腔室110。该设置方式可进一步减小全部的第一电子器件200的占用面积，具体实施中，分别位于基板100两侧且互相对应的两个第一腔室110的深度可相同也可不同，一种具体实施方式中，如图2所示，分别位于基板100两侧、且互相对应的两个第一腔室110在基板100厚度方向上的深度之和小于基板100的厚度，可便于互相对应的两个第一腔室110进行交叠设置。
在分别位于基板两侧的两个第一电子器件之间需要进行连接时，为减小两个第一电子器件之间的连接路径，一种具体实施方式中，基板为导电材料制备的基板，具体地，本申请实施例提供的基板可采用铜、铝等导电材料制成，参见图2所示，在分别位于基板100两侧且互相对应的两个第一腔室110中，两个第一腔室110内的两个第一电子器件200的引脚220通过两个第一腔室110之间的基板100连接。具体地，每个第一电子器件200的两侧均设有引脚，图2所示的两个第一电子器件200各自的引脚220相对设置，并可通过第一腔室110之间的基板100进行连接，两个第一电子器件200各自的引脚210相背设置，并分别与导电线路层400连接，可实现与外部线路的连接。在两个第一电子器件200各自的引脚220通过基板100连接时，在两个第一电子器件200之间不需要额外设置导电线路，缩短了连接路径，从而减小了线路损耗。
为使本实施例提供的嵌入式基板还可封装厚度较大的电子器件，参见图2所示，一种具体实施方式中，本实施例提供的嵌入式基板还包括一个第二电子器件500，在基板100厚度方向上，每个第二电子器件500的厚度大于每个第一电子器件200的厚度；基板100上设有一个沿基板100厚度方向贯穿基板100的第二腔室120，第二电子器件500与第二腔室120对应设置、并位于对应的第二腔室120内；具体实施中，在基板100上可设置有多个第二腔室120和多个第二电子器件500，第二电子器件500可为有源器件，例如三极管、运算放大器等，第二电气器件也可为无源器件，例如电容、电阻等，每个第二电气器件具有多个引脚510，引脚510可位于第二电气器件的一侧或两侧。
继续参见图2所示，封装层300填充于每个第二腔室120内并包覆每个第二腔室120内的第二电子器件500，封装层300设有多个第二连接孔320，每个第二连接孔320与一个第二电子器件500的一个引脚510对应设置、并与对应的引脚510导通；每个第二电子器件500同样采用封装层300固定于对应的第二腔室120内，在第二电子器件500两侧均设有引脚510时，则封装层300在第二电子器件500的两侧均对应设有第二连接孔320。
继续参见图2所示，导电线路层400的一部分填充于多个第二连接孔320内并与每个第二连接孔320对应的引脚510连接。在第二电子器件500的两侧均设有引脚510时，导电线路层400与第二电子器件500两侧的引脚510连接，可实现第二电子器件500的双面互联。
基板100上设有第二腔室120和第二电子器件500，可进一步提高嵌入式基板的封装集成度，且可在基板100上封装厚度不同的第一电子器件200和第二电子器件500，可提高嵌入式基板的适用范围。
由于第一电子器件200和第二电子器件500之间的高度差可通过设置第一腔室110的深度进行补偿，厚度相差较大的第一电子器件200和第二电子器件500均可采用本实施例提供的嵌入式基板进行封装，且可减小封装层300上的第一连接孔310和第二连接孔320的深度差，从而在形成导电线路层400时不易形成气泡和凹坑缺陷。本实施例提供的嵌入式基板中，在基板100厚度方向上，每个第二电子器件500与每个第一电子器件200的厚度的差值最大值为200μm，可提高嵌入式基板的适用范围。
为实现基板100两侧的第一电子器件200的连接、或实现第二电子器件500的双面互连，一种具体实施方式中，参见图2所示，基板100上还设有一个过孔130，每个过孔130沿基板100的厚度方向贯穿基板100，导电线路层400的一部分设置于每个过孔130的内壁。具体实施中，过孔130的数量可为多个，应根据所需连接的第一电子器件200或第二电子器件500的数量进行设置。一种具体实施方式中，位于基板100两侧的第一电子器件200或第二电子器件500可通过过孔130内的导电线路层400进行连接，具体地，位于基板100一侧的至少一个第一电子器件200的引脚210与基板100另一侧的至少一个第一电子器件200的引脚210通过至少一个过孔130内的导电线路层400连接，或，至少一个第二电子器件500两侧的引脚510通过至少一个过孔130内的导电线路层400连接，可缩短基板100两侧的第一电子器件200或第二电子器件500的连接路径，减少线路损耗。
具体实施中，本申请实施例提供的嵌入式基板还包括图2所示的阻焊层600。
本实施例提供的嵌入式基板可应用于手机、平板电脑、笔记本电脑或智能穿戴设备等电子产品中，可减小电子产品的体积。
具体实施中，本申请实施例提供的嵌入式基板的制备方法参见图4所示，图4是本申请实施例提供的嵌入式基板的制备方法流程图，包括下列步骤：
步骤S10，在基板上形成第一腔室和第二腔室。参见图5和图6所示，图5是基板的结构示意图，图6是加工后的基板结构示意图。具体实施中，基板采用铜、铝等导电材料制成，可通过刻蚀法在基板100上形成第一腔室110和第二腔室120，还可同时在基板上形成过孔130。
步骤S20，在基板一侧的第一腔室内固定第一电子器件，在第二腔室内固定第二电子器件。参见图7所示，图7是固定第一电子器件和第二电子器件后的基板结构示意图，具体实施中，可采用胶带01贴装的方法在第二腔室120内固定第二电子器件500，采用银烧结方法在第一腔室110内固定第一电子器件200。
步骤S30，在第二腔室和基板一侧的第一腔室内形成部分封装层。参见图8所示，图8是形成部分封装层后的基板结构示意图，具体实施中，可采用热压合的方法将树脂填充到第一腔室110、第二腔室120以及过孔130内，形成部分封装层300。
步骤S40，在基板另一侧的第一腔室内固定第一电子器件。参见图9所示，图9为固定另一个第一电子器件后的基板结构示意图，具体实施中，同样可采用银烧结方法固定另一个第一电子器件200。
步骤S50，在基板另一侧的第一腔室内形成另一部分封装层。参见图10所示，图10是形成另一部分封装层后的基板结构示意图，具体实施中，可采用热压合的方法将树脂填充到基板100另一侧的第一腔室110内，形成另一部分封装层300。
步骤S60，在封装层上形成第一连接孔和第二连接孔。参见图11所示，图11是形成第一连接孔和第二连接孔后的基板结构示意图，具体实施中，可采用激光钻孔工艺在封装层300上形成第一连接孔310和第二连接孔320，同时还可将过孔130内的封装层300钻通。
步骤S70，在封装层上形成导电线路层。参见图12所示，图12是形成导电线路层后的基板结构示意图，具体实施中，可采用填孔镀铜工艺形成导电线路层400。
为形成图2所示结构的嵌入式基板，后续还需进行将导电线路层400图案化处理和形成阻焊层600的工艺步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种嵌入式基板，其特征在于，包括：
    基板，所述基板厚度方向上的两侧分别设有至少一个第一腔室，每个第一腔室在所述基板厚度方向上的深度小于所述基板的厚度；
    至少两个第一电子器件，每个第一电子器件与一个第一腔室对应设置、并位于对应的第一腔室内；
    封装层，所述封装层填充于每个第一腔室内并包覆每个第一腔室内的第一电子器件，所述封装层设有多个第一连接孔，每个第一连接孔与一个第一电子器件的一个引脚对应设置、并与对应的引脚导通；
    导电线路层，所述导电线路层的一部分填充于所述多个第一连接孔内并与每个第一连接孔对应的引脚连接。
  2. 根据权利要求1所述的嵌入式基板，其特征在于，位于所述基板一侧的至少一部分第一腔室中，每个第一腔室在所述基板的另一侧的投影覆盖另一侧的至少一个第一腔室的至少一部分。
  3. 根据权利要求2所述的嵌入式基板，其特征在于，位于所述基板一侧的每个第一腔室与所述基板另一侧的一个第一腔室对应设置，且在所述基板的另一侧的投影覆盖对应的第一腔室。
  4. 根据权利要求3所述的嵌入式基板，其特征在于，分别位于所述基板两侧且互相对应的两个第一腔室在所述基板厚度方向上的深度之和小于所述基板的厚度。
  5. 根据权利要求4所述的嵌入式基板，其特征在于，所述基板为导电材料制备的基板，在分别位于所述基板两侧且互相对应的两个第一腔室中，所述两个第一腔室内的两个第一电子器件的引脚通过所述两个第一腔室之间的基板连接。
  6. 根据权利要求1-5任一项所述的嵌入式基板，其特征在于，还包括至少一个第二电子器件；
    所述基板上设有至少一个沿所述基板厚度方向贯穿所述基板的第二腔室，每个第二电子器件与一个第二腔室对应设置、并位于对应的第二腔室内；
    所述封装层填充于每个第二腔室内并包覆每个第二腔室内的第二电子器件，所述封装层设有多个第二连接孔，每个第二连接孔与一个第二电子器件的一个引脚对应设置、并与对应的引脚导通；
    所述导电线路层的一部分填充于所述多个第二连接孔内并与每个第二连接孔对应的引脚连接。
  7. 根据权利要求6所述的嵌入式基板，其特征在于，在所述基板厚度方向上，每个第二电子器件的厚度大于每个第一电子器件的厚度。
  8. 根据权利要求7所述的嵌入式基板，其特征在于，在所述基板厚度方向上，每个第二电子器件与每个第一电子器件的厚度的差值最大值为200μm。
  9. 根据权利要求6所述的嵌入式基板，其特征在于，所述第一电子器件为有源器件或无源器件，所述第二电子器件为有源器件或无源器件。
  10. 根据权利要求6所述的嵌入式基板，其特征在于，所述基板上还设有至少一个过孔，每个过孔沿所述基板的厚度方向贯穿所述基板，所述导电线路层的一部分设 置于每个过孔的内壁。
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