WO2021052327A1 - 一种电路板 - Google Patents

一种电路板 Download PDF

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Publication number
WO2021052327A1
WO2021052327A1 PCT/CN2020/115357 CN2020115357W WO2021052327A1 WO 2021052327 A1 WO2021052327 A1 WO 2021052327A1 CN 2020115357 W CN2020115357 W CN 2020115357W WO 2021052327 A1 WO2021052327 A1 WO 2021052327A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
pad
signal line
present
hole
Prior art date
Application number
PCT/CN2020/115357
Other languages
English (en)
French (fr)
Inventor
尹昌刚
易毕
魏仲民
Original Assignee
中兴通讯股份有限公司
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Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP20866258.5A priority Critical patent/EP4009752A4/en
Priority to US17/635,916 priority patent/US11696399B2/en
Priority to JP2022511343A priority patent/JP7353467B2/ja
Publication of WO2021052327A1 publication Critical patent/WO2021052327A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/04—Fixed joints
    • H01P1/047—Strip line joints
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0776—Resistance and impedance
    • H05K2201/0792—Means against parasitic impedance; Means against eddy currents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09463—Partial lands, i.e. lands or conductive rings not completely surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical

Definitions

  • the embodiment of the present invention relates to but not limited to the field of electronic power technology, and specifically relates to but not limited to a circuit board.
  • the speed of high-speed products has reached more than 25Gbps, which is a very big challenge to the signal integrity of high-speed interconnection channels. Facing this kind of challenge, it is necessary to carry out in-depth optimization design for the passive components that make up the high-speed interconnection channel.
  • the key passive component of the high-speed interconnection channel the performance of the via is directly related to the signal integrity performance of the entire high-speed channel.
  • the main factor affecting its signal integrity is that its impedance is low compared to the transmission line, resulting in discontinuity in impedance.
  • the factors that affect the resistance of vias include aperture, pad diameter, anti-pad diameter, and dielectric permittivity, etc.
  • anti-pad optimization also has a limit, and via pads are due to drilling Alignment needs are generally 10mil larger than the aperture, which cannot be reduced, resulting in a large capacitive and large capacitive impedance will reduce, so the impedance of the entire hole is low, which affects signal integrity.
  • the circuit board provided by the embodiment of the present invention aims to solve the problem at least to a certain extent that the impedance of the via holes on the current circuit board is less than the impedance of the signal line, resulting in discontinuity in impedance, which affects the signal integrity and the circuit board.
  • the differential vias use serpentine winding, which affects the increase in trace density.
  • an embodiment of the present invention provides a circuit board, including: a circuit board main body, at least one via device disposed on the circuit board main body; the via device includes a circuit board main body formed on the circuit board main body; A via hole, a via pad surrounding the via hole and separate from the via hole, and a conductor electrically connecting the via pad and the via hole.
  • Figure 1 is a three-dimensional schematic diagram of a via device
  • FIG. 2 is a schematic structural diagram of a via device provided by Embodiment 1 of the present invention.
  • Embodiment 3 is a schematic structural diagram of another via device provided by Embodiment 1 of the present invention.
  • Embodiment 4 is a schematic structural diagram of another via device provided by Embodiment 1 of the present invention.
  • Embodiment 1 of the present invention is a schematic structural diagram of another via device provided by Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of another via device provided by Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural diagram of a differential via device according to the second embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of another differential via device provided by the second embodiment of the present invention.
  • FIG. 9 is a diagram of the simulation results of the BGA differential via impedance before and after the application of the present invention provided by the second embodiment of the present invention.
  • FIG. 10 is a diagram of simulation results of BGA differential via insertion loss before and after the application of the present invention provided by the second embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a differential via provided by the third embodiment of the present invention without using the present invention.
  • FIG. 13 is a schematic diagram of comparison of current paths provided by Embodiment 3 of the present invention.
  • FIG. 14 is a schematic structural diagram of a differential via provided by Embodiment 3 of the present invention.
  • FIG. 1 is a three-dimensional schematic diagram of a via device
  • FIG. 2 is a schematic structural diagram of a via device on a main body of a circuit board provided by an embodiment of the present invention.
  • the circuit board in the embodiment of the present invention includes a circuit board main body and at least one via device formed on the circuit board main body. As shown in FIG. A via pad 201 is provided separately from the hole 101, a conductor 301 that electrically connects the via hole 101 and the via pad 201, and a signal line 401.
  • the via devices on the circuit board may all be the via device structure of the present invention; they may also be part of the via device structure of the present invention, and some may be other via device structures.
  • the parasitic capacitance formula of the via is shown in formula (1):
  • ⁇ r is the dielectric constant of the PCB
  • D1 is the diameter of the via pad
  • D2 is the diameter of the via anti-pad.
  • the structure of the via device in the embodiment of the present invention is shown in FIG. 2.
  • the via pad used in the embodiment of the present invention is a circular via pad, and the size of the ring outer ring is consistent with the design size of the existing pad.
  • the hole and the pad are connected by a conductor, as shown in Figure 2, which can greatly reduce the capacitance of the pad, thereby increasing the overall impedance of the via and making it more matched with the impedance of the transmission line.
  • the via pad is a non-closed ring mounting pad, as shown in FIG. 3.
  • the conductive body between the via hole and the via pad is fan-shaped, as shown in FIG. 4, it is understandable that the shape of the conductive body can be any shape.
  • the via pad is a special-shaped annular pad, as shown in FIG. 5.
  • the via is a special-shaped via, as shown in FIG. 6.
  • a circuit board provided by an embodiment of the present invention includes a circuit board body and at least one via device provided on the circuit board body; the via device includes a via hole formed on the circuit board body, surrounding the via hole, and Via pads provided separately from the vias and conductors that electrically connect the via pads to the vias, through the use of ring pads, the capacitance of the pads can be greatly reduced.
  • the inclusion of but It is not limited to increasing the impedance of the via, but it is more matched with the impedance of the transmission line, thereby improving the signal integrity of the via and the system channel.
  • FIG. 7 is a schematic structural diagram of a differential via device in the inner layer of a circuit board provided by an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a differential via device on the surface of a circuit board provided by an embodiment of the present invention.
  • the circuit board in the embodiment of the present invention has a BGA chip differential via structure with an interval of 1.0 mm, and the hole depth is 3 mm.
  • the circuit board includes a circuit board main body, a differential via device on the inner layer of the circuit board and a differential via device on the surface of the circuit board.
  • the differential via device in the inner layer of the circuit board, as shown in FIG. 7, the differential via device includes a via 101 and a via 102, and a via pad 201 that surrounds the via 101 and is disposed separately from the via 101.
  • the differential via device on the surface of the circuit board is shown in Figure 8.
  • the differential via device includes a via 103 and a via 104, a via pad 203 surrounding the via 103 and separate from the via 103, surrounding the via pad 203 Hole 104, via pad 204 provided separately from via 104, conductor 303 for electrically connecting via hole 103 and via pad 203, and conductor 304 for electrically connecting via hole 104 and via pad 204 ,
  • the via pads are all circular pads.
  • the diameters of via 101, via 102, via 103, and via 104 are all 0.2mm; the outer diameters of via pad 201, via pad 202, via pad 203, and via pad 204 are all 0.4mm, the ring width is 2 mil; the conductor 301, the conductor 302, the conductor 303, and the conductor 304 are all strips with a width of 2 mils.
  • the pads 201-204 in the embodiment of the present invention are no longer the overall circular shape of the current technology but a ring structure, the conductor area is greatly reduced, thereby reducing the capacitance of the surface and inner pads.
  • the ring width and the width of the conductor connection structure are only 2 mils.
  • FIG. 11 and FIG. 12 The simulation results of the BGA differential via impedance and insertion loss before and after using the present invention are shown in FIG. 11 and FIG. 12. It can be seen that after adopting the present invention, the impedance at the surface pad and the inner pad have been increased by 4.3 ohm and 8 ohm, respectively. The improvement effect is very obvious, the insertion loss is reduced by 28% compared with the current design, and the differential via insertion is improved. The problem of large losses.
  • the hole depth is 2mm. Since the crimp connectors are assembled in the form of crimping, there are no signal lines on the surface, but there are also surface pads. And the inner layer pad, and the main influence on the impedance of the crimped via is the inner layer pad.
  • the ring pad provided by the present invention can also be used to increase the impedance of the via pad, thereby increasing the impedance of the entire via and improving the overpass. Signal integrity of holes and system channels.
  • a circuit board provided by an embodiment of the present invention includes a circuit board main body and a differential via device disposed on the circuit board main body; the differential via device includes a via formed on the circuit board main body, surrounding the via, and the via Separate via pads and conductors that electrically connect the via pads to the vias.
  • the capacitance of the pads can be greatly reduced. In some implementations, it can be achieved including but not limited to improving The impedance of the via makes it more matched with the impedance of the transmission line, thereby improving the signal integrity of the via and system channel, and at the same time improving the problem of large differential via insertion loss.
  • FIG. 14 is a schematic structural diagram of a differential via device provided by an embodiment of the present invention.
  • the embodiment of the present invention provides a circuit board.
  • the circuit board has a BGA chip fan-out differential hole structure with an interval of 1.0mm.
  • the differential via device on the surface of the circuit board is shown in FIG. 11, and the differential via device includes a via 107 , Via 108, via pad 207, via pad 208, signal line 407, signal line 409, and BGA chip bonding pad 705 and BGA chip bonding pad 706; the differential via device in the inner layer of the circuit board is shown in the figure As shown in 12, the differential via device includes a via 107, a via 108, a via pad 209, a via pad 210, a signal line 408, and a signal line 410.
  • the length of the signal line 410 will be obviously shorter than that of 408.
  • the phase of the current is different, the signal line 410 is shown in Figure 11
  • the serpentine winding will take up more wiring space, affect the increase of the wiring density, and is not conducive to reducing the size of the product single board.
  • FIG. 13 is a schematic diagram of the current path comparison provided by the embodiment of the present invention, as shown in FIG. 13, Among them (a) in the figure, the current flows through the entire length of the ring after entering the pad from the signal line, and (b) in the figure, the current enters the via from the conductor bar immediately after the signal line enters the pad, the same input signal situation Next, by changing the position of the conductor, changing the path of the circuit flowing through the signal line, to the conductor and then waiting to the via pad, so that the signal that finally enters the via has a significant phase difference.
  • the differential signal can be achieved by this technology.
  • the phase difference caused by the bending of the trace is adjusted, without the need for serpentine winding, so that the trace density can be increased and the product competitiveness can be improved.
  • FIG. 14 is a structure of a differential via provided by an embodiment of the present invention.
  • the differential via structure includes a via 105 and a via 106, a via pad 211 that surrounds the via 105 and is disposed separately from the via 105, and surrounds the via 106 and is connected to the via 106.
  • Separate via pads 212, conductors 307 that electrically connect vias 105 and via pads 205, and conductors 308 that electrically connect vias 106 and via pads 206, are connected to via pads 211
  • the signal line 411 is a signal line 412 connected to the via pad 212.
  • the apertures of the via 105 and the via 106 are both 0.2mm, the outer diameter of the via pad 211 and the via pad 212 are both 0.4mm, the ring width is 1.5mil, and the conductor 307 and the conductor 308 are strips. , The width is 2mil. Adjust the positions of the conductor 307 and the conductor 308. Specifically, the shortest distance from the signal line 411 to the via pad 211 to the conductor 307 and then to the via 105 is equal to the current passing through the signal line 412 to the via hole. The shortest distance from the pad 212 to the conductor 308 to the via 106 is the same. As a result, the length difference between the signal line 411 and the signal line 412 is compensated at the via pad and the conductor, and the serpentine winding is no longer needed, which reduces the space occupied by the wiring.
  • a circuit board provided by an embodiment of the present invention includes a circuit board main body and a differential via device disposed on the circuit board main body; the differential via device includes a via formed on the circuit board main body, surrounding the via, and the via Separate via pads and conductors that electrically connect the via pads to the vias.
  • the capacitance of the pads is greatly reduced, and by changing the position of the conductors, the length of the signal line is different.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

一种电路板，包括电路板主体，设置于电路板主体上的至少一个过孔装置；该过孔装置包括在电路板主体上形成的过孔(101)、围绕过孔、且与过孔分离设置的过孔焊盘(201)，以及将过孔焊盘(201)与过孔(101)电连接的导电体(301)。

Description

一种电路板
相关申请的交叉引用
本申请基于申请号为201910872663.5、申请日为2019年9月16日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明实施例涉及但不限于电子电力技术领域，具体而言，涉及但不限于一种电路板。
背景技术
目前高速产品速率已经达到25Gbps以上，这对高速互连通道信号完整性是一个非常大的挑战。面对这种挑战，需要对组成高速互连通道的无源部件进行深入的优化设计。而过孔作为高速互连通道关键无源部件，其性能优劣直接关系到整个高速通道信号完整性性能优劣。对于过孔来说，影响其信号完整性的主要因素是其阻抗与传输线相比偏低，造成阻抗不连续。影响过孔阻抗的因素有孔径、焊盘径、反焊盘径以及介质介电常数等，由于板材和孔径一般都无法改变，而反焊盘优化也具有极限，而过孔焊盘由于钻孔对位需要一般比孔径要大10mil，无法缩小，导致其容性偏大，容性大阻抗会降低，所以造成整个孔的阻抗偏低，影响信号完整性。
发明内容
本发明实施例提供的一种电路板，旨在至少在一定程度上解决的问题是目前的电路板上的过孔的阻抗小于信号线阻抗，导致阻抗不连续，影响信号完整性以及电路板上的差分过孔使用蛇形绕线，影响走线密度的提升。
有鉴于此，本发明实施例提供一种电路板，包括：电路板主体，设置于所述电路板主体上的至少一个过孔装置；所述过孔装置包括在所述电路板主体上形成的过孔、围绕所述过孔、且与所述过孔分离设置的过孔焊盘，以及将所述过孔焊盘与所述过孔电连接的导电体。
本发明其他特征和相应的有益效果在说明书的后面部分进行阐述说明，且应当理解，至少部分有益效果从本发明说明书中的记载变的显而易见。
附图说明
图1为过孔装置的立体示意图；
图2为本发明实施例一提供的一种过孔装置的结构示意图；
图3为本发明实施例一提供的另一种过孔装置的结构示意图；
图4为本发明实施例一提供的另一种过孔装置的结构示意图；
图5为本发明实施例一提供的另一种过孔装置的结构示意图；
图6为本发明实施例一提供的另一种过孔装置的结构示意图；
图7为本发明实施例二提供的一种差分过孔装置的结构示意图；
图8为本发明实施例二提供的另一种差分过孔装置的结构示意图；
图9为本发明实施例二提供的采用本发明前后BGA差分过孔阻抗仿真结果图；
图10为本发明实施例二提供的采用本发明前后BGA差分过孔插损仿真结果图；
图11为本发明实施例三提供的未采用本发明的一种差分过孔的结构示意图；
图12为本发明实施例三提供的未采用本发明的另一种差分过孔的结构示意图；
图13为本发明实施例三提供的电流路径对比示意图；
图14为本发明实施例三提供的一种差分过孔的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本发明实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
为了提高电路板过孔的阻抗，改善过孔和系统通道的信号完整性，本发明实施例提供了一种电路板。图1为过孔装置的立体示意图；图2为本发明实施例提供的电路板的主体上的一种过孔装置的结构示意图。
本发明实施例中的电路板包括电路板主体和电路板主体上形成的至少一个过孔装置，如图2所示，该过孔装置包括：包括过孔101，围绕过孔101、且与过孔101分离设置的过孔焊盘201，将过孔101和过孔焊盘201电连接的导电体301，信号线401。
可以理解的是，在一些实施例中，电路板上的过孔装置可都为本发明的过孔装置结构；也可部分为本发明的过孔装置结构，部分为其他过孔装置结构。
过孔寄生电容公式如公式(1)所示：
Figure PCTCN2020115357-appb-000001
其中，ε r为PCB介质介电常数，D1为过孔焊盘直径，D2为过孔反焊盘直径。
从公式1看到，过孔焊盘直径D1越大，过孔的寄生电容越大。
又根据阻抗公式(2)，寄生电感一定的情况下，寄生电容越大，过孔的阻抗越低。
Figure PCTCN2020115357-appb-000002
本发明实施例的过孔装置的结构如图2所示，本发明实施例采用的过孔焊盘是圆环形的过孔焊盘，环形外圈尺寸与现有焊盘设计尺寸一致，过孔和焊盘之间通过导电体进行连接，如图2所示，这样可以大幅降低焊盘的容性，从而可以提高过孔整体的阻抗，使其与传输线的阻抗更加匹配。
在一些发明实施例中，过孔焊盘为非封闭环装焊盘，如图3所示。
在一些发明实施例中，过孔与过孔焊盘之间的导电体为扇形，如图4所示，可理解的是，导电体的形状可以是任意形状。
在一些发明实施例中，过孔焊盘为异形环形焊盘，如图5所示。
在一些发明实施例中，过孔为异形过孔，如图6所示。
有益效果
本发明实施例提供的一种电路板，包括电路板主体，设置于电路板主体上的至少一个过孔装置；过孔装置包括在所述电路板主体上形成的过孔、围绕过孔、且与过孔分离设置的过孔焊盘，以及将过孔焊盘与过孔电连接的导电体，通过使用环形焊盘，大幅降低焊盘的容性，在某些实施过程中可实现包括但不限于提高过孔的阻抗，是其与传输线的阻抗更加匹配，从而改善了过孔和系统通道的信号完整性。
实施例二:
为了提高电路板过孔的阻抗，改善过孔和系统通道的信号完整性，本发明实施例提供了一种电路板。图7为本发明实施例提供的电路板内层的差分过孔装置的结构示意图。图8为本发明实施例提供的电路板表层的差分过孔装置的结构示意图。
本发明实施例中的电路板为间隔1.0mm的BGA芯片差分过孔结构，孔深3mm。电路板包括，电路板主体，电路板内层的差分过孔装置和电路板表层的差分过孔装置。电路板内层的差分过孔装置，如图7所示，该差分过孔装置包括过孔101和过孔102，围绕过孔101、且与过孔101分离设置的过孔焊盘201，围绕过孔102、且与过孔102分离设置的过孔焊盘202，将过孔101和过孔焊盘201电连接的导电体301，将过孔102和过孔焊盘202电连接的导电体302，信号线401，信号线402。电路板表层的差分过孔装置如图8所示，该差分过孔装置包括，过孔103和过孔104，围绕过孔103、且与过孔103分离设置的过孔焊盘203，围绕过孔104、且与过孔104分离设置的过孔焊盘204，将过孔103和过孔焊盘203电连接的导电体303，将过孔104和过孔焊盘204电连接的导电体304，信号线403，信号线404以及BGA芯片焊接焊盘701和BGA芯片焊接焊盘702。在本发明实施例中过孔焊盘均为圆环形焊盘。过孔101、过孔102、过孔103、过孔104的孔径均为0.2mm；过孔焊盘201、过孔焊盘202、过孔焊盘203、过孔焊盘204的外径均为0.4mm，环宽均为2mil；导电体301、导电体302、导电体303、导电体304均为条状，宽度为2mil。
由于本发明实施例中的焊盘201-204不再是当前技术整体的圆形而是一个环形结构，导体面积大幅减小，从而降低了表层和内层焊盘的容性，又由于焊盘环宽和导电体连接结构宽度只有2mil，相对于圆形焊盘的电感增加，由公式2可知，电感L增加，电容C减小，阻抗增加，从而提高整个过孔的阻抗，改善过孔和系统通道的信号完整性。
采用本发明前后BGA差分过孔阻抗和插损仿真结果如图11和图12所示。可以看到，采用本发明后，表层焊盘和内层焊盘处的阻抗分别提升了4.3ohm和8ohm，提升效果非常 明显，插损与当前设计比降低了28％，改善了差分过孔插损大的问题。
在一些发明实施例中，电路板上是间隔为1.2mm的高速压接连接器，孔深2mm，由于压接连接器采用压接的形式进行装配所以表层没有信号线，但是同样存在表层焊盘和内层焊盘，而影响压接过孔阻抗的主要是内层焊盘，同样可以使用本发明提供的环形焊盘，增加过孔焊盘的阻抗，从而提升整个过孔的阻抗，改善过孔和系统通道的信号完整性。
有益效果
本发明实施例提供的一种电路板，包括电路板主体，设置于电路板主体的差分过孔装置；差分过孔装置包括在电路板主体上形成的过孔、围绕过孔、且与过孔分离设置的过孔焊盘，以及将过孔焊盘与过孔电连接的导电体，通过使用环形焊盘，大幅降低焊盘的容性，在某些实施过程中可实现包括但不限于提高过孔的阻抗，使其与传输线的阻抗更加匹配，从而改善了过孔和系统通道的信号完整性，同时改善了差分过孔插损大的问题。
实施例三
为了提高电路板过孔的阻抗，改善过孔和系统通道的信号完整性，以及增加信号线的走线密度，本发明实施例提供了一种电路板。图14为本发明实施例提供的一种差分过孔装置的结构示意图。
本发明实施例提供了一种电路板，电路板上有间隔1.0mm的BGA芯片扇出差分孔结构，电路板表层的差分过孔装置如图11所示，该差分过孔装置包括过孔107、过孔108，过孔焊盘207、过孔焊盘208，信号线407、信号线409以及BGA芯片焊接焊盘705和BGA芯片焊接焊盘706；电路板内层的差分过孔装置如图12所示，该差分过孔装置包括过孔107、过孔108，过孔焊盘209、过孔焊盘210，信号线408、信号线410。若信号线410采用直线走线，那么信号线410的长度明显会比408短，在一些情形中为了解决电流流经的长度不同，而导致电流的相位不同，信号线410采用如图11所示的蛇形绕线，会占用更多的走线空间，影响走线密度的提升，不利于缩小产品单板尺寸。
在本发明实施例中，过孔焊盘采用环形焊盘，通过改变导电体的位置，改变电流流经的路径，图13为本发明实施例提供的电流路径对比示意图，如图13所示，其中(a)图中电流从信号线进入焊盘后，会流经圆环所有长度，而(b)图中电流从信号线进入焊盘后立即由导体条进入过孔，同样的输入信号情况下，通过改变导电体的位置，改变电路流经信号线，到导电体再等到过孔焊盘的路径，使得最终进入过孔的信号具有明显的相位差，差分信号可以利用这一技术来达到调节走线弯折带来的相位差，而不必再进行蛇形绕线，从而可提升走线密度，提高产品竞争力。
图14为本发明实施例提供的一种差分过孔的结构。如图14所示，该差分过孔结构包括，过孔105和过孔106，围绕过孔105、且与过孔105分离设置的过孔焊盘211，围绕过孔106、且与过孔106分离设置的过孔焊盘212，将过孔105和过孔焊盘205电连接的导电体307，将过孔106和过孔焊盘206电连接的导电体308，与过孔焊盘211相连的信号线 411，与过孔焊盘212相连的信号线412。其中过孔105、过孔106的孔径均为0.2mm，过孔焊盘211、过孔焊盘212的外径均为0.4mm，环宽为1.5mil，导电体307和导电体308为条状，宽度为2mil。调节导电体307和导电体308的位置，具体来讲使电流通过信号线411，到过孔焊盘211再到导电体307再到过孔105的最短距离等于电流通过信号线412，到过孔焊盘212再到导电体308再到过孔106的最短距离相等。从而使信号线411和信号线412的长度差在过孔焊盘和导电体处得到补偿，就不再需要蛇形绕线，减小了走线占用空间。
有益效果
本发明实施例提供的一种电路板，包括电路板主体，设置于电路板主体的差分过孔装置；差分过孔装置包括在电路板主体上形成的过孔、围绕过孔、且与过孔分离设置的过孔焊盘，以及将过孔焊盘与过孔电连接的导电体，通过使用环形焊盘，大幅降低焊盘的容性，通过改变导电体的位置，使信号线的长度差得到补偿，在某些实施过程中可实现包括但不限于提高过孔的阻抗，使其与传输线的阻抗更加匹配，从而改善了过孔和系统通道的信号完整性，改善了差分过孔插损大的问题，同时不需要蛇形绕线，可减少走线占用空间，最终提升产品竞争力。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种电路板，包括电路板主体，设置于所述电路板主体上的至少一个过孔装置；
    所述过孔装置包括在所述电路板主体上形成的过孔、围绕所述过孔、且与所述过孔分离设置的过孔焊盘，以及将所述过孔焊盘与所述过孔电连接的导电体。
  2. 如权利要求1所述的电路板，其中，所述过孔焊盘为围绕所述过孔设置的环状焊盘。
  3. 如权利要求2所述的电路板，其中，所述环状焊盘为圆环焊盘。
  4. 如权利要求2所述的电路板，其中，所述环状焊盘为封闭的环状焊盘。
  5. 如权利要求1-4任一项所述的电路板，其中，所述电路板主体上设置的过孔装置中包括第一过孔装置和第二过孔装置；
    所述第一过孔装置包括第一过孔、围绕所述第一过孔且与所述第一过孔分离设置的第一过孔焊盘，以及将所述第一过孔焊盘与所述第一过孔电连接的第一导电体；
    所述第二过孔装置包括第二过孔、围绕所述第二过孔且与所述第二过孔分离设置的第二过孔焊盘，以及将所述第二过孔焊盘与所述第二过孔电连接的第二导电体。
  6. 如权利要求5所述的电路板，其中，所述电路板主体还设置有与所述第一过孔焊盘连接的第一信号线，与所述第二过孔焊盘连接的第二信号线，电流通过所述第一过孔焊盘到所述第一导电体再到所述第一过孔的最短距离为第一距离，电流通过所述第二过孔焊盘到所述第二导电体再到所述第二过孔的最短距离为第二距离。
  7. 如权利要求6所述的电路板，其中，所述第一信号线的长度大于所述第二信号线的长度，所述第一距离小于所述第二距离。
  8. 如权利要求6所述的电路板，其中，所述第一信号线的长度等于所述第二信号线的长度，所述第一距离等于所述第二距离。
  9. 如权利要求6-8任一项所述的电路板，其中，所述第一信号线和所述第二信号线的走线方式为非蛇形绕线。
  10. 如权利要求1-9任一项所述的电路板，其中，所述过孔为圆形过孔。
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