WO2020071357A1 - 接合構造体の製造方法 - Google Patents

接合構造体の製造方法

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Publication number
WO2020071357A1
WO2020071357A1 PCT/JP2019/038727 JP2019038727W WO2020071357A1 WO 2020071357 A1 WO2020071357 A1 WO 2020071357A1 JP 2019038727 W JP2019038727 W JP 2019038727W WO 2020071357 A1 WO2020071357 A1 WO 2020071357A1
Authority
WO
WIPO (PCT)
Prior art keywords
reflow
pressure
solder
test
atmosphere
Prior art date
Application number
PCT/JP2019/038727
Other languages
English (en)
French (fr)
Inventor
怜史 大谷
光康 古澤
Original Assignee
株式会社弘輝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社弘輝 filed Critical 株式会社弘輝
Priority to EP19869346.7A priority Critical patent/EP3838465B1/en
Priority to KR1020217005009A priority patent/KR102259122B1/ko
Priority to US17/276,990 priority patent/US11446752B2/en
Priority to CN201980058479.5A priority patent/CN112654453B/zh
Publication of WO2020071357A1 publication Critical patent/WO2020071357A1/ja

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/008—Soldering within a furnace
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/085—Using vacuum or low pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/086—Using an inert gas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/087—Using a reactive gas

Definitions

  • the present invention relates to a method for manufacturing a joint structure.
  • a joint structure in which a joint component such as an electronic component is joined to a substrate is formed by applying a solder paste containing a solder alloy and a flux to an electrode portion on the surface of the substrate, and then applying the solder paste to the electrode portion of the electronic component. And heating (reflow) by contacting the electrode portion on the surface of the substrate through the substrate.
  • the board and the electronic component are joined via a joint made of solder paste.
  • Patent Document 1 a method of reducing the atmosphere in a reflow furnace to a pressure lower than the atmospheric pressure and performing reflow (hereinafter also referred to as vacuum reflow) has been known (for example, Patent Document 1).
  • vacuum reflow a method of reducing the atmosphere in the reflow furnace to a pressure lower than the atmospheric pressure and performing reflow
  • the magnitude of the pressure to be reduced in the reflow furnace is increased, a large amount of voids are discharged out of the joint during reflow, so that the solder material (solder foil, solder paste, or the like) is easily scattered. As a result, there has been a problem that short-circuiting between electrodes of the joint component, contamination of the substrate, and the like occur.
  • the present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a joint structure in which voids in a joint portion are reduced and scattering of a solder material is suppressed.
  • the present inventors in the reflow step, after melting the solder alloy in a state where the atmosphere in the reflow furnace is reduced to a pressure lower than atmospheric pressure, and then reduced the pressure to a lower pressure It has been found that by melting the solder alloy by the method described above, it is possible to obtain a joint structure in which voids in the joint portion are reduced and the scattering of the solder material is suppressed.
  • the gist of the present invention is as follows.
  • the method for manufacturing a joint structure according to the present invention includes a reflow step of heating a solder material and a first member in contact with each other in a reflow furnace to melt a solder alloy forming the solder material, reflow process, a first reflow process to melt the atmosphere the solder alloy in a state of reduced pressure first to the pressure P 1 is lower than the atmospheric pressure of the reflow furnace, after the first reflow process, the reflow furnace and a second reflow process to melt the solder alloy in a state of reduced pressure as low as the second pressure P 2 than the first pressure P 1 atmosphere.
  • the first member and the second member are heated in a reflow furnace in a state where the first member and the second member are in contact with each other via a solder material, thereby forming the solder material.
  • the solder alloy may be melted.
  • a ratio (P 2 / P 1 ) of the second pressure P 2 to the first pressure P 1 is preferably 0.0017 to 0.8.
  • the method of manufacturing a joined structure according to the present invention in the first reflow process, the first hold time T 1 and held at the peak temperature, and in the second reflow process, the second holding time T 2 and held at the peak temperature,
  • the ratio (T 2 / T 1 ) of the second holding time T 2 to the first holding time T 1 is preferably 0.017 to 59.
  • the reflow step further includes, after the second reflow step, a third step of pressurizing an atmosphere in the reflow furnace to atmospheric pressure at a temperature equal to or higher than a melting point of the solder alloy. It is preferable to include a reflow step.
  • FIG. 1 is a graph showing an example of a reflow temperature profile and a change in pressure in a reflow furnace in the method for manufacturing a joined structure according to the present embodiment.
  • the solder material is heated in a reflow furnace in a state where the substrate (first member) and the joint component (second member) are in contact with each other via a solder material.
  • a reflow process to melt the solder alloy constituting the said reflow step first reflow process to melt the solder alloy in a state of reduced pressure atmosphere of the reflow furnace to a first pressure P 1 is lower than the atmospheric pressure
  • a second reflow process to melt the solder alloy in a state where the rear first reflow process and vacuum atmosphere of the reflow furnace lower to the second pressure P 2 than the first pressure P 1.
  • the solder material used in the method for manufacturing a joint structure according to the present embodiment is not particularly limited, and for example, a solder foil made of a solder alloy, a solder paste made of a solder alloy powder and a flux, or the like can be used.
  • the solder alloy include a Sn-Ag alloy, a Sn-Ag-Cu alloy (SAC alloy), a Sn-Ag-Cu-Sb alloy, a Sn-Ag-Cu-Bi alloy, and a Sn-Ag alloy.
  • solder alloys such as -Sb-based alloys, Sn-Cu-based alloys, Sn-Bi-based alloys, Sn-Zn-based alloys, Sn-In-based alloys, and Pb-Sn-based alloys can be used.
  • the flux is not particularly limited, and for example, a known flux including a base resin, an activator, a solvent, a thixotropic agent, and the like can be used.
  • Such a solder material can be arranged on the surface of the substrate (first member) by using a known method such as printing with a solder printing apparatus, transfer printing, coating with a dispenser, mounting with a mounter, or the like.
  • the substrate (first member) is not particularly limited, and for example, a known substrate such as a printed substrate, a DBC substrate, a base plate, a lead frame, and a silicon wafer can be used.
  • the joining component (second member) is arranged so as to be in contact with the substrate (first member) via the solder material.
  • the joining component (second member) is not particularly limited, and is, for example, a known joining component such as a chip component (such as an IC chip), a resistor, a diode, a capacitor, a transistor, a semiconductor chip (such as a Si chip), and a heat sink. Can be used.
  • the method for manufacturing a joint structure according to the present embodiment exhibits excellent effects even when a Si chip is used as the joint component.
  • the method for manufacturing the joined structure according to the present embodiment is not limited to the first member being the substrate.
  • the first member other than the substrate include a chip component (such as an IC chip), a resistor, a diode, a capacitor, a transistor, a semiconductor chip (such as a Si chip), and a heat sink.
  • the method for manufacturing a joint structure according to the present embodiment is not limited to the second member being a joint component.
  • the second member other than the joining component include a printed board, a DBC board, a base plate, a lead frame, a heat sink, and the like.
  • the solder material and the first member are heated in contact with each other without using the second member, and the solder alloy constituting the solder material is melted. Is also good.
  • the joint structure formed in this manner include a solder bump and the like.
  • the substrate (first member) and the joint component (second member) that have come into contact with each other via the solder material are arranged in a reflow furnace.
  • the reflow furnace has a shutter that can be opened and closed, and the furnace can be hermetically closed by closing the shutter. Further, in the reflow furnace, the atmosphere in the furnace can be reduced to about 10 Pa by exhausting the gas in the furnace using a vacuum pump. Further, an inert gas such as nitrogen and a reducing gas such as formic acid and hydrogen can be introduced into the reflow furnace.
  • the reflow furnace in which the substrate (first member) and the joining component (second member) that are in contact with each other via the solder material are arranged, exhausts the gas in the reflow furnace, and then purges an inert gas such as nitrogen. It is preferable to reduce the oxygen concentration in the reflow furnace by repeating the step of introducing.
  • FIG. 1 is a graph showing an example of a reflow temperature profile and a change in pressure in a reflow furnace in the method for manufacturing a joined structure according to the present embodiment.
  • the atmosphere in the reflow furnace to melt the solder alloy in a state of reduced pressure first to 1 pressure P 1 is lower than atmospheric pressure (first reflow process).
  • first reflow process the atmosphere in the reflow furnace to melt the solder alloy in a state of reduced pressure first to 1 pressure P 1 is lower than atmospheric pressure (first reflow process).
  • heating the reflow furnace, before the solder alloy melts i.e., before reaching the melting point of the solder reflow temperature alloys
  • reducing the pressure of the atmosphere in the reflow furnace to a first pressure P 1 is lower than the atmospheric pressure .
  • the heating rate is not particularly limited and can be appropriately selected according to the solder material, and can be, for example, in the range of 0.5 to 5.0 ° C./s.
  • the first pressure P 1 is not particularly limited and may be suitably selected in accordance with the solder material, for example, it can be in the range of 200 Pa ⁇ 30000 Pa.
  • T 1 holds the first hold time.
  • the peak temperature is not particularly limited and can be appropriately selected depending on the solder material, and can be, for example, in the range of 230 to 400 ° C.
  • the first hold time T 1 is not particularly limited and may be suitably selected in accordance with the solder material, for example, be in the range of 10 ⁇ 300 s, preferably a range of 30 ⁇ 120s can do.
  • the manufacturing method of the bonded structure of the present embodiment although the solder alloy is subjected to reduced pressure to the first pressure P 1 before melting, is not limited thereto, the solder alloy is melted from the start, i.e., it may initiate a vacuum to said first pressure P 1 after becoming higher than the melting point of the solder reflow temperature alloys.
  • a method of manufacturing a joined structure according to the present embodiment has been first hold time T 1 held at the peak temperature, it is not limited thereto, it may not be performed held at the peak temperature.
  • the second pressure P 2 is not particularly limited and may be suitably selected in accordance with the solder material, for example, it can be in the range of 50 Pa ⁇ 5000 Pa.
  • T 2 After depressurizing the atmosphere in the reflow furnace to a second pressure P 2, with keeping the reflow temperature to a peak temperature, T 2 holds the second holding time.
  • the peak temperature can be in the same range as the peak temperature in the first reflow step.
  • the second holding time T 2 are not particularly limited and may be suitably selected in accordance with the solder material, for example, be in the range of 10 ⁇ 300 s, preferably a range of 30 ⁇ 120s can do.
  • the second holding time T 2 was held at the peak temperature, it is not limited thereto, it may not be performed held at the peak temperature.
  • the ratio (P 2 / P 1 ) of the second pressure P 2 to the first pressure P 1 is preferably 0.0017 or more, and more preferably 0.8 or less. Further, the ratio P 2 / P 1 is more preferably 0.05 or more, particularly preferably 0.1 or more, more preferably 0.5 or less, and 0.25 or less. Is particularly preferred.
  • the ratio (T 2 / T 1 ) of the second holding time T 2 to the first holding time T 1 is preferably 0.017 or more, and more preferably 59 or less. Further, T 2 / T 1 is more preferably 0.33 or more, and more preferably 3 or less.
  • the atmosphere in the reflow furnace is pressurized to an atmospheric pressure at a temperature equal to or higher than the melting point of the solder alloy (third reflow step).
  • the pressure can be increased to the atmospheric pressure by introducing an inert gas such as nitrogen into the reflow furnace.
  • the atmosphere in the reflow furnace is pressurized to atmospheric pressure at a temperature equal to or higher than the melting point of the solder alloy, but is not limited thereto.
  • the atmosphere in the reflow furnace may be pressurized to atmospheric pressure at a temperature lower than the melting point of the solder alloy.
  • a preheating step may be performed before the above-described reflow step.
  • the preheating step is performed, for example, by heating and holding the substrate and the bonding component contacted via the solder material to a preheating temperature in the reflow furnace.
  • the preheating temperature is not particularly limited and can be appropriately selected depending on the solder material, and can be, for example, in the range of 120 to 310 ° C.
  • the holding time at the preheating temperature is not particularly limited and can be appropriately selected depending on the solder material, and can be, for example, in a range of 0 to 900 s.
  • the gas in the reflow furnace may be evacuated using a vacuum pump while maintaining the preheat temperature, and then the atmosphere in the reflow furnace may be pressurized to atmospheric pressure.
  • a reducing gas such as formic acid or hydrogen may be introduced.
  • the introduction of the reducing gas may be started before exhausting the gas in the reflow furnace, and may be continuously introduced in the preheating step.
  • the gas in the reflow furnace may be evacuated using a vacuum pump, and then a reducing gas such as formic acid or hydrogen may be introduced.
  • the method for manufacturing a joint structure includes a reflow step of heating a solder material and a first member in contact with each other in a reflow furnace and melting a solder alloy constituting the solder material, the reflow process, a first reflow process to melt the solder alloy in a state of reduced pressure atmosphere in the reflow furnace to a first pressure P 1 is lower than the atmospheric pressure, after the first reflow process, the atmosphere in the reflow furnace and a second reflow process to melt the solder alloy in a state where the pressure was reduced to lower the second pressure P 2 than the first pressure P 1.
  • the second reflow step small voids remaining in the joint in the first reflow step can be discharged out of the joint.
  • the second reflow process the comparison with the first reflow process, the amount of voids is discharged to the outside of the joint is small, vacuum wherein to a second pressure P 2 lower than the first pressure P 1 Even if it does, the scattering of the solder material can be suppressed.
  • the reflow step is configured such that the first member and the second member are heated in a reflow furnace in a state where the first member and the second member are in contact with each other via a solder material, thereby forming the solder material. May be melted. Also in such a configuration, it is possible to reduce voids in the joint portion and suppress scattering of the solder material.
  • a ratio (P 2 / P 1 ) of the second pressure P 2 to the first pressure P 1 is preferably 0.0017 to 0.8.
  • the method of manufacturing a joined structure according to the present embodiment in the first reflow process, the first hold time T 1 and held at the peak temperature, and in the second reflow process, the second holding time T 2 and held at peak temperature
  • the ratio (T 2 / T 1 ) of the second holding time T 2 to the first holding time T 1 is preferably 0.017 to 59.
  • the reflow step further includes: after the second reflow step, pressurizing the atmosphere in the reflow furnace to atmospheric pressure at a temperature equal to or higher than the melting point of the solder alloy. It is preferable to include three reflow steps. With such a configuration, it is possible to obtain a bonded structure in which voids in the bonded portion are further reduced.
  • Test 1 ⁇ Preparation of test board> (Test Nos. 1-1 to 1-14)
  • a substrate of an oxygen-free Cu plate (size: 44 ⁇ 35 mm) via a solder foil (size: 10 ⁇ 10 mm, thickness: 100 ⁇ m) made of alloy A (96.5Sn / 3.0Ag / 0.5Cu); It was placed in a reflow furnace of a reflow apparatus (trade name: VS1, manufactured by Origin Electric Co.) in a state of contact with an Au / Ni-plated Si chip (size: 10 ⁇ 10 mm). Then, by performing a preheating step and a reflow step described later, the test No. Test substrates 1-1 to 1-14 were produced.
  • the preheating step first, heating was performed at a heating rate of 1.7 ° C / s to a preheating temperature of 200 ° C in a nitrogen atmosphere. Then, at the preheating temperature, the gas in the reflow furnace is evacuated using a vacuum pump and maintained for 30 seconds, and then the formic acid (3%) is introduced to pressurize the atmosphere in the reflow furnace to atmospheric pressure and maintained for 240 seconds. did.
  • the reflow step first, after reducing the pressure of the atmosphere in the reflow furnace to the first pressure P 1, and heated to a peak temperature 250 ° C. at a heating rate of 2.6 ° C. / s, the first hold time T 1 holding (First reflow step). Then, after reducing the pressure of the atmosphere in the reflow furnace to a second pressure P 2, the second holding time T 2 holds (second reflow process). Finally, at a peak temperature of 250 ° C., the pressure was increased to atmospheric pressure by introducing nitrogen into the reflow furnace. Table 1 shows detailed conditions of the first reflow step and the second reflow step.
  • Test Nos. 2-1 to 2-6 Except that the second reflow step was not performed, test Nos. Test Nos. As in the case of 1-1 to 1-14. Test substrates 2-1 to 2-6 were produced. Table 1 shows detailed conditions of the reflow process.
  • Test No. 1-15 A Ni-plated Cu plate (size: 44 ⁇ 35 mm) through a solder foil (size: 15 ⁇ 15 mm, thickness: 100 ⁇ m) made of alloy A (96.5Sn / 3.0Ag / 0.5Cu); It was placed in a reflow furnace of a reflow apparatus (trade name: VS1, manufactured by Origin Electric Co.) in a state of contact with a Ni plate (size: 15 ⁇ 15 mm). In the reflow process, test No. 1 was performed except that the temperature was raised to the peak temperature at the atmospheric pressure, and after reaching the peak temperature, the pressure was reduced to the first pressure P1. Test substrates were prepared in the same manner as in 1-1 to 1-14. Table 1 shows detailed conditions of the reflow process.
  • test No. 2--7 Except that the second reflow step was not performed, test Nos.
  • a test substrate was prepared in the same manner as in 1-15. Table 1 shows detailed conditions of the reflow process.
  • ⁇ Void evaluation> An X-ray transmission photograph was taken at the mounting location of the Si chip on each test substrate.
  • the imaging apparatus used was TUX-3100 (manufactured by Mars Token Co.), and the imaging conditions were: tube voltage: 75.0 V, tube current: 80.0 ⁇ A, filament current: 3.130 A.
  • the photographed photograph was binarized to calculate the void ratio of the joint.
  • the test No. The test substrates Nos. 1-1 to 1-14 are test Nos.
  • test substrates 2-1 to 2-6 the value of the first pressure P 1 in the first reflow step, and the total holding time (T 1 + T 2) at the peak temperature in the first reflow step and the second reflow step ) was compared with a test substrate having the same value, thereby calculating a reduction rate of the void fraction.
  • Table 1 shows the results.
  • Test Nos Satisfying all the constituent requirements of the present invention.
  • the test substrates No. 1-1 to 1-15 have the test Nos. In which the second reflow step is not performed. Compared with the test substrates 2-1 to 2-7, the voids at the joints can be reduced and the scattering of the solder material can be suppressed.
  • Test board 2 ⁇ Preparation of test board> (Test No. 3-1) First, an alloy A (96.5Sn / 3.0Ag / 0.5Cu) powder and a flux (2-ethyl-1,3-hexanediol: 90% by mass, stearamide: 10% by mass) were mixed and soldered. A paste was made. Next, the solder paste was applied to a substrate of an oxygen-free Cu plate (size: 44 ⁇ 35 mm) using a 200 ⁇ m-thick metal mask so as to have an aperture ratio of 100%. The thickness of the applied solder paste was 200 ⁇ m.
  • an Au / Ni-plated Si chip (size: 10 ⁇ 10 mm) is mounted, and a substrate of an oxygen-free Cu plate (size: 44 ⁇ 35 mm) and an Au / Ni-plated Si chip are mounted via the solder paste.
  • the chip (size: 10 ⁇ 10 mm) was placed in a reflow furnace of a reflow apparatus (trade name: VS1, manufactured by Origin Electric Co.) in a state of contact with the chip (size: 10 ⁇ 10 mm). Then, by performing a preheating step and a reflow step described later, the test No. A test substrate 3-1 was produced.
  • the reflow step first, after reducing the pressure of the atmosphere in the reflow furnace to the first pressure P 1, and heated to a peak temperature 250 ° C. at a heating rate of 2.6 ° C. / s, the first hold time T 1 holding (First reflow step). Then, after reducing the pressure of the atmosphere in the reflow furnace to a second pressure P 2, the second holding time T 2 holds (second reflow process). Finally, at a peak temperature of 250 ° C., the pressure was increased to atmospheric pressure by introducing nitrogen into the reflow furnace. Table 2 shows detailed conditions of the reflow process.
  • test No. 3-2 Except that the preheating step was performed in a nitrogen atmosphere, test Nos. A test substrate was prepared in the same manner as in 3-1.
  • Test No. 3-3 Without preheating step, the under formic acid atmosphere, after reducing the pressure of the atmosphere in the reflow furnace to the first pressure P 1, except that heated to a peak temperature, Test No. A test substrate was prepared in the same manner as in 3-1.
  • Test No. 3-4 Test No. 2 was conducted except that alloy B (89.0 Sn / 3.0 Ag / 8.0 Sb) was used as the solder powder and the peak temperature in the reflow process was changed.
  • a test substrate was prepared in the same manner as in 3-1.
  • Test No. 1 was performed except that alloy C (95.0 Pb / 5.0 Sn) was used as the solder powder, the preheating holding temperature was 230 ° C., and the first pressure P 1 and the peak temperature in the reflow process were changed.
  • a test substrate was prepared in the same manner as in 3-1. Table 2 shows detailed conditions of the reflow process.
  • Test Nos. 4-1 to 4-5 Except that the second reflow step was not performed, each of Test Nos. Test Nos. As in 3-1 to 3-5. Test substrates 4-1 to 4-5 were produced. Table 2 shows detailed conditions of the reflow process.
  • the test substrates Nos. 3-1 to 3-5 have the test Nos. In which the second reflow step is not performed. Compared to the test substrates 4-1 to 4-5, voids at the joints can be reduced, and scattering of the solder material can be suppressed.
  • solder paste was prepared by mixing alloy A (96.5Sn / 3.0Ag / 0.5Cu) powder and flux.
  • a paste flux product name: paste flux (RMA type) manufactured by KOKI Co., Ltd.
  • a glass epoxy substrate size: 50 ⁇ 50 mm, thickness: 1.6 mm
  • preflux trade name “Tough Ace”, manufactured by Shikoku Chemicals
  • the solder paste was applied to the substrate using a 150 ⁇ m-thick metal mask so as to have an aperture ratio of 400%, and placed in a reflow furnace of a reflow apparatus (trade name: VS1, manufactured by Origin Electric Co., Ltd.).
  • the thickness of the applied solder paste was 150 ⁇ m. Then, by performing a preheating step and a reflow step described later, the test No. 5 test substrates were produced.
  • the preheating step first, heating was performed at a heating rate of 1.7 ° C / s to a preheating temperature of 200 ° C in a nitrogen atmosphere. Then, at this preheating temperature, the gas in the reflow furnace is evacuated using a vacuum pump and maintained for 30 seconds, and then the formic acid (3%) is introduced to pressurize the atmosphere in the reflow furnace to atmospheric pressure and maintained for 240 seconds. did.
  • the reflow furnace was heated to a peak temperature of 250 ° C. at a temperature increasing rate of 2.6 ° C./s, and then heated for 60 s (first pressure P 1 ). Holding time T 1 ) was held (first reflow step).
  • second pressure P 2 the atmosphere was held for 60 s (second holding time T 2 ) (second reflow step).
  • the pressure was increased to atmospheric pressure by introducing nitrogen into the reflow furnace. Table 3 shows the conditions of the first reflow step and the second reflow step.
  • Test No. 6 Except that the second reflow step was not performed, test Nos. As in Test No. 5, 6 test substrates were produced. Table 3 shows detailed conditions of the reflow process.
  • Test Nos. Satisfying all the constituent requirements of the present invention.
  • the test substrate of Test No. 5 which does not perform the second reflow process is the test substrate of Test No. 5.
  • the voids at the joints can be reduced and the scattering of the solder material can be suppressed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本発明に係る接合構造体の製造方法は、リフロー炉内で、はんだ材料と第１部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させるリフロー工程を備え、前記リフロー工程は、前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態で前記はんだ合金を溶融させる第１リフロー工程と、前記第１リフロー工程後、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態で前記はんだ合金を溶融させる第２リフロー工程と、を含む。

Description

接合構造体の製造方法 関連出願の相互参照
　本願は、日本国特願２０１８－１８６５７４号の優先権を主張し、引用によって本願明細書の記載に組み込まれる。
　本発明は、接合構造体の製造方法に関する。
　電子部品等の接合部品が基板に接合された接合構造体は、例えば、はんだ合金とフラックスとを含むソルダペーストを基板表面の電極部に塗布し、その後、電子部品の電極部を、前記ソルダペーストを介して前記基板表面の電極部に接触させて加熱（リフロー）することにより、製造することができる。このような接合構造体は、ソルダペーストからなる接合部を介して、基板と電子部品とが接合される。
　従来、このような接合構造体では、リフロー時に発生するガスが接合部中にボイド（気泡）となって残存することが問題となっていた。特に、接合部品としてＳｉチップを用いた接合構造体では、接合部中に多量のボイドが発生することが知られている。接合部中にボイドが存在すると、接合部品と基板との接触面積が低下して電気抵抗が増加するため、接合構造体の電気的な信頼性を損なう。また、接合部中のボイドは熱伝導を妨げるため、接合構造体の放熱性を低下させる。
　近年、リフロー炉内の雰囲気を大気圧よりも低い圧力に減圧してリフロー（以下、真空リフローともいう）を行う方法が知られている（例えば、特許文献１）。当該方法では、リフロー炉内の雰囲気を減圧することにより、接合部中に形成されたボイドが膨張して接合部の外へ排出されやすくなるため、接合部中のボイドを低減することができる。
国際公開第２０１７／０５７６５１号
　真空リフローでは、リフロー炉内において減圧する圧力の大きさが大きいほど、ボイドが接合部の外へ排出されやすくなるため、結果として、接合部中のボイドをより低減することができる。しかしながら、リフロー炉内において減圧する圧力の大きさを大きくすると、リフロー時にボイドが多量に接合部の外へ排出されるため、はんだ材料（はんだ箔、ソルダペースト等）が飛散しやすくなる。その結果、接合部品の電極間のショート、基板の汚染等を生じさせるという問題があった。このような問題は、接合部品がはんだ材料を介して基板に接合された接合構造体だけでなく、基板にはんだ材料を塗布することにより形成された接合構造体（例えば、はんだバンプ等）でも生じていた。
　本発明は、上記事情に鑑みてなされたものであり、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制した接合構造体の製造方法を提供することを課題とする。
　はんだ溶融直後は、ガスが多量に発生し、接合部中に形成されたボイド内部の圧力が高くなる。これにより、ボイドは膨張し、接合部の外へ排出されやすくなる。一方、はんだが溶融してある程度の時間が経過すると、ガスの発生量が少なくなり、接合部中に形成されたボイド内部の圧力とリフロー炉内の圧力との差が小さくなる。これにより、ボイドは接合部の外へ排出されにくくなり、結果として、接合部中に小さなボイドとして残存する。このような事情に鑑みて、本発明者らは、リフロー工程において、リフロー炉内の雰囲気を大気圧よりも低い圧力まで減圧した状態ではんだ合金を溶融させた後、さらに低い圧力まで減圧した状態ではんだ合金を溶融させることにより、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制した接合構造体が得られることを見出した。本発明の要旨は、以下の通りである。
　本発明に係る接合構造体の製造方法は、リフロー炉内で、はんだ材料と第１部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させるリフロー工程を備え、前記リフロー工程は、前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態で前記はんだ合金を溶融させる第１リフロー工程と、前記第１リフロー工程後、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態で前記はんだ合金を溶融させる第２リフロー工程と、を含む。
　本発明に係る接合構造体の製造方法において、前記リフロー工程は、リフロー炉内で、はんだ材料を介して第１部材と第２部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させてもよい。
　本発明に係る接合構造体の製造方法において、前記第１圧力Ｐ１に対する前記第２圧力Ｐ２の比（Ｐ２／Ｐ１）は、０．００１７～０．８であることが好ましい。
　本発明に係る接合構造体の製造方法において、前記第１リフロー工程では、ピーク温度で第１保持時間Ｔ１保持し、前記第２リフロー工程では、ピーク温度で第２保持時間Ｔ２保持し、前記第１保持時間Ｔ１に対する前記第２保持時間Ｔ２の比（Ｔ２／Ｔ１）は、０．０１７～５９であることが好ましい。
　本発明に係る接合構造体の製造方法において、前記リフロー工程は、さらに、前記第２リフロー工程後、前記はんだ合金の融点以上の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧する第３リフロー工程を含むことが好ましい。
図１は、本実施形態に係る接合構造体の製造方法におけるリフロー温度プロファイル及びリフロー炉内の圧力変化の一例を示すグラフである。
　以下、本発明の実施形態に係る接合構造体の製造方法について説明する。
　＜接合構造体の製造方法＞
　本実施形態に係る接合構造体の製造方法は、リフロー炉内で、はんだ材料を介して基板（第１部材）と接合部品（第２部材）とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させるリフロー工程を備え、前記リフロー工程は、前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態で前記はんだ合金を溶融させる第１リフロー工程と、前記第１リフロー工程後、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態で前記はんだ合金を溶融させる第２リフロー工程と、を含む。
　本実施形態に係る接合構造体の製造方法に用いられるはんだ材料としては、特に限定されず、例えば、はんだ合金からなるはんだ箔、はんだ合金粉末とフラックスとからなるソルダペースト等を用いることができる。前記はんだ合金としては、例えば、Ｓｎ－Ａｇ系合金、Ｓｎ－Ａｇ－Ｃｕ系合金（ＳＡＣ系合金）、Ｓｎ－Ａｇ－Ｃｕ－Ｓｂ系合金、Ｓｎ－Ａｇ－Ｃｕ－Ｂｉ系合金、Ｓｎ－Ａｇ－Ｓｂ系合金、Ｓｎ－Ｃｕ系合金、Ｓｎ－Ｂｉ系合金、Ｓｎ－Ｚｎ系合金、Ｓｎ－Ｉｎ系合金、Ｐｂ－Ｓｎ系合金等の公知のはんだ合金を用いることができる。前記フラックスとしては、特に限定されず、例えば、ベース樹脂、活性剤、溶剤、チキソ剤等を含む公知のフラックスを用いることができる。
　このようなはんだ材料は、はんだ印刷装置による印刷、転写印刷、ディスペンサーによる塗布、マウンターによる搭載等の公知の方法を用いて、基板（第１部材）の表面に配置することができる。前記基板（第１部材）としては、特に限定されず、例えば、プリント基板、ＤＢＣ基板、ベースプレート板、リードフレーム、シリコンウエハ等の公知の基板を用いることができる。
　そして、前記はんだ材料を介して前記基板（第１部材）と接触するように、前記接合部品（第２部材）を配置する。前記接合部品（第２部材）としては、特に限定されず、例えば、チップ部品（ＩＣチップ等）、抵抗器、ダイオード、コンデンサ、トランジスタ、半導体チップ（Ｓｉチップ等）、ヒートシンク等の公知の接合部品を用いることができる。特に、本実施形態に係る接合構造体の製造方法は、前記接合部品としてＳｉチップを用いた場合にも、優れた効果を発揮する。
　ここで、本実施形態に係る接合構造体の製造方法は、第１部材が基板であることに限定されるものではない。基板以外の第１部材としては、例えば、チップ部品（ＩＣチップ等）、抵抗器、ダイオード、コンデンサ、トランジスタ、半導体チップ（Ｓｉチップ等）、ヒートシンク等が挙げられる。また、本実施形態に係る接合構造体の製造方法は、第２部材が接合部品であることに限定されるものではない。接合部品以外の第２部材としては、例えば、プリント基板、ＤＢＣ基板、ベースプレート、リードフレーム、ヒートシンク等が挙げられる。
　なお、本実施形態に係る接合構造体の製造方法では、第２部材を用いず、はんだ材料と第１部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させてもよい。このようにして形成される接合構造体としては、例えば、はんだバンプ等が挙げられる。
　はんだ材料を介して接触した基板（第１部材）と接合部品（第２部材）とは、リフロー炉内に配置される。当該リフロー炉は、開閉可能なシャッターを有しており、当該シャッターを閉めることにより、炉内を密閉することができる。また、前記リフロー炉は、真空ポンプを用いて炉内の気体を排気することにより、炉内の雰囲気を１０Ｐａ程度まで減圧することができる。さらに、前記リフロー炉内には、窒素等の不活性ガス、ギ酸、水素等の還元ガス等を導入することができる。
　なお、はんだ材料を介して接触した基板（第１部材）と接合部品（第２部材）とを配置した前記リフロー炉は、該リフロー炉内の気体を排気した後、窒素等の不活性ガスを導入する工程を繰り返すことにより、前記リフロー炉内の酸素濃度を低下させておくことが好ましい。
　次に、リフロー炉内で、前記はんだ材料を介して前記基板（第１部材）と前記接合部品（第２部材）とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させる（リフロー工程）。図１は、本実施形態に係る接合構造体の製造方法におけるリフロー温度プロファイル及びリフロー炉内の圧力変化の一例を示すグラフである。
　前記リフロー工程では、まず、前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態で前記はんだ合金を溶融させる（第１リフロー工程）。以下、前記第１リフロー工程について、詳細に説明する。
　まず、リフロー炉内を加熱し、はんだ合金が溶融する前、すなわち、リフロー温度がはんだ合金の融点に達する前に、前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧する。はんだ合金が溶融する前に前記第１圧力Ｐ１への減圧を行うことにより、はんだ材料の飛散をより抑制することができる。なお、昇温速度は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、０．５～５．０℃／ｓの範囲とすることができる。また、前記第１圧力Ｐ１は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、２００Ｐａ～３００００Ｐａの範囲とすることができる。
　続いて、リフロー炉内をさらに加熱し、リフロー温度がピーク温度に達した後、第１保持時間Ｔ１保持する。前記ピーク温度は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、２３０～４００℃の範囲とすることができる。また、前記第１保持時間Ｔ１は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、１０～３００ｓの範囲とすることができ、好ましくは、３０～１２０ｓの範囲とすることができる。
　なお、本実施形態に係る接合構造体の製造方法は、はんだ合金が溶融する前に前記第１圧力Ｐ１への減圧を行ったが、これに限定されるものではなく、はんだ合金が溶融し始めてから、すなわち、リフロー温度がはんだ合金の融点以上になってから前記第１圧力Ｐ１への減圧を開始してもよい。
　また、本実施形態に係る接合構造体の製造方法は、ピーク温度で第１保持時間Ｔ１保持したが、これに限定されるものではなく、ピーク温度での保持を行わなくてもよい。
　前記リフロー工程では、前記第１リフロー工程後、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態で前記はんだ合金を溶融させる（第２リフロー工程）。以下、前記第２リフロー工程について、詳細に説明する。
　まず、前記第１リフロー工程において第１保持時間Ｔ１での保持が終了した後、リフロー温度をピーク温度に保つとともに、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧する。前記第２圧力Ｐ２は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、５０Ｐａ～５０００Ｐａの範囲とすることができる。
　前記リフロー炉内の雰囲気を第２圧力Ｐ２まで減圧した後、リフロー温度をピーク温度に保つとともに、第２保持時間Ｔ２保持する。前記ピーク温度は、前記第１リフロー工程におけるピーク温度と同様の範囲とすることができる。また、前記第２保持時間Ｔ２は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、１０～３００ｓの範囲とすることができ、好ましくは、３０～１２０ｓの範囲とすることができる。
　なお、本実施形態に係る接合構造体の製造方法は、ピーク温度で第２保持時間Ｔ２保持したが、これに限定されるものではなく、ピーク温度での保持を行わなくてもよい。
　前記第１圧力Ｐ１に対する前記第２圧力Ｐ２の比（Ｐ２／Ｐ１）は、０．００１７以上であることが好ましく、０．８以下であることが好ましい。また、前記Ｐ２／Ｐ１は、０．０５以上であることがより好ましく、０．１以上であることが特に好ましく、０．５以下であることがより好ましく、０．２５以下であることが特に好ましい。
　前記第１保持時間Ｔ１に対する前記第２保持時間Ｔ２の比（Ｔ２／Ｔ１）は、０．０１７以上であることが好ましく、５９以下であることが好ましい。また、前記Ｔ２／Ｔ１は、０．３３以上であることがより好ましく、３以下であることがより好ましい。
　前記リフロー工程では、さらに、前記第２リフロー工程後、前記はんだ合金の融点以上の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧する（第３リフロー工程）。具体的には、リフロー炉内に窒素等の不活性ガスを導入することにより大気圧まで加圧することができる。
　なお、本実施形態に係る接合構造体の製造方法では、前記はんだ合金の融点以上の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧したが、これに限定されるものではなく、前記はんだ合金の融点未満の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧してもよい。
　本実施形態に係る接合構造体の製造方法は、上述のリフロー工程の前に、予熱工程を行ってもよい。前記予熱工程は、例えば、前記リフロー炉内で、前記はんだ材料を介して接触させた前記基板と前記接合部品とを予熱温度まで加熱して保持することにより行う。前記予熱温度は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、１２０～３１０℃の範囲とすることができる。また、前記予熱温度における保持時間は、特に限定されず、はんだ材料に応じて適宜選択することができ、例えば、０～９００ｓの範囲とすることができる。
　前記予熱工程では、前記予熱温度での保持中に、真空ポンプを用いて前記リフロー炉内の気体を排気し、保持した後、前記リフロー炉内の雰囲気を大気圧まで加圧してもよい。また、前記リフロー炉内の雰囲気を大気圧まで加圧する際、ギ酸、水素等の還元ガスを導入してもよい。前記予熱工程において、前記リフロー炉内に還元ガスを導入することにより、上述のリフロー工程において、接合部におけるボイドをより低減することができる。なお、前記還元ガスは、前記リフロー炉内の気体を排気する前に導入を開始し、前記予熱工程において連続して導入し続けてもよい。また、前記予熱工程を開始する前に、真空ポンプを用いて前記リフロー炉内の気体を排気した後、ギ酸、水素等の還元ガスを導入してもよい。
　本実施形態に係る接合構造体の製造方法では、リフロー炉内で、はんだ材料と第１部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させるリフロー工程を備え、前記リフロー工程は、リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態ではんだ合金を溶融させる第１リフロー工程と、該第１リフロー工程後、リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態ではんだ合金を溶融させる第２リフロー工程と、を含む。これにより、前記第２リフロー工程では、前記第１リフロー工程において接合部に残った小さなボイドを、接合部の外へ排出することができる。その結果、接合部におけるボイドを低減することができる。また、前記第２リフロー工程では、前記第１リフロー工程に比べて、接合部の外へ排出されるボイドの量が少ないため、前記第１圧力Ｐ１よりも低い前記第２圧力Ｐ２まで減圧したとしても、はんだ材料の飛散を抑制することができる。
　本実施形態に係る接合構造体の製造方法において、前記リフロー工程は、リフロー炉内で、はんだ材料を介して第１部材と第２部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させてもよい。斯かる構成においても、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制することができる。
　本実施形態に係る接合構造体の製造方法において、前記第１圧力Ｐ１に対する前記第２圧力Ｐ２の比（Ｐ２／Ｐ１）は、０．００１７～０．８であることが好ましい。斯かる構成により、接合部におけるボイドをより低減し、かつ、はんだ材料の飛散をより抑制した接合構造体が得られる。
　本実施形態に係る接合構造体の製造方法において、前記第１リフロー工程では、ピーク温度で第１保持時間Ｔ１保持し、前記第２リフロー工程では、ピーク温度で第２保持時間Ｔ２保持し、前記第１保持時間Ｔ１に対する前記第２保持時間Ｔ２の比（Ｔ２／Ｔ１）は、０．０１７～５９であることが好ましい。斯かる構成により、接合部におけるボイドをより低減し、かつ、はんだ材料の飛散をより抑制した接合構造体が得られる。
　本実施形態に係る接合構造体の製造方法において、前記リフロー工程は、さらに、前記第２リフロー工程後、前記はんだ合金の融点以上の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧する第３リフロー工程を含むことが好ましい。斯かる構成により、接合部におけるボイドをより低減した接合構造体が得られる。
　以下、本発明の実施例について説明するが、本発明は、以下の実施例に限定されるものではない。
　［試験１］
　＜試験基板の作製＞
　（試験Ｎｏ．１－１～１－１４）
　合金Ａ（９６．５Ｓｎ／３．０Ａｇ／０．５Ｃｕ）からなるはんだ箔（サイズ：１０×１０ｍｍ、厚さ：１００μｍ）を介して、無酸素Ｃｕ板（サイズ：４４×３５ｍｍ）の基板と、Ａｕ／ＮｉめっきされたＳｉチップ（サイズ：１０×１０ｍｍ）とが接触した状態でリフロー装置（商品名：ＶＳ１、オリジン電気社製）のリフロー炉内に配置した。そして、後述する予熱工程及びリフロー工程を行うことにより、試験Ｎｏ．１－１～１－１４の試験基板を作製した。
　予熱工程では、まず、窒素雰囲気下において、昇温速度１．７℃／ｓで予熱温度２００℃まで加熱した。そして、該予熱温度において、真空ポンプを用いてリフロー炉内の気体を排気して３０ｓ保持した後、ギ酸（３％）を導入することによりリフロー炉内の雰囲気を大気圧まで加圧して２４０ｓ保持した。
　続いて、リフロー工程では、まず、リフロー炉内の雰囲気を第１圧力Ｐ１へ減圧した後、昇温速度２．６℃／ｓでピーク温度２５０℃まで加熱し、第１保持時間Ｔ１保持した（第１リフロー工程）。次に、リフロー炉内の雰囲気を第２圧力Ｐ２まで減圧した後、第２保持時間Ｔ２保持した（第２リフロー工程）。最後に、ピーク温度２５０℃にて、リフロー炉内に窒素を導入することにより大気圧まで加圧した。前記第１リフロー工程及び前記第２リフロー工程の詳細な条件を表１に示す。
　（試験Ｎｏ．２－１～２－６）
　前記第２リフロー工程を行わなかったこと以外は、試験Ｎｏ．１－１～１－１４と同様に試験Ｎｏ．２－１～２－６の試験基板を作製した。リフロー工程の詳細な条件を表１に示す。
　（試験Ｎｏ．１－１５）
　合金Ａ（９６．５Ｓｎ／３．０Ａｇ／０．５Ｃｕ）からなるはんだ箔（サイズ：１５×１５ｍｍ、厚さ：１００μｍ）を介して、ＮｉめっきＣｕ板（サイズ：４４×３５ｍｍ）の基板と、Ｎｉ板（サイズ：１５×１５ｍｍ）とが接触した状態でリフロー装置（商品名：ＶＳ１、オリジン電気社製）のリフロー炉内に配置した。リフロー工程では、ピーク温度まで大気圧で昇温し、ピーク温度に到達してから第１圧力Ｐ１へ減圧を行ったこと以外は、試験Ｎｏ．１－１～１－１４と同様に試験基板を作製した。リフロー工程の詳細な条件を表１に示す。
　（試験Ｎｏ．２－７）
　前記第２リフロー工程を行わなかったこと以外は、試験Ｎｏ．１－１５と同様に試験基板を作製した。リフロー工程の詳細な条件を表１に示す。
　＜ボイド評価＞
　各試験基板のＳｉチップ搭載箇所におけるＸ線透過写真を撮影した。撮影装置はＴＵＸ－３１００（マース東研社製）を用い、撮影条件は管電圧：７５．０Ｖ、管電流：８０．０μＡ、フィラメント電流：３．１３０Ａとした。次に、撮影した写真を二値化処理することにより、接合部のボイド率を算出した。なお、試験Ｎｏ．１－１～１－１４の試験基板は、試験Ｎｏ．２－１～２－６の試験基板のうち、第１リフロー工程における第１圧力Ｐ１の値、並びに、第１リフロー工程及び第２リフロー工程におけるピーク温度での合計保持時間（Ｔ１＋Ｔ２）が等しい試験基板と比較することにより、ボイド率の低減率を算出した。結果を表１に示す。
　＜飛散評価＞
　各試験基板を上面から目視で観察し、下記の基準に基づき評価した。
　◎：飛散がほとんど無かった。
　○：飛散がわずかに確認された。
　×：飛散が多く確認された。
Figure JPOXMLDOC01-appb-T000001
　表１の結果から分かるように、本発明の構成要件をすべて満たす試験Ｎｏ．１－１～１－１５の試験基板は、第２リフロー工程を行わない試験Ｎｏ．２－１～２－７の試験基板と比較して、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制することができる。
　［試験２］
　＜試験基板の作製＞
　（試験Ｎｏ．３－１）
　まず、合金Ａ（９６．５Ｓｎ／３．０Ａｇ／０．５Ｃｕ）粉末とフラックス（２－エチルー１，３－ヘキサンジオール：９０質量％、ステアリン酸アミド：１０質量％）とを混合して、ソルダペーストを作製した。次に、無酸素Ｃｕ板（サイズ：４４×３５ｍｍ）の基板に該ソルダペーストを、厚さ２００μｍのメタルマスクを用いて開口率１００％となるように塗布した。塗布したソルダペーストの厚さは２００μｍであった。その後、Ａｕ／ＮｉめっきされたＳｉチップ（サイズ：１０×１０ｍｍ）を搭載し、該ソルダペーストを介して、無酸素Ｃｕ板（サイズ：４４×３５ｍｍ）の基板と、Ａｕ／ＮｉめっきされたＳｉチップ（サイズ：１０×１０ｍｍ）とが接触した状態でリフロー装置（商品名：ＶＳ１、オリジン電気社製）のリフロー炉内に配置した。そして、後述する予熱工程及びリフロー工程を行うことにより、試験Ｎｏ．３－１の試験基板を作製した。
　予熱工程では、まず、ギ酸（３％）雰囲気下において、昇温速度１．７℃／ｓで予熱温度２００℃まで加熱し、２４０ｓ保持した。
　続いて、リフロー工程では、まず、リフロー炉内の雰囲気を第１圧力Ｐ１へ減圧した後、昇温速度２．６℃／ｓでピーク温度２５０℃まで加熱し、第１保持時間Ｔ１保持した（第１リフロー工程）。次に、リフロー炉内の雰囲気を第２圧力Ｐ２まで減圧した後、第２保持時間Ｔ２保持した（第２リフロー工程）。最後に、ピーク温度２５０℃にて、リフロー炉内に窒素を導入することにより大気圧まで加圧した。リフロー工程の詳細な条件を表２に示す。
　（試験Ｎｏ．３－２）
　予熱工程を窒素雰囲気下で行ったこと以外は、試験Ｎｏ．３－１と同様に試験基板を作製した。
　（試験Ｎｏ．３－３）
　予熱工程を行わず、ギ酸雰囲気下において、リフロー炉内の雰囲気を第１圧力Ｐ１へ減圧した後、ピーク温度まで加熱したこと以外は、試験Ｎｏ．３－１と同様に試験基板を作製した。
　（試験Ｎｏ．３－４）
　はんだ粉末として合金Ｂ（８９．０Ｓｎ／３．０Ａｇ／８．０Ｓｂ）を用い、リフロー工程におけるピーク温度を変更したこと以外は、試験Ｎｏ．３－１と同様に試験基板を作製した。
　（試験Ｎｏ．３－５）
　はんだ粉末として合金Ｃ（９５．０Ｐｂ／５．０Ｓｎ）を用い、予熱保持温度を２３０℃とし、さらに、リフロー工程における第１圧力Ｐ１及びピーク温度を変更したこと以外は、試験Ｎｏ．３－１と同様に試験基板を作製した。リフロー工程の詳細な条件を表２に示す。
　（試験Ｎｏ．４－１～４－５）
　第２リフロー工程を行わなかったこと以外は、それぞれ、試験Ｎｏ．３－１～３－５と同様に試験Ｎｏ．４－１～４－５の試験基板を作製した。リフロー工程の詳細な条件を表２に示す。
　＜ボイド評価＞
　試験１と同様の方法で、ボイドの評価を行った。結果を表２に示す。
　＜飛散評価＞
　試験１と同様の方法で、ボイドの評価を行った。結果を表２に示す。
Figure JPOXMLDOC01-appb-T000002
　表２の結果から分かるように、本発明の構成要件をすべて満たす試験Ｎｏ．３－１～３－５の試験基板は、第２リフロー工程を行わない試験Ｎｏ．４－１～４－５の試験基板と比較して、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制することができる。
　［試験３］
　＜試験基板の作製＞
　（試験Ｎｏ．５）
　まず、合金Ａ（９６．５Ｓｎ／３．０Ａｇ／０．５Ｃｕ）粉末とフラックスとを混合して、ソルダペーストを作製した。前記フラックスは、ペーストフラックス（弘輝社製、製品名：ペーストフラックス（ＲＭＡタイプ））を用いた。次に、ガラスエポキシ基板（サイズ：５０×５０ｍｍ、厚み：１．６ｍｍ）を準備した。前記基板上には銅箔にてφ０．２ｍｍのパターンを形成し、プリフラックス（商品名「タフエース」、四国化成社製）で処理した。前記基板に前記ソルダペーストを、厚さ１５０μｍのメタルマスクを用いて開口率４００％となるように塗布し、リフロー装置（商品名：ＶＳ１、オリジン電気社製）のリフロー炉内に配置した。塗布したソルダペーストの厚さは１５０μｍであった。そして、後述する予熱工程及びリフロー工程を行うことにより、試験Ｎｏ．５の試験基板を作製した。
　予熱工程では、まず、窒素雰囲気下において、昇温速度１．７℃／ｓで予熱温度２００℃まで加熱した。そして、該予熱温度において、真空ポンプを用いてリフロー炉内の気体を排気して３０ｓ保持した後、ギ酸（３％）を導入することによりリフロー炉内の雰囲気を大気圧まで加圧して２４０ｓ保持した。
　続いて、リフロー工程では、まず、リフロー炉内の雰囲気を５０００Ｐａ（第１圧力Ｐ１）へ減圧した後、昇温速度２．６℃／ｓでピーク温度２５０℃まで加熱し、６０ｓ（第１保持時間Ｔ１）保持した（第１リフロー工程）。次に、リフロー炉内の雰囲気を１００Ｐａ（第２圧力Ｐ２）まで減圧した後、６０ｓ（第２保持時間Ｔ２）保持した（第２リフロー工程）。最後に、ピーク温度２５０℃にて、リフロー炉内に窒素を導入することにより大気圧まで加圧した。前記第１リフロー工程及び前記第２リフロー工程の条件を表３に示す。
　（試験Ｎｏ．６）
　第２リフロー工程を行わなかったこと以外は、試験Ｎｏ．５と同様に試験Ｎｏ．６の試験基板を作製した。リフロー工程の詳細な条件を表３に示す。
　＜ボイド評価＞
　試験１と同様の方法で、ボイドの評価を行った。結果を表３に示す。
　＜飛散評価＞
　試験１と同様の方法で、ボイドの評価を行った。結果を表３に示す。
Figure JPOXMLDOC01-appb-T000003
　表３の結果から分かるように、本発明の構成要件をすべて満たす試験Ｎｏ．５の試験基板は、第２リフロー工程を行わない試験Ｎｏ．６の試験基板と比較して、接合部におけるボイドを低減し、かつ、はんだ材料の飛散を抑制することができる。
 

Claims (5)

  1. 　リフロー炉内で、はんだ材料と第１部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させるリフロー工程を備え、
    　前記リフロー工程は、
    　前記リフロー炉内の雰囲気を大気圧よりも低い第１圧力Ｐ１まで減圧した状態で前記はんだ合金を溶融させる第１リフロー工程と、
    　前記第１リフロー工程後、前記リフロー炉内の雰囲気を前記第１圧力Ｐ１よりも低い第２圧力Ｐ２まで減圧した状態で前記はんだ合金を溶融させる第２リフロー工程と、
    　を含む、接合構造体の製造方法。
  2. 　前記リフロー工程は、リフロー炉内で、はんだ材料を介して第１部材と第２部材とを接触させた状態で加熱し、前記はんだ材料を構成するはんだ合金を溶融させる、請求項１に記載の接合構造体の製造方法。
  3. 　前記第１圧力Ｐ１に対する前記第２圧力Ｐ２の比（Ｐ２／Ｐ１）は、０．００１７～０．８である、請求項１又は２に記載の接合構造体の製造方法。
  4. 　前記第１リフロー工程では、ピーク温度で第１保持時間Ｔ１保持し、
    　前記第２リフロー工程では、ピーク温度で第２保持時間Ｔ２保持し、
    　前記第１保持時間Ｔ１に対する前記第２保持時間Ｔ２の比（Ｔ２／Ｔ１）は、０．０１７～５９である、請求項１～３のいずれか一つに記載の接合構造体の製造方法。
  5. 　前記リフロー工程は、さらに、前記第２リフロー工程後、前記はんだ合金の融点以上の温度で、前記リフロー炉内の雰囲気を大気圧まで加圧する第３リフロー工程を含む、請求項１～４のいずれか一つに記載の接合構造体の製造方法。
     
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005205418A (ja) * 2004-01-20 2005-08-04 Denso Corp 接合構造体の製造方法
JP2010000513A (ja) * 2008-06-18 2010-01-07 Sharp Corp 接合構造体の製造方法
JP2012129482A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置の製造方法
JP2016155141A (ja) * 2015-02-24 2016-09-01 株式会社タムラ製作所 はんだ接合構造体の製造方法
WO2017057651A1 (ja) 2015-09-30 2017-04-06 オリジン電気株式会社 還元ガス用ソルダペースト、半田付け製品の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440101A (en) * 1993-04-19 1995-08-08 Research, Incorporated Continuous oven with a plurality of heating zones
JP3649950B2 (ja) * 1999-06-14 2005-05-18 株式会社日立製作所 冷却部品取付方法
JP2001058259A (ja) * 1999-06-18 2001-03-06 Shinko Seiki Co Ltd 半田付け方法及び半田付け装置
JP2001077524A (ja) * 1999-09-03 2001-03-23 Fujitsu Ltd リフロー半田付け装置及びリフロー半田付け方法
JP4404000B2 (ja) * 2005-04-05 2010-01-27 トヨタ自動車株式会社 接合構造体の製造方法
JP4956963B2 (ja) * 2005-11-02 2012-06-20 富士通セミコンダクター株式会社 リフロー装置、リフロー方法、および半導体装置の製造方法
JP2007180447A (ja) 2005-12-28 2007-07-12 Toyota Industries Corp 半田付け方法、半田付け装置、及び半導体装置の製造方法
DE102007005345B4 (de) * 2007-02-02 2014-06-18 Seho Systemtechnik Gmbh Verfahren zum Reflow-Löten sowie Vorrichtung zur Durchführung des Verfahrens
JP5378078B2 (ja) * 2009-06-19 2013-12-25 株式会社東芝 半導体装置の製造方法
US8061578B2 (en) * 2010-02-03 2011-11-22 Indium Corporation Solder preform
JP5540916B2 (ja) * 2010-06-15 2014-07-02 デクセリアルズ株式会社 接続構造体の製造方法
WO2012070264A1 (ja) 2010-11-23 2012-05-31 三菱電機株式会社 リフローはんだ付け装置およびリフローはんだ付け方法
JP5835533B2 (ja) * 2013-07-23 2015-12-24 千住金属工業株式会社 はんだ付け装置及び真空はんだ付け方法
MY176643A (en) * 2016-11-22 2020-08-19 Senju Metal Industry Co Soldering method
CN107222982B (zh) 2017-05-25 2019-09-03 杭州晶志康电子科技有限公司 一种smt贴片工艺

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005205418A (ja) * 2004-01-20 2005-08-04 Denso Corp 接合構造体の製造方法
JP2010000513A (ja) * 2008-06-18 2010-01-07 Sharp Corp 接合構造体の製造方法
JP2012129482A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置の製造方法
JP2016155141A (ja) * 2015-02-24 2016-09-01 株式会社タムラ製作所 はんだ接合構造体の製造方法
WO2017057651A1 (ja) 2015-09-30 2017-04-06 オリジン電気株式会社 還元ガス用ソルダペースト、半田付け製品の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3838465A4

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CN112654453B (zh) 2023-03-24
JP6709944B2 (ja) 2020-06-17
EP3838465C0 (en) 2024-01-17
TWI825188B (zh) 2023-12-11
KR20210029820A (ko) 2021-03-16
KR102259122B1 (ko) 2021-06-01
TW202021717A (zh) 2020-06-16

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