WO2020066490A1 - 積層体および積層体の製造方法 - Google Patents

積層体および積層体の製造方法 Download PDF

Info

Publication number
WO2020066490A1
WO2020066490A1 PCT/JP2019/034548 JP2019034548W WO2020066490A1 WO 2020066490 A1 WO2020066490 A1 WO 2020066490A1 JP 2019034548 W JP2019034548 W JP 2019034548W WO 2020066490 A1 WO2020066490 A1 WO 2020066490A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
main surface
region
connection pad
laminate
Prior art date
Application number
PCT/JP2019/034548
Other languages
English (en)
French (fr)
Inventor
岩本　敬
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201980062405.9A priority Critical patent/CN112740382B/zh
Publication of WO2020066490A1 publication Critical patent/WO2020066490A1/ja
Priority to US17/203,850 priority patent/US12002779B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H01L2224/17055—Bump connectors having different shapes of their bonding interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H01L2224/221—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/058—Holders; Supports for surface acoustic wave devices
    • H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps

Definitions

  • the present invention relates to a laminate in which a plurality of electronic components are connected using solder bumps.
  • the laminated body described in Patent Literature 1 is formed by mounting another electronic component with a solder bump on a terminal of a structure including an electronic component therein.
  • an object of the present invention is to reduce the size of a laminate while enhancing the connection strength of the laminate.
  • a laminate of the present invention includes a first electronic component, a first region and a second region in plan view, a structure in which the first electronic component is arranged in the second region, and a connection pad connected to the structure. And the second electronic component bump-mounted.
  • the surface of the first region and the surface of the second region have a step.
  • the connection pad is formed on a surface of the first region, a surface of the second region, and a step surface formed by the step.
  • connection pad is larger than when the first region and the second region are flush with each other. For this reason, the area of the connecting portion between the first electronic component and the second electronic component is increased, and the connection strength of the laminate of the first electronic component and the second electronic component can be improved.
  • the increase in the area of the connection portion is formed by the step between the first region and the second region, the increase in the area of the structure in plan view can be suppressed, and the size of the stacked body can be reduced.
  • the method for manufacturing a laminate according to the present invention includes the following steps.
  • This manufacturing method includes a step of arranging the first electronic component on the surface of the support via the temporary fixing material, and a step of covering the temporary fixing material and the first electronic component, and supporting the first electronic component in an area other than the area where the first electronic component is arranged.
  • the above-described desired laminate is easily and accurately manufactured.
  • the method for manufacturing a laminate according to the present invention includes the following steps.
  • This manufacturing method includes a step of burying a part of the first electronic component in a temporary fixing material formed on the surface of the support, and a step of sealing with a resin so as to cover the temporary fixing material and the first electronic component. Removing the support and the temporary fixing material, and forming a connection pad so as to straddle a surface of the resin on which the support is disposed and a surface of the first electronic component on which the temporary fixing material is disposed. And bump mounting the second electronic component via the connection pad.
  • FIG. 1A is a side cross-sectional view showing a configuration of a laminate 10 according to a first embodiment of the present invention
  • FIG. 1B is a side cross-sectional view in which a part of FIG.
  • FIG. 2 is a plan view of the laminated body 10 according to the first embodiment of the present invention as viewed from the front side.
  • FIG. 3 is a flowchart showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • FIGS. 4A to 4D are side sectional views showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • 5A to 5C are side sectional views showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • FIG. 6A is a side cross-sectional view illustrating a configuration of a laminate 10A according to a second embodiment of the present invention
  • FIG. 6B is a side cross-sectional view in which a part of FIG. 6A is enlarged.
  • FIG. FIG. 7 is a flowchart showing a method for manufacturing the laminated body 10A according to the second embodiment of the present invention.
  • 8A to 8D are side cross-sectional views illustrating a method for manufacturing a laminated body 10A according to the second embodiment of the present invention.
  • FIGS. 9A to 9E are side cross-sectional views illustrating a method of manufacturing the laminated body 10A according to the second embodiment of the present invention.
  • FIGS. 14A to 14C are plan views of the laminate according to the seventh embodiment of the present invention as viewed from the front side.
  • FIG. 14A to 14C are plan views of the laminate according to the seventh embodiment of the present invention as viewed from the front side.
  • FIG. 15A is a side cross-sectional view illustrating a configuration of a stacked body 10J according to the eighth embodiment of the present invention
  • FIG. 15B is a stacked body 10J according to the eighth embodiment of the present invention.
  • FIG. 3 is a plan view when viewed from the front side.
  • FIG. 1A is a side cross-sectional view showing a configuration of a laminate 10 according to a first embodiment of the present invention
  • FIG. 1B is a side cross-sectional view in which a part of FIG.
  • FIG. 2 is a plan view of the laminated body 10 according to the first embodiment of the present invention as viewed from the front side.
  • FIG. 3 is a flowchart showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • FIGS. 4A to 4D are side sectional views showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • 5A to 5C are side sectional views showing a method for manufacturing the laminated body 10 according to the first embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are appropriately emphasized and described, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10 includes a first electronic component 100, a structure 150, a wiring electrode 161, a terminal electrode 162, a through electrode 165, solder resist layers 170 and 175, a connection pad 180, and a second pad.
  • the electronic component 200 includes a solder bump 300.
  • the first electronic component 100 is arranged on the structure 150.
  • the second electronic component 200 is mounted on the structure 150 on which the connection pads 180 are formed using the solder bumps 300.
  • the connection pad 180 is formed of, for example, Ni, Au, Pt, Pd, or the like.
  • the first electronic component 100 includes a main surface 101 and a main surface 102 that are substantially orthogonal to the height direction indicated by the thick arrow in FIG.
  • the main surface 101 is the “surface of the first electronic component” of the present invention.
  • the first electronic component 100 and the second electronic component 200 have, for example, a rectangular parallelepiped shape, and are an IC using a semiconductor substrate, a SAW filter using a piezoelectric substrate, or the like.
  • the structure 150 is formed of resin.
  • the structure 150 has a first region R1 and a second region R2 in plan view.
  • the second region R2 has a shape sandwiched between the first regions R1.
  • the first region R1 has a main surface 151 and a main surface 152 that are substantially perpendicular to the height direction and face each other.
  • the main surface 151 is the “surface of the first region” of the present invention.
  • the second region R2 has a main surface 153 and a main surface 154 that are substantially orthogonal to the height direction and face each other.
  • the structure 150 includes a first side surface S1 and a second side surface S2 that are substantially parallel to the height direction and face each other.
  • the main surface 152 of the first region R1 and the main surface 154 of the second region R2 are flush.
  • the main surface 151 of the first region R1 is formed at a position higher than the main surface 153 of the second region R2 in the height direction. At this time, the height difference between the main surface 151 and the main surface 153 is larger than the height of the first electronic component 100.
  • a through electrode 165 is formed inside the structure 150 in the first region R1.
  • a wiring electrode 161 is formed on the main surface 151.
  • the terminal electrode 162 is formed on the main surface 152.
  • the wiring electrode 161 is connected to the terminal electrode 162 via the through electrode 165.
  • Part of the terminal electrode 162 is covered with a solder resist layer 175.
  • the structure of the second region R2 of the structure 150 will be described.
  • the first electronic component 100 is arranged in the second region R2.
  • the first electronic component 100 is configured such that the main surface 102 of the first electronic component 100 and the main surface 153 of the structure 150 are in contact with each other, or the main surface 102 of the first electronic component 100 and the main surface 153 of the structure 150 are in contact with each other. It is arranged via an insulating layer and a metal conductor.
  • the position of the main surface 151 in the first region R1 is higher than the position of the main surface 101 of the first electronic component 100 in the height direction. Specifically, in the height direction, main surface 101 and main surface 151 have a step H1.
  • the step in the present invention is a height difference between the main surface 101 and the main surface 151 in the height direction, and the shape is not limited.
  • a height difference formed between a plurality of planes and a height difference formed between a high position and a low position are all described as steps.
  • the wiring electrode 161 is formed continuously from the main surface 151 described above to the main surface 101 of the first electronic component 100. That is, it is formed so as to straddle the step surface B1 connected to the main surface 151 of the structure 150 and the main surface 101 of the first electronic component 100.
  • the step surface B1 is a side surface of the first region R1 on the second region R2 side in the structure 150.
  • the main surface 101 of the second region R2 It is a surface exposed to the side.
  • the step surface B1 is a surface formed by the step H1.
  • connection pad 180 is opposite to the surface of the wiring electrode 161 opposite to the surface on the structure 150 side, that is, the surface of the wiring electrode 161 that is in contact with the main surface 151, the main surface 101 of the first electronic component 100, and the step surface B1. Formed on the side surface.
  • the second electronic component 200 is mounted on the connection pad 180 via the solder bump 300. At this time, the solder bumps 300 are connected so as to include the area of the step surface B1.
  • connection pad 180 is larger than the case where the main surface 101 and the main surface 151 are flush with each other by an area substantially equal to the area of the step surface B1. Therefore, the area of the connection portion with the solder bump 300 (hereinafter, connection area) can be increased.
  • the main surface 101 is lower than the main surface 151, and a portion of the connection pad 180 abutting on the step surface B ⁇ b> 1 is formed on the center side of the laminate 10 (the second region R ⁇ b> 2 side of the structure 150).
  • the laminated body 10 has a structure in which the region on the center side is more concave than the region on the outer edge side (the first region R1 side in the structure 150).
  • the thermal stress generated between the structure 150 and the second electronic component 200 is a force of the second electronic component 200 extending in a direction orthogonal to the height direction with respect to the main surface 151 of the structure 150.
  • the solder bump 300 is formed between the step surface B1 (step H1 portion) and the connection pad 180. It is pressed against the portion that contacts the step surface B1. Therefore, the connection strength between the connection pad 180 and the solder bump 300 is improved, and breakage can be suppressed.
  • FIG. 2 is a plan view of the laminated body 10 as viewed from the side on which the second electronic component 200 is mounted, in other words, from the main surface 101 side (the main surface 151 side).
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • FIG. 2 only the connection pads 180 and the solder bumps 300 are shown to indicate the direction of the step H1, and other configurations are omitted.
  • the solder bump 300 is formed so as to straddle the first region R1 and the second region R2. Further, two solder bumps 300 are formed at positions symmetrical with respect to the center position of the laminate 10.
  • the direction of the step H1 from the high surface (the main surface 151) to the low surface (the main surface 101) is from the first side surface S1.
  • the direction extends to the second side surface S2.
  • the direction from the high surface (main surface 151) to the low surface (main surface 101) of the step H1 of the right connection pad 180 (the connection pad 180 on the second side surface S2 side) is from the second side surface S2 to the first side surface. This is the direction extending to S1.
  • the solder bump 300 and the connection pad 180 is pressed against the step surface B1. Therefore, the connection strength between the solder bump 300 and the connection pad 180 is improved.
  • the contact area between the connection pad 180 and the solder bump 300 is increased by the step H1 (step surface B1) extending in the height direction, so that the side on which the second electronic component 200 is mounted, in other words, for example, it is possible to suppress an increase in the area of the connection pad 180 or the solder bump 300 when viewed from the main surface 101 side (main surface 151 side) in a plan view. Therefore, miniaturization of the laminate 10 can be realized.
  • FIG. 3 is a flowchart showing a method for manufacturing the laminate 10.
  • 4 (A), 4 (B), 4 (C), 4 (D), 5 (A), 5 (B), and 5 (C) show a method of manufacturing the laminated body 10. It is sectional drawing which shows the shape in the main process in the 1st example.
  • the support 440, the adhesive layer 430, and the power supply layer 420 are laminated in this order.
  • a through electrode 165 is formed on the surface of the power supply layer 420 opposite to the surface on which the support 440 is arranged by an electrolytic plating method or the like (S101).
  • the temporary fixing material 410 is partially disposed (between the through electrodes 165) on the surface of the power supply layer 420 opposite to the surface on which the support 440 is disposed, and the first temporary fixing material 410 is provided on the temporary fixing material 410.
  • the electronic component 100 is arranged (S102).
  • the temporary fixing member 410 is formed of, for example, a resin-based material such as a resin made of a polymer material or a resin containing a solvent.
  • the side of the power supply layer 420 opposite to the surface on which the support 440 is arranged is sealed with a resin and cured.
  • the penetrating electrode 165, the temporary fixing material 410, and the first electronic component 100 are sealed with resin so as to cover the through electrode 165, the temporary fixing material 410, and the first electronic component 100.
  • the structure 150 is formed in a region where the temporary fixing material 410 does not exist (S103).
  • the temporary fixing material 410, the power supply layer 420, the adhesive layer 430, and the support 440 are removed (S104).
  • the step H1 is formed by removing the temporary fixing material 410. That is, the step H1 is determined by the thickness of the temporary fixing material 410.
  • the wiring electrode 161 is formed on the side of the through electrode 165 where the structure 150 is not formed, in other words, on the portion where the temporary fixing material 410 is removed.
  • the wiring electrode 161 is formed so as to straddle a portion having the step H1 (portion of the step surface B1).
  • the connection pad 180 is formed so as to be in contact with the wiring electrode 161, that is, so as to straddle the portion having the step H1 (portion of the step surface B1) (S105).
  • the solder resist layer 170 is formed on the main surface of the structure 150 and the first electronic component 100 on the side where the wiring electrode 161 is formed, and on the wiring electrode 161. It may be formed.
  • the solder resist layer 170 is formed on a part of the solder resist layer 170 formed on the wiring electrode 161, specifically, on a part having a step H1.
  • the connection pad 180 that straddles the step surface B1 can be obtained.
  • the solder resist layer 170 is formed after the connection pad 180 is formed, the solder resist layer 170 is formed so as not to cover at least a part of the connection pad 180, so that the solder resist layer 170 extends over the step surface B1.
  • the connection pad 180 is obtained.
  • the main surface of the structure 150 on the side where the first electronic component 100 is not arranged is ground to expose the through electrode 165 (S106).
  • the terminal electrode 162 is formed so as to be connected to the through electrode 165.
  • a solder resist layer 175 is formed so as to cover a part of the terminal electrode 162 (S107).
  • the second electronic component 200 is mounted on the connection pad 180 via the solder bump 300 (S108).
  • FIG. 6A is a side cross-sectional view illustrating a configuration of a laminate 10A according to a second embodiment of the present invention
  • FIG. 6B is a side cross-sectional view in which a part of FIG. 6A is enlarged.
  • FIG. FIG. 7 is a flowchart illustrating a method for manufacturing the laminated body 10A.
  • 8A to 8D are side cross-sectional views illustrating a method for manufacturing a laminated body 10A according to the second embodiment of the present invention.
  • FIGS. 9A to 9D are side cross-sectional views illustrating a method of manufacturing the laminated body 10A according to the second embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are appropriately emphasized and described, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10A according to the second embodiment is different from the laminate 10 according to the first embodiment in that the first electronic component 100 shown in FIG. (A) differs in the arrangement position in the height direction indicated by the thick arrow, and in the shape of the step H2, the wiring electrode 161A, and the connection pad 180A.
  • the other basic configuration of the stacked body 10A is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • the first region R1 has a main surface 151 and a main surface 152 facing each other.
  • the second region R2 has a main surface 153A and a main surface 154 facing each other.
  • the main surface 152 of the first region R1 and the main surface 154 of the second region R2 are flush.
  • the main surface 151 is formed at a position higher than the main surface 153A in the height direction. However, the height difference between the main surface 151 and the main surface 153A is smaller than the height of the first electronic component 100.
  • the first electronic component 100 is disposed in the second region R2 of the structure 150A.
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • the first electronic component 100 is configured such that the main surface 102 of the first electronic component 100 abuts against the main surface 153A of the structure 150A, or the main surface 102 of the first electronic component 100 and the main surface 153A of the structure 150 contact each other. It is arranged via an insulating layer and a metal conductor.
  • the position of the main surface 151 in the first region R1 is lower than the position of the main surface 101 of the first electronic component 100 in the height direction.
  • the main surface 101 and the main surface 151 have a step H2.
  • the wiring electrode 161A is formed continuously over the main surface 101 of the first electronic component 100 and the main surface 151 of the structure 150A. That is, it is formed so as to straddle the step surface B2 of the main surface 151 of the structure 150A.
  • the step surface B2 is a side surface of the first region R1 on the second region R2 side in the structure 150A.
  • the main surface 101 of the second region R2 is removed. It is a surface exposed to the side.
  • the step surface B2 is a surface formed by the step H2.
  • connection pad 180A has a surface opposite to the surface of the wiring electrode 161A on the structure 150A side, that is, a surface that contacts the main surface 101, the main surface 151 of the first electronic component 100, and the step surface B2 in the wiring electrode 161A. It is formed on the opposite surface.
  • the second electronic component 200 is mounted on the connection pad 180A via the solder bump 300. At this time, the solder bumps 300 are connected so as to include the area of the step surface B2.
  • the main surface 101 and the main surface 151 have the step H2. That is, the connection pad 180A is larger than the case where the main surface 101 and the main surface 151 are flush with each other by an area substantially equal to the area of the step surface B2. Therefore, the connection area between the solder bump 300 and the connection pad 180A can be increased.
  • the stacked body 10A has a structure in which the main surface 101 is higher than the main surface 151, and a portion of the connection pad 180 that contacts the stepped surface B2 is exposed on the outer edge side of the stacked body 10A (on the first region R1 side in the structure 150A). It is. In other words, the region on the center side (the second region R2 side in the structure 150A) of the stacked body 10A protrudes from the region on the outer edge side.
  • the second electronic component 200 contracts in a direction perpendicular to the height direction with respect to the main surface 151 of the structure 150A.
  • the solder bumps 300 are connected to the step surface B2 (step H2 portion) and the connection pad 180A. Is pressed against a portion that contacts the step surface B2. Therefore, the connection strength between the connection pad 180A and the solder bump 300 is improved, and breakage can be suppressed.
  • step H2 step surface B2 extending in the height direction increases the contact area between the connection pad 180A and the solder bump 300, so that the side on which the second electronic component 200 is mounted, in other words, the main surface 101 side (the main surface 101 side) When viewed from above (from the surface 151 side), an increase in the area of the connection pads 180A and the solder bumps 300 can be suppressed. Therefore, miniaturization of the laminated body 10A can be realized.
  • FIG. 7 is a flowchart illustrating a method for manufacturing the laminated body 10A.
  • 8 (A), 8 (B), 8 (C), 8 (D), 8 (E), 9 (A), 9 (B), 9 (C), 9 (D) and FIG. 9 (E) are cross-sectional views showing shapes in main steps in a second example of the method of manufacturing the laminated body 10A.
  • the support 440, the temporary fixing material 410, and the power supply layer 420 are laminated in this order.
  • the through electrode 165 is formed on the surface of the power supply layer 420 opposite to the surface on which the support 440 is arranged by an electrolytic plating method, a conductive paste filling method, or the like (S201).
  • the temporary fixing material 410 also functions as an adhesive layer 430 for adhering the support 440 and the power supply layer 420.
  • the power supply layer 420 is etched to form the power supply electrode 425, and the temporary fixing material 410 in the arrangement region of the first electronic component 100 is exposed (S202).
  • the first electronic component 100 is arranged in the exposed area of the temporary fixing material 410 (S203). At this time, the first electronic component 100 is arranged on the temporary fixing material 410 such that the first electronic component 100 fills the temporary fixing material 410 at a predetermined depth.
  • the side of the temporary fixing material 410 opposite to the surface on which the support 440 is arranged is sealed with a resin and cured (S204). At this time, sealing is performed with resin so as to cover the through electrode 165, the temporary fixing material 410, and the first electronic component 100. Thereby, the structure 150A is formed.
  • the portion of the structure 150A opposite to the temporary fixing member 410 is ground to expose the through electrode 165 (S205).
  • the temporary fixing material 410, the power supply layer 425, and the support 440 are removed (S206).
  • the first electronic component 100 is disposed so as to be buried in the temporary fixing member 410 at a predetermined depth.
  • a step H2 is formed. That is, the step H2 is determined by the amount of the first electronic component 100 embedded in the temporary fixing member 410.
  • the wiring electrode 161A is formed on the side of the through electrode 165 where the structure 150A is not formed, in other words, on the side where the temporary fixing material 410 is removed.
  • the wiring electrode 161A is formed so as to straddle the portion having the step H2 (the portion of the step surface B2).
  • the connection pad 180A is formed so as to be in contact with the wiring electrode 161A, that is, so as to straddle the portion having the step H2 (portion of the step surface B2) (S207).
  • the solder resist layer 170 is placed on the main surface of the structure 150A and the first electronic component 100 on the side where the wiring electrode 161A is formed, and on the wiring electrode 161A. It may be formed.
  • the solder resist layer 170 is formed before the connection pad 180A is formed, the solder resist layer 170 is formed on a part of the solder resist layer 170 formed on the wiring electrode 161A, specifically, on a part having a step H2.
  • a connection pad 180A that straddles the step surface B2 can be obtained.
  • the solder resist layer 170 is formed after the connection pad 180A is formed, the solder resist layer 170 is formed so as not to cover at least a part of the connection pad 180A, so that the solder resist layer 170 extends over the step surface B2.
  • the connection pad 180A is obtained.
  • the terminal electrode 162 is formed so as to be connected to the through electrode 165.
  • a solder resist layer 175 is formed so as to cover a part of the terminal electrode 162 (S208).
  • the second electronic component 200 is mounted on the connection pad 180A via the solder bump 300 (S209).
  • FIG. 10 is a side cross-sectional view illustrating a configuration of a laminate 10B according to the third embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are emphasized as appropriate, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10B according to the third embodiment is different from the laminate 10 according to the first embodiment in that a resin film 190 is provided and a connection electrode 195 is provided. , And the shapes of the wiring electrode 161B and the connection pad 180B.
  • the other basic configuration of the stacked body 10B is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • the laminated body 10B includes the first electronic component 100, the structure 150, the terminal electrode 162, the wiring electrode 161B, the through electrode 165, the solder resist layers 170 and 175, the connection pad 180B, the resin film 190, and the connection.
  • An electrode 195, a second electronic component 200, and a solder bump 300 are provided.
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • the resin film 190 is formed continuously over the main surface 151, the step surface B1, and the main surface 101.
  • the resin film 190 is formed so as to straddle the step H1. More specifically, the resin film 190 covers an angle (a sharp portion) generated between the step surface B1 of the step H1 and the main surface 151 and between the step surface B1 and the main surface 101, and 151 and the main surface 101 are formed so as to be connected in a gentle shape (slope shape).
  • the wiring electrode 161B is formed so as to cover the surface of the resin film 190 opposite to the surface on the main surface 151, 101 side. Note that a connection electrode 195 is formed on the resin film 190, and the wiring electrode 161B is connected to the through electrode 165 via the connection electrode 195.
  • connection pad 180B is formed on the surface of the wiring electrode 161B opposite to the main surface 101, the step surface B1, and the main surface 151 of the first electronic component 100. More specifically, the connection pad 180B is formed so as to cover a slope-shaped surface connecting the first electronic component 100 and the structure 150 via the wiring electrode 161B and the resin film 190.
  • the second electronic component 200 is connected to the connection pad 180B via the solder bump 300.
  • the main surface 101 and the main surface 151 have the step H1. That is, the area of the connection pad 180B is larger than when the main surface 101 and the main surface 151 are flush with each other, and the connection area between the solder bump 300 and the connection pad 180B can be increased.
  • the stacked body 10B has a structure in which the main surface 101 is lower than the main surface 151 and the central region of the stacked body 10B is recessed from the outer edge region.
  • the thermal stress generated between the structure 150 and the second electronic component 200 is a force of the second electronic component 200 extending in a direction orthogonal to the height direction with respect to the main surface 151 of the structure 150.
  • the solder bump 300 is pressed against the step surface B1 (the portion of the step H1). Therefore, the connection strength between the connection pad 180B and the solder bump 300 is improved, and breakage can be suppressed.
  • FIG. 11 is a side cross-sectional view illustrating a configuration of a stacked body 10C according to the fourth embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are appropriately emphasized and described, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10C according to the fourth embodiment is different from the laminate 10A according to the second embodiment in that a resin film 190 is provided and a connection electrode 195 is provided. , And the shapes of the wiring electrode 161C and the connection pad 180C.
  • the other basic configuration of the stacked body 10C is the same as that of the stacked body 10A, and the description of the same portions will be omitted.
  • the laminate 10C includes a first electronic component 100, a structure 150C, a terminal electrode 162, a wiring electrode 161C, a through electrode 165, solder resist layers 170 and 175, connection pads 180C, a resin film 190, and a connection.
  • An electrode 195, a second electronic component 200, and a solder bump 300 are provided.
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • the resin film 190 is formed continuously over the main surface 151, the step surface B2, and the main surface 101.
  • the resin film 190 is formed so as to straddle the portion having the step H2. More specifically, the resin film 190 covers an angle (a sharp portion) generated between the step surface B2 of the step H2 and the main surface 151 and between the step surface B2 and the main surface 101, and 151 and the main surface 101 are formed so as to be connected in a gentle shape (slope shape).
  • the wiring electrode 161C is formed so as to cover the surface of the resin film 190 opposite to the surface on the main surface 151, 101 side.
  • the connection electrode 195 is formed on the resin film 190, and the wiring electrode 161C is connected to the through electrode 165 via the connection electrode 195.
  • connection pad 180C is formed on the surface of the wiring electrode 161C opposite to the main surface 101, the step surface B2, and the main surface 151 of the first electronic component 100. More specifically, the connection pad 180C is formed so as to cover a slope-shaped surface connecting the first electronic component 100 and the structure 150C via the wiring electrode 161C and the resin film 190.
  • the second electronic component 200 is connected to the connection pad 180C via the solder bump 300.
  • the main surface 101 and the main surface 151 have a step H2. That is, the area of the connection pad 180C is larger than in the case where the main surface 101 and the main surface 151 are flush with each other, and the connection area between the solder bump 300 and the connection pad 180 can be increased.
  • the thermal stress generated between the structure 150C and the second electronic component 200 is a force that causes the second electronic component 200 to shrink in a direction perpendicular to the height direction with respect to the main surface 151 of the structure 150C.
  • the solder bump 300 is pressed against the step H2. Therefore, the connection strength between the connection pad 180C and the solder bump 300 is improved, and breakage can be suppressed.
  • FIG. 12 is a side cross-sectional view illustrating a configuration of a stacked body 10D according to the fifth embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are emphasized as appropriate, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10D according to the fifth embodiment differs from the laminate 10 according to the first embodiment in that resin layers 191 and 192 are provided and connection electrodes 195 and 196 are provided.
  • the difference is in the provision thereof and the shapes of the wiring electrodes 161D and 163D and the connection pad 180D.
  • the other basic configuration of the stacked body 10D is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • the laminate 10D includes the first electronic component 100, the structure 150, the terminal electrodes 162, the wiring electrodes 161D and 163D, the through electrodes 165, the solder resist layers 170 and 175, the connection pads 180D, and the resin film 191. , 192, connection electrodes 195, 196, second electronic component 200, and solder bump 300.
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • the resin film 191 is formed continuously over the main surface 151, the step surface B1, and the main surface 101.
  • the resin film 191 is formed so as to straddle the portion having the step H1. More specifically, the resin film 191 covers an angle (an acute angle portion) generated between the step surface B1 of the step H1 and the main surface 151 and between the step surface B1 and the main surface 101, and 151 and the main surface 101 are formed so as to have a gentle shape (slope shape).
  • the wiring electrode 161D is formed so as to cover the surface of the resin film 191 on the side opposite to the surface on the main surface 151, 101 side.
  • the connection electrode 195 is formed on the resin film 191, and the wiring electrode 161D is connected to the through electrode 165 via the connection electrode 195.
  • the resin film 192 is formed so as to cover the surface of the resin film 191 and the wiring electrode 161D on the side opposite to the surface on the resin film 191 side. Similarly to the resin film 191, the resin film 192 is formed continuously over the main surface 151, the step surface B1, and the main surface 101.
  • the resin film 192 is formed so as to straddle the portion having the step H1. More specifically, the resin film 192 covers an angle (an acute angle portion) generated between the step surface B1 of the step H1 and the main surface 151 and between the step surface B1 and the main surface 101. 151 and the main surface 101 are formed so as to be connected in a gentle shape (slope shape).
  • the wiring electrode 163D is formed so as to cover the surface of the resin film 192 on the side opposite to the surface on the side of the wiring electrode 161D. Note that a connection electrode 196 is formed on the resin film 192. The wiring electrode 163D is connected to the wiring electrode 161D via the connection electrode 196.
  • connection pad 180D is formed on the surface of the wiring electrode 163D opposite to the main surface 101, the step surface B1, and the main surface 151 of the first electronic component 100. More specifically, the connection pad 180D is formed so as to cover a slope-shaped surface connecting the first electronic component 100 and the structure 150 via the wiring electrodes 161D and 163D and the resin films 191 and 192. .
  • the second electronic component 200 is connected to the connection pad 180D via the solder bump 300.
  • the main surface 101 and the main surface 151 have the step H1. That is, the area of the connection pad 180D is larger than when the main surface 101 and the main surface 151 are flush with each other, and the connection area between the solder bump 300 and the connection pad 180 can be increased.
  • the corners (sharp portions) formed between the step surface B1 of the step H1 and each of the main surfaces 151 and 101 are covered with a plurality of resin films 191 and 192, so that the sharp portions are covered with one resin film.
  • the stress of the solder bump 300 is less likely to concentrate at a specific location. Therefore, breakage in the solder bump 300 can be further suppressed.
  • the cushioning property of the laminate 10D can be improved, and damage to the laminate 10 at the time of mounting the second electronic component 200 or the like can be suppressed.
  • the stacked body 10D has a structure in which the main surface 101 is lower than the main surface 151, and the central region of the stacked body 10D is recessed from the outer edge region.
  • the thermal stress generated between the structure 150 and the second electronic component 200 is a force of the second electronic component 200 extending in a direction orthogonal to the height direction with respect to the main surface 151 of the structure 150.
  • the solder bump 300 is pressed against the step surface B1 (the portion of the step H1). Therefore, the connection strength between the connection pad 180D and the solder bump 300 is improved, and breakage can be suppressed.
  • the laminate 10C according to the above-described fourth embodiment may have a configuration including a plurality of resin films that straddle the step surface B1. In this case, the same effect as that of the present embodiment can be obtained.
  • FIG. 13 is a side cross-sectional view illustrating a configuration of a stacked body 10E according to the sixth embodiment of the present invention.
  • the vertical and horizontal dimensional relationships are emphasized as appropriate, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • the laminate 10E according to the sixth embodiment differs from the laminate 10 according to the first embodiment in that a plurality of auxiliary members 400 are provided.
  • the other basic configuration of the laminated body 10E is the same as that of the laminated body 10, and the description of the same parts will be omitted.
  • the plurality of auxiliary members 400 are formed on the surface of the connection pad 180 on the side where the second electronic component 200 is mounted.
  • the auxiliary member 400 is preferably a conductor.
  • the auxiliary member 400 is made of the same material as the connection pad 180, there is no difference in linear expansion coefficient between the auxiliary member 400 and the connection pad 180, so that it is more preferable in that high reliability can be obtained.
  • connection area between the solder bump 300 and the connection pad 180 can be further increased.
  • the position at which the plurality of auxiliary members 400 are arranged may be any position on the surface of the connection pad 180 where the connection pad 180 and the solder bump 300 are in contact.
  • the position where the auxiliary member 400 is arranged is such that a step is formed on the surface of the connection pad 180 (the surface opposite to the surface of the connection pad 180 on the wiring electrode 161 side) with the solder bump 300 by the auxiliary member 400.
  • the configuration in which two auxiliary members 400 are formed has been described. However, one or three or more configurations may be used, and a number that does not hinder the connection between the connection pad 180 and the solder bump 300 may be used. May be provided.
  • connection area is increased by forming the plurality of auxiliary members 400
  • the same effect can be obtained by making the surface of the connection pad 180 rough.
  • the solder bumps 300 enter the rough portion on the surface of the connection pad 180, the connection area increases, and the connection strength between the connection pad 180 and the solder bump 300 further improves.
  • the thickness of the step H1 in the height direction is preferably larger than the thickness of the roughest portion on the surface of the connection pad 180 described above. Thereby, the connection strength between the connection pad 180 and the solder bump 300 is more remarkably improved.
  • FIGS. 14A to 14C are plan views of the laminate according to the seventh embodiment of the present invention as viewed from the front side.
  • the vertical and horizontal dimensional relationships are appropriately emphasized, and do not always match the vertical and horizontal dimensional relationships in the actual size.
  • 14 (A), 14 (B), and 14 (C) show only the solder bumps 300, and other components are omitted.
  • the first electronic component 100 is arranged so as to overlap the second electronic component 200 in a plan view.
  • the stacked body 10F according to the seventh embodiment is different from the stacked body 10 according to the first embodiment in that two solder bumps 300F are provided on the first side surface S1 side, The difference is that two portions are formed on the two side surfaces S2. That is, the connection pads 180 connected to each of the solder bumps 300F are also formed at two places on the first side face S1 side and two places on the second side face S2 side.
  • the other basic configuration of the laminated body 10F is the same as that of the laminated body 10, and the description of the same portions will be omitted.
  • connection area of the connection pad 180 and the solder bump 300F can be further increased. Further, since the step H1 is formed in the height direction of the stacked body 10F, the area when the stacked body 10F is viewed in plan does not increase. Therefore, miniaturization of the laminate 10F can be realized.
  • the stacked body 10G according to the seventh embodiment is different from the stacked body 10 according to the first embodiment in that three solder bumps 300G are provided on the first side surface S1 side, and The difference is that three portions are formed on the two side surfaces S2. That is, the connection pads 180 connected to each of the solder bumps 300G are also formed at three places on the first side face S1 side and three places on the second side face S2 side.
  • the other basic configuration of the stacked body 10G is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • connection area of the connection pad 180 and the solder bump 300G can be further increased. Further, since the step H1 is formed in the height direction of the stacked body 10G, the area when the stacked body 10G is viewed in plan does not increase. Therefore, miniaturization of the stacked body 10G can be realized.
  • the stacked body 10H according to the seventh embodiment is different from the stacked body 10 according to the first embodiment in that the solder bumps 300H are different from the first side surface S1 and the second side surface S2.
  • the third side S1 and the second side S2 extend in a direction connecting the second side S2, and are different from each other in that one is formed on each of the third side S3 and the fourth side S4 facing each other.
  • the solder bump 300H is formed so as to straddle a step surface B1 (not shown) on the first side surface S1 side among a plurality of step surfaces B1 formed between the first electronic component 100 and the structure 150.
  • the step surface B1 formed on the first side surface S1 side and the second side surface S2 side is the "first step surface" of the present invention.
  • solder bump 300H is connected to a connection pad 180 formed so as to straddle a step surface B1 (not shown) on the third side surface S3 side among step surfaces formed between the first electronic component 100 and the structure 150. And two solder bumps 300H connected to the respective connection pads 180 formed so as to straddle the step surface B1 (not shown) on the fourth side surface S4 side.
  • the step surface B1 formed on the third side surface S3 side and the fourth side surface S4 side is the “second step surface” of the present invention.
  • the other basic configuration of the stacked body 10H is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • connection pad 180 can have a larger connection area with the solder bump 300H. Furthermore, since the step H1 is formed in the height direction of the stacked body 10H, the area when the stacked body 10H is viewed in plan does not increase. Therefore, miniaturization of the laminate 10H can be realized.
  • the first side surface S1 and the second side surface S2 are connected by the two solder bumps 300H on the first side surface S1 side and the second side surface S2 side and the connection pads 180 connected thereto.
  • the connection strength against the stress in the direction can be improved.
  • the two solder bumps 300H on the third side S3 side and the fourth side S4 side and the connection pads 180 connected thereto are parallel to the first side S1 and the second side S2.
  • the connection strength against stress in various directions can also be improved. As described above, even when the directions in which the plurality of stresses are generated are different from each other, the connection strength between the first electronic component 100 and the structure 150 and the second electronic component 200 can be improved. It can be further improved.
  • each of the laminates 10F to 10H according to the seventh embodiment includes a plurality of connection pads 180.
  • the second electronic component 200 is easily fixed to the first electronic component 100 and the structure 150, and the connection strength of the stacked bodies 10F to 10H is further improved.
  • the configuration in which the main surface 101 of the first electronic component 100 is exposed has been described.
  • the main surface 101 of the first electronic component 100 may be covered with the solder resist layer 170.
  • the configuration for exposing the main surface 101 can be omitted, and the above-described laminates 10 to 10H can be formed at low cost.
  • FIG. 15A is a side cross-sectional view illustrating a configuration of a multilayer body 10J according to the eighth embodiment of the present invention
  • FIG. 15B is a cross-sectional view illustrating the multilayer body 10J according to the eighth embodiment of the present invention. It is the top view seen from the surface side. 15A and 15B, vertical and horizontal dimensional relationships are appropriately emphasized and described, and do not always match the vertical and horizontal dimensional relationships in actual dimensions.
  • the laminate 10J according to the eighth embodiment is different from the laminate 10 according to the first embodiment in that only one step H1 is formed. Is different.
  • the other basic configuration of the stacked body 10J is the same as that of the stacked body 10, and the description of the same portions will be omitted.
  • the stacked body 10J has only one step H1 (left side in FIG. 15A).
  • the penetrating electrode 165 in the portion where the step H1 is not formed (the right side in FIG. 15A) is connected to the second electron via the wiring electrode 161, the connection pad 180, and the solder bump 300 substantially parallel to the main surface 151. It is connected to the component 200.
  • the main surface 101 and the main surface 151 have the step H1.
  • the connection pad 180 is larger than the case where the main surface 101 and the main surface 151 are flush with each other by an area substantially equal to the area of the step surface B1. Therefore, the connection area between the solder bump 300 and the connection pad 180 can be increased.
  • the thermal stress generated between the structure 150 and the second electronic component 200 is a force that extends the second electronic component 200 in a direction orthogonal to the height direction with respect to the main surface 151 of the structure 150.
  • the solder bump 300 is formed on the step surface B1 (the portion of the step H1) and the step of the connection pad 180. It is pressed against the portion that comes into contact with the surface B1. Therefore, the connection strength between the connection pad 180 and the solder bump 300 is improved, and breakage can be suppressed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Acoustics & Sound (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

積層体（１０）は、第１電子部品（１００）と、平面視において第１領域（Ｒ１）と第２領域（Ｒ２）とを備え、第１電子部品（１００）が第２領域（Ｒ２）に配置された構造体（１５０）と、構造体（１５０）に接続パッド（１８０）を介してバンプ実装された第２電子部品（２００）とを備える。構造体（１５０）の高さ方向において、第１領域（Ｒ１）の表面と第２領域（Ｒ２）の表面とは、段差（Ｈ１）を有する。接続パッド（１８０）は、第１領域（Ｒ１）の表面、第２領域（Ｒ２）の表面、および段差（Ｈ１）によって形成された段差面（Ｂ１）に形成されている。

Description

積層体および積層体の製造方法
　本発明は、半田バンプを用いて複数の電子部品を接続した、積層体に関する。
　従来、各種の積層体が実用化されている。例えば、特許文献１に記載の積層体は、電子部品を内部に備える構造体の端子に、他の電子部品を半田バンプで実装することによって形成されている。
特開２０１６－２０１５６５号公報
　特許文献１に示す構成では、構造体の端子と、積層される電子部品の半田バンプとの接続部分の面積が小さい場合に接続強度が確保できず、熱応力が繰り返しかかること等によって当該接続部分で破断する虞がある。また、構造体の端子と、電子部品との接続部分の面積を大きくした場合には、それに伴い積層体が大型化してしまう。
　したがって、本発明の目的は、積層体の接続強度を強化しつつ、積層体の小型化を図ることである。
　この発明の積層体は、第１電子部品と、平面視において第１領域と第２領域とを備え、第１電子部品が第２領域に配置された構造体と、構造体に接続パッドを介してバンプ実装された第２電子部品とを備える。構造体の高さ方向において、第１領域の表面と第２領域の表面とは、段差を有する。接続パッドは、第１領域の表面、第２領域の表面、および段差によって形成された段差面に形成されている。
　この構成では、第１領域と第２領域とが面一の場合よりも接続パッドの表面積は大きくなる。このため、第１電子部品と第２電子部品との接続部分の面積が大きくなり、第１電子部品と第２電子部品との積層体の接続強度を向上できる。また、当該接続部分における面積の増加は、第１領域と第２領域の段差で形成されるため、平面視における構造体の面積の増大を抑制でき、積層体を小型化できる。
　この発明の積層体の製造方法は、次の各工程を有する。この製造方法は、支持体の表面に仮固定材を介して第１電子部品を配置する工程と、仮固定材と第１電子部品とを覆い、第１電子部品の配置領域を除く領域では支持体に当接するように、樹脂で封止する工程と、支持体と仮固定材とを取り除く工程と、樹脂における支持体が配置された側の面と第１電子部品における仮固定材が配置された面とを跨ぐように、接続パッドを形成する工程と、第２電子部品を、接続パッドを介してバンプ実装する工程とを有する。
　この製造方法では、上述の所望の積層体が、容易、且つ、精度良く製造される。
　この発明の積層体の製造方法は、次の各工程を有する。この製造方法は、支持体の表面に形成された仮固定材に、第１電子部品の一部を埋める工程と、仮固定材と第１電子部品とを覆うように樹脂で封止する工程と、支持体と仮固定材とを取り除く工程と、樹脂における支持体が配置された側の面と第１電子部品における仮固定材が配置された面とを跨ぐように、接続パッドを形成する工程と、第２電子部品を、接続パッドを介してバンプ実装する工程とを有する。
　この製造方法では、上述の所望の構造体が、容易、且つ、精度良く製造される。
　この発明によれば、積層体の接続強度を強化しつつ、積層体の小型化を図ることができる。
図１（Ａ）は、本発明の第１の実施形態に係る積層体１０の構成を示す側面断面図であり、図１（Ｂ）は、図１（Ａ）の一部を拡大した側面断面図である。 図２は本発明の第１の実施形態に係る積層体１０を表面側から視た平面図である。 図３は本発明の第１の実施形態に係る積層体１０の製造方法を示すフローチャートである。 図４（Ａ）－図４（Ｄ）は、本発明の第１の実施形態に係る積層体１０の製造方法を示す側面断面図である。 図５（Ａ）－図５（Ｃ）は、本発明の第１の実施形態に係る積層体１０の製造方法を示す側面断面図である。 図６（Ａ）は、本発明の第２の実施形態に係る積層体１０Ａの構成を示す側面断面図であり、図６（Ｂ）は、図６（Ａ）の一部を拡大した側面断面図である。 図７は本発明の第２の実施形態に係る積層体１０Ａの製造方法を示すフローチャートである。 図８（Ａ）－図８（Ｄ）は、本発明の第２の実施形態に係る積層体１０Ａの製造方法を示す側面断面図である。 図９（Ａ）－図９（Ｅ）は、本発明の第２の実施形態に係る積層体１０Ａの製造方法を示す側面断面図である。 図１０は本発明の第３の実施形態に係る積層体１０Ｂの構成を示す側面断面図である。 図１１は本発明の第４の実施形態に係る積層体１０Ｃの構成を示す側面断面図である。 図１２は本発明の第５の実施形態に係る積層体１０Ｄの構成を示す側面断面図である。 図１３は本発明の第６の実施形態に係る積層体１０Ｅの構成を示す側面断面図である。 図１４（Ａ）－図１４（Ｃ）は、本発明の第７の実施形態に係る積層体を表面側から視た平面図である。 図１５（Ａ）は、本発明の第８の実施形態に係る積層体１０Ｊの構成を示す側面断面図であり、図１５（Ｂ）は、本発明の第８の実施形態に係る積層体１０Ｊを表面側から視た平面図である。
　（第１の実施形態）
　本発明の第１の実施形態に係る積層体について、図を参照して説明する。図１（Ａ）は、本発明の第１の実施形態に係る積層体１０の構成を示す側面断面図であり、図１（Ｂ）は、図１（Ａ）の一部を拡大した側面断面図である。図２は、本発明の第１の実施形態に係る積層体１０を表面側から視た平面図である。図３は、本発明の第１の実施形態に係る積層体１０の製造方法を示すフローチャートである。図４（Ａ）－図４（Ｄ）は、本発明の第１の実施形態に係る積層体１０の製造方法を示す側面断面図である。図５（Ａ）－図５（Ｃ）は、本発明の第１の実施形態に係る積層体１０の製造方法を示す側面断面図である。各図において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　＜積層体の構造＞
　図１（Ａ）に示すように、積層体１０は、第１電子部品１００、構造体１５０、配線電極１６１、端子電極１６２、貫通電極１６５、ソルダーレジスト層１７０，１７５、接続パッド１８０、第２電子部品２００、半田バンプ３００を備える。
　第１電子部品１００は、構造体１５０に配置されている。第２電子部品２００は、半田バンプ３００を用いて、接続パッド１８０が形成された構造体１５０に実装されている。詳細な配置構造、実装構造については後述する。接続パッド１８０は、例えば、Ｎｉ、Ａｕ、Ｐｔ、Ｐｄ等で形成されている。
　第１電子部品１００は、図１（Ａ）の太矢印で示す高さ方向に略直交し、互いに対向する主面１０１、主面１０２を備えている。主面１０１が本発明の「第１電子部品の表面」である。
　第１電子部品１００、第２電子部品２００は、例えば直方体形状であり、半導体基板を用いたＩＣまたは圧電体基板を用いたＳＡＷフィルタ等である。
　構造体１５０は、樹脂で形成されている。構造体１５０は、平面視において、第１領域Ｒ１、第２領域Ｒ２を有する。第２領域Ｒ２は、第１領域Ｒ１の間に挟まれる形状である。第１領域Ｒ１は、高さ方向に略直交し、互いに対向する主面１５１、主面１５２を有する。主面１５１が本発明の「第１領域の表面」である。第２領域Ｒ２は、高さ方向に略直交し、互いに対向する主面１５３、主面１５４を有する。構造体１５０は、高さ方向に略平行で、互いに対向する第１側面Ｓ１、第２側面Ｓ２を備える。
　第１領域Ｒ１の主面１５２と第２領域Ｒ２の主面１５４は面一である。第１領域Ｒ１の主面１５１は、高さ方向において、第２領域Ｒ２の主面１５３よりも高い位置に形成されている。この際、主面１５１と主面１５３との高低差は、第１電子部品１００の高さよりも大きい。
　構造体１５０の第１領域Ｒ１の構造について説明する。第１領域Ｒ１における構造体１５０の内部には、貫通電極１６５が形成されている。主面１５１には、配線電極１６１が形成されている。主面１５２には、端子電極１６２が形成されている。配線電極１６１は、貫通電極１６５を介して、端子電極１６２に接続されている。端子電極１６２の一部は、ソルダーレジスト層１７５で覆われている。
　構造体１５０の第２領域Ｒ２の構造について説明する。第２領域Ｒ２には、第１電子部品１００が配置されている。第１電子部品１００は、第１電子部品１００の主面１０２と、構造体１５０の主面１５３が当接するように、あるいは第１電子部品１００の主面１０２と構造体１５０の主面１５３との間に絶縁層と金属導体を介して、配置されている。
　図１（Ｂ）に示すように、高さ方向において、第１領域Ｒ１における主面１５１の位置は、第１電子部品１００の主面１０１の位置よりも高い。具体的には、高さ方向において、主面１０１と主面１５１は、段差Ｈ１を有する。
　本願発明における段差とは、高さ方向において、主面１０１と主面１５１との間における高低差であり、形状については限定しない。なお、以下に示す構造について、複数の平面で形成される高低差、また高い位置と低い位置で形成される高低差は、全て段差として説明する。
　配線電極１６１は、上述の主面１５１から第１電子部品１００の主面１０１に亘って連続して形成されている。すなわち、構造体１５０の主面１５１と、第１電子部品１００の主面１０１とにつながる段差面Ｂ１を跨ぐように形成されている。なお、段差面Ｂ１とは、構造体１５０における第１領域Ｒ１の第２領域Ｒ２側の側面であり、配線電極１６１および接続パッド１８０を取り除いた構造体１５０において、第２領域Ｒ２の主面１０１側に露出する面である。言い換えれば、段差面Ｂ１は、段差Ｈ１で形成される面である。
　接続パッド１８０は、配線電極１６１における構造体１５０側の面と反対側の面、すなわち、配線電極１６１において主面１５１、第１電子部品１００の主面１０１および段差面Ｂ１に当接する面と反対側の面に形成されている。
　第２電子部品２００は、半田バンプ３００を介して、接続パッド１８０に実装されている。この際、半田バンプ３００は、段差面Ｂ１の領域を含むように接続している。
　上述のとおり、主面１０１と主面１５１は、段差Ｈ１を有する。すなわち、接続パッド１８０は、主面１０１と主面１５１が面一である場合よりも、段差面Ｂ１の面積と略同じ面積分だけ大きくなる。したがって、半田バンプ３００との接続部分の面積（以下、接続面積）を大きくできる。
　積層体１０は、主面１０１が主面１５１よりも低く、接続パッド１８０のうち段差面Ｂ１に当接する部分が積層体１０の中心側（構造体１５０における第２領域Ｒ２側）に形成される構造である。言い換えれば、積層体１０の中心側の領域が外縁側（構造体１５０における第１領域Ｒ１側）の領域よりも凹んだ構造である。ここで、構造体１５０と第２電子部品２００との間に生じる熱応力が、第２電子部品２００が構造体１５０の主面１５１に対して、高さ方向に直交する方向に延びる力である場合、すなわち、積層体１０の中心側の領域から外縁側の領域に向かう方向に掛かる力である場合には、半田バンプ３００が段差面Ｂ１（段差Ｈ１の部分）、および、接続パッド１８０のうち段差面Ｂ１に当接する部分に押しつけられる。したがって、接続パッド１８０と半田バンプ３００との間の接続強度が向上して、破断を抑制できる。
　具体的には、次に示す通りである。図２は、積層体１０の第２電子部品２００が実装された側、言い換えれば主面１０１側（主面１５１側）から視た平面図である。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。なお、図２では、段差Ｈ１の向きを示すため、接続パッド１８０、半田バンプ３００のみを示しており、その他の構成は省略している。
　半田バンプ３００は、第１領域Ｒ１と第２領域Ｒ２を跨ぐように形成されている。また、積層体１０の中心位置に対して対称な位置に、半田バンプ３００は２箇所形成されている。
　図２において、左側の接続パッド１８０（第１側面Ｓ１側の接続パッド１８０）では、段差Ｈ１における高い面（主面１５１）から低い面（主面１０１）に並ぶ向きは、第１側面Ｓ１から第２側面Ｓ２へ延びる方向である。逆に右側の接続パッド１８０（第２側面Ｓ２側の接続パッド１８０）の段差Ｈ１における高い面（主面１５１）から低い面（主面１０１）に並ぶ向きは、第２側面Ｓ２から第１側面Ｓ１へ延びる方向である。したがって、第２電子部品２００が延びた時、すなわち、第２電子部品２００において積層体１０の中心側の領域から外縁側の領域に向かう方向に力が掛かった時は、半田バンプ３００と接続パッド１８０とが段差面Ｂ１に押しつけられる。よって、半田バンプ３００と接続パッド１８０との間の接続強度は、向上する。
　また、図２に示すように、高さ方向に延びる段差Ｈ１（段差面Ｂ１）によって、接続パッド１８０と半田バンプ３００との接触面積が大きくなるため、第２電子部品２００を実装する側、言い換えれば主面１０１側（主面１５１側）から平面視した場合の、接続パッド１８０や半田バンプ３００の面積の増加を抑制できる。したがって、積層体１０の小型化を実現できる。
　＜積層体の製造方法＞
　図３は、積層体１０の製造方法を示すフローチャートである。図４（Ａ）、図４（Ｂ）、図４（Ｃ）、図４（Ｄ）、図５（Ａ）、図５（Ｂ）、図５（Ｃ）は、積層体１０の製造方法の第１例における主要工程での形状を示す断面図である。
　図３、図４（Ａ）に示すように、支持体４４０、接着層４３０、給電層４２０をこの順に積層する。給電層４２０の支持体４４０が配置されている面とは逆側の面に貫通電極１６５を電解めっき法等で形成する（Ｓ１０１）。同様に、給電層４２０の支持体４４０が配置されている面とは逆側の面に仮固定材４１０を部分的に（貫通電極１６５同士の間に）配置し、仮固定材４１０に第１電子部品１００を配置する（Ｓ１０２）。なお、仮固定材４１０は、例えば、高分子材からなる樹脂や溶剤を含有した樹脂などの樹脂主体材料で形成されている。
　図３、図４（Ｂ）に示すように、給電層４２０の支持体４４０が配置されている面とは逆側を樹脂で封止し硬化させる。この際、貫通電極１６５、仮固定材４１０、および、第１電子部品１００を覆うように、貫通電極１６５、仮固定材４１０、および、第１電子部品１００を樹脂で封止する。このことによって、仮固定材４１０が存在しない領域に構造体１５０が形成される（Ｓ１０３）。
　図３、図４（Ｃ）に示すように、仮固定材４１０、給電層４２０、接着層４３０、支持体４４０を除去する（Ｓ１０４）。この際、仮固定材４１０が除去されることによって、段差Ｈ１が形成される。すなわち、段差Ｈ１は、仮固定材４１０の厚みによって決定される。
　図３、図４（Ｄ）に示すように、貫通電極１６５の構造体１５０が形成されていない側、言い換えれば、仮固定材４１０を除去した部分に配線電極１６１を形成する。配線電極１６１は、段差Ｈ１を有する部分（段差面Ｂ１の部分）を跨ぐように形成される。次に、配線電極１６１に当接するように、すなわち段差Ｈ１有する部分（段差面Ｂ１の部分）を跨ぐように、接続パッド１８０を形成する（Ｓ１０５）。
　なお、接続パッド１８０が形成される前後に、ソルダーレジスト層１７０が、構造体１５０、および、第１電子部品１００における配線電極１６１が形成された側の主面上と、配線電極１６１上とに形成されてもよい。
　例えば、接続パッド１８０が形成される前にソルダーレジスト層１７０を形成する場合には、配線電極１６１上に形成されたソルダーレジスト層１７０の一部、具体的には、段差Ｈ１を有する部分に形成されたソルダーレジスト層１７０を除去した部分に接続パッド１８０を形成することで、段差面Ｂ１を跨ぐような接続パッド１８０を得られる。また、ソルダーレジスト層１７０を接続パッド１８０が形成された後に形成する場合には、ソルダーレジスト層１７０を接続パッド１８０の少なくとも一部を覆わないように形成することで、段差面Ｂ１を跨ぐような接続パッド１８０を得られる。
　図３、図５（Ａ）に示すように、構造体１５０における第１電子部品１００が配置されていない側の主面を研削し、貫通電極１６５を露出させる（Ｓ１０６）。
　図３、図５（Ｂ）に示すとおり、貫通電極１６５と接続するように端子電極１６２を形成する。端子電極１６２の一部を覆うようにソルダーレジスト層１７５を形成する（Ｓ１０７）。
　図３、図５（Ｃ）に示すように、第２電子部品２００を、半田バンプ３００を介して接続パッド１８０に実装する（Ｓ１０８）。
　このような製造方法を用いることによって、上述の積層体１０の構成を確実且つ高精度に実現できる。
　（第２の実施形態）
　次に、第２の実施形態に係る積層体について、図を参照して説明する。図６（Ａ）は、本発明の第２の実施形態に係る積層体１０Ａの構成を示す側面断面図であり、図６（Ｂ）は、図６（Ａ）の一部を拡大した側面断面図である。図７は、積層体１０Ａの製造方法を示すフローチャートである。図８（Ａ）－図８（Ｄ）は、本発明の第２の実施形態に係る積層体１０Ａの製造方法を示す側面断面図である。図９（Ａ）－図９（Ｄ）は、本発明の第２の実施形態に係る積層体１０Ａの製造方法を示す側面断面図である。各図において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　＜積層体の構造＞
　図６（Ａ）、図６（Ｂ）に示すように、第２の実施形態に係る積層体１０Ａは、第１の実施形態に係る積層体１０に対して、第１電子部品１００の図６（Ａ）に太矢印で示す高さ方向における配置位置、および段差Ｈ２、配線電極１６１Ａ、接続パッド１８０Ａの形状において異なる。積層体１０Ａにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　第１領域Ｒ１は、互いに対向する主面１５１、主面１５２を有する。第２領域Ｒ２は、互いに対向する主面１５３Ａ、主面１５４を有する。
　第１領域Ｒ１の主面１５２と第２領域Ｒ２の主面１５４は面一である。主面１５１は、高さ方向において、主面１５３Ａよりも高い位置に形成されている。しかしながら、主面１５１と主面１５３Ａとの高低差は、第１電子部品１００の高さよりも小さい。
　構造体１５０Ａの第２領域Ｒ２には、第１電子部品１００が配置されている。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。第１電子部品１００は、第１電子部品１００の主面１０２と、構造体１５０Ａの主面１５３Ａが当接するように、あるいは第１電子部品１００の主面１０２と構造体１５０の主面１５３Ａとの間に絶縁層と金属導体を介して、配置されている。このように第１電子部品１００を主面１０２に配置することによって、高さ方向における主面１５１の位置は、第１電子部品１００の主面１０１の位置よりも低くなる。言い換えれば、主面１０１は、主面１５１よりも高くなる。
　より具体的には、図６（Ｂ）に示すように、高さ方向において、第１領域Ｒ１における主面１５１の位置は、第１電子部品１００の主面１０１の位置よりも低い。具体的には、高さ方向において、主面１０１と主面１５１は、段差Ｈ２を有する。
　配線電極１６１Ａは、第１電子部品１００の主面１０１と構造体１５０Ａの主面１５１とに亘って連続して形成されている。すなわち、構造体１５０Ａの主面１５１の段差面Ｂ２を跨ぐように形成されている。なお、段差面Ｂ２とは、構造体１５０Ａにおける第１領域Ｒ１の第２領域Ｒ２側の側面であり、配線電極１６１Ａおよび接続パッド１８０Ａを取り除いた構造体１５０において、第２領域Ｒ２の主面１０１側に露出する面である。言い換えれば、段差面Ｂ２は、段差Ｈ２で形成される面である。
　接続パッド１８０Ａは、配線電極１６１Ａにおける構造体１５０Ａ側の面と反対側の面、すなわち、配線電極１６１Ａにおいて主面１０１、第１電子部品１００の主面１５１および、段差面Ｂ２に当接する面と反対側の面に形成されている。
　第２電子部品２００は、半田バンプ３００を介して、接続パッド１８０Ａに実装されている。この際、半田バンプ３００は、段差面Ｂ２の領域を含むように接続している。
　上述のとおり、主面１０１と主面１５１は、段差Ｈ２を有する。すなわち、接続パッド１８０Ａは、主面１０１と主面１５１が面一である場合よりも、段差面Ｂ２の面積と略同じ面積分だけ大きくなる。したがって、半田バンプ３００と接続パッド１８０Ａとの接続面積を大きくできる。
　積層体１０Ａは、主面１０１が主面１５１よりも高く、接続パッド１８０のうち段差面Ｂ２に当接する部分が積層体１０Ａの外縁側（構造体１５０Ａにおける第１領域Ｒ１側）に露出する構造である。言い換えれば、積層体１０Ａの中心側（構造体１５０Ａにおける第２領域Ｒ２側）の領域が外縁側の領域よりも出っ張った構造である。ここで、構造体１５０Ａと第２電子部品２００との間に生じる熱応力が生じる場合、第２電子部品２００が構造体１５０Ａの主面１５１に対して、高さ方向に直交する方向に縮む力である場合、すなわち、積層体１０の外縁側の領域から中心側の領域に向かう方向に掛かる力である場合には、半田バンプ３００が段差面Ｂ２（段差Ｈ２の部分）、および、接続パッド１８０Ａのうち段差面Ｂ２に当接する部分に押しつけられる。したがって、接続パッド１８０Ａと半田バンプ３００との間の接続強度が向上して、破断を抑制できる。
　また、高さ方向に延びる段差Ｈ２（段差面Ｂ２）によって、接続パッド１８０Ａと半田バンプ３００との接触面積が大きくなるため、第２電子部品２００を実装する側、言い換えれば主面１０１側（主面１５１側）から平面視した場合の、接続パッド１８０Ａや半田バンプ３００の面積の増加を抑制できる。したがって、積層体１０Ａの小型化を実現できる。
　＜積層体の製造方法＞
　図７は、積層体１０Ａの製造方法を示すフローチャートである。図８（Ａ）、図８（Ｂ）、図８（Ｃ）、図８（Ｄ）、図８（Ｅ）、図９（Ａ）、図９（Ｂ）、図９（Ｃ）、図９（Ｄ）、図９（Ｅ）は、積層体１０Ａの製造方法の第２例における主要工程での形状を示す断面図である。
　図７、図８（Ａ）に示すように、支持体４４０、仮固定材４１０、給電層４２０をこの順に積層する。給電層４２０の支持体４４０が配置されている面とは逆側の面に貫通電極１６５を電解めっき法や導電ペースト充填法などで形成する（Ｓ２０１）。このとき、仮固定材４１０は、支持体４４０と給電層４２０とを接着する接着層４３０としても機能する。
　図７、図８（Ｂ）に示すように、給電層４２０をエッチングし、給電電極４２５を形成するとともに、第１電子部品１００の配置領域の仮固定材４１０を露出させる（Ｓ２０２）。
　図７、図８（Ｃ）に示すように、仮固定材４１０の露出された領域に、第１電子部品１００を配置する（Ｓ２０３）。この際、第１電子部品１００が仮固定材４１０を所定の深さで埋まるように、第１電子部品１００を仮固定材４１０に配置する。
　図７、図８（Ｄ）に示すように、仮固定材４１０の支持体４４０が配置されている面とは逆側を樹脂で封止し硬化させる（Ｓ２０４）。この際、貫通電極１６５、仮固定材４１０、および、第１電子部品１００を覆うように樹脂で封止する。このことによって、構造体１５０Ａが形成される。
　図７、図９（Ａ）に示すように、構造体１５０Ａにおける仮固定材４１０と反対側の部分を研削し、貫通電極１６５を露出させる（Ｓ２０５）。
　図７、図９（Ｂ）に示すように、仮固定材４１０、給電層４２５、支持体４４０を除去する（Ｓ２０６）。上述のとおり、第１電子部品１００が仮固定材４１０に所定の深さで埋まるように配置されている。この仮固定材４１０を除去することによって、段差Ｈ２が形成される。すなわち、段差Ｈ２は、仮固定材４１０に対する第１電子部品１００の埋め込み量によって決定される。
　図７、図９（Ｃ）に示すように、貫通電極１６５の構造体１５０Ａが形成されていない側、言い換えれば、仮固定材４１０を除去した側に配線電極１６１Ａを形成する。配線電極１６１Ａは、段差Ｈ２を有する部分（段差面Ｂ２の部分）を跨ぐように形成される。次に、配線電極１６１Ａに当接するように、すなわち段差Ｈ２を有する部分（段差面Ｂ２の部分）を跨ぐように、接続パッド１８０Ａを形成する（Ｓ２０７）。
　なお、接続パッド１８０が形成される前後に、ソルダーレジスト層１７０が、構造体１５０Ａ、および、第１電子部品１００における配線電極１６１Ａが形成された側の主面上と、配線電極１６１Ａ上とに形成されてもよい。
　例えば、接続パッド１８０Ａが形成される前にソルダーレジスト層１７０を形成する場合には、配線電極１６１Ａ上に形成されたソルダーレジスト層１７０の一部、具体的には、段差Ｈ２を有する部分に形成されたソルダーレジスト層１７０を除去した部分に接続パッド１８０Ａを形成することで、段差面Ｂ２を跨ぐような接続パッド１８０Ａを得られる。また、ソルダーレジスト層１７０を接続パッド１８０Ａが形成された後に形成する場合には、ソルダーレジスト層１７０を接続パッド１８０Ａの少なくとも一部を覆わないように形成することで、段差面Ｂ２を跨ぐような接続パッド１８０Ａを得られる。
　図７、図９（Ｄ）に示すとおり、貫通電極１６５と接続するように端子電極１６２を形成する。端子電極１６２の一部を覆うようにソルダーレジスト層１７５を形成する（Ｓ２０８）。
　図７、図９（Ｅ）に示すように、第２電子部品２００を、半田バンプ３００を介して接続パッド１８０Ａに実装する（Ｓ２０９）。
　このような製造方法を用いることによって、上述の積層体１０Ａの構成を確実且つ高精度に実現できる。
　（第３の実施形態）
　次に、第３の実施形態に係る積層体について、図を参照して説明する。図１０は、本発明の第３の実施形態に係る積層体１０Ｂの構成を示す側面断面図である。図１０において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　図１０に示すように、第３の実施形態に係る積層体１０Ｂは、第１の実施形態に係る積層体１０に対して、樹脂膜１９０を備えている点、接続電極１９５を備えている点、および配線電極１６１Ｂ、接続パッド１８０Ｂの形状において異なる。積層体１０Ｂにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　図１０に示すように、積層体１０Ｂは、第１電子部品１００、構造体１５０、端子電極１６２、配線電極１６１Ｂ、貫通電極１６５、ソルダーレジスト層１７０，１７５、接続パッド１８０Ｂ、樹脂膜１９０、接続電極１９５、第２電子部品２００、半田バンプ３００を備える。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。
　樹脂膜１９０は、主面１５１、段差面Ｂ１、主面１０１に亘って、連続して形成されている。
　すなわち、樹脂膜１９０は、段差Ｈ１を跨ぐように形成されている。より具体的には、樹脂膜１９０は、段差Ｈ１の段差面Ｂ１と主面１５１との間、および、段差面Ｂ１と主面１０１との間に生じる角（鋭角な部分）を覆い、主面１５１と、主面１０１とをなだらかな形状（スロープ状）で接続するように形成されている。
　配線電極１６１Ｂは、樹脂膜１９０における主面１５１，１０１側の面とは反対側の面を覆うように形成されている。なお、樹脂膜１９０には、接続電極１９５が形成されており、配線電極１６１Ｂは、接続電極１９５を介して、貫通電極１６５に接続されている。
　接続パッド１８０Ｂは、配線電極１６１Ｂにおける、主面１０１、段差面Ｂ１、第１電子部品１００の主面１５１とは反対側の面に形成されている。より具体的には、接続パッド１８０Ｂは、配線電極１６１Ｂ、樹脂膜１９０を介して、第１電子部品１００と構造体１５０とを繋ぐスロープ状の面を覆うように形成されている。
　第２電子部品２００は、半田バンプ３００を介して、接続パッド１８０Ｂに接続されている。
　このような構成であっても、主面１０１と主面１５１は、段差Ｈ１を有する。すなわち、主面１０１と主面１５１が面一である場合よりも、接続パッド１８０Ｂの面積は大きくなり、半田バンプ３００と接続パッド１８０Ｂとの接続面積を大きくできる。
　さらに、段差Ｈ１の段差面Ｂ１と主面１５１，１０１のそれぞれとの間に生じる角（鋭角な部分）を樹脂膜１９０で覆うことにより、半田バンプ３００において応力が特定の箇所に集中し難くなる。したがって、半田バンプ３００内の破断を抑制できる。
　積層体１０Ｂは、主面１０１が主面１５１よりも低く、積層体１０Ｂの中央領域が外縁領域よりも凹んだ構造である。ここで、構造体１５０と第２電子部品２００の間に生じる熱応力が、第２電子部品２００が構造体１５０の主面１５１に対して、高さ方向に直交する方向に延びる力であった場合、半田バンプ３００は、段差面Ｂ１（段差Ｈ１の部分）に押しつけられる。したがって、接続パッド１８０Ｂと半田バンプ３００との接続強度が向上して、破断を抑制できる。
　また、第２電子部品２００を実装する側、言い換えれば主面１０１側（主面１５１側）から平面視した場合の面積の増加を抑制できる。したがって、積層体１０Ｂの小型化を実現できる。
　（第４の実施形態）
　次に、第４の実施形態に係る積層体について、図を参照して説明する。図１１は、本発明の第４の実施形態に係る積層体１０Ｃの構成を示す側面断面図である。図１１において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　図１１に示すように、第４の実施形態に係る積層体１０Ｃは、第２の実施形態に係る積層体１０Ａに対して、樹脂膜１９０を備えている点、接続電極１９５を備えている点、および配線電極１６１Ｃ、接続パッド１８０Ｃの形状において異なる。積層体１０Ｃにおける他の基本構成は、積層体１０Ａと同様であり、同様の箇所の説明は省略する。
　図１１に示すように、積層体１０Ｃは、第１電子部品１００、構造体１５０Ｃ、端子電極１６２、配線電極１６１Ｃ、貫通電極１６５、ソルダーレジスト層１７０，１７５、接続パッド１８０Ｃ、樹脂膜１９０、接続電極１９５、第２電子部品２００、半田バンプ３００を備える。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。
　樹脂膜１９０は、主面１５１、段差面Ｂ２、主面１０１に亘って、連続して形成されている。
　すなわち、樹脂膜１９０は、段差Ｈ２を有する部分を跨ぐように形成されている。より具体的には、樹脂膜１９０は、段差Ｈ２の段差面Ｂ２と主面１５１との間、および、段差面Ｂ２と主面１０１との間に生じる角（鋭角な部分）を覆い、主面１５１と、主面１０１とをなだらかな形状（スロープ状）で接続するように形成されている。
　配線電極１６１Ｃは、樹脂膜１９０における主面１５１，１０１側の面とは反対側の面を覆うように形成されている。なお、樹脂膜１９０には、接続電極１９５が形成されており、配線電極１６１Ｃは、接続電極１９５を介して、貫通電極１６５に接続されている。
　接続パッド１８０Ｃは、配線電極１６１Ｃにおける、主面１０１、段差面Ｂ２、第１電子部品１００の主面１５１と反対側の面に形成されている。より具体的には、接続パッド１８０Ｃは、配線電極１６１Ｃ、樹脂膜１９０を介して、第１電子部品１００と構造体１５０Ｃとを繋ぐスロープ状の面を覆うように形成されている。
　第２電子部品２００は、半田バンプ３００を介して、接続パッド１８０Ｃに接続されている。
　このような構成であっても、主面１０１と主面１５１は、段差Ｈ２を有する。すなわち、主面１０１と主面１５１が面一である場合よりも、接続パッド１８０Ｃの面積は大きくなり、半田バンプ３００と接続パッド１８０との接続面積を大きくできる。
　さらに、段差Ｈ２の段差面Ｂ２と主面１５１，１０１のそれぞれとの間に生じる角（鋭角な部分）を樹脂膜１９０で覆うことにより、半田バンプ３００において応力が特定の箇所に集中し難くなる。したがって、半田バンプ３００内の破断を抑制できる。
　また、構造体１５０Ｃと第２電子部品２００の間に生じる熱応力が、第２電子部品２００が構造体１５０Ｃの主面１５１に対して、高さ方向に直交する方向に縮む力であった場合、半田バンプ３００は、段差Ｈ２の部分に押しつけられる。したがって、接続パッド１８０Ｃと半田バンプ３００との接続強度が向上し、破断を抑制できる。
　また、第２電子部品２００を実装する側、言い換えれば主面１０１側（主面１５１側）から平面視した場合の面積の増加を抑制できる。したがって、積層体１０Ｃの小型化を実現できる。
　（第５の実施形態）
　次に、第５の実施形態に係る積層体について、図を参照して説明する。図１２は、本発明の第５の実施形態に係る積層体１０Ｄの構成を示す側面断面図である。図１２において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　図１２に示すように、第５の実施形態に係る積層体１０Ｄは、第１の実施形態に係る積層体１０に対して、樹脂膜１９１，１９２を備えている点、接続電極１９５，１９６を備えている点、および配線電極１６１Ｄ，１６３Ｄ、接続パッド１８０Ｄの形状において異なる。積層体１０Ｄにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　図１２に示すように、積層体１０Ｄは、第１電子部品１００、構造体１５０、端子電極１６２、配線電極１６１Ｄ，１６３Ｄ、貫通電極１６５、ソルダーレジスト層１７０，１７５、接続パッド１８０Ｄ、樹脂膜１９１，１９２、接続電極１９５，１９６、第２電子部品２００、半田バンプ３００を備える。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。
　樹脂膜１９１は、主面１５１、段差面Ｂ１、主面１０１に亘って、連続して形成されている。
　樹脂膜１９１は、段差Ｈ１を有する部分を跨ぐように形成されている。より具体的には、樹脂膜１９１は、段差Ｈ１の段差面Ｂ１と主面１５１との間、および、段差面Ｂ１と主面１０１との間に生じる角（鋭角な部分）を覆い、主面１５１と、主面１０１とをなだらかな形状（スロープ状）とするように形成されている。
　配線電極１６１Ｄは、樹脂膜１９１における主面１５１，１０１側の面とは反対側の面を覆うように形成されている。なお、樹脂膜１９１には、接続電極１９５が形成されており、配線電極１６１Ｄは、接続電極１９５を介して貫通電極１６５に接続されている。
　樹脂膜１９２は、樹脂膜１９１、配線電極１６１Ｄにおける樹脂膜１９１側の面とは反対側の面を覆うように形成されている。樹脂膜１９２は、樹脂膜１９１と同様に、主面１５１、段差面Ｂ１、主面１０１に亘って連続して形成されている。
　すなわち、樹脂膜１９２は、段差Ｈ１を有する部分を跨ぐように形成されている。より具体的には、樹脂膜１９２は、段差Ｈ１の段差面Ｂ１と主面１５１との間、および、段差面Ｂ１と主面１０１との間に生じる角（鋭角な部分）を覆い、主面１５１と、主面１０１とをなだらかな形状（スロープ状）で接続するように形成されている。
　配線電極１６３Ｄは、樹脂膜１９２における配線電極１６１Ｄ側の面とは反対側の面を覆うように形成されている。なお、樹脂膜１９２には、接続電極１９６が形成されている。配線電極１６３Ｄは、接続電極１９６を介して、配線電極１６１Ｄに接続されている。
　接続パッド１８０Ｄは、配線電極１６３Ｄにおける、主面１０１、段差面Ｂ１、第１電子部品１００の主面１５１と反対側の面に形成されている。より具体的には、接続パッド１８０Ｄは、配線電極１６１Ｄ，１６３Ｄ、樹脂膜１９１，１９２を介して、第１電子部品１００と構造体１５０とを繋ぐスロープ状の面を覆うように形成されている。
　第２電子部品２００は、半田バンプ３００を介して、接続パッド１８０Ｄに接続されている。
　このような構成であっても、主面１０１と主面１５１は、段差Ｈ１を有する。すなわち、主面１０１と主面１５１が面一である場合よりも、接続パッド１８０Ｄの面積は大きくなり、半田バンプ３００と接続パッド１８０との接続面積を大きくできる。
　さらに、段差Ｈ１の段差面Ｂ１と主面１５１，１０１のそれぞれとの間に生じる角（鋭角な部分）を複数の樹脂膜１９１，１９２で覆うことにより、当該鋭角な部分を１つの樹脂膜で覆う場合と比べて、半田バンプ３００の応力が特定の箇所により集中し難くなる。したがって、半田バンプ３００内の破断をさらに抑制できる。
　また、樹脂膜１９１，１９２を形成することによって、積層体１０Ｄにおけるクッション性を向上させることができ、第２電子部品２００の実装時等の積層体１０の破損を抑制できる。
　積層体１０Ｄは、主面１０１が主面１５１よりも低く、積層体１０Ｄの中央領域が外縁領域よりも凹んだ構造である。ここで、構造体１５０と第２電子部品２００の間に生じる熱応力が、第２電子部品２００が構造体１５０の主面１５１に対して、高さ方向に直交する方向に延びる力であった場合に、半田バンプ３００は、段差面Ｂ１（段差Ｈ１の部分）に押しつけられる。したがって、接続パッド１８０Ｄと半田バンプ３００との間の接続強度が向上し、破断を抑制できる。
　また、第２電子部品２００を実装する側、言い換えれば主面１０１側（主面１５１側）から平面視した場合の面積の増加を抑制できる。したがって、積層体１０Ｄの小型化を実現できる。
　なお、上述の第４の実施形態に係る積層体１０Ｃは、段差面Ｂ１を跨ぐ複数の樹脂膜を有する構成であってもよい。この場合にも、本実施形態と同様の効果が得られる。
　（第６の実施形態）
　次に、第６の実施形態に係る積層体について、図を参照して説明する。図１３は、本発明の第６の実施形態に係る積層体１０Ｅの構成を示す側面断面図である。図１３において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　図１３に示すように、第６の実施形態に係る積層体１０Ｅは、第１の実施形態に係る積層体１０に対して、補助部材４００を複数備えている点において異なる。積層体１０Ｅにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　図１３に示すように、複数の補助部材４００は、接続パッド１８０の第２電子部品２００が実装されている側の面に形成されている。補助部材４００は、導体であることが好ましい。また、補助部材４００が接続パッド１８０と同じ材質である場合には、補助部材４００と接続パッド１８０との線膨張率の差が生じないため、高い信頼性を得られる点でより好ましい。
　この構成では、補助部材４００が形成されていることにより、半田バンプ３００と接続パッド１８０との接続面積をさらに大きくできる。
　複数の補助部材４００を配置する位置は、接続パッド１８０において、接続パッド１８０と半田バンプ３００とが接する側の面上のいずれかの位置であればよい。すなわち、補助部材４００を配置する位置は、補助部材４００により接続パッド１８０の表面（接続パッド１８０における配線電極１６１側の面とは反対側の面）に半田バンプ３００と接続される段差ができるような位置であれば、限定する必要はない。また、本実施形態では補助部材４００を２つ形成する構成について示したが、１つ、または、３つ以上の構成であってもよく、接続パッド１８０と半田バンプ３００との接続を妨げない数の補助部材４００を設けてもよい。
　なお、上述の構成では、複数の補助部材４００を形成することによって、接続面積を大きくする構成について示した。しかしながら、接続パッド１８０の表面を粗くすることでも同様の効果を得ることができる。このことによって、接続パッド１８０の表面における粗い部分に半田バンプ３００が入り込み、接続面積が増加し、接続パッド１８０と半田バンプ３００の接続強度がより向上する。
　なお、高さ方向における段差Ｈ１の厚みは、上述の接続パッド１８０表面の最も粗い部分の厚みよりも大きいことが好ましい。このことによって、接続パッド１８０と半田バンプ３００の接続強度がより顕著に向上する。
　（第７の実施形態）
　次に、第７の実施形態に係る積層体について、図を参照して説明する。図１４（Ａ）－図１４（Ｃ）は、本発明の第７の実施形態に係る積層体を表面側から視た平面図である。図１４（Ａ）、図１４（Ｂ）、図１４（Ｃ）において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。また、図１４（Ａ）、図１４（Ｂ）、図１４（Ｃ）においては、半田バンプ３００のみを示しており、その他の構成は省略している。第１電子部品１００は、平面視において第２電子部品２００と重なるように配置されている。
　図１４（Ａ）に示すように、第７の実施形態に係る積層体１０Ｆは、第１の実施形態に係る積層体１０に対して、半田バンプ３００Ｆが第１側面Ｓ１側に２箇所、第２側面Ｓ２側に２箇所形成されている点で異なる。すなわち、半田バンプ３００Ｆのそれぞれと接続される接続パッド１８０も第１側面Ｓ１側に２箇所、第２側面Ｓ２側に２箇所形成されている。積層体１０Ｆにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　この構成であっても、接続パッド１８０は、半田バンプ３００Ｆと接続面積をより大きくできる。さらに、段差Ｈ１は、積層体１０Ｆの高さ方向に形成されているため、積層体１０Ｆを平面視した場合の面積は増加しない。したがって、積層体１０Ｆの小型化を実現できる。
　図１４（Ｂ）に示すように、第７の実施形態に係る積層体１０Ｇは、第１の実施形態に係る積層体１０に対して、半田バンプ３００Ｇが第１側面Ｓ１側に３箇所、第２側面Ｓ２側に３箇所形成されている点で異なる。すなわち、半田バンプ３００Ｇのそれぞれと接続される接続パッド１８０も第１側面Ｓ１側に３箇所、第２側面Ｓ２側に３箇所形成されている。積層体１０Ｇにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　この構成であっても、接続パッド１８０は、半田バンプ３００Ｇと接続面積をさらに大きくできる。さらに、段差Ｈ１は、積層体１０Ｇの高さ方向に形成されているため、積層体１０Ｇを平面視した場合の面積は増加しない。したがって、積層体１０Ｇの小型化を実現できる。
　図１４（Ｃ）に示すように、第７の実施形態に係る積層体１０Ｈは、第１の実施形態に係る積層体１０に対して、半田バンプ３００Ｈが第１側面Ｓ１側、第２側面Ｓ２側に加えて、第１側面Ｓ１と第２側面Ｓ２とを結ぶ方向に延び、かつ、互いに対向する第３側面Ｓ３側、第４側面Ｓ４側にそれぞれ１箇所ずつ形成されている点で異なる。
　具体的には、半田バンプ３００Ｈは、第１電子部品１００と構造体１５０との間にできる複数の段差面Ｂ１のうち、第１側面Ｓ１側の段差面Ｂ１（不図示）を跨ぐように形成された接続パッド１８０と、第２側面Ｓ２側の段差面Ｂ１（不図示）を跨ぐように形成された接続パッド１８０のそれぞれと接続される２つの半田バンプ３００Ｈを含む。なお、第１側面Ｓ１側と第２側面Ｓ２側に形成されている段差面Ｂ１が、本発明の「第１段差面」である。
　また、半田バンプ３００Ｈは、第１電子部品１００と構造体１５０との間にできる段差面のうち、第３側面Ｓ３側の段差面Ｂ１（不図示）を跨ぐように形成された接続パッド１８０と、第４側面Ｓ４側の段差面Ｂ１（不図示）を跨ぐように形成された接続パッド１８０のそれぞれと接続される２つの半田バンプ３００Ｈを含む。なお、第３側面Ｓ３側と第４側面Ｓ４側に形成されている段差面Ｂ１が、本発明の「第２段差面」である。積層体１０Ｈにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　この構成であっても、接続パッド１８０は、半田バンプ３００Ｈとの接続面積をより大きくできる。さらに、段差Ｈ１は、積層体１０Ｈの高さ方向に形成されているため、積層体１０Ｈを平面視した場合の面積は増加しない。したがって、積層体１０Ｈの小型化を実現できる。
　さらに、複数の半田バンプ３００Ｈのうち、第１側面Ｓ１側、および、第２側面Ｓ２側の２つの半田バンプ３００Ｈとそれらに接続される接続パッド１８０により第１側面Ｓ１、第２側面Ｓ２を結ぶ方向の応力に対する接続強度を向上できる。また、複数の半田バンプ３００Ｈのうち、第３側面Ｓ３側、および、第４側面Ｓ４側の２つの半田バンプ３００Ｈとそれらに接続される接続パッド１８０によって第１側面Ｓ１、第２側面Ｓ２に平行な方向の応力に対する接続強度も向上できる。このように、複数の応力が生じる方向がそれぞれ異なる場合であっても、第１電子部品１００および構造体１５０と第２電子部品２００との接続強度を向上できるため、積層体１０Ｈの接続強度をさらに向上できる。
　なお、第７の実施形態に係る積層体１０Ｆ～積層体１０Ｈはいずれも、接続パッド１８０を複数個備えている。これにより、第２電子部品２００が第１電子部品１００および構造体１５０に固定されやすくなるため、積層体１０Ｆ～１０Ｈの接続強度は、さらに向上する。
　上述の構成では、第１電子部品１００の主面１０１が露出している構成について説明した。しかしながら、第１電子部品１００の主面１０１は、ソルダーレジスト層１７０で覆われていてもよい。この構成であれば、主面１０１を露出させる構成を省略することができ、上述の積層体１０～積層体１０Ｈを安価に形成できる。
　（第８の実施形態）
　次に、第８の実施形態に係る積層体について、図を参照して説明する。１５（Ａ）は、本発明の第８の実施形態に係る積層体１０Ｊの構成を示す側面断面図であり、図１５（Ｂ）は、本発明の第８の実施形態に係る積層体１０Ｊを表面側から視た平面図である。図１５（Ａ）、図１５（Ｂ）において縦横の寸法関係は適宜強調して記載しており、実寸での縦横の寸法関係と一致しているとは限らない。
　図１５（Ａ）、図１５（Ｂ）に示すように、第８の実施形態に係る積層体１０Ｊは、第１の実施形態に係る積層体１０に対して、段差Ｈ１が１箇所のみ形成されている点で異なる。積層体１０Ｊにおける他の基本構成は、積層体１０と同様であり、同様の箇所の説明は省略する。
　図１５（Ａ）に示すように、積層体１０Ｊは、段差Ｈ１が１箇所のみ（図１５（Ａ）における左側）形成されている。段差Ｈ１が形成されていない部分（図１５（Ａ）における右側）における貫通電極１６５は、主面１５１に略平行な形状の配線電極１６１、接続パッド１８０、半田バンプ３００を介して、第２電子部品２００に接続されている。
　この構成であっても、主面１０１と主面１５１は、段差Ｈ１を有する。すなわち、少なくとも１箇所でも段差Ｈ１が形成されていれば、接続パッド１８０は、主面１０１と主面１５１が面一である場合よりも、段差面Ｂ１の面積と略同じ面積分だけ大きくなる。したがって、半田バンプ３００と接続パッド１８０との接続面積を大きくできる。
　また、構造体１５０と第２電子部品２００との間に生じる熱応力が、第２電子部品２００が構造体１５０の主面１５１に対して、高さ方向に直交する方向に延びる力である場合、すなわち、積層体１０Ｊの中心側の領域から外縁側の領域に向かう方向に掛かる力である場合には、半田バンプ３００が段差面Ｂ１（段差Ｈ１の部分）、および、接続パッド１８０のうち段差面Ｂ１に当接する部分に押しつけられる。したがって、接続パッド１８０と半田バンプ３００との間の接続強度が向上して、破断を抑制できる。
　なお、上述の各実施形態の構成に限られるものではなく、これらの実施形態の組み合わせを変更したものであっても良い。
Ｂ１、Ｂ２…段差面
Ｈ１、Ｈ２…段差
Ｒ１…第１領域
Ｒ２…第２領域
Ｓ１…第１側面
Ｓ２…第２側面
Ｓ３…第３側面
Ｓ４…第４側面
１０、１０Ａ、１０Ｂ、１０Ｃ、１０Ｄ、１０Ｅ、１０Ｆ、１０Ｇ、１０Ｈ、１０Ｊ…積層体
１００…第１電子部品
１０１、１０２、１５１、１５２、１５３、１５３Ａ、１５４…主面
１５０、１５０Ａ、１５０Ｃ…構造体
１６１、１６１Ａ、１６１Ｂ、１６１Ｃ、１６１Ｄ、１６３Ｄ…配線電極
１６２…端子電極
１６５…貫通電極
１７０、１７５…ソルダーレジスト層
１８０、１８０Ａ、１８０Ｂ、１８０Ｃ、１８０Ｄ…接続パッド
１９０、１９１、１９２…樹脂膜
１９５、１９６…接続電極
２００…第２電子部品
３００、３００Ｆ、３００Ｇ、３００Ｈ…半田バンプ
４００…補助部材
４１０…仮固定材
４２０…給電層
４２５…給電電極
４３０…接着層
４４０…支持体

Claims (10)

  1. 　第１電子部品と、
    　平面視において、第１領域と第２領域とを備え、前記第１電子部品が前記第２領域に配置された構造体と、
    　前記構造体に、接続パッドを介してバンプ実装された第２電子部品と、
    　を備え、
    　前記構造体の高さ方向において、前記第１領域の表面と、前記第２領域の表面とは段差を有し、
    　前記接続パッドは、前記第１領域の表面、前記第２領域の表面、および前記段差によって形成された段差面に、形成されている、
    　積層体。
  2. 　前記構造体の高さ方向において、
    　前記第１領域の表面の位置は、前記第２領域の表面の位置よりも高い、請求項１に記載の積層体。
  3. 　前記構造体の高さ方向において、
    　前記第１領域の表面の位置は、前記第２領域の表面の位置よりも低い、請求項１に記載の積層体。
  4. 　前記段差を有する部分と、前記接続パッドとの間に樹脂膜が形成されている、
    　請求項１乃至請求項３のいずれかに記載の積層体。
  5. 　前記樹脂膜は、
    　複数の樹脂膜を積層して形成されている、請求項４に記載の積層体。
  6. 　前記接続パッドは、前記接続パッド上に形成された複数の補助部材を有する、
    　請求項１乃至請求項５のいずれかに記載の積層体。
  7. 　前記第１領域の表面、前記第２領域の表面、および、前記段差面に形成された、複数の前記接続パッドを有し、
    　前記第１電子部品は、複数の前記接続パッドを介して、実装されている、
    　請求項１乃至請求項６のいずれかに記載の積層体。
  8. 　複数の前記段差面を備え、
    　前記構造体は互いに対向する第１側面および第２側面と、前記第１側面および前記第２側面を結ぶ方向に延び、かつ、互いに対向する第３側面および第４側面を有し、
    　複数の前記段差面は、前記第１側面および前記第２側面のうち少なくとも一方の側面側に形成された第１段差面と、前記第３側面および前記第４側面のうち少なくとも一方の側面側に形成された第２段差面と、を含み、
    　複数の前記接続パッドは、
    　前記第１段差面または、前記第２段差面に形成されている、
    　請求項７に記載の積層体。
  9. 　支持体の表面に仮固定材を介して、第１電子部品を配置する工程と、
    　前記仮固定材と、前記第１電子部品とを覆うように樹脂で封止する工程と、
    　前記支持体と、前記仮固定材と、を取り除く工程と、
    　前記樹脂における前記支持体が配置された側の面と、前記第１電子部品における前記仮固定材が配置された面とを跨ぐように、接続パッドを形成する工程と、
    　第２電子部品を、前記接続パッドを介してバンプ実装する工程と、
    　を備える、積層体の製造方法。
  10. 　支持体の表面に形成された仮固定材に、第１電子部品の一部を埋める工程と、
    　前記仮固定材と、前記第１電子部品とを覆うように樹脂で封止する工程と、
    　前記支持体と、前記仮固定材と、を取り除く工程と、
    　前記樹脂における前記支持体が配置された側の面と、前記第１電子部品における前記仮固定材が配置された面とを跨ぐように、接続パッドを形成する工程と、
    　第２電子部品を、前記接続パッドを介してバンプ実装する工程と、
    　を備える、積層体の製造方法。
PCT/JP2019/034548 2018-09-28 2019-09-03 積層体および積層体の製造方法 WO2020066490A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980062405.9A CN112740382B (zh) 2018-09-28 2019-09-03 层叠体及层叠体的制造方法
US17/203,850 US12002779B2 (en) 2018-09-28 2021-03-17 Multilayer body and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-183240 2018-09-28
JP2018183240 2018-09-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/203,850 Continuation US12002779B2 (en) 2018-09-28 2021-03-17 Multilayer body and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2020066490A1 true WO2020066490A1 (ja) 2020-04-02

Family

ID=69950547

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/034548 WO2020066490A1 (ja) 2018-09-28 2019-09-03 積層体および積層体の製造方法

Country Status (3)

Country Link
US (1) US12002779B2 (ja)
CN (1) CN112740382B (ja)
WO (1) WO2020066490A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110088894B (zh) * 2016-12-21 2023-09-12 株式会社村田制作所 电子部件内置基板的制造方法、电子部件内置基板、电子部件装置及通信模块

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099637A (ja) * 2007-10-15 2009-05-07 Fujitsu Ltd 回路基板、半導体装置、および半導体装置の製造方法
WO2013168223A1 (ja) * 2012-05-08 2013-11-14 富士機械製造株式会社 半導体パッケージ及びその製造方法
WO2018096830A1 (ja) * 2016-11-28 2018-05-31 株式会社村田製作所 電子部品及びその製造方法
WO2018116799A1 (ja) * 2016-12-21 2018-06-28 株式会社村田製作所 電子部品内蔵基板の製造方法、電子部品内蔵基板、電子部品装置及び通信モジュール

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5228890B2 (ja) * 2008-12-24 2013-07-03 株式会社村田製作所 電子部品およびその製造方法
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
JP5884653B2 (ja) * 2011-09-01 2016-03-15 株式会社村田製作所 実装構造
JP5693763B2 (ja) * 2014-02-20 2015-04-01 新光電気工業株式会社 半導体装置及びその製造方法
JP2018032657A (ja) * 2016-08-22 2018-03-01 イビデン株式会社 プリント配線板およびプリント配線板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099637A (ja) * 2007-10-15 2009-05-07 Fujitsu Ltd 回路基板、半導体装置、および半導体装置の製造方法
WO2013168223A1 (ja) * 2012-05-08 2013-11-14 富士機械製造株式会社 半導体パッケージ及びその製造方法
WO2018096830A1 (ja) * 2016-11-28 2018-05-31 株式会社村田製作所 電子部品及びその製造方法
WO2018116799A1 (ja) * 2016-12-21 2018-06-28 株式会社村田製作所 電子部品内蔵基板の製造方法、電子部品内蔵基板、電子部品装置及び通信モジュール

Also Published As

Publication number Publication date
CN112740382A (zh) 2021-04-30
CN112740382B (zh) 2024-06-21
US12002779B2 (en) 2024-06-04
US20210203302A1 (en) 2021-07-01

Similar Documents

Publication Publication Date Title
JP4450378B2 (ja) 表面実装型コンデンサ及びその製造方法
KR101475172B1 (ko) 부품내장 배선기판
US10555421B2 (en) Component-embedded resin substrate and method for manufacturing same
JP5093353B2 (ja) 部品内蔵モジュールの製造方法及び部品内蔵モジュール
TW200428609A (en) Package for semiconductor devices
JP4930567B2 (ja) 中継基板、プリント基板ユニットおよび中継基板の製造方法
KR101253401B1 (ko) 본딩용 패드의 제조 방법
JP2010212595A (ja) パッケージ基板
JPWO2020100849A1 (ja) 実装型電子部品、および、電子回路モジュール
WO2020066490A1 (ja) 積層体および積層体の製造方法
JP2010123839A (ja) 半導体モジュール
WO2017183394A1 (ja) 多層基板および電子機器
JP6562076B2 (ja) 樹脂基板、部品搭載樹脂基板およびその製造方法
KR20070105982A (ko) 접속 부품, 적층 기판
JP2008118155A (ja) 半導体装置用パッケージ
JP6813682B2 (ja) 電子部品収納用パッケージ、電子装置および電子モジュール
US20080048310A1 (en) Carrier Board Structure Embedded with Semiconductor Component and Method for Fabricating the Carrier Board Structure
JP6191808B1 (ja) 多層基板および電子機器
JP2006202870A (ja) 立体的電子回路モジュールとその製造方法およびそれらを用いた電子装置
JP6399006B2 (ja) 部品実装基板の製造方法
JP5825171B2 (ja) 電子装置およびその製造方法
US11004759B2 (en) Electronic component and method for manufacturing the same
JPWO2013121977A1 (ja) 部品内蔵基板
JP5574067B2 (ja) 部品内蔵基板
JP2006344631A (ja) 部品内蔵基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19867759

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19867759

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP