WO2020047971A1 - 晶圆级封装方法以及封装结构 - Google Patents

晶圆级封装方法以及封装结构 Download PDF

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Publication number
WO2020047971A1
WO2020047971A1 PCT/CN2018/113100 CN2018113100W WO2020047971A1 WO 2020047971 A1 WO2020047971 A1 WO 2020047971A1 CN 2018113100 W CN2018113100 W CN 2018113100W WO 2020047971 A1 WO2020047971 A1 WO 2020047971A1
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Prior art keywords
chip
wafer
electrode
chips
insulating
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PCT/CN2018/113100
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English (en)
French (fr)
Inventor
罗海龙
德劳利·克里夫
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中芯集成电路（宁波）有限公司
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Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Priority to US16/229,360 priority Critical patent/US10756051B2/en
Publication of WO2020047971A1 publication Critical patent/WO2020047971A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a wafer-level packaging method and a packaging structure.
  • wafer level package system Compared with traditional system packaging, wafer-level system packaging is a package integration process completed on the wafer, which has the advantages of significantly reducing the area of the packaging structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, which can significantly reduce Workload and equipment requirements.
  • Wafer-level system packaging mainly includes two important processes: physical connection and electrical connection.
  • the bonding process is used to realize the physical connection between the chip to be integrated and the wafer; the electrical connection between the semiconductor devices is achieved by electroplating technology; Sexual connection.
  • the problem solved by the present invention is to provide a wafer-level packaging method and a packaging structure to simplify the packaging process.
  • the present invention provides a wafer-level packaging method, including: providing a device wafer, the device wafer including a plurality of first chips, the first chip including a first electrode, and the first electrode is provided by the device The wafer is exposed, and the surface of the device wafer where the first electrode is exposed is the front side of the wafer; a plurality of second chips are provided, the second chip includes a second electrode, and the second electrode is formed by the second electrode.
  • the chip is exposed, the surface of the second chip exposing the second electrode is the front of the chip, and the surface opposite to the front of the chip is the back of the chip; the back of the chip of the second chip is bonded to the first chip A front surface of the wafer between the two sides; forming an insulating side wall on a side wall of the second chip; and forming a conductive layer conformally covering the front side of the chip, the insulating side wall, and the front side of the wafer.
  • the step of forming an insulating sidewall on a side wall of the second chip includes: forming an insulating layer conformally covering the front side of the wafer between the second chip and the second chip; removing the second chip The insulating layer on the front side and the front side of the wafer, and the insulating layer remaining on the side wall of the second chip constitutes the insulating side wall.
  • the insulating layers on the front surface of the second chip and the front surface of the wafer are removed by dry etching.
  • the step of forming an insulating layer conformally covering the front surface of the wafer between the second chip and the second chip includes: the thickness of the insulating layer is in the range of 0.1 to 5 microns ... .
  • the material of the insulating layer is silicon nitride, silicon oxide, or silicon oxynitride.
  • the insulating layer is formed by a chemical vapor deposition method.
  • the insulating side wall completely exposes the first electrode and the second electrode.
  • the material of the conductive layer is one or more of copper, aluminum, tin, and nickel.
  • a conductive layer is formed by a chemical vapor deposition method.
  • the step of forming a conductive layer conformally covering the front side of the chip, the insulating sidewall spacer, and the front side of the wafer includes: the thickness of the conductive layer is in a range of 0.1 to 5 microns.
  • the packaging method further comprises: after forming the conductive layer, covering the packaging layer with the conductive layer.
  • the step of providing a device wafer includes: a first dielectric layer is formed on a front surface of the wafer between the first chips; the step of providing a plurality of second chips includes: a back surface of the chip of the second chip is formed A second dielectric layer; the step of bonding the back surface of the chip of the second chip to the front surface of the wafer between the first chips includes: through the bonding of the first dielectric layer and the second dielectric layer, The back side of the chip of the second chip is bonded to the front side of the wafer between the first chips.
  • the bonding between the first dielectric layer and the second dielectric layer is fusion bonding.
  • the present invention also provides a wafer-level package structure, including: a device wafer, the device wafer including a plurality of first chips, the first chip including a first electrode, and the first electrode is composed of The device wafer is exposed, and the surface of the device wafer where the first electrode is exposed is the front side of the wafer; a plurality of second chips are bonded to the front side of the wafer, and the second chip and the wafer are The front-bonded side is the back of the chip, and the side opposite to the back of the chip is the front of the chip.
  • the second chip includes a second electrode exposed from the front of the chip; an insulating sidewall is located on the second chip side.
  • a conductive layer that conformally covers the front side of the chip, the insulating side wall, and the front side of the wafer.
  • the material of the insulating side wall is silicon nitride, silicon oxide, or silicon oxynitride.
  • the material of the conductive layer is one or more of copper, aluminum, tin, and nickel.
  • the thickness of the conductive layer is in the range of 0.1 to 5 microns.
  • the thickness of the insulating side wall is in the range of 0.1 to 5 microns.
  • the packaging structure further includes: a packaging layer on the conductive layer.
  • the package structure further includes: a first dielectric layer on a front side of the wafer between the first chips; a second dielectric layer on a back side of the chip of the second chip; and a key opposite to the first dielectric layer Together.
  • an insulating side wall is formed on the side wall of the second chip, and then a conductive layer conformally covering the front surface of the chip, the insulating side wall, and the front surface of the wafer is formed.
  • the conductive layer is covered on the front side of the chip and is in contact with the second electrode on the front side of the chip; the conductive layer is also covered on the front side of the wafer and is in contact with the first electrode exposed on the front side of the wafer.
  • the conductive layer realizes the electrical connection between the first electrode and the second electrode, and further realizes the electrical connection between the first chip and the second chip, and the process is relatively simple.
  • the conductive layer also covers the insulation of the second chip. Side wall, so as to achieve insulation between the conductive layer and the second chip side wall, the insulating side wall insulates the conductive layer and the second chip from each other, thereby avoiding the performance of the conductive layer on the second chip Impact.
  • FIG. 1 to 4 are schematic structural diagrams corresponding to steps in an embodiment of a wafer-level packaging method according to the present invention.
  • 5 to 10 are schematic structural diagrams corresponding to steps in another embodiment of a wafer-level packaging method according to the present invention.
  • the present invention provides a wafer-level packaging method, including: providing a device wafer, the device wafer including a plurality of first chips, the first chip including a first electrode, and the The first electrode is exposed from the device wafer, and the surface of the device wafer that exposes the first electrode is the front side of the wafer; a plurality of second chips are provided, the second chip includes the second electrode, and the first The two electrodes are exposed by the second chip, the surface of the second chip exposing the second electrode is the front side of the chip, and the surface opposite to the front side of the chip is the back side of the chip; A front surface of the wafer combined between the first chip; an insulating side wall is formed on a side wall of the second chip; and a conductive layer conformally covering the front surface of the chip, the insulating side wall, and the front surface of the wafer is formed.
  • an insulating side wall is formed on the side wall of the second chip, and then a conductive layer conformally covering the front surface of the chip, the insulating side wall, and the front surface of the wafer is formed.
  • the conductive layer is covered on the front side of the chip and is in contact with the second electrode on the front side of the chip; the conductive layer is also covered on the front side of the wafer and is in contact with the first electrode exposed on the front side of the wafer.
  • the conductive layer realizes the electrical connection between the first electrode and the second electrode, and further realizes the electrical connection between the first chip and the second chip, and the process is relatively simple.
  • the conductive layer also covers the insulation of the second chip. Side wall, so as to achieve insulation between the conductive layer and the second chip side wall, the insulating side wall insulates the conductive layer and the second chip from each other, thereby avoiding the performance of the conductive layer on the second chip Impact.
  • the wafer-level packaging method in this embodiment includes:
  • a device wafer 10 is provided.
  • the device wafer 10 includes a plurality of first chips 11.
  • the first chip 11 includes a first electrode 110, and the first electrode 110 is formed by the device crystal.
  • the circle 10 is exposed, and the surface of the device wafer 10 from which the first electrode 110 is exposed is the wafer front side 101.
  • the device wafer 10 is a CMOS Wafer to be packaged.
  • the semiconductor substrate of the device wafer 10 is a silicon substrate.
  • the material of the semiconductor substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
  • the semiconductor substrate may also be a silicon substrate on an insulator. Or another type of substrate such as a germanium substrate on an insulator.
  • the material of the semiconductor substrate may be a material suitable for process requirements or easily integrated. According to actual process requirements, the thickness of the device wafer 10 is 10 ⁇ m to 100 ⁇ m.
  • the plurality of first chips 11 formed in the device wafer 10 may be chips of the same type or different types.
  • the device wafer 10 can be made by using integrated circuit manufacturing technology, for example, an N-Metal-Oxide-Semiconductor is formed on a semiconductor substrate by a process such as deposition and etching. NMOS) devices and P-Metal-Oxide-Semiconductor (PMOS) devices, etc., on which a dielectric layer, a metal interconnect structure, and a pad electrically connected to the metal interconnect junction are formed. Etc., so that a plurality of first chips 11 are integrated in the device wafer 10.
  • the first electrode 110 on the surface of the first chip 11 is used to achieve electrical connection between the first chip 11 and other semiconductor devices.
  • the first electrode 110 may be a lead pad.
  • the second chip 12 includes a second electrode 120, and the second electrode 120 is exposed by the second chip 12, and the second chip 12 is exposed.
  • a surface of the second electrode 120 is a chip front surface 121, and a surface opposite to the chip front surface 121 is a chip back surface 122.
  • the second chip 12 is used as a chip to be integrated in a wafer-level system package.
  • the packaging method of this embodiment is used to achieve heterogeneous integration.
  • the plurality of second chips 12 may be chips made of silicon wafers, or chips made of other materials.
  • the number of the second chips 12 is at least one, and when the number of the second chips 12 is multiple, the functions of the plurality of second chips 12 may be the same or different.
  • the second chip 12 may be made by an integrated circuit manufacturing technology, and may be a memory chip, a communication chip, a processor, or a logic chip.
  • the second chip 12 generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate.
  • the second electrode 120 on the surface of the second chip 12 is used to achieve electrical connection between the second chip 12 and other semiconductor devices.
  • the second electrode 120 may be a lead pad (Pad).
  • the chip back surface 122 of the second chip 12 is bonded to the wafer front surface 101 between the first chips 11.
  • the second chip 12 bonded to the device wafer 10 and the first chip 11 in the device wafer 10 are staggered from each other, that is, the first chip 11 and the second chip 12 are in the The projections on the device wafer 10 do not coincide. In this way, when the conductive layer is conformally covered, the conductive layer can cover the second chip 12 and the first chip 11 on the device wafer 10.
  • the bonding of the second chip 12 and the device wafer 10 may be implemented by means of an adhesive bond or a glass dielectric bond.
  • an insulating sidewall 131 is formed on a sidewall of the second chip 12.
  • the step of forming an insulating sidewall 131 on a side wall of the second chip 12 includes: forming an insulating layer that conformally covers the front surface 101 of the wafer between the second chip 12 and the second chip 12; The insulating layers of the second chip front surface 121 and the first chip front surface 111 are removed, and the insulating layer remaining on the side wall of the second chip 12 constitutes the insulating side wall 131.
  • the insulating side wall 131 completely exposes the first electrode 110 and the second electrode 120. That is, the insulating side wall 131 does not shield the first electrode 110 on the first chip 11 on the front side 101 of the wafer, and does not cover the second electrode 120 on the second chip 12. This can increase the contact area between the subsequent conductive layer and the first electrode 110 and the second electrode 120, thereby increasing the reliability of the electrical connection.
  • the insulating side wall may partially shield the first electrode or partially cover the second electrode.
  • the conductive layer can contact the first electrode or the second electrode, the first electrode and the second electrode can be realized. Electrical connection of the second electrode.
  • the step of forming an insulating layer conformally covering the wafer front side 101 between the second chip 12 and the second chip 12 includes: forming the insulating layer by a chemical vapor deposition method.
  • the step of forming an insulating layer conformally covering the wafer front side 101 between the second chip 12 and the second chip 12 includes: the thickness of the insulating layer is in a range of 0.1 to 5 micrometers.
  • the step of forming an insulating layer conformally covering the front side of the wafer 101 between the second chip 12 and the second chip 12 includes: the material of the insulating layer is silicon nitride, silicon oxide, or silicon oxynitride .
  • the step of removing the insulation layers of the second chip front surface 121 and the first chip front surface 111 includes: removing the insulation layers of the second chip front surface 121 and the first chip front surface 111 by dry etching.
  • a conductive layer 14 is formed to conformally cover the chip front surface 121, the insulating sidewall spacer 131, and the wafer front surface 101.
  • the steps of the chip front surface 121, the insulating sidewall spacer 131, and the conductive layer 14 of the wafer front surface 101 include: forming a conductive layer 14 by a chemical vapor deposition method.
  • the thickness of the conductive layer 14 is in the range of 0.1 to 5 microns.
  • the material of the conductive layer 14 is one or more of copper, aluminum, tin, and nickel.
  • the wafer-level packaging method further includes: after forming the conductive layer 14, covering the conductive layer 14 with a packaging layer (not shown).
  • the packaging layer can play the role of insulation, sealing, and moisture resistance, and can reduce the probability of the first chip 11 and the second chip 12 being damaged, polluted, or oxidized, thereby helping optimize the performance of the obtained packaging structure.
  • 5 to 10 are schematic structural diagrams corresponding to steps in another embodiment of a wafer-level packaging method according to the present invention.
  • This embodiment is different from the previous embodiment in the step of bonding the second chip 200 and the device wafer 300.
  • a device wafer 300 is provided.
  • the device wafer 300 includes a plurality of first chips 310.
  • the first chip 310 includes a first electrode 320, and the first electrode 320 is formed by the device crystal.
  • the circle 300 is exposed, and the surface of the device wafer 300 from which the first electrode 320 is exposed is a wafer front surface 301; a first dielectric layer 350 is formed on the wafer front surface 301 between the first chips 310.
  • the first dielectric layer 350 is used to implement the bonding between the device wafer 300 and the second chip.
  • the first dielectric layer 130 is spaced from the first chip 310 and corresponds to the position of the second chip to be bonded.
  • the first dielectric layer 350 is used to implement the bonding between the device wafer 300 and the second chip by means of fusion bonding.
  • the material of the first dielectric layer 350 in this embodiment is silicon oxide.
  • the material of the first dielectric layer 350 may be other oxide materials.
  • the front surface of the device wafer 300 may be covered with a dielectric layer material by a chemical vapor deposition process, and then a patterning process (such as photolithography and etching) is performed on the dielectric layer material, and a first chip is formed in the device wafer 300.
  • a first dielectric layer 350 is formed on the surfaces between 310.
  • the second chip 200 includes a second electrode 210, and the second electrode 210 is exposed by the second chip 200 and the second chip 200 is exposed.
  • a surface of the second electrode 210 is a chip front surface 202, and a surface of the second chip 200 opposite to the chip front surface 202 is a chip back surface 201.
  • a second dielectric layer 250 is formed on the chip back surface 201.
  • the second dielectric layer 250 is used to implement bonding between the second chip 200 and the device wafer 300.
  • the second dielectric layer 250 is used to implement the bonding between the device wafer 300 and the second chip by means of fusion bonding.
  • the material of the second dielectric layer 250 in this embodiment is silicon oxide.
  • the material of the second dielectric layer 250 may be other oxide materials.
  • a silicon oxide may be formed on the chip back surface 201 of the second chip 200 through a thermal oxidation process.
  • the first dielectric layer 350 and the second dielectric layer 250 are beneficial for bonding the front surface 301 of the wafer to the back surface 201 of the second chip to be integrated, so as to achieve physical connection between the wafer 300 and the second chip 200. .
  • the step of bonding the second chip back surface 201 to the wafer front surface 301 between the first chips 310 includes: arranging the first dielectric layer 350 and the second dielectric layer 250 opposite to each other and Bonding, bonding the second chip 200 and the device wafer 300.
  • the bonding between the first dielectric layer 350 and the second dielectric layer 250 is a fusion bonding.
  • Melt bonding is a process that mainly uses interface chemical forces to complete bonding.
  • a covalent bond is formed on the contact surface of the first dielectric layer 350 and the second dielectric layer 250 Bonding is achieved in a covalent bond manner, and the first dielectric layer 350 and the second dielectric layer 250 have higher bonding strength, thereby improving the device wafer 300 and the second wafer
  • the bonding strength of the chip 200, and the subsequent process has less influence on the bonding strength, and accordingly improves the package yield of the wafer-level system package.
  • the process temperature of the annealing treatment in the fusion bonding process is reasonably reduced, thereby reducing the influence of the fusion bonding process on other film layers.
  • the steps of the fusion bonding process include: performing plasma activation treatment on the surfaces of the first dielectric layer 350 and the second dielectric layer 250, and wetting and drying with deionized water.
  • the plasma activation process according to a preset relative positional relationship between the device wafer 300 and the second chip 200, the first dielectric layer 350 and the second dielectric layer 250 are oppositely disposed and attached to each other.
  • the device wafer 300 and the second chip 200 apply a bonding pressure to perform a pre-bonding process.
  • the step of the fusion bonding process further includes: performing an annealing process on the device wafer 300 and the second chip 200 after the pre-bonding process.
  • an insulating sidewall spacer 450 is formed on a sidewall of the second chip 200.
  • the step of forming an insulating sidewall 450 on a side wall of the second chip 200 includes: forming an insulating layer 400 that conformally covers the front surface 301 of the wafer between the second chip 200 and the second chip 200. .
  • the insulating layer 400 further covers the first dielectric layer 350 and the second dielectric layer 250.
  • the insulating sidewall 450 is further covered on the sidewalls of the first dielectric layer 350 and the second dielectric layer 250 which are oppositely disposed.
  • a conductive layer 500 is formed to conformally cover the first chip front surface 311, the second chip front surface 202, the insulating sidewall spacer 450, and the wafer front surface 301.
  • the conductive layer 500 covers the chip front surface 121 and is in contact with the second electrode 120 on the chip front surface 121.
  • the conductive layer 500 also covers the wafer front surface 301, and the first electrode exposed from the wafer front surface 301 surface.
  • the step of forming a conductive layer 500 conformally covering the first chip front surface 311, the second chip front surface 202, the insulating sidewall spacer 450, and the wafer front surface 301 includes forming a conductive layer 500 by a chemical vapor deposition method.
  • the thickness of the conductive layer 500 is in the range of 0.1 to 5 microns.
  • the material of the conductive layer 500 is one or more of copper, aluminum, tin, and nickel.
  • the packaging method further includes: after forming the conductive layer 500, covering the packaging layer 600 on the conductive layer 500.
  • the material of the encapsulation layer 600 is a polymer or a dielectric.
  • the step of forming the packaging layer 600 includes: forming the packaging layer 600 by an injection molding process.
  • the filling performance of the injection molding process is good, and the packaging layer 600 can have good insulation and sealing effects on the first chip 310 and the second chip 200.
  • the material of the encapsulation layer 600 is epoxy.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the material of the encapsulation layer may also be a thermosetting material such as polyimide or silica gel, or the encapsulation layer may also be a dielectric material such as alumina or aluminum nitride.
  • the invention also provides a wafer-level packaging structure.
  • FIG. 4 is a schematic structural diagram of a wafer-level package structure according to an embodiment of the present invention.
  • the wafer-level package structure includes a device wafer 10 including a plurality of first chips 11.
  • the first chip 11 includes a first electrode 110, and the first electrode 110 is formed by the first electrode 110.
  • the device wafer 10 is exposed, and the surface of the device wafer 10 that exposes the first electrode 110 is the wafer front side 101.
  • the device wafer 10 is a CMOS Wafer to be packaged.
  • the semiconductor substrate of the device wafer 10 is a silicon substrate.
  • the material of the semiconductor substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
  • the semiconductor substrate may also be a silicon substrate on an insulator. Or another type of substrate such as a germanium substrate on an insulator.
  • the material of the semiconductor substrate may be a material suitable for process requirements or easily integrated. According to actual process requirements, the thickness of the device wafer 10 is 10 ⁇ m to 100 ⁇ m.
  • the plurality of first chips 11 formed in the device wafer 10 may be chips of the same type or different types.
  • the device wafer 10 can be made by using integrated circuit manufacturing technology, for example, an N-Metal-Oxide-Semiconductor is formed on a semiconductor substrate by a process such as deposition and etching. NMOS) devices and P-Metal-Oxide-Semiconductor (PMOS) devices, etc., on which a dielectric layer, a metal interconnect structure, and a pad electrically connected to the metal interconnect junction are formed. Etc., so that a plurality of first chips 11 are integrated in the device wafer 10.
  • the first electrode 110 on the surface of the first chip 11 is used to achieve electrical connection between the first chip 11 and other semiconductor devices.
  • the first electrode 110 may be a lead pad.
  • a plurality of second chips 12 are bonded to the front surface 101 of the wafer, and a surface on which the second chip 12 is bonded to the front surface of the wafer 101 is a back surface 122 of the chip, which is opposite to the back surface 122 of the second chip.
  • the surface is the chip front surface 121.
  • the second chip 12 includes a second electrode 120 and is exposed from the second chip front surface 121.
  • the second chip 12 is used as a chip to be integrated in a wafer-level system package.
  • the packaging structure of this embodiment is heterogeneous integration.
  • the plurality of second chips 12 may be chips made of silicon wafers or chips made of other materials.
  • the number of the second chips 12 is at least one, and when the number of the second chips 12 is multiple, the functions of the plurality of second chips 12 may be the same or different.
  • the second chip 12 may be made by an integrated circuit manufacturing technology, and may be a memory chip, a communication chip, a processor, or a logic chip.
  • the second chip 12 generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate.
  • the second chip 12 is bonded on the front surface 101 of the wafer between the first chips 11. Specifically, the second chip 12 bonded to the device wafer 10 and the first chip 11 in the device wafer 10 are staggered from each other, that is, the first chip 11 and the second chip 12 are in the The projections on the device wafer 10 do not coincide. In this way, when the insulating layer is conformally covered on the bonding structure in sequence, the insulating layer can cover the first chip 11 and the second chip 12.
  • the second electrode 120 on the surface of the second chip 12 is used to achieve electrical connection between the second chip 12 and other semiconductor devices.
  • the second electrode 120 may be a lead pad (Pad).
  • the second chip 12 is bonded or bonded to the device wafer 10 with a glass medium.
  • the insulating side wall 131 is located on a side wall of the second chip 12 and is used to insulate the side wall of the second chip from other devices.
  • the material of the insulating side wall 131 is an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the thickness of the insulating side wall 131 is in a range of 0.1 to 5 micrometers.
  • the conductive layer 14 conformally covers the chip front surface 121, the insulating sidewall spacer 131, and the wafer front surface 101.
  • the conductive layer 14 covers the chip front surface 121 and is in contact with the second electrode 120 on the chip front surface 121.
  • the conductive layer 14 also covers the wafer front surface 101 and the first electrode exposed on the wafer front surface 101. 110 contacts.
  • the electrical connection between the first electrode 110 and the second electrode 120 is realized through the conductive layer 14, and the electrical connection between the first chip 11 and the second chip 12 is further achieved.
  • the process is relatively simple.
  • the thickness of the conductive layer 14 is in a range of 0.1 to 5 micrometers.
  • the material of the conductive layer 14 is one or more of copper, aluminum, tin, and nickel.
  • the packaging structure further includes a packaging layer on the conductive layer 14.
  • the encapsulation layer can play the role of insulation, sealing, and moisture resistance, and can reduce the probability of the second chip 12 being damaged, polluted, or oxidized, which is beneficial to optimize the performance of the obtained encapsulation structure.
  • the material of the encapsulation layer may be a polymer or a dielectric.
  • the material of the encapsulation layer is epoxy.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the material of the encapsulation layer may also be a thermosetting material such as polyimide or silica gel, or the encapsulation layer may also be a dielectric material such as alumina or aluminum nitride.
  • FIG. 10 a schematic diagram of another embodiment of the wafer-level package structure of the present invention is also shown.
  • the packaging structure of this embodiment is the same as that of the previous embodiment, and the wafer-level packaging structure of this embodiment is different from the previous embodiment in that:
  • the package structure further includes: a first dielectric layer 350 on the front side of the wafer between the first chips 310; and a second dielectric layer 250 on the back side of the chip of the second chip 200, which is opposite to the first dielectric layer 350 Bond.
  • the first dielectric layer 350 and the second dielectric layer 250 are oppositely disposed and bonded to each other, so as to realize physical connection between the device wafer 300 and the second chip 200.
  • the bonding between the first dielectric layer 350 and the second dielectric layer 250 is a fusion bonding.
  • a material of the first dielectric layer 350 is silicon oxide.
  • the material of the first dielectric layer 350 may be other oxide materials.
  • a material of the second dielectric layer 250 is silicon oxide.
  • the material of the second dielectric layer 250 may be other oxide materials.

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Abstract

一种晶圆级封装方法和封装结构，所述晶圆级封装方法包括：提供器件晶圆（10），所述器件晶圆（10）包括多个第一芯片（11），所述第一芯片（11）包括第一电极（110），且所述第一电极（110）由所述器件晶圆（10）露出，所述器件晶圆（10）露出所述第一电极（110）的面为晶圆正面（101）；提供多个第二芯片（12），所述第二芯片（12）包括第二电极（120），且所述第二电极（120）由所述第二芯片（12）露出，所述第二芯片（12）露出所述第二电极（120）的面为芯片正面（121），与所述芯片正面（121）相背的面为芯片背面（122）；使所述第二芯片（12）的芯片背面（122）键合于所述第一芯片（11）之间的晶圆正面（101）；在所述第二芯片（12）的侧壁上形成绝缘侧墙（131）；形成保形覆盖所述芯片正面（121）、绝缘侧墙（131）和晶圆正面（101）的导电层（14）。该封装结构仅通过一层导电层实现了第一芯片（11）和第二芯片（12）之间的电性连接，工艺较为简单。

Description

晶圆级封装方法以及封装结构 技术领域
本发明涉及半导体技术领域，尤其涉及一种晶圆级封装方法以及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball Grid Array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer Level Package ，WLP)、三维封装(3D) 和系统封装(System in Package，SiP)等。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装（Wafer Level Package System in Package，WLPSiP）。与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺。比如：采用键合工艺实现待集成芯片与晶圆之间的物理连接，通过电镀技术实现半导体器件之间的电性连接，通过硅通孔（Through-SiliconVia，TSV）实现芯片与外部电路的电性连接。
但是，目前晶圆级系统封装的电性连接的方法有待进一步简化。
 技术问题
本发明解决的问题是提供一种晶圆级封装方法以及封装结构，简化封装工艺。
 技术解决方案
本发明提供一种晶圆级封装方法，包括：提供器件晶圆，所述器件晶圆包括多个第一芯片，所述第一芯片包括第一电极，且所述第一电极由所述器件晶圆露出，所述器件晶圆露出所述第一电极的面为晶圆正面；提供多个第二芯片，所述第二芯片包括第二电极，且所述第二电极由所述第二芯片露出，所述第二芯片露出所述第二电极的面为芯片正面，与所述芯片正面相背的面为芯片背面；使所述第二芯片的芯片背面键合于所述第一芯片之间的晶圆正面；在所述第二芯片的侧壁上形成绝缘侧墙；形成保形覆盖所述芯片正面、绝缘侧墙和晶圆正面的导电层。
可选的，所述在所述第二芯片的侧壁上形成绝缘侧墙的步骤包括：形成保形覆盖所述第二芯片和第二芯片之间晶圆正面的绝缘层；去除第二芯片正面和晶圆正面的绝缘层，保留在第二芯片侧壁上的绝缘层构成所述绝缘侧墙。
可选的，通过干法刻蚀去除第二芯片正面和晶圆正面的绝缘层。
可选的，所述形成保形覆盖所述第二芯片和第二芯片之间晶圆正面的绝缘层的步骤包括：所述绝缘层的厚度在0.1至5微米的范围内……的范围内。
可选的，所述绝缘层的材料为氮化硅、氧化硅或氮氧化硅。
可选的，通过化学气相沉积的方法形成所述绝缘层。
可选的，所述绝缘侧墙完全露出所述第一电极和所述第二电极。
可选的，所述导电层的材料为铜、铝、锡和镍中的一种或多种。
可选的，通过化学气相沉积的方法形成导电层。
可选的，所述形成保形覆盖所述芯片正面、绝缘侧墙和晶圆正面的导电层的步骤包括：所述导电层的厚度在0.1至5微米的范围内。
可选的，所述封装方法还包括：在形成所述导电层之后，在所述导电层上覆盖封装层。
可选的，提供器件晶圆的步骤包括：所述第一芯片之间的晶圆正面形成有第一介质层；提供多个第二芯片的步骤包括：所述第二芯片的芯片背面形成有第二介质层；使所述第二芯片的芯片背面键合于所述第一芯片之间的晶圆正面的步骤包括：通过所述第一介质层和所述第二介质层的键合，使所述第二芯片的芯片背面键合于所述第一芯片之间的晶圆正面。
可选的，所述第一介质层和所述第二介质层的键合为熔融键合。
相应的，本发明还提供一种晶圆级封装结构，包括：器件晶圆，所述器件晶圆包括多个第一芯片，所述第一芯片包括第一电极，且所述第一电极由所述器件晶圆露出，所述器件晶圆露出所述第一电极的面为晶圆正面；多个第二芯片，键合于所述晶圆正面，所述第二芯片与所述晶圆正面键合的面为芯片背面，与所述芯片背面相背的面为芯片正面，所述第二芯片包括第二电极，由所述芯片正面露出；绝缘侧墙，位于所述第二芯片侧壁；导电层，保形覆盖于所述芯片正面、绝缘侧墙和晶圆正面。
可选的，所述绝缘侧墙的材料为氮化硅、氧化硅或氮氧化硅。
可选的，所述导电层的材料为铜、铝、锡和镍中的一种或多种。
可选的，所述导电层的厚度在0.1至5微米的范围内。
可选的，所述绝缘侧墙的厚度在0.1至5微米的范围内。
可选的，所述封装结构还包括：位于所述导电层上的封装层。
可选的，所述封装结构还包括：位于所述第一芯片之间晶圆正面的第一介质层；位于第二芯片的芯片背面的第二介质层，与所述第一介质层相对键合。
 有益效果
本发明先在所述第二芯片的侧壁上形成绝缘侧墙，再形成保形覆盖于所述芯片正面、绝缘侧墙和晶圆正面的导电层。所述导电层覆盖在芯片正面，与位于芯片正面的第二电极相接触；所述导电层还覆盖在所述晶圆正面，与晶圆正面露出的第一电极相接触，本发明通过一层导电层的实现了第一电极与第二电极之间的电连接，进而实现了第一芯片和第二芯片的电连接，工艺较为简单；此外，所述导电层还覆盖在第二芯片的绝缘侧墙上，从而实现了导电层与第二芯片侧壁之间绝缘，所述绝缘侧墙使所述导电层与所述第二芯片之间相互绝缘，从而避免了导电层对第二芯片性能的影响。
 附图说明
图1至图4是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图；
图5至图10是本发明晶圆级封装方法另一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，现有技术封装结构的工艺较为复杂，分析其原因在于：现有技术中，在将待集成的裸芯片键合于晶圆之后，需形成与裸芯片相连的第一连接结构、与晶圆中的芯片相连的第二连接结构以及与第一连接结构和第二连接结构相连的互连结构，工艺较为复杂。
为了解决所述技术问题，本发明提供一种晶圆级封装方法，包括：提供器件晶圆，所述器件晶圆包括多个第一芯片，所述第一芯片包括第一电极，且所述第一电极由所述器件晶圆露出，所述器件晶圆露出所述第一电极的面为晶圆正面；提供多个第二芯片，所述第二芯片包括第二电极，且所述第二电极由所述第二芯片露出，所述第二芯片露出所述第二电极的面为芯片正面，与所述芯片正面相背的面为芯片背面；使所述第二芯片的芯片背面键合于所述第一芯片之间的晶圆正面；在所述第二芯片的侧壁上形成绝缘侧墙；形成保形覆盖所述芯片正面、绝缘侧墙和晶圆正面的导电层。
本发明先在所述第二芯片的侧壁上形成绝缘侧墙，再形成保形覆盖于所述芯片正面、绝缘侧墙和晶圆正面的导电层。所述导电层覆盖在芯片正面，与位于芯片正面的第二电极相接触；所述导电层还覆盖在所述晶圆正面，与晶圆正面露出的第一电极相接触，本发明通过一层导电层的实现了第一电极与第二电极之间的电连接，进而实现了第一芯片和第二芯片的电连接，工艺较为简；此外，所述导电层还覆盖在第二芯片的绝缘侧墙上，从而实现了导电层与第二芯片侧壁之间绝缘，所述绝缘侧墙使所述导电层与所述第二芯片之间相互绝缘，从而避免了导电层对第二芯片性能的影响。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至4是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。本实施例晶圆级封装方法包括：
如图1所示，提供器件晶圆10，所述器件晶圆10包括多个第一芯片11，所述第一芯片11包括第一电极110，且所述第一电极110由所述器件晶圆10露出，所述器件晶圆10露出所述第一电极110的面为晶圆正面101。
具体地，所述器件晶圆10为完成器件制作的待封装晶圆（CMOS Wafer）。本实施例中，所述器件晶圆10的半导体衬底为硅衬底。在其他实施例中，所述半导体衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述半导体衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述半导体衬底的材料可以是适宜于工艺需要或易于集成的材料。根据实际工艺需求，所述器件晶圆10的厚度为10微米至100微米。
具体地，形成于所述器件晶圆10中的多个第一芯片11可以为同一类型或不同类型的芯片。需要说明的是，所述器件晶圆10可以采用集成电路制作技术所制成，例如在半导体衬底上通过沉积、刻蚀等工艺形成N型金属氧化物半导体（N-Metal-Oxide-Semiconductor，NMOS）器件和P型金属氧化物半导体（P-Metal-Oxide-Semiconductor，PMOS）器件等器件，在所述器件上形成介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构，从而使所述器件晶圆10中集成多个第一芯片11。
具体地，位于所述第一芯片11表面的第一电极110用于实现所述第一芯片11与其他半导体器件的电性连接。具体地，所述第一电极110可以是引线焊盘（pad）。
如图2所示，提供多个第二芯片12，所述第二芯片12包括第二电极120，且所述第二电极120由所述第二芯片12露出，所述第二芯片12露出所述第二电极120的面为芯片正面121，与所述芯片正面121相背的面为芯片背面122。
具体地，所述第二芯片12用于作为晶圆级系统封装中的待集成芯片。
本实施例封装方法用于实现异质集成，相应地，所述多个第二芯片12的可以是硅晶圆制成的芯片，也可以是其他材质形成的芯片。
所述第二芯片12的数量至少为一个，且当所述第二芯片12的数量为多个时，所述多个第二芯片12的功能可以相同也可以不相同。所述第二芯片12可以采用集成电路制造技术所制成，可以为存储芯片、通讯芯片、处理器或逻辑芯片。所述第二芯片12通常包括形成于半导体衬底上的NMOS器件或PMOS器件等器件。
具体地，位于所述第二芯片12表面的第二电极120用于实现所述第二芯片12与其他半导体器件的电性连接。具体地，所述第二电极120可以是引线焊盘（Pad）。
继续参考图3，使所述第二芯片12的芯片背面122键合于所述第一芯片11之间的晶圆正面101。
具体地，键合于所述器件晶圆10的第二芯片12与所述器件晶圆10中的第一芯片11相互错开，即所述第一芯片11与所述第二芯片12在所述器件晶圆10上的投影不重合。这样在保形覆盖导电层时，所述导电层能覆盖在所述第二芯片12以及位于器件晶圆10的第一芯片11上。
具体地，可以是通过粘结键合或玻璃介质键合等方式实现第二芯片12与器件晶圆10的键合。
如图3所示，在所述第二芯片12的侧壁上形成绝缘侧墙131。
具体地，所述在所述第二芯片12的侧壁上形成绝缘侧墙131的步骤包括：形成保形覆盖所述第二芯片12和第二芯片12之间晶圆正面101的绝缘层；去除第二芯片正面121和第一芯片正面111的绝缘层，保留在第二芯片12侧壁上的绝缘层构成所述绝缘侧墙131。
本实施例中，所述绝缘侧墙131完全露出所述第一电极110和第二电极120。也就是说，所述绝缘侧墙131对位于晶圆正面101上第一芯片11上的第一电极110没有遮挡，对位于第二芯片12上的第二电极120没有覆盖。这样可以增加后续导电层与所述第一电极110和第二电极120的接触面积，从而增加电连接的可靠性。
在其他实施例中，所述绝缘侧墙还可以对第一电极有部分遮挡或对第二电极有部分覆盖，只要导电层能与第一电极或第二电极相接触就能实现第一电极和第二电极的电连接。
具体地，所述形成保形覆盖所述第二芯片12和第二芯片12之间晶圆正面101的绝缘层的步骤包括：通过化学气相沉积的方法形成所述绝缘层。
需要说明的是，如果绝缘层的厚度过大，相应的绝缘侧墙131厚度过大，容易对第一芯片11造成遮挡或增加封装结构的体积；如果绝缘层的厚度过程小，相应的绝缘侧墙131的厚度过小，则容易影响导电层与第二芯片12之间的绝缘性。因此，所述形成保形覆盖所述第二芯片12和第二芯片12之间晶圆正面101的绝缘层的步骤包括：所述绝缘层的厚度在0.1至5微米的范围内。
具体地，所述形成保形覆盖所述第二芯片12和第二芯片12之间晶圆正面101的绝缘层的步骤包括：所述绝缘层的材料为氮化硅、氧化硅或氮氧化硅。
具体地，所述去除第二芯片正面121和第一芯片正面111的绝缘层的步骤包括：通过干法刻蚀去除第二芯片正面121和第一芯片正面111的绝缘层。
如图4所示，形成保形覆盖所述芯片正面121、绝缘侧墙131和晶圆正面101的导电层14。
具体地，所述芯片正面121、绝缘侧墙131和晶圆正面101的导电层14的步骤包括：通过化学气相沉积的方法形成导电层14。
需要说明的是，如果导电层14的厚度过小，覆盖力不够，容易影响电连接；如果导电层14的厚度过大，容易造成第二芯片12上导电层14之间的桥接。所以，对所述导电层14的厚度在0.1至5微米的范围内。
具体地，所述导电层14的材料为铜、铝、锡和镍中的一种或多种。
如图4所示，晶圆级封装方法还包括：在形成所述导电层14之后，在所述导电层14上覆盖封装层（图未示）。
封装层能够起到绝缘、密封以及防潮的作用，可以减小所述第一芯片11和第二芯片12受损、被污染或被氧化的概率，进而有利于优化所获得封装结构的性能。
图5至10是本发明晶圆级封装方法另一实施例中各步骤对应的结构示意图。
本实施例与前一实施例不同之处在于，第二芯片200与器件晶圆300相键合的步骤。
如图5所示，提供器件晶圆300，所述器件晶圆300包括多个第一芯片310，所述第一芯片310包括第一电极320，且所述第一电极320由所述器件晶圆300露出，所述器件晶圆300露出所述第一电极320的面为晶圆正面301；在第一芯片310之间的晶圆正面301形成有第一介质层350。
所述第一介质层350用于实现器件晶圆300与第二芯片之间的键合。本实施例中，所述第一介质层130与所述第一芯片310间隔设置，且与待键合的第二芯片位置相对应。
具体地，所述第一介质层350用于通过熔融键合的方式实现器件晶圆300与第二芯片的键合。
本实施例中所述第一介质层350的材料为氧化硅。或者，所述第一介质层350的材料还可以是其他氧化物材料。
可以通过化学气相沉积的工艺在器件晶圆300的正面覆盖介质层材料，之后对所述介质层材料执行图形化工艺（比如光刻和刻蚀），在所述器件晶圆300中第一芯片310之间的表面上形成第一介质层350。
如图6所示，提供多个第二芯片200，所述第二芯片200包括第二电极210，且所述第二电极210由所述第二芯片200露出，所述第二芯片200露出所述第二电极210的面为芯片正面202，所述第二芯片200中与所述芯片正面202相背的面为芯片背面201。所述芯片背面201形成有第二介质层250。
所述第二介质层250用于实现第二芯片200与器件晶圆300之间的键合。
具体地，所述第二介质层250用于通过熔融键合的方式实现器件晶圆300与第二芯片的键合。
本实施例中所述第二介质层250的材料为氧化硅。或者，所述第二介质层250的材料还可以是其他氧化物材料。
可以通过热氧化工艺，在第二芯片200的芯片背面201形成氧化硅。
本实施例中，第一介质层350和第二介质层250有利于将所述晶圆正面301与待集成的第二芯片背面201键合，从而实现晶圆300与第二芯片200的物理连接。
具体地，使所述第二芯片背面201键合于所述第一芯片310之间的晶圆正面301的步骤包括：将所述第一介质层350和所述第二介质层250相对设置并键合，使所述第二芯片200与所述器件晶圆300键合。
本实施例中，所述第一介质层350和所述第二介质层250的键合为熔融键合。
熔融键合是一种主要利用界面化学力完成键合的工艺，在所述熔融键合工艺过程中，在所述第一介质层350和所述第二介质层250的接触面形成共价键并以共价键结合的方式实现键合，且所述第一介质层350和所述第二介质层250之间具有较高的键合强度，从而提高了所述器件晶圆300和第二芯片200的键合强度，且后续工艺对所述键合强度的影响较小，相应提高了晶圆级系统封装的封装成品率。而且，通过采用低温熔融键合工艺的方式，合理降低熔融键合工艺中退火处理的工艺温度，从而减小所述熔融键合工艺对其他膜层的影响。
具体地，所述熔融键合工艺的步骤包括：对所述第一介质层350和所述第二介质层250表面进行等离子体活化处理，以及去离子水润湿和干燥。在等离子体活化处理后，根据所述器件晶圆300和第二芯片200的预设相对位置关系，将所述第一介质层350和所述第二介质层250相对设置并贴合，对所述器件晶圆300和第二芯片200施加键合压力，进行预键合处理。
所述熔融键合工艺的步骤还包括：在所述预键合处理后，对所述器件晶圆300和第二芯片200进行退火处理。
如图7至8所示，在所述第二芯片200的侧壁上形成绝缘侧墙450。
具体地，所述在所述第二芯片200的侧壁上形成绝缘侧墙450的步骤包括：形成保形覆盖所述第二芯片200和第二芯片200之间晶圆正面301的绝缘层400。
本实施例中，所述绝缘层400还覆盖所述第一介质层350和第二介质层250。
-去除所述第二芯片正面202和第一芯片正面311的绝缘层400，保留在所述第二芯片200侧壁上的绝缘层400构成所述绝缘侧墙450；所述绝缘侧墙450完全露出所述第一电极320和第二电极210。
本实施例中，所述绝缘侧墙450还覆盖在相对设置的第一介质层350和第二介质层250的侧壁上。
如图9所示，形成保形覆盖所述第一芯片正面311、第二芯片正面202、绝缘侧墙450和晶圆正面301的导电层500。
所述导电层500覆盖在芯片正面121，与位于芯片正面121的第二电极120相接触；所述导电层500还覆盖在所述晶圆正面301，与晶圆正面301面露出的第一电极320相接触，本实施例通过一层导电层500的实现了第一电极320320与第二电极210之间的电连接，进而实现了第一芯片310和第一芯片200的电连接，工艺较为简单。
具体地，所述形成保形覆盖所述第一芯片正面311、第二芯片正面202、绝缘侧墙450和晶圆正面301的导电层500的步骤包括：通过化学气相沉积的方法形成导电层500；所述导电层500的厚度在0.1至5微米的范围内。
具体地，所述导电层500的材料为铜、铝、锡和镍中的一种或多种。
如图10所示，所述封装方法还包括：在形成所述导电层500之后，在所述导电层500上覆盖封装层600。
具体地，所述封装层600的材料为聚合物或电介质。
本实施例中，形成封装层600的步骤包括：通过注塑工艺形成所述封装层600。注塑工艺的填充性能较好，可以使所述封装层600对所述第一芯片310和第二芯片200具有良好的绝缘和密封效果。
本实施例中，所述封装层600的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。在其他实施例中，所述封装层的材料还可以为聚酰亚胺或硅胶等热固性材料，或者，所述封装层还可以是氧化铝或氮化铝等介电材料。
本发明还提供一种晶圆级封装结构。请参考图4，示出了本发明晶圆级封装结构的一实施例的结构示意图。
所述晶圆级封装结构包括：器件晶圆10，所述器件晶圆10包括多个第一芯片11，所述第一芯片11包括第一电极110，且所述第一电极110由所述器件晶圆10露出，所述器件晶圆10露出所述第一电极110的面为晶圆正面101。
具体地，所述器件晶圆10为完成器件制作的待封装晶圆（CMOS Wafer）。本实施例中，所述器件晶圆10的半导体衬底为硅衬底。在其他实施例中，所述半导体衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述半导体衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述半导体衬底的材料可以是适宜于工艺需要或易于集成的材料。根据实际工艺需求，所述器件晶圆10的厚度为10微米至100微米。
具体地，形成于所述器件晶圆10中的多个第一芯片11可以为同一类型或不同类型的芯片。需要说明的是，所述器件晶圆10可以采用集成电路制作技术所制成，例如在半导体衬底上通过沉积、刻蚀等工艺形成N型金属氧化物半导体（N-Metal-Oxide-Semiconductor，NMOS）器件和P型金属氧化物半导体（P-Metal-Oxide-Semiconductor，PMOS）器件等器件，在所述器件上形成介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构，从而使所述器件晶圆10中集成多个第一芯片11。
具体地，位于所述第一芯片11表面的第一电极110用于实现所述第一芯片11与其他半导体器件的电性连接。具体地，所述第一电极110可以是引线焊盘（pad）。
多个第二芯片12，键合于所述晶圆正面101上，所述第二芯片12与所述晶圆正面101键合的面为芯片背面122，与所述第二芯片背面122相背的面为芯片正面121，所述第二芯片12包括第二电极120，由所述第二芯片正面121露出。
具体地，所述第二芯片12用于作为晶圆级系统封装中的待集成芯片。
本实施例封装结构为异质集成，相应地，所述多个第二芯片12的可以是硅晶圆制成的芯片，也可以是其他材质形成的芯片。
所述第二芯片12的数量至少为一个，且当所述第二芯片12的数量为多个时，所述多个第二芯片12的功能可以相同也可以不相同。所述第二芯片12可以采用集成电路制造技术所制成，可以为存储芯片、通讯芯片、处理器或逻辑芯片。所述第二芯片12通常包括形成于半导体衬底上的NMOS器件或PMOS器件等器件。
本实施例中，所述第二芯片12键合在第一芯片11之间的晶圆正面101上。具体地，键合于所述器件晶圆10的第二芯片12与所述器件晶圆10中的第一芯片11相互错开，即所述第一芯片11与所述第二芯片12在所述器件晶圆10上的投影不重合。这样在键合结构上依次保形覆盖绝缘层时，所述绝缘层能覆盖在所述第一芯片11和第二芯片12上。
具体地，位于所述第二芯片12表面的第二电极120用于实现所述第二芯片12与其他半导体器件的电性连接。具体地，所述第二电极120可以是引线焊盘（Pad）。
具体地，第二芯片12粘结键合或玻璃介质键合于器件晶圆10。
绝缘侧墙131，位于所述第二芯片12的侧壁上；用于起到使所述第二芯片的侧壁与其他器件绝缘的作用。
所述绝缘侧墙131的材料为氮化硅、氧化硅或氮氧化硅等的绝缘材料。
如果绝缘侧墙131的厚度过大，容易对第一芯片造成遮挡或增加封装结构的体积；如果绝缘侧墙131的厚度过小，则容易影响导电层与第二芯片之间的绝缘性。因此，绝缘侧墙131的厚度在0.1至5微米的范围内。
导电层14，保形覆盖于所述芯片正面121、绝缘侧墙131和晶圆正面101。所述导电层14覆盖在芯片正面121，与位于芯片正面121的第二电极120相接触；所述导电层14还覆盖在所述晶圆正面101，与晶圆正面101面露出的第一电极110相接触，本实施例通过导电层14的实现了第一电极110与第二电极120之间的电连接，进而实现了第一芯片11和第二芯片12的电连接，工艺较为简单。
具体地，所述导电层14的厚度在0.1至5微米的范围内。
具体地，所述导电层14的材料为铜、铝、锡和镍中的一种或多种。
所述封装结构还包括位于所述导电层14上的封装层。
具体地，封装层能够起到绝缘、密封以及防潮的作用，可以减小第二芯片12受损、被污染或被氧化的概率，进而有利于优化所获得封装结构的性能。
具体地，所述封装层的材料可以为聚合物或电介质。
本实施例中，所述封装层的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。在其他实施例中，所述封装层的材料还可以为聚酰亚胺或硅胶等热固性材料，或者，所述封装层还可以是氧化铝或氮化铝等介电材料。
参考图10，还示出了本发明晶圆级封装结构另一实施例的示意图。本实施例封装结构与前一实施例的相同之处不在赘述，本实施例晶圆级封装结构与前一实施例的不同之处在于：
所述封装结构还包括：位于所述第一芯片310之间晶圆正面的第一介质层350；位于第二芯片200的芯片背面的第二介质层250，与所述第一介质层350相对键合。
所述第一介质层350和所述第二介质层250相对设置并键合，用于实现所述器件晶圆300和第二芯片200的物理连接。
本实施例中，所述第一介质层350和所述第二介质层250的键合为熔融键合。
具体地，所述第一介质层350的材料为氧化硅。或者，所述第一介质层350的材料还可以是其他氧化物材料。
具体地，所述第二介质层250的材料为氧化硅。或者，所述第二介质层250的材料还可以是其他氧化物材料。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种晶圆级封装方法，其特征在于，包括：
    提供器件晶圆，所述器件晶圆包括多个第一芯片，所述第一芯片包括第一电极，且所述第一电极由所述器件晶圆露出，所述器件晶圆露出所述第一电极的面为晶圆正面；
    提供多个第二芯片，所述第二芯片包括第二电极，且所述第二电极由所述第二芯片露出，所述第二芯片露出所述第二电极的面为芯片正面，与所述芯片正面相背的面为芯片背面；
    使所述第二芯片的所述芯片背面键合于所述第一芯片之间的所述晶圆正面；
    在所述第二芯片的侧壁上形成绝缘侧墙；
    形成保形覆盖所述芯片正面、绝缘侧墙和晶圆正面的导电层。
  2. 如权利要求1所述的封装方法，其特征在于，所述在所述第二芯片的侧壁上形成绝缘侧墙的步骤包括：形成保形覆盖所述第二芯片和第二芯片之间所述晶圆正面的绝缘层；
    去除所述第二芯片正面和晶圆正面的绝缘层，保留在所述第二芯片侧壁上的所述绝缘层构成所述绝缘侧墙。
  3. 如权利要求2所述的封装方法，其特征在于，通过干法刻蚀去除所述第二芯片正面和晶圆正面的绝缘层。
  4. 如权利要求2所述的封装方法，其特征在于，所述形成保形覆盖所述第二芯片和第二芯片之间晶圆正面的绝缘层的步骤包括：所述绝缘层的厚度在0.1至5微米的范围内。
  5. 如权利要求2所述的封装方法，其特征在于，所述绝缘层的材料为氮化硅、氧化硅或氮氧化硅。
  6. 如权利要求2所述的封装方法，其特征在于，通过化学气相沉积的方法形成所述绝缘层。
  7. 如权利要求1所述的封装方法，其特征在于，所述绝缘侧墙完全露出所述第一电极和所述第二电极。
  8. 如权利要求1所述的封装方法，其特征在于，所述导电层的材料为铜、铝、锡和镍中的一种或多种。
  9. 如权利要求1所述的封装方法，其特征在于，通过化学气相沉积的方法形成所述导电层。
  10. 如权利要求1所述的封装方法，其特征在于，所述形成保形覆盖所述芯片正面、绝缘侧墙和晶圆正面的导电层的步骤包括：所述导电层的厚度在0.1至5微米的范围内。
  11. 如权利要求1所述的封装方法，其特征在于，所述封装方法还包括：在形成所述导电层之后，在所述导电层上覆盖封装层。
  12. 如权利要求1所述的封装方法，其特征在于，提供器件晶圆的步骤包括：所述第一芯片之间的晶圆正面形成有第一介质层；
    提供多个第二芯片的步骤包括：所述第二芯片的芯片背面形成有第二介质层；
    使所述第二芯片的所述芯片背面键合于所述第一芯片之间的所述晶圆正面的步骤包括：通过所述第一介质层和所述第二介质层的键合，使所述第二芯片的所述芯片背面键合于所述第一芯片之间的所述晶圆正面。
  13. 如权利要求12所述的封装方法，其特征在于，所述第一介质层和所述第二介质层的键合为熔融键合。
  14. 一种晶圆级封装结构，其特征在于，包括：
    器件晶圆，所述器件晶圆包括多个第一芯片，所述第一芯片包括第一电极，且所述第一电极由所述器件晶圆露出，所述器件晶圆露出所述第一电极的面为晶圆正面；
    多个第二芯片，键合于所述晶圆正面，所述第二芯片与所述晶圆正面键合的面为芯片背面，与所述芯片背面相背的面为芯片正面，所述第二芯片包括第二电极，由所述芯片正面露出；
    绝缘侧墙，位于所述第二芯片侧壁；
    导电层，保形覆盖于所述芯片正面、绝缘侧墙和晶圆正面。
  15. 如权利要求14所述的封装结构，其特征在于，所述绝缘侧墙的材料为氮化硅、氧化硅或氮氧化硅。
  16. 如权利要求14所述的封装结构，其特征在于，所述导电层的材料为铜、铝、锡和镍中的一种或多种。
  17. 如权利要求14所述的封装结构，其特征在于，所述导电层的厚度在在0.1至5微米的范围内。
  18. 如权利要求14所述的封装结构，其特征在于，所述绝缘侧墙的厚度在0.1至5微米的范围内。
  19. 如权利要求14所述的封装结构，其特征在于，所述封装结构还包括：位于所述导电层上的封装层。
  20. 如权利要求14所述的封装结构，其特征在于，所述封装结构还包括：
    位于所述第一芯片之间晶圆正面的第一介质层；
    位于第二芯片的芯片背面的第二介质层，与所述第一介质层相对键合。
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