WO2020024796A1 - 光电二极管芯片及其制作方法 - Google Patents

光电二极管芯片及其制作方法 Download PDF

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Publication number
WO2020024796A1
WO2020024796A1 PCT/CN2019/096395 CN2019096395W WO2020024796A1 WO 2020024796 A1 WO2020024796 A1 WO 2020024796A1 CN 2019096395 W CN2019096395 W CN 2019096395W WO 2020024796 A1 WO2020024796 A1 WO 2020024796A1
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electrode
layer
region
boss
electrode ring
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PCT/CN2019/096395
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English (en)
French (fr)
Chinese (zh)
Inventor
刘宏亮
杨彦伟
陆一锋
刘格
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芯思杰技术(深圳)股份有限公司
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Priority to JP2021600081U priority Critical patent/JP3233263U/ja
Publication of WO2020024796A1 publication Critical patent/WO2020024796A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of semiconductor devices, and more particularly, to a photodiode chip and a manufacturing method thereof.
  • photodiode chips are widely used in people's daily life and work.
  • fiber optic communication, data centers, optical detection and other fields have a wide range of applications, bringing people's daily life and work
  • Great convenience has become an indispensable tool for today's people.
  • the photodiode chip needs to be connected and used with other components.
  • the structure of the traditional photodiode chip will result in a higher inductance after connection and low reliability during connection.
  • the technical solution of the present invention provides a photodiode chip and a manufacturing method thereof, which can reduce the inductance after the photodiode chip is connected with other components and improve the reliability of the photodiode chip.
  • the present invention provides the following technical solutions:
  • a photodiode chip includes:
  • An epitaxial functional layer provided on a surface of one side of the chip substrate; the epitaxial functional layer having a negative electrode boss on the surface of the chip substrate and a positive electrode on a surface of the negative electrode side facing away from the chip substrate A boss; a surface of the negative electrode boss facing away from the chip substrate has a first region and a second region surrounding the first region, and the positive electrode boss is located in the first region;
  • a first electrode ring located on a surface of the positive electrode boss facing away from the negative electrode boss;
  • a second electrode ring located in the second region
  • the first electrode ring is connected to one pad, and the second electrode ring is connected to two pads.
  • all the pads are located on the same plane.
  • a surface of the positive electrode boss facing away from the negative electrode boss includes a light-passing window and a peripheral region surrounding the light-passing window;
  • the first electrode ring is located in the peripheral region and surrounds the light-passing window
  • the second electrode ring is located in the second region and surrounds the positive electrode boss.
  • a side surface of the chip substrate on which the epitaxial functional layer is disposed includes: a third region and a fourth region surrounding the third region;
  • the epitaxial functional layer is located in the third region;
  • the pads are all located in the fourth region.
  • the photodiode chip further includes a passivation layer covering the fourth region, the negative electrode boss, and the positive electrode boss, and the passivation layer corresponds to the light-passing window and the passivation layer.
  • the first electrode ring and the second electrode have openings;
  • All the pads are located on a side of the passivation layer facing away from the chip substrate.
  • the photodiode chip further includes an anti-reflection coating covering the light transmission window, and the anti-reflection coating further covers the passivation layer.
  • the second electrode ring has an opening, and the opening is used to lead out the pad connected by the first electrode ring;
  • the second electrode ring includes a middle portion, and a first portion and a second portion respectively connected to both ends of the middle portion, and the opening is provided between the first portion and the second portion.
  • one end of the first portion opposite to the second portion is connected with the pad, and one end of the second portion opposite to the first portion is connected with another pad.
  • said pad connected by said first electrode ring is located between two said pads connected by said second electrode ring;
  • two pads are connected to a side of the middle portion facing away from the opening.
  • the first electrode ring is a closed ring.
  • the chip substrate is a Fe-doped semi-insulating InP substrate
  • the epitaxial functional layer includes a plurality of sub-functional layers matching the lattice of the semi-insulating InP substrate;
  • the multi-layered sub-functional layers are stacked in a direction perpendicular to the chip substrate.
  • the multilayer sub-functional layer includes: a buffer layer, an absorption layer, and a top layer that are sequentially epitaxially grown on the same side of the chip substrate; a contact layer is provided on the surface of the top layer;
  • the buffer layer is used to form the negative electrode boss, and the absorption layer and the top layer are used to form the positive electrode boss;
  • the contact layer includes a contact unit between the first electrode ring and the top layer for reducing contact resistance.
  • the present invention also provides a method for manufacturing a photodiode chip, which is used for manufacturing the photodiode chip according to any one of the above, wherein the manufacturing method includes:
  • the wafer including a plurality of chip substrates, and a cutting channel between adjacent chip substrates;
  • the epitaxial functional layer Forming a patterned epitaxial functional layer on one surface of the wafer, the epitaxial functional layer having a negative electrode boss on the surface of the chip substrate and a negative electrode protrusion on the surface of the chip substrate for each region of the chip substrate; A positive boss on a surface of the negative substrate facing away from the chip substrate; a surface of the negative boss having a surface facing away from the chip substrate having a first region and a second region surrounding the first region; A station is located in the first area;
  • the electrode structure comprising a first electrode ring located on a surface of the positive electrode boss facing away from the negative electrode boss and a second electrode ring located in the second region; wherein the first electrode ring One pad is connected, and the second electrode ring is connected with two pads;
  • the method for forming an electrode structure includes:
  • a surface of the positive electrode boss facing away from the negative electrode boss includes a light-passing window and a peripheral region surrounding the light-passing window;
  • the method for forming an electrode structure includes:
  • the second electrode ring is formed in the second region, and the second electrode ring surrounds the positive electrode boss.
  • a side surface of the chip substrate on which the epitaxial functional layer is disposed includes: a third region and a fourth region surrounding the third region; the epitaxial functional layer is located in the first region.
  • the method for forming an electrode structure includes: forming all the pads in the fourth region.
  • the method before forming the electrode structure, the method further includes:
  • All the pads are located on a side of the passivation layer facing away from the chip substrate.
  • the second electrode ring has an opening for leading out the pad connected by the first electrode ring;
  • the second electrode ring includes a middle portion, and A first portion and a second portion that are respectively connected to both ends of the intermediate portion, and the opening is provided between the first portion and the second portion;
  • the connected pads are located between two of the pads connected by the second electrode ring;
  • two pads are connected to a side of the middle portion facing away from the opening.
  • the forming a patterned epitaxial functional layer on one surface of the wafer includes:
  • the top surface is provided with a contact layer; the contact layer includes a contact unit located between the first electrode ring and the top layer to reduce contact resistance.
  • the photodiode chip includes: a chip substrate; an epitaxial functional layer provided on one surface of the chip substrate; and the epitaxial functional layer A negative electrode boss on the surface of the chip substrate and a positive electrode boss on a surface of the negative electrode side facing away from the chip substrate; A region and a second region surrounding the first region, the positive electrode boss is located in the first region; a first electrode ring located on a surface of the positive electrode boss facing away from the negative electrode boss; A second electrode ring in the second region; wherein the first electrode ring is connected to a pad, and the second electrode ring is connected to two pads.
  • the second electrode ring is provided with two pads, and the second electrode ring can have inductance when connected to other components through two parallel metal wires. After being connected with other components, it has lower inductance.
  • the gold wire connection can improve the reliability of the device connection.
  • 1 is a plan view of an electrode structure of a conventional photodiode chip
  • FIG. 2 is a front plan view of a photodiode chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a negative electrode in the photodiode chip shown in FIG. 2;
  • FIG. 4 is a cross-sectional view of the photodiode chip shown in FIG. 2 in the A-A direction;
  • FIG. 5 is a front plan view of another photodiode chip according to an embodiment of the present invention.
  • 6 to 15 are schematic flowcharts of a manufacturing method according to an embodiment of the present invention.
  • a photodiode chip needs to be connected and used with other components.
  • a photodiode chip is usually used in conjunction with a transimpedance amplifier.
  • the electric signal is amplified with a certain intensity and low noise, so that subsequent circuits can perform signal processing based on the amplified electric signal.
  • FIG. 1 is a plan view of an electrode structure of a conventional photodiode chip.
  • the positive electrode 42 has a pad 421 and the negative electrode 41 has a pad 411.
  • the pad 411 and the pad 421 are electrically connected to different pads of other elements through a metal line, respectively.
  • the diameter of the metal wire is relatively small, such as a commonly used 25 ⁇ m gold wire, which has a larger inductance after being connected.
  • the positive and negative pads are connected by a metal wire, which has poor reliability.
  • the negative electrode is provided with two pads, and the negative electrode can be electrically connected to different pads of other components through two parallel metal wires, thereby reducing the inductance after connection and improving the inductance. Overall device performance. In addition, by connecting two metal wires in parallel to other components, the reliability of the electrical connection can also be improved. If one metal wire has failures such as false soldering or breakage, the other metal wire is connected intact and can play a dual protection role.
  • FIG. 2 is a front plan view of a photodiode chip according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a negative electrode in the photodiode chip shown in FIG. 2
  • FIG. 4 is a photodiode shown in FIG. 2.
  • the cross-sectional view of the chip in the AA direction shows that the photodiode chip includes: a chip substrate 1; an epitaxial functional layer 100 disposed on a surface of one side of the chip substrate 1.
  • the epitaxial functional layer 100 has a negative electrode boss 101 on the surface of the chip substrate 1 and a positive electrode boss 102 on a surface of the negative electrode boss 101 facing away from the chip substrate 1; the negative electrode boss 101 A surface facing away from the chip substrate 1 has a first region and a second region surrounding the first region, and the positive electrode boss 102 is located in the first region.
  • the photodiode chip further includes: a first electrode ring 13 located on a surface of the positive electrode boss 102 facing away from the negative electrode boss 101; and a second electrode ring 12 located in the second region.
  • One pad 15 is connected to the first electrode ring 13, and two pads 14 and 16 are connected to the second electrode ring 12.
  • the first electrode ring 13 and the connected pad 15 constitute a positive electrode of the chip.
  • the second electrode ring 12 and the connected pads 14 and 16 constitute a negative electrode of the chip.
  • the photodiode chip according to the embodiment of the present invention has a different electrode structure from the conventional chip.
  • the positive electrode includes a first electrode ring 13 and a pad 15, and the negative electrode includes a second electrode ring 12. And two pads 14,16.
  • the negative electrode of the photodiode chip provided by the embodiment of the present invention can be electrically connected to different pads of other components through two parallel metal wires, reducing the inductance after connection and improving Chip reliability.
  • the other components include, but are not limited to, a transimpedance amplifier.
  • all the pads are arranged on the same plane.
  • a surface of the positive boss 102 facing away from the negative boss 101 includes a light-passing window 17 and a peripheral region surrounding the light-passing window 17; the first electrode ring 13 is located at In the peripheral region, the first electrode ring 13 surrounds the light-passing window 17; the second electrode ring 12 is located in the second region, and the second electrode ring 12 surrounds the positive electrode boss 102.
  • a surface of the chip substrate 1 on which the epitaxial functional layer 100 is disposed includes: a third region and a fourth region surrounding the third region; the epitaxial functional layer 100 is located in the epitaxial functional layer 100.
  • the pads are all located in the fourth region, so that all the pads can be ensured to be on the same plane.
  • the photodiode chip further includes a passivation layer 7 covering the fourth region, the negative electrode boss 101 and the positive electrode boss 102, and the passivation layer 7 corresponds to the light-passing window 17, and the
  • the first electrode ring 13 and the second electrode ring 12 have openings at positions.
  • the first electrode ring 13 is electrically connected to the top layer 5 through a corresponding opening
  • the second electrode ring 12 is electrically connected to the buffer layer 2 through a corresponding opening. All the pads are located on a side of the passivation layer 7 facing away from the chip substrate 1.
  • the passivation layer 7 includes at least one sublayer, and when there are multiple sublayers, the sublayers are stacked.
  • the optional passivation layer 7 may include two sub-layers, and the two sub-layers are a silicon nitride layer and a silicon dioxide layer.
  • a silicon nitride layer may be disposed on a side facing the epitaxial functional layer 100.
  • the photodiode chip further includes: an anti-reflection film 9 covering the light-passing window 17.
  • the anti-reflection film 9 can increase the light transmittance at the position of the light-passing window 17 and improve the photoelectric conversion efficiency of the photodiode chip.
  • the second electrode ring 12 has an opening K1, and the opening K1 is used to lead out the pad 15 connected to the first electrode ring 13.
  • the second electrode ring 12 includes a middle portion 121, and a first portion 122 and a second portion 123 respectively connected to both ends of the middle portion 121.
  • the first portion 122 and the second portion 123 have a space therebetween.
  • the pad 14 is connected to the opposite end of the first portion 122 and the second portion 123, and the other pad 16 is connected to the opposite end of the second portion 123 and the first portion 122;
  • the pads 15 connected to the first electrode ring 13 are located between the two pads 14 and 16 connected to the second electrode 12 in a ring.
  • the first electrode ring 13 is a closed ring.
  • the chip substrate 1 is a Fe-doped semi-insulating InP substrate; the epitaxial functional layer 100 includes a plurality of sub-layers matching the lattice of the semi-insulating InP substrate. A functional layer; the multilayer sub-functional layers are stacked and arranged in a direction perpendicular to the chip substrate 1.
  • the epitaxial functional layer 100 may be formed by an epitaxial growth process.
  • the epitaxial functional layer may be prepared by a MOCVD epitaxial growth apparatus.
  • the multi-layer sub-function layer includes: a buffer layer 2, an absorption layer 3, and a top layer 5 which are sequentially epitaxially grown on the same side of the chip substrate 1; a contact layer 6 is provided on the surface of the top layer 5;
  • the buffer layer 2 is used to form the negative electrode boss 101, the absorption layer 3 and the top layer 5 are used to form the positive electrode boss 102;
  • the contact layer 6 includes the first electrode ring 13 and the The contact unit between the top layers 5 is used to reduce the contact resistance.
  • the chip substrate 1 is a Fe-doped semi-insulating InP substrate, and an epitaxial functional layer 100 with a lattice matching can be formed on the surface of the chip substrate through an epitaxial growth process, and a receiving rate can be formed as
  • the 10Gbps photodiode chip enables the photodiode chip to receive 1310nm or 1550nm optical signals over long distances (several kilometers, even tens of kilometers). You can adjust some design parameters in the photodiode chip to adjust the communication distance.
  • the thickness of the chip substrate 1 is greater than 2 ⁇ m;
  • the buffer layer 2 is an InP buffer layer with a doping concentration greater than 1 ⁇ 1018 cm-3, and the thickness is greater than 2 ⁇ m and less than 5 ⁇ m;
  • the absorption layer 3 is The InGaAs absorption layer with a doping concentration of less than 5 ⁇ 1014cm-3 has a thickness of more than 0.5 ⁇ m and less than 3 ⁇ m. This layer has the lowest doping concentration. The lower the doping concentration of the layer, the better.
  • the doping concentration is too high, and the depletion layer (absorptive layer 3 in the figure) is difficult to be in a depleted state, which will cause the chip capacitance to increase and fail to meet the high-speed bandwidth requirements.
  • the thickness of the absorption layer 3 provided in the embodiment of the present application It can make its doping concentration lower under the current process conditions to avoid the problem that its high doping concentration can not meet the requirements of high-speed bandwidth;
  • the top layer 5 is an InP top layer with a thickness greater than 0.5 ⁇ m and less than 2 ⁇ m;
  • the contact layer 6 is an InGaAs contact Layer with a thickness greater than 0.1 and less than 0.5 ⁇ m.
  • An active region 4 is formed in the top layer 5 by a Zn diffusion technology, and the diffusion depth of the active region 4 is greater than the thickness of the top layer 5, so that a part of the active region 4 is located in the absorption layer 3.
  • the diffusion depth of the active region 4 is 1 ⁇ m to 1.5 ⁇ m.
  • the diffusion depth of the active region 4 is smaller than the sum of the thicknesses of the top layer 5 and the absorption layer 3.
  • the active region 7 is a circular region with a diameter ranging from 20 ⁇ m to 40 ⁇ m.
  • a surface of the chip substrate 1 facing away from the epitaxial functional layer 100 is further provided with a soldering layer 18.
  • the solder layer 18 may be an Au layer.
  • the soldering layer 18 is used to fix the photodiode chip on a predetermined carrier board, and the carrier board may be a ceramic board with a soldering layer or the like.
  • a contact layer 6 is formed on a surface of the epitaxial functional layer 100 facing away from the chip substrate 1, and the contact layer is patterned to form a corresponding layer.
  • the positive electrode boss 102 and the negative electrode boss 101 are formed by etching.
  • a passivation layer 7 and an anti-reflection film 9 are formed.
  • An opening is provided on the passivation layer 7.
  • the opening includes a through hole 8 for connecting the first electrode ring 13, a through hole 10 for connecting the second electrode ring 12, and an exposed light window 17.
  • the through hole 8 is used to expose the contact unit, so that the first electrode ring 13 is in electrical contact with the contact unit.
  • the through hole 10 is used to expose a portion of the buffer layer 2 so that the second electrode ring 12 is in electrical contact with the portion of the buffer layer 2.
  • the anti-reflection film 9 has a through hole at a position corresponding to the through hole 8 so that the first electrode ring 13 is in electrical contact with the contact unit.
  • a first electrode ring 13 is connected to a pad 15, and a second electrode ring 12 is connected to the first pad 14 and
  • the second pad 16 is a conventional structure in which both the first electrode ring and the second electrode ring are a pad.
  • the photodiode chip according to the embodiment of the present invention can reduce the inductance when the photodiode chip is connected to a transimpedance amplifier. Since the second electrode ring 12 is connected to two pads 14 and 16, when connected to the transimpedance amplifier, the two pads 14 and 16 may be connected to one corresponding pad of the transimpedance amplifier through a metal wire respectively.
  • the two metal wires are in parallel. Compared with the existing method using one metal wire, the inductance can be greatly reduced.
  • the transimpedance amplifier has three pads for electrical connection with the photodiode chip.
  • the second electrode ring 12 is provided with two pads, and the first electrode ring 13 is provided with one pad for easier pad layout.
  • the two pads of the second electrode ring 12 can be connected to the two pads of the transimpedance amplifier respectively through a metal wire with a diameter of 25 ⁇ m. Since the two metal wires are connected in parallel, the inductance after the connection is connected L can be expressed as follows:
  • the inductance value L introduced by the metal wire is compared with the one metal wire method used in the conventional structure to connect a negative pad to a pad
  • the negative electrode has two pads, and two metal wires are respectively connected to the two pads of the transimpedance amplifier, which is equivalent to doubling the diameter of the metal wire and reducing the inductance value by about double.
  • the layout position of the two pads 14 and 16 connected to the second electrode ring 12 is not limited to the manner shown in FIG. 2 and FIG. 3, and may also be shown in FIG. 5, which is the present invention.
  • FIG. 15 is a schematic flowchart of a manufacturing method according to an embodiment of the present invention.
  • the manufacturing method includes:
  • Step S11 As shown in FIG. 6 and FIG. 7, a wafer 50 is provided.
  • the wafer 50 includes a plurality of chip substrates 1, and a cutting channel 51 is provided between adjacent chip substrates 1.
  • FIG. 6 is a plan view of the wafer 50
  • FIG. 7 is a cross-sectional view of the wafer 50 in the direction of P-P '.
  • the wafer 50 is a Fe-doped semi-insulating InP wafer.
  • the thickness of the wafer 50 is larger than 2 ⁇ m.
  • each of the chip substrates 1 is a Fe-doped semi-insulating InP substrate.
  • Step S12 As shown in FIGS. 8 and 9, a patterned epitaxial functional layer 100 is formed on one surface of the wafer 50.
  • the epitaxial functional layer 100 has, for each region of the chip substrate 1, a negative electrode boss 101 located on a surface of the chip substrate 1 and a surface of the negative electrode boss 101 on a surface facing away from the chip substrate 1.
  • Positive electrode boss 102; a surface of the negative electrode boss 101 facing away from the chip substrate 1 has a first region and a second region surrounding the first region, and the positive electrode boss 102 is located in the first region .
  • forming the patterned epitaxial functional layer 100 on one surface of the wafer 50 includes:
  • a buffer layer 2, an absorption layer 3, and a top layer 5 are sequentially formed on the surface of the wafer 50 by an epitaxial growth process.
  • a contact layer 6 is disposed on a surface of the top layer 5.
  • the contact layer 6 can also be formed by an epitaxial growth process.
  • a circular active region 7 is formed by a Zn diffusion technique.
  • the absorption layer 3 and the top layer 5 are etched to form the positive electrode boss 102, and the buffer layer 2 is etched to form the negative electrode boss 101.
  • the contact layer 6 is etched, the contact layer 6 is patterned, and the patterned contact layer 6 includes a contact unit between the first electrode ring 13 and the top layer 5 for reducing contact resistance.
  • the contact layer 6 may be patterned by photolithography and wet etching to form a plurality of contact units corresponding to the chip substrate 1 one-to-one. In another manner, the contact layer 6 may be patterned by a RIE (Reactive Ion Etching) method. Each of the chip substrates is correspondingly provided with one of the contact units, the contact units are ring-shaped, and the ring-shaped middle region is a light-passing window 17.
  • RIE Reactive Ion Etching
  • the absorption layer 3, the and the top layer 5 may be patterned by photolithography and wet etching to form the positive electrode boss 102.
  • the positive electrode boss 102 may also be formed by RIE.
  • a method is used to pattern the absorption layer 3 and the top layer 5 to form the positive electrode boss 102.
  • the surface of the positive boss 102 facing away from the chip substrate 1 is circular, and the diameter of the circle ranges from 40 ⁇ m to 70 ⁇ m. The diameter is too small, the process is difficult, it affects the coupling efficiency of the subsequent device level, and it affects the chip bandwidth and speed. Not reach 10Gbps.
  • the buffer layer 2 may be patterned by using the same process scheme to form the negative electrode boss 101. Both the positive electrode boss 102 and the negative electrode boss 101 are circular at the interface parallel to the chip substrate 1. The height of the negative electrode boss 101 is determined by the thickness of the replacement layer 2.
  • Step S13 As shown in FIGS. 10-12, an electrode structure is formed.
  • the electrode structure Before forming the electrode structure, it further includes: forming a passivation layer 7 covering the fourth region, the negative electrode boss, and the positive electrode boss, and the passivation layer 7 corresponds to the light-passing window 17,
  • the first electrode ring 13 and the second electrode 12 have openings. All the pads are located on a side of the passivation layer 7 facing away from the chip substrate.
  • the electrode structure includes a first electrode ring 13 located on a surface of the positive electrode boss 102 facing away from the negative electrode boss 101 and a second electrode ring 12 located in the second region.
  • the top view of the electrode structure may be as shown in the above FIG. 2 and FIG. 5.
  • the first electrode ring 13 is connected to a pad 15, and the second electrode ring is connected to two pads 14 and 16.
  • the method for forming an electrode structure includes: preparing the first electrode ring 13, the second electrode ring 12, and all the pads through the same conductive layer; wherein all the pads are located at the same flat.
  • a surface of the positive electrode boss 102 facing away from the negative electrode boss 101 includes a light-passing window 17 and a peripheral area surrounding the light-passing window.
  • the method for forming an electrode structure includes: The first electrode ring 13 is formed in a peripheral region, and the first electrode ring 13 surrounds the light-passing window 17; the second electrode ring 12 is formed in the second region, and the second electrode ring 12 surrounds Mentioned positive boss 102.
  • the side surface of the chip substrate 1 on which the epitaxial functional layer 100 is disposed includes: a third region and a fourth region surrounding the third region; the epitaxial functional layer 100 is located in the third region;
  • the method of electrode structure includes forming all the pads in the fourth region.
  • the forming an electrode structure includes:
  • a passivation layer 7 is formed to cover the epitaxial functional layer.
  • a silicon nitride layer and a silicon dioxide layer can be sequentially deposited on the surface of the patterned epitaxial functional layer 100 as a passivation layer 7 by a PECVD device.
  • the thickness of the passivation layer 7 is greater than 0.1 ⁇ m and less than 1 ⁇ m.
  • the passivation layer 7 is patterned.
  • An opening is formed on the surface of the passivation layer 7 to expose the light-passing window 17, and a through-hole 8 for connecting the first electrode ring 13 is formed.
  • An ohmic contact layer can be formed in the through-hole 8 through photolithographic stripping and evaporation processes to further reduce the contact resistance.
  • the first electrode ring 13 and the second electrode ring 12 are fabricated.
  • an anti-reflection coating 9 covering the light-passing window 17.
  • the anti-reflection film 9 also covers the passivation layer 7.
  • the anti-reflection film 9 is formed by a PECVD device, and the thickness is greater than 0.1 ⁇ m and less than 0.5 ⁇ m.
  • the anti-reflection film 9 has a through hole 11 for providing a first electrode ring 13 and a through hole 10 for providing a second electrode ring 12.
  • the through hole 10 penetrates the passivation layer 7 and the anti-reflection film 9.
  • the first electrode ring 13 is electrically connected to the contact layer 6 through the through hole 11 and the through hole 8.
  • an ohmic contact layer may be formed in the through-hole 11 and the through-hole 10 by a method such as sputtering or e-beam (electron beam) evaporation and photolithographic lift-off. Then, the first electrode ring 13 and the second electrode ring 12 are formed by a method such as sputtering, e-beam (electron beam) evaporation, and photolithographic stripping.
  • a first electrode ring 13 is prepared on the positive electrode boss 102 through the same conductive layer, a second electrode ring 12 is formed on the negative electrode boss 101, and a pad connected to the two electrodes.
  • the first electrode ring 13 is in electrical contact with the contact layer 6 through the through hole 8 and the through hole 11.
  • the second electrode ring 12 is in electrical contact with the buffer layer 2 through the through hole 10.
  • the conductive layer for making the electrode structure includes a Ti layer, a Pt layer, and an Au layer that are sequentially stacked, and the Au layer is located at the outermost side.
  • the Ti layer can increase the bonding stability with the underlying material, and Pt is a transition layer, which can increase the diffusion between Ti and Au, improve the reliability of the electrode, and avoid contaminating the epitaxial functional layer 100 after Au diffusion.
  • Pt is a transition layer, which can increase the diffusion between Ti and Au, improve the reliability of the electrode, and avoid contaminating the epitaxial functional layer 100 after Au diffusion.
  • the Ti layer thickness range is Pt layer thickness range
  • Au layer thickness range is The Ti layer and the Pt layer have a certain blocking effect on the diffusion of the Au layer into the chip, and can effectively prevent the problem of mutual diffusion of Au and the chip substrate 1 during the heat treatment process.
  • Step S14 As shown in FIG. 13 to FIG. 15, dividing is performed based on the cutting channel 51 to form a plurality of single photodiode chips.
  • a patterned solder layer 18 is formed on a surface of the wafer 50 facing away from the epitaxial functional layer 100.
  • solder layer 18 covering the surface of the wafer 50 is formed, and then as shown in FIG. 14, the solder layer 18 between adjacent chip substrates 1 is separated to facilitate subsequent division of the wafer 50. deal with.
  • the solder layer 18 can be formed by sputtering or e-beam (electron beam) evaporation, and the solder layer 18 between adjacent chip substrates 1 can be separated by a photolithographic lift-off method.
  • An Au layer can be evaporated on the surface of the wafer 50 as the solder layer 18 by a thermal resistance evaporation process.
  • the surface of the side of the wafer 50 facing away from the epitaxial functional layer 100 may be thinned to reduce the overall thickness of the chip to 120 ⁇ m ⁇ 10 ⁇ m.
  • the wafer 50 is divided by a dicing process to form a plurality of single photodiode chips.
  • the manufacturing method according to the embodiment of the present invention can be used to manufacture the photodiode chip according to the embodiment, the manufacturing method is simple, and the manufacturing cost is low.
  • the second electrode ring 12 has two pads, and the second electrode ring 12 can have the inductance when connected to other components through two parallel metal wires, and has a lower inductance when connected to other components. Can improve the overall performance of the device after wire bonding, and improve the reliability of metal wire bonding.

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PCT/CN2019/096395 2018-08-02 2019-07-17 光电二极管芯片及其制作方法 WO2020024796A1 (zh)

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CN113990983B (zh) * 2021-10-25 2023-07-04 西安微电子技术研究所 一种光吸收能力强的光敏二极管及制备方法

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