WO2019242550A1 - 太阳能电池及其制作方法 - Google Patents

太阳能电池及其制作方法 Download PDF

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WO2019242550A1
WO2019242550A1 PCT/CN2019/090920 CN2019090920W WO2019242550A1 WO 2019242550 A1 WO2019242550 A1 WO 2019242550A1 CN 2019090920 W CN2019090920 W CN 2019090920W WO 2019242550 A1 WO2019242550 A1 WO 2019242550A1
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layer
doped
patterned
dielectric protection
doped layer
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PCT/CN2019/090920
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English (en)
French (fr)
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梁建军
龙巍
郁操
刘霖
徐希翔
李沅民
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君泰创新（北京）科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the disclosure belongs to the field of solar photovoltaic technology, and particularly relates to a back-contact heterojunction single crystal silicon solar cell and a manufacturing method thereof.
  • the back contact electrode structure is one of the main technological development directions of higher efficiency photovoltaic solar cells.
  • HBC cell technology combined with the heterojunction process is the key technology to ensure the high efficiency of the cell.
  • the difficulty of HBC battery technology lies in the realization of the backside process integration, how to arrange the positive and negative electrodes adjacent to the same side of the silicon wafer.
  • the currently known methods are implemented using a very complicated photolithography process. With the problems of many process steps, high requirements for equipment and environment, and high costs, it is difficult to achieve large-scale production.
  • the present disclosure provides a method for manufacturing a solar cell and a solar cell manufactured by the method.
  • One aspect of the present disclosure provides a method for manufacturing a solar cell, including: sequentially forming a first passivation layer (2) and a first doped layer (3) on a first surface of a silicon substrate (1); A first dielectric protection layer (4) is formed on the surface of the doped layer (3); the first dielectric protection layer (4) is etched with a laser in a predetermined pattern to form a pattern on the first doped layer (3) A first dielectric protection layer (41); using the patterned first dielectric protection layer (41) as a mask to remove the first passivation layer (2) and the first doped layer that are not covered by the mask (3) forming a patterned first passivation layer (21) and a patterned first doped layer (31) and exposing a part of the silicon substrate (1); the patterned first dielectric protection layer (41) ), A first portion (51) of a second passivation layer and a first portion (61) of a second doped layer, which are sequentially stacked, and a second passivation layer, which is sequentially stacked, on the exposed portion
  • An etch barrier layer (7) is formed on the second part (62) of the layer; the first step (51) of removing the second passivation layer formed on the patterned first dielectric protection layer (41) And the first portion (61) of the second doped layer; removing the patterned first dielectric protection layer (41) and the etch barrier layer (7), exposing the patterned first doping Layer (31) and the second portion (62) of the second doped layer on the second portion (52) of the second passivation layer; on the patterned first doped layer (31) And a second dielectric protection layer (9) is formed on the second portion (62) of the second doped layer on the second portion (52) of the second passivation layer;
  • the second dielectric protection layer (9) forms a patterned second dielectric protection layer (91), and the patterned second dielectric protection layer (91) covers the
  • the laser etching is picosecond or femtosecond laser etching.
  • the method further comprises: forming a passivation and anti-reflection layer (8) on a second surface opposite to the first surface of the silicon substrate (1).
  • Another aspect of the present disclosure provides a method for manufacturing a solar cell, including: sequentially forming a first passivation layer (2) and a first doped layer (3) on a first surface of a silicon substrate (1); A first dielectric protection layer (4) is formed on a surface of a doped layer (3); the first dielectric protection layer (4) is etched with a laser in a predetermined pattern to form a pattern on the first doped layer (3) A patterned first dielectric protection layer (41); using the patterned first dielectric protection layer (41) as a mask to remove a first doped layer (3) in an area not covered by the mask to form a patterned A first doped layer (31) and a portion of the first passivation layer (2) are exposed; a first portion (61) of a second doped layer is formed on the patterned first dielectric protection layer (41); and A second portion (62) of a second doped layer is formed on the exposed portion of the first passivation layer (2); the second doped layer is formed on the first passivation layer (2) An etch stop layer (7)
  • the laser etching is picosecond or femtosecond laser etching.
  • the method further comprises: forming a passivation and anti-reflection layer (8) on a second surface opposite to the first surface of the silicon substrate (1).
  • Another aspect of the present disclosure also provides a solar cell manufactured by the above method.
  • the first doped layer (3) is a P-type doped amorphous silicon or microcrystalline silicon layer
  • the second portion (62) of the doped layer is an N-type doped amorphous silicon or microcrystalline silicon layer.
  • the first doped layer (3) is an N-type doped amorphous silicon or microcrystalline silicon layer, and the first portion (61) of the second doped layer and the first The second part (62) of the two doped layer is a P-type doped amorphous silicon or microcrystalline silicon layer.
  • the thickness of the first doped layer (3), the first portion (61) of the second doped layer, and the second portion (62) of the second doped layer is 5nm-100nm, and the thickness of the first portion (61) of the second doped layer and the second portion (62) of the second doped layer are the same.
  • the first dielectric protection layer (4) and the second dielectric protection layer (9) include at least one of silicon nitride and silicon oxide.
  • the thicknesses of the first dielectric protection layer (4) and the second dielectric protection layer (9) are 100 nm-500 nm, respectively.
  • the transparent conductive layer (101, 102) includes at least one of ITO, AZO, or BZO.
  • the metal electrode (11, 12) includes at least one of silver and aluminum.
  • the existing back-contact battery requires at least three photolithography processes, and the present disclosure uses laser etching in combination with the first dielectric protection layer to replace the photolithography process, reducing the number of processes and simplifying the process flow without losing battery efficiency. Possibility of low-cost large-scale production.
  • the present disclosure employs picosecond or femtosecond lasers to act on dielectric materials, such as silicon dioxide, silicon nitride, silicon materials, and the like. Since the mechanism by which picosecond or femtosecond lasers interact with materials is "cold" processing, the effect on the properties of the material itself is relatively small.
  • FIG. 1, FIG. 2, FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, and FIG. 8A are schematic diagrams of a method for manufacturing a solar cell according to an embodiment of the present disclosure.
  • 3B, 4B, 5B, 6B, 7B, and 8B are schematic diagrams of a method for manufacturing a solar cell according to another embodiment of the present disclosure.
  • the silicon substrate 1 after single-face texturing (the second surface is texturing and the first surface is chemically polished) is chemically cleaned to remove organic matter, particles, and metal ions from the surface of the silicon wafer.
  • a passivation antireflection film (not shown in the figure), such as a SiN layer, is deposited on the second surface of the silicon substrate 1 with a thickness of 5 nm-100 nm.
  • a first passivation layer 2 is formed on the first surface, and then a first doped layer 3 is formed on the first passivation layer 2.
  • the first passivation layer 2 may be formed on the silicon substrate 1 by PECVD or HWCVD.
  • the first passivation layer 2 may be an intrinsic amorphous silicon layer.
  • the first doped layer 3 may be a P-type doped layer, such as a P-type doped amorphous silicon or microcrystalline silicon layer, or may be an N-type doped layer, such as an N-type doped amorphous silicon or microcrystalline silicon layer. .
  • the P-type doped layer may be formed by doping TMB or B 2 H 6 .
  • the N-type doped layer can be formed by doping with PH 3 .
  • the thickness of this layer is between about 5 nm and 100 nm.
  • a first dielectric protection layer 4 is formed thereon.
  • the first dielectric protection layer 4 may be at least one of silicon nitride and silicon oxide. The thickness of this layer is between 100 nm and 500 nm.
  • the first dielectric protection layer 4 is etched with a laser to form a patterned first dielectric protection layer 41.
  • the laser etching is preferably picosecond or femtosecond laser etching.
  • FIG. 2 shows the structure after laser etching.
  • the first doped layer 3 and the first passivation layer 2 that are not covered by the mask are removed by using the patterned first dielectric protection layer 41 as a mask, and exposed.
  • the substrate 1 forms a patterned first passivation layer 21 and a patterned first doped layer 31.
  • using the patterned first dielectric protection layer 41 as a mask only the first doped layer 3 of the uncovered area of the mask is removed, and the first passivation layer 2 is exposed to form a pattern. ⁇ ⁇ ⁇ ⁇ ⁇ 31 ⁇ The first doped layer 31.
  • the structure for removing the first doped layer 3 and the first passivation layer 2 is shown in FIG. 3A.
  • the first doped layer 3 and the first passivation layer 2 that are not covered by the first dielectric protection layer 41 can be removed by chemical etching to form a patterned first passivation layer 21 and a patterned first dopant.
  • a second passivation layer and a second doping layer are formed on the patterned first dielectric protection layer 41 and the exposed silicon substrate 1, and a second passivation layer is sequentially formed on the patterned first dielectric protection layer 41.
  • a first portion 51 and a second doped layer 61 are formed on the exposed substrate 1 in order to form a second portion 52 of a second passivation layer and a second portion 62 of the second doped layer.
  • the first and second portions 51 and 52 of the second passivation layer, and the first and second portions 61 and 62 of the second doped layer may be formed by PECVD or HWCVD deposition.
  • the first doped layer 3 and the second and first doped layers 61 and 62 are different types of doping.
  • first doped layer 3 is a P-type doped layer
  • first and second portions 61 and 62 of the second doped layer are N-type doped layers. If the first doped layer 3 is an N-type doped layer, the first and second portions 61 and 62 of the second doped layer are P-type doped layers.
  • the deposited structure is shown in Figure 4A.
  • an etch barrier layer 7 is formed on the second portion 62 of the second doped layer.
  • the etch stop layer 7 may be, but is not limited to, a polymer layer to protect the second passivation layer 52 and the second doped layer 62 formed on the substrate 1 in a subsequent etching process.
  • the etch barrier layer 7 may be formed by screen printing.
  • the first portion 51 of the second passivation layer and the first portion 61 of the second doped layer on the patterned first dielectric protection layer 41 may be removed by any method such as chemical etching.
  • the structure after removing the first portion 51 of the second passivation layer and the first portion 61 of the second doped layer is shown in FIG. 5A.
  • the patterned first dielectric protection layer 41 and the etch barrier layer 7 are removed.
  • the patterned first dielectric protection layer 41 may be removed by chemical etching.
  • the etching stopper layer 7 is removed with a different chemical agent. Since the chemical etching will damage the passivation anti-reflection film (not shown) formed on the second surface of the silicon substrate 1, the passivation anti-reflection layer 8 can be newly formed on the second surface after this step. It is shown, but those skilled in the art can understand that the passivation and anti-reflection layer 8 can be two layers of passivation layer and anti-reflection layer, and the anti-reflection layer can also be two or more layers.
  • the passivation antireflection layer 8 may be, but is not limited to, for example, a-Si, SiO 2 , SiN, etc., or a double-layer antireflection.
  • a second dielectric protection layer 9 is formed on the patterned first doped layer 31 and the second portion 62 of the second doped layer.
  • the second dielectric protection layer 9 may be at least one of silicon nitride and silicon oxide.
  • the structures forming the passivation anti-reflection layer 8 and the second dielectric protection layer 9 are shown in FIG. 6A.
  • the second dielectric protection layer 9 is etched with a laser in a predetermined pattern to form a patterned second dielectric protection layer 91, as shown in FIG. 7A.
  • Picosecond or femtosecond laser etching is preferred.
  • the patterned second dielectric protection layer 91 should cover the boundary between the patterned first doped layer 31 and the second portion 62 of the second doped layer.
  • transparent conductive layers 101 and 102 are formed by using the patterned second dielectric protection layer 91 as a mask.
  • the transparent conductive layer 101 is formed on the patterned first doped layer 31 and the transparent conductive layer 102 is formed on the first conductive layer. Over the second portion 62 of the two doped layer.
  • the transparent conductive layers 101 and 102 may be formed by screen printing.
  • the transparent conductive layer 101 or 102 may be formed of at least one of ITO, AZO, and BZO.
  • a first electrode 11 is formed on the transparent conductive layer 101, and a second electrode 12 is formed on the transparent conductive oxide layer 102.
  • the first electrodes 11 and the second electrodes 12 have opposite polarities.
  • the first electrode 11 and the second electrode 12 may be metal electrodes, for example, at least one of Ag and Al.
  • the resulting structure is shown in Figure 8A.
  • first doped layer 3 is removed using the patterned first dielectric protection layer 41 as a mask, and a portion of the first passivation layer 2 is exposed to form a patterned first A doped layer 31.
  • the first doped layer 3 can be removed by chemical etching. The structure is shown in Figure 3B.
  • a first portion (61) of the second doped layer is formed on the patterned first dielectric protection layer 41, and a second doped layer is formed on the exposed portion of the first passivation layer 2.
  • the first doped layer 3 is different from the first portion 61 of the second doped layer and the second portion 62 of the second doped layer. If the first doped layer 3 is a P-type doped layer, the first portion 61 of the second doped layer and the second portion 62 of the second doped layer are N-type doped layers. If the first doped layer is an N-type doped layer, the first portion 61 of the second doped layer and the second portion 62 of the second doped layer are P-type doped layers.
  • the second doped layer (61 and 62) can be formed by PECVD or HWCVD deposition. The deposited structure is shown in Figure 4B.
  • an etch stop layer 7 is formed on the second portion 62 of the second doped layer on the first passivation layer 2.
  • the etch barrier layer 7 may be, but is not limited to, a polymer layer to protect the passivation layer 2 and the second portion 62 of the second doped layer formed on the substrate 1 in a subsequent etching process.
  • the etch barrier layer 7 may be formed by screen printing.
  • the first portion 61 of the second doped layer on the patterned first dielectric protection layer 41 may be removed by any method such as chemical etching. The structure after removing the second doped layer 61 is shown in FIG. 5B.
  • the patterned first dielectric protection layer 41 and the etch barrier layer 7 are removed.
  • the patterned first dielectric protection layer 41 may be removed by chemical etching.
  • the etching stopper layer 7 is removed with a different chemical agent. Since the chemical etching will damage the passivation antireflection film (not shown in the figure) formed on the second surface of the silicon substrate 1, the passivation antireflection layer 8 can be newly formed on the second surface after this step, as shown in FIG. 6B
  • the figure is represented by one layer, but those skilled in the art can understand that the passivation and anti-reflection layer 8 can be two layers of passivation and anti-reflection layer, and the anti-reflection layer can also be two or more layers.
  • the passivation antireflection layer 8 may be, but is not limited to, for example, a-Si, SiO 2 , SiN, etc., or a double-layer antireflection.
  • a second dielectric protection layer 9 is formed on the patterned first doped layer 31 and the second portion 62 of the second doped layer.
  • the second dielectric protection layer 9 may be at least one of silicon nitride and silicon oxide.
  • the second dielectric protection layer 9 is etched by a laser in a predetermined pattern to form a patterned second dielectric protection layer 91, as shown in FIG. 7B.
  • Picosecond or femtosecond laser etching is preferred.
  • the patterned second dielectric protection layer 91 should cover the boundary between the patterned first doped layer 31 and the second portion 62 of the second doped layer.
  • transparent conductive layers 101 and 102 are formed on the patterned first doped layer 31 and the second portion 62 of the second doped layer, respectively.
  • the transparent conductive layers 101 and 102 may be formed by screen printing.
  • the transparent conductive layers 101 and 102 may be formed of at least one of ITO, AZO, and BZO.
  • a first electrode 11 is formed on the transparent conductive layer 101
  • a second electrode 12 is formed on the transparent conductive layer 102.
  • the first electrodes 11 and the second electrodes 12 have opposite polarities.
  • the first electrode 11 and the second electrode 12 may be metal electrodes, for example, at least one of Ag and Al.
  • the resulting structure is shown in Figure 8B.
  • the existing back-contact battery requires at least 3 photolithography processes, and the present disclosure uses ultra-laser etching combined with the first dielectric protection layer to replace the photolithography process, reducing the number of processes and simplifying the process flow without losing battery efficiency. With the feasibility of low-cost large-scale production.
  • the present disclosure employs picosecond or femtosecond lasers to act on dielectric materials, such as silicon dioxide, silicon nitride, silicon materials, and the like. Since the mechanism by which picosecond or femtosecond lasers interact with materials is "cold" processing, the effect on the properties of the material itself is relatively small.

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Abstract

一种太阳能电池的制作方法，包括：在硅基底（1）表面依次形成第一钝化层（2）和第一掺杂层（3）；在第一掺杂层（3）表面形成第一电介质保护层（4）；按预定图案利用激光刻蚀第一电介质保护层（4）；以第一电介质保护层（4）为掩模除去第一钝化层（2）和第一掺杂层（3）；在第一电介质保护层（4）和露出的硅基底（1）上形成图案化的第二钝化层和第二掺杂层；在形成于硅基底（1）上的第二掺杂层上形成刻蚀阻挡层（7）；除去形成于第一电介质保护层（4）上的第二钝化层和第二掺杂层；除去第一电介质保护层（4）和刻蚀阻挡层（7）；形成第二电介质保护层（9）；按预定图案利用激光刻蚀第二电介质保护层（9）；最后形成透明导电层（101,102）和电极（11,12）。通过利用激光刻蚀结合第一电介质保护层（4）替代光刻工艺，在不损失电池效率的前提下，简化工艺流程，具备低成本大规模生产的可行性。

Description

太阳能电池及其制作方法 技术领域
本公开属于太阳能光伏技术领域，尤其涉及一种背接触异质结单晶硅太阳能电池及其制作方法。
背景技术
背接触电极结构是更高效率光伏太阳能电池的主要技术发展方向之一，结合了异质结工艺的HBC电池技术是保证电池高效率的关键技术。HBC电池工艺的难点在背面工艺集成的实现，如何将正负电极相邻安排在硅片同一面。目前已知的方法是采用非常复杂的光刻工艺来实现，伴随工艺步骤多、对设备和环境要求高、成本高等问题，很难实现大规模生产。
发明内容
为了克服现有缺陷，本公开提供一种太阳能电池的制作方法及该方法制作的太阳能电池。
本公开一方面提供一种太阳能电池的制作方法，包括：在硅基底(1)的第一表面依次形成第一钝化层(2)和第一掺杂层(3)；在所述第一掺杂层(3)表面形成第一电介质保护层(4)；按预定图案利用激光刻蚀所述第一电介质保护层(4)，在所述第一掺杂层(3)上形成图案化的第一电介质保护层(41)；以所述图案化的第一电介质保护层(41)为掩模除去所述掩模未覆盖区域的第一钝化层(2)和第一掺杂层(3)，形成图案化的第一钝化层(21)和图案化的第一掺杂层(31)且露出部分硅基底(1)；在所述图案化的第一电介质保护层(41)上形成依次层叠的第二钝化层的第一部分(51)和第二掺杂层的第一部分(61)，以及在所述露出的部分硅基底(1)上形成依次层叠的第二钝化层的第二部分(52)和第二掺杂层的第二部分(62)；在依次层叠的所述硅基底(1)、所述第二钝化层的第二部分(52)上和所述第二掺杂层的第二部分(62)上形成刻蚀阻挡层(7)；除去形成于所述图案化的第一电介质保护层(41)上的所述第二钝化层的第一步(51)和所述第二掺杂层的第一部分(61)；除去所述图案化的第一电介质保护层(41)和所述刻蚀阻挡层(7)，露出所述图案化的第一掺杂层(31)和所述第二钝化层的第二部分(52)上的所述第二掺杂层的第二部分(62)；在所述图案化的第一掺杂层(31)和所述第二钝化层的第二部分(52)上的所述第二掺杂层的第二部分(62)上形成第二电介质保护层(9)；按预定图案利用激光刻蚀所述第二电介质保护层(9)，形成图案化的第二电介质保护层(91)，所述图案化的第二电介质保护层(91)覆盖所述图案化的第一掺杂层(31)与所述第二掺杂层的第二部分(62)的交界处；以所述图案化的第二电介质保护层(91)为掩模形成透明导电层(101,102)；在所述透明导电层(101,102)上形成电极(11,12)。
根据本公开的一实施方式，所述激光刻蚀是皮秒或者飞秒激光刻蚀。
根据本公开的另一实施方式，所述方法还包括：在与所述硅基底(1)的第一表面相对的第二表面形成钝化减反层(8)。
本公开另一方面提供一种太阳能电池的制作方法，包括：在硅基底(1)的第一表面依次形成第一钝化层(2)和第一掺杂层(3)；在所述第一掺杂层(3)表面形成第一电介质保护层(4)；按预定图案利用激光刻蚀所述第一电介质保护层(4)，在所述第一掺杂层(3)上形成图案化的第一电介质保护层(41)；以所述图案化的第一电介质保护层(41)为掩模除去所述掩模未覆盖区域的第一掺杂层(3)，形成图案化的第一掺杂层(31)且露出部分第一钝化层(2)；在所述图案化的第一电介质保护层(41)上形成第二掺杂层的第一部分(61)；且在所述露出的部分第一钝化层(2)上形成第二掺杂层的第二部分(62)；在形成于所述第一钝化层(2)上的所述第二掺杂层的第二部分(62)上形成刻蚀阻挡层(7)；除去形成于所述图案化的第一电介质保护层(41)上的所述第二掺杂层的第一部分(61)；除去所述图案化的第一电介质保护层(41)和所述刻蚀阻挡层(7)，露出所述第二掺杂层的第二部分(62)和所述图案化的第一掺杂层(31)；在所述图案化的第一掺杂层(31)和所述第二掺杂层的第二部分(62)上形成第二电介质保护层(9)；按预定图案利用激光刻蚀所述第二电介质保护层(9)，形成图案化的第二电介质保护层(91)，所述图案化的第二电介质保护层(91)覆盖所述图案化的第一掺杂层(31)与所述第二掺杂层的第二部分(62)的交界处；以所述图案化的第二电介质保护层(91)为掩模形成透明导电层(101,102)；在所述透明导电层(101,102)上形成电极(11,12)。
根据本公开的一实施方式，所述激光刻蚀是皮秒或者飞秒激光刻蚀。
根据本公开的另一实施方式，所述方法还包括：在与所述硅基底(1)的第一表面相对的第二表面形成钝化减反层(8)。
本公开的另一方面还提供一种太阳能电池，由上述方法制作。
根据本公开的一实施方式，所述第一掺杂层(3)是P型掺杂非晶硅或微晶硅层，所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)是N型掺杂非晶硅或微晶硅层。
根据本公开的另一实施方式，所述第一掺杂层(3)是N型掺杂非晶硅或微晶硅层，所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)是P型掺杂非晶硅或微晶硅层。
根据本公开的另一实施方式，所述第一掺杂层(3)、所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)的厚度分别是5nm-100nm，且所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)的厚度相同。
根据本公开的另一实施方式，所述第一电介质保护层(4)和第二电介质保护层(9)包括氮化硅、氧化硅中的至少一种。
根据本公开的另一实施方式，所述第一电介质保护层(4)和第二电介质保护层(9)的厚度分别是100nm-500nm。
根据本公开的另一实施方式，所述透明导电层(101,102)包括ITO、AZO或BZO中的 至少一种。
根据本公开的另一实施方式，所述金属电极(11,12)包括银和铝中的至少一种。
现有背接触电池至少需要3次光刻工艺，而本公开的利用激光刻蚀结合第一电介质保护层替代光刻工艺，在不损失电池效率的前提下，减少了工序次数，简化工艺流程，具备低成本大规模生产的可行性。
更进一步，本公开采用皮秒或飞秒激光作用于电介质材料，例如，二氧化硅，氮化硅，硅材料等。由于皮秒或飞秒激光同材料相互作用的机理是“冷”处理，因此对材料本身性能的影响相对很小。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1、图2、图3A、图4A、图5A、图6A、图7A和图8A为本公开一实施方式的太阳能电池的制作方法的示意图。
[根据细则91更正 15.08.2019]　
图3B、图4B、图5B、图6B、图7B和图8B为本公开又一实施方式的太阳能电池的制作方法的示意图。
其中，附图标记说明如下：
1-硅基底；2-第一钝化层；21-图案化的第一钝化层；3-第一掺杂层；31-图案化的第一掺杂层；4-第一电介质保护层；41-图案化的第一电介质保护层；51-第二钝化层的第一部分；52-第二钝化层的第二部分；61-第二掺杂层的第一部分；62-第二掺杂层的第二部分；7-刻蚀阻挡层；8-钝化减反层；9-第二电介质保护层；91-图案化的第二电介质保护层；101,102-透明导电层；11-第一电极；12-第二电极
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中，为了清晰，夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
需要说明的是，本公开中上、下等用语，仅为互为相对概念或是以产品的正常使用状态为参考的，而不应该认为是具有限制性的。
如图1所示，首先将单面制绒(第二表面制绒、第一表面进行化学抛光处理)后的硅基底1进行化学清洗，去除硅片表面的有机物、颗粒和金属离子等污染。在硅基底1的第二表面沉积钝化减反膜(图中未示出)，例如SiN层等，厚度在5nm-100nm。然后，在第一表面形成第一钝化层2，然后在第一钝化层2上形成第一掺杂层3。可以通过PECVD或 者HWCVD在硅基底1上沉积形成第一钝化层2，第一钝化层2可以是本征非晶硅层。第一掺杂层3可以是P型掺杂层，例如P型掺杂非晶硅或微晶硅层，也可以是N型掺杂层，例如N型掺杂非晶硅或微晶硅层。P型掺杂层可以由掺杂TMB或B 2H 6生长形成。N型掺杂层可以由掺杂PH 3生长形成。该层的厚度大约在5nm-100nm之间。形成第一掺杂层3之后，在其上形成第一电介质保护层4。第一电介质保护层4可以是氮化硅、氧化硅中的至少一种。该层的厚度为100nm-500nm之间。之后用激光刻蚀第一电介质保护层4形成图案化的第一电介质保护层41。激光刻蚀优选为皮秒或者飞秒激光刻蚀。图2示出激光刻蚀后的结构。
根据本申请的第一种实施方式，激光刻蚀之后，以图案化的第一电介质保护层41为掩模除去掩模未覆盖区域的第一掺杂层3和第一钝化层2，露出基底1，形成图案化的第一钝化层21和图案化的第一掺杂层31。或者，根据本申请的第二种实施方式，以图案化的第一电介质保护层41为掩模仅除去掩模未覆盖区域的第一掺杂层3，露出第一钝化层2，形成图案化的第一掺杂层31。以下结合相应的附图分别说明这两种实施方式制作太阳能电池的过程。
除去第一掺杂层3和第一钝化层2的结构如图3A所示。可以通过化学刻蚀，除去没有被第一电介质保护层41覆盖部分的第一掺杂层3和第一钝化层2，形成图案化的第一钝化层21和图案化的第一掺杂层31。
之后，在图案化的第一电介质保护层41和露出的硅基底1上形成第二钝化层和第二掺杂层，在图案化的第一电介质保护层41上依次形成第二钝化层的第一部分51和第二掺杂层61，在露出的基底1上依次形成第二钝化层的第二部分52和第二掺杂层的第二部分62。可以通过PECVD或者HWCVD沉积形成第二钝化层的第一部分51和第二钝化层的第二部分52，及第二掺杂层的第一部分61和第二掺杂层第二部分62。第一掺杂层3与第二掺杂层第一部分61和第二部分62是不同类型的掺杂。若第一掺杂层3是P型掺杂层，则第二掺杂层第一部分61和第二部分62是N型掺杂层。若第一掺杂层3是N型掺杂层，则第二掺杂层第一部分61和第二部分62是P型掺杂层。沉积后的结构如图4A所示。
随后，在第二掺杂层的第二部分62上形成刻蚀阻挡层7。之后，除去形成于图案化的第一电介质保护层41上的第二钝化层的第一部分51和第二掺杂层的第一部分61。刻蚀阻挡层7可以是，但不限于聚合物层，以保护后续的刻蚀过程中形成在基底1上的第二钝化层52和第二掺杂层62。可以通过丝网印刷形成刻蚀阻挡层7。可以通过化学刻蚀等任何方式除去图案化的第一介质保护层41上的第二钝化层的第一部分51和第二掺杂层的第一部分61。除去第二钝化层的第一部分51和第二掺杂层的第一部分61后的结构如图5A所示。
然后，除去图案化的第一电介质保护层41和刻蚀阻挡层7。可以通过化学刻蚀除去图案化的第一电介质保护层41。然后，用不同的化学试剂除去刻蚀阻挡层7。由于化学刻蚀会损伤硅基底1第二表面形成的钝化减反膜(图中未示出)，因此该步骤之后可以在第 二表面重新形成钝化减反层8，图中用一层表示，但本领域技术人员可以理解，钝化减反层8可以钝化层和减反层两层，减反层也可以是双层或多层。钝化减反层8可以是，但不限于例如a-Si,SiO 2,SiN等，或者双层减反射等。并在图案化的第一掺杂层31和第二掺杂层的第二部分62上形成第二电介质保护层9。第二电介质保护层9可以氮化硅、氧化硅中的至少一种。形成钝化减反层8和第二电介质保护层9的结构如图6A所示。
随后，按预定图案利用激光刻蚀第二电介质保护层9，形成图案化的第二电介质保护层91，结构如图7A所示。优选为皮秒或者飞秒激光刻蚀。很明显地，本领域的普通技术人员知晓，图案化的第二电介质保护层91应覆盖图案化的第一掺杂层31与第二掺杂层的第二部分62的交界处。
随后，以图案化的第二电介质保护层91为掩模形成透明导电层101和102，其中，透明导电层101形成于图案化的第一掺杂层31之上，透明导电层102形成于第二掺杂层的的第二部分62之上。可以通过丝网印刷形成透明导电层101和102。透明导电层101或102可以由ITO、AZO、BZO中的至少一种形成。最后在透明导电层101上形成第一电极11，在透明导电氧化物层102上形成第二电极12。第一电极11和第二电极12的极性相反。第一电极11和第二电极12可以是金属电极，例如Ag、Al中的至少一种。形成的结构图8A所示。
根据本申请的第二种实施方式，激光刻蚀之后以图案化的第一电介质保护层41为掩模仅除去第一掺杂层3，露出部分第一钝化层2，形成图案化的第一掺杂层31。可以通过化学刻蚀，除去第一掺杂层3。结构如图3B所示。
除去第一掺杂层3，则在图案化的第一电介质保护层41上形成第二掺杂层的第一部分(61)，且露出的部分第一钝化层2上形成第二掺杂层的第二部分62。第一掺杂层3与第二掺杂层的第一部分61和第二掺杂层的第二部分62是不同类型的掺杂。若第一掺杂层3是P型掺杂层，则第二掺杂层的第一部分61和第二掺杂层的第二部分62是N型掺杂层。若第一掺杂层是N型掺杂层，则第二掺杂层的第一部分61和第二掺杂层的第二部分62是P型掺杂层。可以通过PECVD或者HWCVD沉积形成第二掺杂层(61和62)。沉积后的结构如图4B所示。
随后，在第一钝化层2上的第二掺杂层的第二部分62上形成刻蚀阻挡层7。刻蚀阻挡层7可以是，但不限于聚合物层，以保护后续的刻蚀过程中形成在基底1上的钝化层2和第二掺杂层的第二部分62。可以通过丝网印刷形成刻蚀阻挡层7。可以通过化学刻蚀等任何方式除去所述图案化的第一介质保护层41上的第二掺杂层的第一部分61。除去第二掺杂层61后的结构如图5B所示。
然后，除去图案化的第一电介质保护层41和刻蚀阻挡层7。可以通过化学刻蚀除去图案化的第一电介质保护层41。然后，用不同的化学试剂除去刻蚀阻挡层7。由于化学刻蚀会损伤硅基底1第二表面形成的钝化减反膜(图中未示出)，因此该步骤之后可以在第二表面重新形成钝化减反层8，如图6B所示，图中用一层表示，但本领域技术人员可以 理解，钝化减反层8可以钝化层和减反层两层，减反层也可以是双层或多层。钝化减反层8可以是，但不限于例如a-Si,SiO 2,SiN等，或者双层减反射等。并在图案化的第一掺杂层31和第二掺杂层的第二部分62上形成第二电介质保护层9。第二电介质保护层9可以氮化硅、氧化硅中的至少一种。
随后，按预定图案利用激光刻蚀第二电介质保护层9，形成图案化的第二电介质保护层91，结构如图7B所示。优选为皮秒或者飞秒激光刻蚀。很明显地，本领域的普通技术人员知晓，图案化的第二电介质保护层91应覆盖图案化的第一掺杂层31与第二掺杂层的第二部分62的交界处。
随后，以图案化的第二电介质保护层91为掩模分别在图案化的第一掺杂层31和第二掺杂层的第二部分62上形成透明导电层101和102。可以通过丝网印刷形成透明导电层101和102。透明导电层101和102可以由ITO、AZO、BZO中的至少一种形成。最后在透明导电层101上形成第一电极11，在透明导电层102形成第二电极12。第一电极11和第二电极12的极性相反。第一电极11和第二电极12可以是金属电极，例如Ag、Al中的至少一种。形成的结构图8B所示。
现有背接触电池至少需要3次光刻工艺，而本公开的利用超激光刻蚀结合第一电介质保护层替代光刻工艺，在不损失电池效率的前提下，减少了工序次数，简化工艺流程，具备低成本大规模生产的可行性。
更进一步，本公开采用皮秒或飞秒激光作用于电介质材料，例如，二氧化硅，氮化硅，硅材料等。由于皮秒或飞秒激光同材料相互作用的机理是“冷”处理，因此对材料本身性能的影响相对更小。
本公开的技术方案已由优选实施例揭示如上。本领域技术人员应当意识到在不脱离本公开所附的权利要求所揭示的本公开的范围和精神的情况下所作的更动与润饰，均属本公开的权利要求的保护范围之内。

Claims (14)

  1. 一种太阳能电池的制作方法，其特征在于，所述方法包括：
    在硅基底(1)的第一表面依次形成第一钝化层(2)和第一掺杂层(3)；
    在所述第一掺杂层(3)表面形成第一电介质保护层(4)；
    按预定图案利用激光刻蚀所述第一电介质保护层(4)，在所述第一掺杂层(3)上形成图案化的第一电介质保护层(41)；
    以所述图案化的第一电介质保护层(41)为掩模除去所述掩模未覆盖区域的第一钝化层(2)和第一掺杂层(3)，形成图案化的第一钝化层(21)和图案化的第一掺杂层(31)且露出部分硅基底(1)；
    在所述图案化的第一电介质保护层(41)上形成依次层叠第二钝化层的第一部分(51)和第二掺杂层的第一部分(61)，以及在所述露出的部分硅基底(1)上形成依次层叠第二钝化层的第二部分(52)和第二掺杂层的第二部分(62)；
    在依次层叠的所述硅基底(1)、所述第二钝化层的第二部分(52)上和所述第二掺杂层的第二部分(62)上形成刻蚀阻挡层(7)；
    除去形成于所述图案化的第一电介质保护层(41)上的所述第二钝化层的第一部分(51)和所述第二掺杂层的第一部分(61)；
    除去所述图案化的第一电介质保护层(41)和所述刻蚀阻挡层(7)，露出所述图案化的第一掺杂层(31)和所述第二钝化层的第二部分(52)上的所述第二掺杂层的第二部分(62)；
    在所述图案化的第一掺杂层(31)和所述第二钝化层的第二部分(52)上的所述第二掺杂层的第二部分(62)上形成第二电介质保护层(9)；
    按预定图案利用激光刻蚀所述第二电介质保护层(9)，形成图案化的第二电介质保护层(91)，所述图案化的第二电介质保护层(91)覆盖所述图案化的第一掺杂层(31)与所述第二掺杂层的第二部分(62)的交界处；
    以所述图案化的第二电介质保护层(91)为掩模形成透明导电层(101,102)；
    在所述透明导电层(101,102)上分别形成电极(11,12)。
  2. 如权利要求1所述的太阳能电池的制作方法，其特征在于，所述激光刻蚀是皮秒或者飞秒激光刻蚀。
  3. 如权利要求1所述的太阳能电池的制作方法，其特征在于，所述方法还包括：
    在与所述硅基底(1)的第一表面相对的第二表面形成钝化减反层(8)。
  4. 一种太阳能电池的制作方法，其特征在于，所述方法包括：
    在硅基底(1)的第一表面依次形成第一钝化层(2)和第一掺杂层(3)；
    在所述第一掺杂层(3)表面形成第一电介质保护层(4)；
    按预定图案利用激光刻蚀所述第一电介质保护层(4)，在所述第一掺杂层(3)上形成图案化的第一电介质保护层(41)；
    以所述图案化的第一电介质保护层(41)为掩模除去所述掩模未覆盖区域的第一掺杂层(3)，形成图案化的第一掺杂层(31)且露出部分第一钝化层(2)；
    在所述图案化的第一电介质保护层(41)上形成第二掺杂层的第一部分(61)；且在所述露出的部分第一钝化层(2)上形成第二掺杂层的第二部分(62)；
    在形成于所述第一钝化层(2)上的所述第二掺杂层的第二部分(62)上形成刻蚀阻挡层(7)；
    除去形成于所述图案化的第一电介质保护层(41)上的所述第二掺杂层的第一部分(61)；
    除去所述图案化的第一电介质保护层(41)和所述刻蚀阻挡层(7)，露出所述第二掺杂层的第二部分(62)和所述图案化的第一掺杂层(31)；
    在所述图案化的第一掺杂层(31)和所述第二掺杂层的第二部分(62)上形成第二电介质保护层(9)；
    按预定图案利用激光刻蚀所述第二电介质保护层(9)，形成图案化的第二电介质保护层(91)，所述图案化的第二电介质保护层(91)覆盖所述图案化的第一掺杂层(31)与所述第二掺杂层的第二部分(62)的交界处；
    以所述图案化的第二电介质保护层(91)为掩模形成透明导电层(101,102)；
    在所述透明导电层(101,102)上形成电极(11,12)。
  5. 如权利要求4所述的太阳能电池的制作方法，其特征在于，所述激光刻蚀是皮秒或者飞秒激光刻蚀。
  6. 如权利要求4所述的太阳能电池的制作方法，其特征在于，所述方法还包括：
    在与所述硅基底(1)的第一表面相对的第二表面形成钝化减反层(8)。
  7. 一种太阳能电池，其特征在于，由权利要求1-3任一方法制作或由权利要求4-6任一方法制作。
  8. 如权利要求7所述的太阳能电池，其特征在于，所述第一掺杂层(3)是P型掺杂非晶硅或微晶硅层，所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)是N型掺杂非晶硅或微晶硅层。
  9. 如权利要求7所述的太阳能电池，其特征在于，所述第一掺杂层(3)是N型掺杂非晶硅或微晶硅层，所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)是P型掺杂非晶硅或微晶硅层。
  10. 如权利要求7所述的太阳能电池，其特征在于，所述第一掺杂层(3)、所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)的厚度均为5nm-100nm，且所述第二掺杂层的第一部分(61)和所述第二掺杂层的第二部分(62)的厚度相同。
  11. 如权利要求7所述的太阳能电池，其特征在于，所述第一电介质保护层(4)和第二电介质保护层(9)包括氮化硅、氧化硅中的至少一种。
  12. 如权利要求7所述的太阳能电池，其特征在于，所述第一电介质保护层(4)和第二电介质保护层(9)的厚度均为100nm-500nm。
  13. 如权利要求7所述的太阳能电池的制作方法，其特征在于，所述透明导电层(101,102)包括ITO、AZO或BZO中的至少一种。
  14. 如权利要求7所述的太阳能电池的制作方法，其特征在于，所述金属电极(11,12)包括银和铝中的至少一种。
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