WO2019237308A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2019237308A1
WO2019237308A1 PCT/CN2018/091295 CN2018091295W WO2019237308A1 WO 2019237308 A1 WO2019237308 A1 WO 2019237308A1 CN 2018091295 W CN2018091295 W CN 2018091295W WO 2019237308 A1 WO2019237308 A1 WO 2019237308A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
wiring layer
metal wiring
layer
hole
Prior art date
Application number
PCT/CN2018/091295
Other languages
English (en)
French (fr)
Inventor
杨雯
刘燕翔
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880089628.XA priority Critical patent/CN111742366B/zh
Priority to PCT/CN2018/091295 priority patent/WO2019237308A1/zh
Priority to EP18922369.6A priority patent/EP3800642A4/en
Publication of WO2019237308A1 publication Critical patent/WO2019237308A1/zh
Priority to US17/120,667 priority patent/US11957062B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory.
  • STT-MRAM Spin-Transfer Torque-Magnetic Random Access Memory
  • SRAM Static Random Access Memory
  • SRAM Random Access Memory
  • STT-MRAM has a huge advantage in terms of static power consumption and area.
  • the present application provides a memory, which can improve the integration density of the memory.
  • a memory including a memory area, where the memory area includes a plurality of memory cells disposed on a substrate; each memory cell includes a transistor disposed on the substrate and an MTJ memory element electrically connected to the transistor. ; MTJ memory element includes a bottom electrode, a top electrode, and an MTJ located therebetween, and the bottom electrode and the drain electrode of the transistor are electrically connected through a conductive structure; the storage area is provided with a plurality of wiring layers between the transistor and the MTJ memory element, A dielectric layer is filled between adjacent wiring layers.
  • the conductive structure includes a first conductive portion, and the first conductive portion includes a first metal wiring, a second metal wiring, and a first metal wiring and a second metal wiring.
  • the first wiring layer includes a first wiring layer, a second wiring layer, and a third wiring layer.
  • the third wiring layer is disposed between the first wiring layer and the second wiring layer.
  • the first wiring layer includes The first metal wiring and the second wiring layer include a second metal wiring, and the first through-hole penetrates the dielectric layer between the first wiring layer and the second wiring layer and the third wiring layer; Connecting passage, a first connecting passage directly connected to the first metal wiring and the second metal wirings, a first connecting passage are not directly connected to the metal wiring on the third wiring layer.
  • the first via of the first conductive portion penetrates the third wiring between the first wiring layer and the second wiring layer.
  • Layer, and the first connection channel provided in the first through hole is directly connected to the first metal wiring and the second metal wiring.
  • the third metal wiring is electrically connected to the third wiring layer.
  • the third metal wiring is omitted in the present application, so that the space occupied by the third metal wiring can be released. Based on this, on the one hand, the space released by the third metal wiring can be used for circuit wiring, thereby alleviating the congestion of the overall circuit wiring; on the other hand, after the third metal wiring is omitted, the minimum spacing of the wiring is met.
  • the area occupied by each memory cell can be reduced, so the integration density of the memory can be improved; on the other hand, the resistance of the via mainly comes from the interface between the via and the metal wiring contacting it below (near the substrate).
  • the first through hole crosses the third wiring layer, there is no interface between the first through hole and the metal wiring on the third wiring layer, which has a smaller resistance and can reduce parasitics.
  • Capacitors can further improve the overall performance of the memory.
  • the transistor is used to control writing, changing, or reading of information in the memory cell.
  • the storage area is provided with a second through hole, and the second through hole penetrates the third wiring layer; the first through hole is adjacent to the second through hole, and the third wiring layer is located at There is no metal wiring on a portion between the first through hole and the second through hole.
  • the storage area is provided with a third through hole, one end of the third through hole starts from the third wiring layer, and the third connection channel and the third through hole in the third through hole are The metal wiring on the three wiring layers is connected, and the third through hole is adjacent to the first through hole.
  • the transistors in two adjacent memory cells share a drain electrode. This can further increase the integration density of the memory.
  • first conducting portions there are at least two first conducting portions, and all the first conducting portions are disposed along a thickness direction of the substrate.
  • two adjacent first conducting portions share the second metal wiring or the first metal wiring.
  • the conducting structure further includes a second conducting portion, and the second conducting portion is disposed between the first conducting portion and the MTJ storage element; the second conducting portion Including a fourth metal wiring and a fourth through hole; the multilayer wiring layer further includes a fourth wiring layer, the fourth wiring layer includes a fourth metal wiring; the fourth through hole penetrates between the fourth wiring layer and the first conductive portion A dielectric layer; the fourth through hole is provided with a fourth connection channel, and the fourth connection channel is directly connected to the fourth metal wiring, the first metal wiring adjacent to the fourth metal wiring, or the second metal wiring.
  • the conductive structure further includes a third conductive portion, and the third conductive portion is disposed between the first conductive portion and the transistor; the third conductive portion includes a first conductive portion Five through holes, a fifth through hole penetrating a dielectric layer between the first conducting portion and the drain electrode of the transistor; a fifth connection channel is provided in the fifth through hole, and the fifth connection channel is connected to the drain electrode of the transistor and the leakage of the transistor
  • the first metal wiring or the second metal wiring adjacent to each other is directly connected.
  • the first through hole penetrates one or two third wiring layers between the first wiring layer and the second wiring layer; In a case where there are at least two first conductive portions of the conductive structure, the first through hole of each first conductive portion penetrates one or two third wiring layers.
  • the first connection channel in each first conducting portion, is located on a side of the first connection channel away from the substrate and is connected to the first
  • the first metal wiring or the second metal wiring directly connected to the channel is an integrated structure;
  • the diffusion barrier layer is disposed on the side and the bottom surface of the integrated structure, and the bottom surface is close to the substrate; wherein the diffusion barrier layer is located on the side and the bottom portion of the first connection channel , Located in the first through hole.
  • the fourth connection channel and the fourth metal wiring are an integrated structure; on this basis, the diffusion barrier layer may be further provided on the first The side and bottom surfaces of the integrated structure formed by the four connection channels and the fourth metal wiring, and the bottom surface is close to the substrate; wherein the diffusion barrier layer is located on the side and bottom surfaces of the fourth connection channel and is located in the fourth through hole.
  • the conducting structure further includes a third conducting portion, the fifth connection channel, the first metal wiring located on the side of the fifth connection channel away from the substrate, and the second metal wiring or the second metal connection is directly connected to the fifth connection channel.
  • the metal wiring is an integrated structure; the diffusion barrier layer may also be provided on the side and the bottom surface of the integrated structure composed of the fifth connection channel and one of the first metal wiring and the second metal wiring, and the bottom surface is close to the substrate; The layer is located on the side and bottom of the fifth connecting channel, and is located in the fifth through hole.
  • a dielectric layer disposed between adjacent wiring layers includes at least a first sublayer and a second sublayer, and the second sublayer is an etch stop layer, and On the side of the first sub-layer close to the substrate.
  • the material of the first sub-layer is a dielectric material with a low dielectric constant or an ultra-low dielectric constant.
  • the length directions of the first metal wiring and the second metal wiring are parallel.
  • a length direction of the fourth metal wiring is parallel to a length direction of the first metal wiring and the second metal wiring. Based on this, in the width direction of the first metal wiring and the second metal wiring, the size of the memory cell is reduced, thereby improving the integration density of the memory.
  • another memory including a memory area, where the memory area includes a plurality of memory cells disposed on a substrate; each memory cell includes a transistor disposed on the substrate and an MTJ memory electrically connected thereto.
  • MTJ memory element includes a bottom electrode, a top electrode, and an MTJ located therebetween, and the bottom electrode and the drain electrode of the transistor are electrically connected through a conductive structure; the memory area is provided with multiple wiring layers between the transistor and the MTJ memory element And a dielectric layer is filled between adjacent wiring layers, between the wiring layer closest to the transistor and the transistor; the conductive structure includes a first conductive portion; the first conductive portion includes a first metal wiring and a first conductive portion; Holes; the multilayer wiring layer includes a first wiring layer and a second wiring layer, the second wiring layer is disposed between the first wiring layer and the transistor; the first wiring layer includes a first metal wiring, and the first through hole penetrates the first The dielectric layer between the wiring layer and the transistor and the second wiring layer; a first connection channel is provided in the first through hole, and the first connection channel is directly connected to the first metal wiring and the drain electrode of the transistor A first connecting passage are not directly connected to the metal wiring on the second wiring layer.
  • the first via of the first conductive portion penetrates the second wiring layer between the first wiring layer and the transistor, and The first connection channel provided in the first via is directly connected to the first metal wiring and the drain electrode of the transistor. Therefore, the drain electrode of the first metal wiring and the transistor is positioned between the second metal wiring and the transistor and is provided at the second The metal wiring on the wiring layer is electrically connected. This application can release the space occupied by the metal wiring on the second wiring layer.
  • the space released by the second wiring layer can be used for circuit wiring, thereby reducing the congestion of the overall circuit wiring; on the other hand, because the second wiring layer is used to connect the drain electrode to the first metal After the metal wiring of the wiring is omitted, the area occupied by each memory cell can be reduced under the condition that the minimum spacing of the wiring is satisfied, so that the integration density of the memory can be improved; on the other hand, the resistance of the via mainly comes from the via and its The interface between the metals in contact below (close to the substrate). In this application, since the first via hole crosses the second wiring layer, there is no existence between the first via hole and the metal wiring on the second wiring layer. The interface has smaller resistance, and can reduce parasitic capacitance, which can improve the overall performance of the memory.
  • the transistor is used to control writing, changing, or reading of information in the storage unit.
  • the transistors in two adjacent memory cells share a drain electrode. This can further increase the integration density of the memory.
  • the first conductive portions are at least two, and all the first conductive portions are disposed along the thickness direction of the substrate; any adjacent first conductive portions are directly connected .
  • the conducting structure further includes a second conducting portion; the second conducting portion is disposed on a side of the first conducting portion away from the substrate; the second conducting portion Including a fourth metal wiring and a fourth through hole; the multilayer wiring layer further includes a fourth wiring layer, the fourth wiring layer includes a fourth metal wiring; the fourth through hole penetrates between the fourth wiring layer and the first conductive portion A dielectric layer; a fourth connection channel is provided in the fourth through hole, and the fourth connection channel is directly connected to the fourth metal wiring and the first metal wiring.
  • the second conducting portions there are at least two second conducting portions, and all the second conducting portions are disposed along the thickness direction of the substrate; among all the second conducting portions, the closest to the first conducting portion
  • the fourth connection channel in one of the second conducting portions of the portion is directly connected to the fourth metal wiring and the first metal wiring; among any adjacent second conducting portions, the fourth metal wiring belonging to the adjacent second conducting portion, respectively. It is directly connected to the fourth connection channel.
  • a length direction of the fourth metal wiring is parallel to a length direction of the first metal wiring. Based on this, the size of the memory cell is reduced in the width direction of the first metal wiring, thereby improving the integration density of the memory.
  • the first through hole penetrates one or two second wiring layers between the first wiring layer and the transistor.
  • each first conducting portion the first connection channel and the first metal wiring directly connected to the first connection channel are an integrated structure.
  • a diffusion barrier layer is disposed on the side and the bottom surface of the integrated structure, and the bottom surface is close to the substrate; wherein the diffusion barrier layer is located on the side and the bottom portion of the first connection channel and is located in the first through hole.
  • the fourth connection channel and the fourth metal wiring are an integrated structure; on this basis, a diffusion barrier layer may be further provided on the fourth connection channel and The side surface and the bottom surface of the integrated structure formed by the fourth metal wiring, the bottom surface is close to the substrate; wherein the diffusion barrier layer is located on the side and bottom surface of the fourth connection channel and is located in the fourth through hole.
  • the dielectric layer disposed between adjacent wiring layers includes at least a first sublayer and a second sublayer, the second sublayer is an etch barrier layer, and On the side of the first sub-layer close to the substrate.
  • the material of the first sub-layer is a material with a low dielectric constant or an ultra-low dielectric constant.
  • FIG. 1 is a schematic top view of a memory provided by the present application.
  • FIG. 2 is a schematic diagram of the connection between a transistor and an MTJ storage element in a memory cell
  • FIG. 3 is a schematic cross-sectional view of a storage unit in a memory provided by the present application.
  • FIG. 4 is a schematic cross-sectional view showing a connection between a drain electrode of a transistor and a bottom electrode of an MTJ memory element
  • FIG. 5 (a) is a schematic perspective view of the wiring of the first wiring layer, the second wiring layer, and the third wiring layer in one memory cell in FIG. 4;
  • FIG. 5 (a) is a schematic perspective view of the wiring of the first wiring layer, the second wiring layer, and the third wiring layer in one memory cell in FIG. 4;
  • FIG. 5 (b) is a schematic perspective view of the wiring of the first wiring layer, the second wiring layer, and the third wiring layer in one memory cell in FIG. 2;
  • Figure 6 shows the trend of the shortest length of the metal wire with the technical nodes
  • FIG. 7 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 8 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • FIG. 9 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 10 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 11 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • FIG. 12 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • FIG. 13 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 14 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • 15 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • 16 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • 17 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 18 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • 19 is a schematic sectional view of a storage unit in another memory provided by the present application.
  • 20 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • 21 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • 22 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • FIG. 23 is a schematic sectional view of a storage unit in another memory provided by the present application.
  • 24 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • 25 is a schematic sectional view of a storage unit in another memory provided by the present application.
  • 26 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 27 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • FIG. 28 is a schematic cross-sectional view of a storage unit in another memory provided by the present application.
  • 29 is a schematic sectional view of a storage unit in another memory provided by the present application.
  • FIG. 30 is a schematic cross-sectional view of another storage unit in a memory provided by the present application.
  • FIG. 31 is a schematic sectional view of a storage unit in another memory provided by the present application.
  • each storage unit 30 includes a storage unit The transistor 40 on the bottom 20 and a magnetic tunnel junction (MTJ) storage element 50 electrically connected thereto.
  • MTJ magnetic tunnel junction
  • the MTJ memory element 50 includes a bottom electrode 51, a top electrode 52, and an MTJ 53 located therebetween.
  • the bottom electrode 51 and the drain electrode 42 of the transistor 40 are electrically connected through a conductive structure 60;
  • a multilayer wiring layer is provided between 40 and the MTJ memory element 50, and a dielectric layer 70 is filled between adjacent wiring layers.
  • the conductive structure 60 includes a first conductive portion 61.
  • the first conductive portion 61 includes a first metal wiring 611, a second metal wiring 612, and is located between the first metal wiring 611 and the second metal wiring 612.
  • the first wiring hole 613; the multilayer wiring layer includes a first wiring layer 81, a second wiring layer 82, and a third wiring layer 83, and the third wiring layer 83 is disposed between the first wiring layer 81 and the second wiring layer 82
  • the first wiring layer 81 includes a first metal wiring 611
  • the second wiring layer 82 includes a second metal wiring 612
  • the first through hole 613 penetrates the dielectric layer 70 between the first wiring layer 81 and the second wiring layer 82
  • the third wiring layer 83; a first connection channel 614 is provided in the first through hole 613, the first connection channel 614 is directly connected to the first metal wiring 611 and the second metal wiring 612, and the first connection channel 614 is not connected to the third wiring
  • the memory area 10 is further provided with a word line 91 and a bit line 93.
  • the word line 92 is used to control the transistor 40 to be turned on or off
  • the bit line 93 is used to read and write data to the corresponding MTJ storage element 50 when the transistor 40 is turned on.
  • the gate electrode 44 of the transistor 40 in each memory cell 30 is electrically connected to the word line 91
  • the source electrode 41 is electrically connected to the source line 92
  • the top electrode 52 of the MTJ memory element 50 is electrically connected to the bit line 93.
  • the storage unit 30 in addition to the storage unit 30, it also includes peripheral circuits, such as a sense amplifier circuit, a read / write circuit, and the like.
  • the circuit wiring may be located in a peripheral area of the storage area 10, and the wiring of the peripheral circuits (including the above-mentioned word line 91, source line 92, bit line 93, etc.) is also provided in the storage area 10.
  • the circuit wiring of the peripheral circuit is distributed in each wiring layer.
  • all metal wirings on the same plane (which is parallel or substantially parallel to the upper surface of the substrate 20) of the dielectric layer 70 in the memory region 10 except the transistor 40 and the MTJ memory element 50 are referred to as One wiring layer; for metal wirings forming the same wiring layer, there is a gap between different metal wirings, and the gap is filled with a dielectric material.
  • the dielectric layer 70 covers the storage area 10.
  • the first through hole 613 penetrates the third wiring layer 83, but the first connection channel 614 provided in the first through hole 613 is not directly connected to the metal wiring on the third wiring layer 83. That is, the third wiring layer 83 can be provided with no metal wiring at a position corresponding to the first through hole 613 to satisfy this condition.
  • Direct connection refers to physical direct contact without passing through other structures.
  • the first through hole 613 penetrates the dielectric layer 70 and the third wiring layer 83 between the first wiring layer 81 and the second wiring layer 82, and the first connection channels 614 and The first metal wiring 611 and the second metal wiring 612 are directly connected. Therefore, it can be seen that both ends of the first through hole 613 are directly connected to the first metal wiring 611 and the second metal wiring 612, respectively.
  • the conductive structure 60 for connecting the bottom electrode 51 and the transistor drain electrode 42 of the MTJ memory element has the same structure in each memory cell 30.
  • the transistor 40 includes a source electrode 41, a gate dielectric layer 43, and a gate electrode 44 in addition to the drain electrode 42.
  • a source electrode 41 In order to distinguish the two electrodes of the transistor 40 other than the gate electrode 44, one of the electrodes is referred to as a source electrode 41 and the other electrode is referred to as a drain electrode 42. Therefore, the source electrode 41 and the drain electrode 42 in this application are only used to distinguish each other. It does not mean that when the transistor 40 is actually connected to the circuit, the drain electrode 42 can only be connected to other components of the circuit as the drain of the transistor 40 in the circuit.
  • the transistor 40 may further include a source region 45 and a drain region 46.
  • the source region 45 is in contact with the source electrode 41
  • the drain region 46 is in contact with the drain electrode 42
  • the source region 45 and the drain are in contact.
  • the region between the pole regions 46 is a channel region.
  • the source region 45 and the drain region 46 may be obtained by performing a doping process on the substrate 20.
  • the material of the substrate 20 is a semiconductor material, such as silicon.
  • the transistor 40 is used to control writing, changing, or reading of information in the storage unit 30. That is, the transistor 40, as a selection device, can control writing, changing, or reading of information in the memory cell 30.
  • a dielectric material is also filled between the transistor 40 and a wiring layer closest to the transistor 40 (for example, the first wiring layer 81 shown in FIG. 3).
  • the MTJ memory element 50 is usually integrated in an intermediate or subsequent process, and the memory region 10 is provided with a multilayer wiring layer between the transistor 40 and the MTJ memory element 50 (the multilayer wiring layer is disposed along the thickness direction of the substrate 20).
  • a first wiring layer 81, a second wiring layer 82, and a third wiring layer 83 are provided between the transistor 40 and the MTJ memory element 50, and the first wiring layer 81 is close to the substrate 20 and the third wiring layer.
  • 83 is provided between the first wiring layer 81 and the second wiring layer 82 as an example. As shown in FIG.
  • the drain electrode 42 of the transistor 40 and the bottom electrode 51 of the MTJ memory element 50 can be electrically connected in the following manner: the second metal wiring 612 in the second wiring layer 82 and the MTJ memory The bottom electrode of the element 50 is directly connected, and the second metal wiring 612 in the second wiring layer 82 and the third metal wiring 831 in the third wiring layer 83 pass through the second wiring layer 82 and the third wiring layer 83.
  • the through hole of the dielectric layer 70 and the connection channel provided in the through hole are directly connected; the third metal wiring 831 in the third wiring layer 83 and the first metal wiring 611 in the first wiring layer 81 are passed through The through hole of the dielectric layer 70 between the third wiring layer 83 and the first wiring layer 81 and the connection channel provided in the through hole are directly connected; the first metal wiring 611 in the first wiring layer 81 is connected to the transistor 40
  • the drain electrode 42 is directly connected through a through hole penetrating the dielectric layer 70 between the first wiring layer 81 and the transistor 40 and a connection channel provided in the through hole, thereby realizing the drain electrode 42 of the transistor 40 and the MTJ memory element 50.
  • the bottom electrode 51 is electrically connected.
  • FIG. 4 the drain electrode 42 of the transistor 40 and the bottom of the MTJ memory element 50 are used.
  • the second metal wiring 612, the third metal wiring 831, and the first metal wiring 611 which are electrically connected to the electrode 51 may be provided as shown in FIG. 5 (a), and the metal wiring of each layer is wired in a one-dimensional manner.
  • the metal wiring size in the wiring layer needs to meet the requirements of the minimum area (planar area).
  • the requirement for the minimum area of metal wiring can be translated into the requirement for the shortest length L of the metal wiring when the metal wiring width is the minimum line width (as shown in Figure 5 (a)), and there is also a shortest distance d between the ends of the metal wiring. Requirements (as shown in Figure 5 (a)). Based on this, based on the electrical connection between the transistor drain electrode 42 and the bottom electrode 51 of the MTJ memory element in FIG. 4, the minimum length of the metal wiring and the minimum distance between adjacent metal wiring ends on the same wiring layer limit the integration of the memory. .
  • the requirement for the minimum area of metal wires continues to deteriorate with the development of technology nodes.
  • the minimum length of metal wiring has been increased from 3.6 times to 6 times the minimum metal line width. That is, with the development of technology nodes, the shortest length of metal wiring is gradually increasing. Therefore, the requirement of the shortest length of metal wiring is gradually becoming a bottleneck that hinders the further improvement of memory integration density.
  • the first through hole 613 penetrates the third wiring layer 83, that is, the third wiring layer 83 is not provided with a metal wiring at a position corresponding to the first through hole 613, so Compared with FIG. 5 (a) and FIG. 5 (b), the first through hole 613 is disposed in FIG. 5 (b), and the first metal wiring 611 and the second metal line 612 in FIG. 5 (a) can be omitted.
  • the third metal wiring 831 is provided between and in the third wiring layer 83. The omission of the third metal wiring 831 disposed on the third wiring layer 83 between the first metal wiring 611 and the second metal line 612 can release the corresponding space occupied by the shortest length of the metal wiring.
  • the first through hole 613 of the first conductive portion 61 penetrates through A third wiring layer 83 between the first wiring layer 81 and the second wiring layer 82, and the first connection channel 614 provided in the first through hole 613 is directly connected to the first metal wiring 611 and the second metal wiring 612 Therefore, with respect to the first metal wiring 611 and the second metal wiring 612 in FIG. 4 being electrically connected through the third metal wiring 831 located between the first metal wiring 611 and the second metal wiring 831, the first The three metal wirings 831 can release the space occupied by the third metal wirings 831.
  • the space released by the third metal wiring 831 can be used for circuit wiring, thereby reducing the congestion of the overall circuit wiring; on the other hand, after the third metal wiring 831 is omitted, the minimum wiring is satisfied.
  • the area occupied by each memory cell 30 can be reduced, so the integration density of the memory can be improved; on the other hand, the resistance of the via mainly comes from the metal wiring that the via is in contact with (under the substrate 20).
  • the interface between the first through hole 613 and the third wiring layer 83 in the present application so there is no interface between the first through hole 613 and the metal wiring on the third wiring layer 83, which has a smaller size. Resistance, and can reduce parasitic capacitance, which can improve the overall performance of the memory.
  • the length direction of the first metal wiring 611 and the second metal wiring 612 are parallel. Based on this, in the width direction of the first metal wiring 611 and the second metal wiring 612, the size of the memory cell 30 is reduced, thereby further improving the integration density of the memory.
  • the source electrode 41 and the drain electrode 42 of the transistor 40 are symmetrical, there is no difference between the source electrode 41 and the drain electrode 42. Therefore, as shown in FIG.
  • the transistor 40 shares a drain electrode 42. This can further increase the integration density of the memory.
  • the storage area 10 is provided with a second through hole 615, the second through hole 615 penetrates the third wiring layer 83; the first through hole 613 is adjacent to the second through hole 615, and the third wiring There is no metal wiring on the portion of the layer 83 between the first through hole 613 and the second through hole 615.
  • first through hole 613 and the second through hole 615 are adjacent, that is, no other through hole is interposed between the first through hole 613 and the second through hole 615.
  • the role of the second through hole 615 is not limited, and can be used to connect circuit wirings located on different wiring layers.
  • the cross-sectional view shown in FIG. 8 is a cross-sectional view taken from another direction of the storage area 10.
  • the connection of the second through hole 615 with the metal wirings in the second wiring layer 82 and the first wiring layer 81 in FIG. 8 is merely schematic.
  • the third wiring layer 83 is not provided with metal wiring at the corresponding positions of the first through hole 613 and the second through hole 615, and there is no metal of the third wiring layer 83 between the first through hole 613 and the second through hole 615.
  • the first through-holes 613 and the second through-holes 615 only need to meet the requirements of the pitch of the through-holes during the setting, so that the integration density of the memory can be made higher.
  • the storage area 10 is provided with a third through hole 616.
  • One end of the third through hole 616 starts from the third wiring layer 83.
  • the third connection channel 617 in the third through hole 616 and The metal wiring on the third wiring layer 83 is connected, and the third through hole 616 and the first through hole 613 are adjacent.
  • the third through hole 616 is adjacent to the first through hole 613, that is, no other through hole is interposed between the third through hole 616 and the first through hole 613.
  • the role of the third through hole 616 is not limited, and can be used to connect circuit wirings located on different wiring layers.
  • the cross-sectional view shown in FIG. 9 is a cross-sectional view taken from another direction of the storage area 10.
  • the connection of the third through hole 616 to the metal wiring on the first wiring layer 81 in FIG. 9 is merely schematic.
  • the third metal wiring 831 is omitted in the solution of the present application, and accordingly, the corresponding released space can be used as a circuit wiring.
  • first conducting portions 61 there are at least two first conducting portions 61, and all the first conducting portions 61 are disposed along the thickness direction of the substrate 20.
  • two adjacent first conducting portions 61 may be connected through a sixth through hole 641 and a sixth connection channel 642 located in the sixth through hole 641; As shown in Figure 11, direct connection.
  • the integration density of the memory can be improved by providing at least two first conducting portions 61 in the conducting structure 60. .
  • any two adjacent first conducting portions 61 share the second metal wiring 612 or the first metal wiring 611.
  • two first conducting portions 61 are illustrated. Taking this as an example, if the multilayer wiring layer of the memory region 10 is provided between the transistor 40 and the MTJ memory element 50, starting from the closest to the substrate 20, it is the first wiring layer 81, the third wiring layer 83, and the second For the wiring layer 82, the third wiring layer 83, and the first wiring layer 81, the two first conductive portions 61 share the second metal wiring 612.
  • the multilayer wiring layer of the memory area 10 is provided between the transistor 40 and the MTJ memory element 50, starting from the substrate 20, the second wiring layer 82, the third wiring layer 83, and the first For the wiring layer 81, the third wiring layer 83, and the second wiring layer 82, the two first conductive portions 61 share the first metal wiring 611.
  • first conductive portion 61 located in the middle When there are three first conductive portions 61 and the first conductive portion 61 located in the middle is adjacent to the first conductive portions 61 on both sides thereof in the direction of the vertical substrate 20, the first conductive portion 61 located in the middle The portion 61 shares the second metal wiring 612 with the first conductive portion 61 on one side thereof, and the first conductive portion 61 located in the middle shares the first metal wiring 611 with the first conductive portion 61 on the other side thereof.
  • the conducting structure 60 further includes a second conducting portion 62, and the second conducting portion 62 is disposed between the first conducting portion 61 and the MTJ storage element 50; the second conducting portion 62 includes a fourth metal wiring 621 and a fourth through hole 622; the multilayer wiring layer further includes a fourth wiring layer 84, and the fourth wiring layer 84 includes a fourth metal wiring 621; the fourth through hole 622 penetrates the fourth wiring layer 84 A dielectric layer 70 between the first conductive portion 61 and the fourth through hole 622; a fourth connection channel 623 is provided in the fourth through hole 622; the fourth connection channel 623 is adjacent to the fourth metal wiring 621, the first metal wiring 621 adjacent to the first The metal wiring 611 or the second metal wiring 612 is directly connected.
  • the length direction of the fourth metal wiring 621 may be parallel to the length direction of the first metal wiring 611 and the second metal wiring 612.
  • the fourth wiring layer 84 is disposed adjacent to the second wiring layer 82 as an example.
  • the fourth connection channel 623 is directly connected to the fourth metal wiring 621 and the second metal wiring 612.
  • the fourth wiring layer 84 is adjacent to the second wiring layer 82, that is, there is no other wiring layer between the fourth wiring layer 84 and the second wiring layer 82.
  • the fourth wiring layer 84 is disposed adjacent to the first wiring layer 81, the fourth connection channel 623 is directly connected to the fourth metal wiring 621 and the first metal wiring 611.
  • the fourth wiring layer 84 is adjacent to the first wiring layer 81, that is, there is no other wiring layer between the fourth wiring layer 84 and the first wiring layer 81.
  • first conducting portions 61 regardless of the number of the first conducting portions 61, all the first conducting portions 61 should be considered as a whole, and the second conducting portions 62 are provided between the first conducting portions 61 and MTJ storage element 50. That is, when there are a plurality of first conductive portions 61, the second conductive portion 62 is disposed between the first conductive portion 61 and the MTJ storage element 50 closest to the MTJ storage element 50.
  • the conducting structure 60 further includes a third conducting portion 63, and the third conducting portion 63 is disposed between the first conducting portion 61 and the transistor 40; the third conducting portion
  • the portion 63 includes a fifth through hole 631, and the fifth through hole 631 penetrates the dielectric layer 70 between the first conductive portion 61 and the transistor drain electrode 42; a fifth connection channel 632 is provided in the fifth through hole 631;
  • the connection channel 632 is directly connected to the first metal wiring 611 or the second metal wiring 612 adjacent to the drain electrode 42 of the transistor 40 and the drain electrode 42 of the transistor 40.
  • the first wiring layer 81 is closer to the transistor 40 as an example.
  • the fifth connection channel 632 is directly connected to the drain electrode 42 of the transistor 40 and the first metal wiring 611.
  • the fifth connection channel 632 is directly connected to the drain electrode 42 of the transistor 40 and the second metal wiring 612.
  • the third conducting portion 63 is provided between the first conducting portions 61 and Between the transistors 40. That is, when there are a plurality of first conductive portions 61, the third conductive portion 63 is provided between the first conductive portion 61 closest to the substrate 20 and the transistor 40.
  • the first through hole 613 penetrates one or two third wiring layers 83 between the first wiring layer 81 and the second wiring layer 82.
  • the first through holes 613 of each first conducting portion 61 penetrate one or two third wiring layers 83.
  • the first through hole 613 of one of the first conducting portions 61 can penetrate a third wiring layer 83 and the other first conducting portion
  • the first through-holes 613 of 61 may penetrate two third wiring layers 83 (as shown in FIG. 13); or, the first through-holes 613 of the two first conductive portions 61 both penetrate one third wiring layer 83 ( (As shown in FIG. 11); or, the first through holes 613 of the two first conducting portions 61 both penetrate through the two third wiring layers 8.
  • the first connection channel 614 is located on the side of the first connection channel 614 away from the substrate 20 and is directly connected to the first connection channel 614.
  • the first metal wiring 611 or the second metal wiring 612 is an integrated structure; on this basis, the diffusion barrier layer 65 is disposed on the side and the bottom surface of the integrated structure, and the bottom surface is close to the substrate 20; wherein the diffusion barrier layer 65 is located at the first The portion connecting the side surface and the bottom surface of the channel 614 is located in the first through hole 613.
  • a first conducting portion 61 is provided as an example for illustration. Since the second metal wiring 612 is located on the side of the first connection channel 614 away from the substrate 20 in the first conducting portion 61, the first connection channel 614 and the second metal wiring 612 directly connected to the first connection channel 614 are an integrated structure. On this basis, the diffusion barrier layer 65 is provided on the side and bottom surfaces of the first connection channel 614 and the second metal wiring 612 of the integrated structure, and the diffusion barrier layer 65 is located on the side and the bottom surface of the first connection channel 614 and is located on the first Through hole 613.
  • two first conducting portions 61 are provided as an example for illustration.
  • the first conductive portion 61 closer to the substrate 20 since the second metal wiring 612 is located on the side of the first connection channel 614 away from the substrate 20, in the first conductive portion 61, the first conductive portion 61 A connection channel 614 and a second metal wiring 612 directly connected to the connection channel 614 are an integrated structure.
  • the diffusion barrier layer 65 is disposed on the side and bottom surfaces of the first connection channel 614 and the second metal wiring 612 of the integrated structure, and the diffusion barrier layer 65 is located on the side and bottom surfaces of the first connection channel 614 and is located in the first through hole 613. .
  • the first metal wiring 611 is located on the side of the first connecting channel 614 away from the substrate 20, in the first conducting portion 61, the first connecting channel 614 and The first metal wiring 611 directly connected thereto is an integrated structure.
  • the diffusion barrier layer 65 is disposed on the side and the bottom surface of the first connection channel 614 and the first metal wiring 611 of the integrated structure, and the diffusion barrier layer 65 is located on the side and the bottom surface of the first connection channel 614 in the first through hole 613. .
  • the "integrated structure” means that the two parts constituting the integrated structure are the same and formed at the same time. Specifically, when the first connection channel 614 and the first metal wiring 611 located on the side of the first connection channel 614 away from the substrate 20 and directly connected to the first connection channel 614 are an integrated structure, the first connection channel 614 and A first metal wiring 611 that is remote from the substrate 20 and is directly connected to the first connection channel 614 is formed at the same time. When the first connection channel 614 and the second metal wiring 612 located on the side of the first connection channel 614 away from the substrate 20 and directly connected to the first connection channel 614 are an integrated structure, the first connection channel 614 and the first connection channel 614 are located in the first connection channel. A second metal wiring 612 that is remote from the substrate 20 and directly connected to the first connection channel 614 is simultaneously formed.
  • the diffusion barrier layer 65 Since some interconnected metal materials, such as copper (Cu), are easily diffused, which results in degradation or failure of the circuit performance, it is necessary to prevent the diffusion by providing a diffusion barrier layer 65. Among them, for different interconnecting metal materials, different materials of the diffusion barrier layer 65 need to be used in combination to ensure the blocking effect of the diffusion barrier layer 65, the adhesion with the integrated structure, and the dielectric layer 90.
  • Cu copper
  • a double layer structure of tantalum nitride (TaN) / tantalum (Ta) may be used as the diffusion barrier layer 65, or a double layer structure of TaN / cobalt (Co) may also be used as Diffusion barrier layer 65.
  • interconnect metal material used in the memory of the present application may also be Co, ruthenium (Ru), tungsten (W), and the like, and whether to provide the diffusion barrier layer 65 may be selected according to the diffusivity of these materials.
  • the conducting structure 60 further includes a second conducting portion 62, as shown in FIG. 17, the fourth connection channel 623 and the fourth metal wiring 621 are an integrated structure; on this basis, the diffusion barrier The layer 65 may also be disposed on the side and bottom surfaces of the integrated structure composed of the fourth connection channel 623 and the fourth metal wiring 621, and the bottom surface is close to the substrate 20; wherein the diffusion barrier layer 65 is located on the side and bottom portions of the fourth connection channel 623 Is located in the fourth through hole 622.
  • the fifth connection channel 632 and the fifth connection channel 632 are located away from the substrate 20 and are connected to the fifth
  • the first metal wiring 611 or the second metal wiring 612 directly connected to the channel 632 is an integrated structure; the diffusion barrier layer 65 may also be disposed on one of the first metal wiring 611 and the second metal wiring 612 by the fifth connection channel 632.
  • the side surface and the bottom surface of the integrated structure are formed, and the bottom surface is close to the substrate 20.
  • the diffusion barrier layer 65 is located on the side surface and the bottom surface of the fifth connection channel 632 in the fifth through hole 631.
  • FIG. 18 illustrates the fifth connection channel 632 and the first metal wiring 611 as an integrated structure.
  • the diffusion barrier layer 65 is provided at the position of the conductive structure 60.
  • a corresponding diffusion barrier layer 65 can also be provided according to the interconnect metal material used. It will not be repeated in this application.
  • FIG. 14 it can be seen in this cross-sectional view that the third wiring layer 83 has circuit wiring. Therefore, as shown in FIG. 19, the circuit wiring side and bottom surfaces of the third wiring layer 83 can also be used.
  • a diffusion barrier layer 65 is provided.
  • the dielectric layer 70 disposed between adjacent wiring layers includes at least a first sublayer 71 and a second sublayer 72, and the second sublayer 72 is an etch barrier layer. It is disposed on a side of the first sub-layer 71 near the substrate 20.
  • the second sub-layer 72 is disposed on a side of the first sub-layer 71 near the substrate 20, that is, the second sub-layer 72 is formed first, and then the first sub-layer 71 is formed.
  • the dielectric layer 70 include a first sub-layer 71 and a second sub-layer 72
  • the second sub-layer 72 is an etch stop layer, and is disposed on a side of the first sub-layer 71 close to the substrate 20, it is possible to avoid forming the When the wiring layer is above the dielectric layer 70 (that is, away from the substrate 20), the wiring layer that has been formed is affected.
  • the material of the first sub-layer 71 is a material with a low dielectric constant or an ultra-low dielectric constant.
  • the low-dielectric constant and ultra-low-dielectric constant media refer to a dielectric material whose value of the dielectric constant is smaller than that of silicon dioxide (dielectric constant of 3.9 to 4).
  • the parasitic capacitance between adjacent wiring layers can be reduced.
  • This application also provides a memory, as shown in FIG. 1, including a storage area 10, and the storage area 10 includes a plurality of storage units 30 disposed on a substrate 20. As shown in FIG. 2, each storage unit 30 includes settings. A transistor 40 on the substrate 20 and an MTJ memory element 50 electrically connected thereto.
  • the MTJ memory element 50 includes a bottom electrode 51, a top electrode 52, and an MTJ 53 located therebetween.
  • the bottom electrode 51 and the drain electrode 42 of the transistor 40 are electrically connected through a conductive structure 60; the memory area 10 is in the transistor
  • a multilayer wiring layer is provided between 40 and the MTJ storage element 50, and a dielectric layer 70 is filled between adjacent wiring layers and between the wiring layer closest to the transistor 40 and the transistor 40.
  • the conductive structure 60 includes a first conductive portion 61; the first conductive portion 61 includes a first metal wiring 611 and a first through hole 613; the multilayer wiring layer includes a first wiring layer 81 and a second wiring Layer 82, the second wiring layer 82 is disposed between the first wiring layer 81 and the transistor 40; the first wiring layer 81 includes a first metal wiring 611, and the first through hole 613 penetrates between the first wiring layer 81 and the transistor 40 Dielectric layer 70 and second wiring layer 82; a first connection channel 614 is provided in the first through hole 613, and the first connection channel 614 is directly connected to the first metal wiring 611 and the drain electrode 42 of the transistor 40, and the first connection channel 614 is not directly connected to the metal wiring on the second wiring layer 82.
  • the first through hole 613 penetrates the second wiring layer 82, but the first connection channel 614 provided in the first through hole 613 is not connected to the second wiring layer 82.
  • the metal wiring is directly connected, that is, the second wiring layer 82 can be provided with no metal wiring at a position corresponding to the first through hole 613 to satisfy this condition.
  • the transistor 40 includes a source electrode 41, a gate dielectric layer 43, and a gate electrode 44 in addition to the drain electrode 42.
  • a source electrode 41 a gate dielectric layer 43
  • a gate electrode 44 in addition to the drain electrode 42.
  • one of the electrodes is referred to as a source electrode 41, and the other electrode is referred to as a drain electrode 42.
  • the transistor 40 may further include a source region 45 and a drain region 46.
  • the source region 45 is in contact with the source electrode 41
  • the drain region 46 is in contact with the drain electrode 42
  • the source region 45 and the drain are in contact.
  • the region between the pole regions 46 is a channel region.
  • the source region 45 and the drain region 46 can be obtained by performing a doping process on the substrate 20.
  • the material of the substrate 20 is a semiconductor material.
  • the transistor 40 controls writing, changing, or reading of information in the storage unit 30. That is, the transistor 40, as a selection device, can control writing, changing, or reading of information in the memory cell 30.
  • the first through hole 613 of the first conductive portion 61 penetrates the first wiring layer 81.
  • the second wiring layer 82 between the transistor 40 and the transistor 40 allows the first connection channel 614 provided in the first through hole 613 to be directly connected to the first metal wiring 611 and the drain electrode 42 of the transistor 40.
  • the metal wiring 611 and the drain electrode 42 of the transistor 40 are electrically connected through the metal wiring disposed between the metal wiring 611 and the second wiring layer 82. This application can release the space occupied by the metal wiring on the second wiring layer 82.
  • the space released by the second wiring layer 82 can be used for circuit wiring, thereby reducing the congestion of the overall circuit wiring; on the other hand, since the second wiring layer 82 is used to connect the drain electrode 42 and After the metal wiring of the first metal wiring 611 is omitted, the area occupied by each memory cell 30 can be reduced under the condition that the minimum wiring pitch is met, so the integration density of the memory can be improved; on the other hand, the resistance of the via hole It mainly comes from the interface between the via and the metal below (close to the substrate 20).
  • the first via 613 crosses the second wiring layer 82 in this application, the first via 613 and the first The interface between the metal wirings on the two wiring layers 82 has a smaller resistance, and can reduce parasitic capacitance, thereby improving the overall performance of the memory.
  • the source electrode 41 and the drain electrode 42 of the transistor 40 are symmetrical, there is no difference between the source electrode 41 and the drain electrode 42. Therefore, as shown in FIG.
  • the transistor 40 shares a drain electrode 42. This can further increase the integration density of the memory.
  • first conductive portions 61 there are at least two first conductive portions 61, and all the first conductive portions 61 are disposed along the thickness direction of the substrate 20; any adjacent first conductive portions 61 are directly connected .
  • the integration density of the memory can be improved by providing at least two first conducting portions 61 in the conducting structure 60. .
  • the conducting structure 60 further includes a second conducting portion 62; the second conducting portion 62 is disposed on a side of the first conducting portion 61 away from the substrate 20; the second conducting portion 62 includes a fourth metal wiring 621 and a fourth through hole 622; the multilayer wiring layer further includes a fourth wiring layer 84, and the fourth wiring layer 84 includes a fourth metal wiring 621; the fourth through hole 622 penetrates the fourth wiring layer 84 A dielectric layer 70 between the first conductive portion 61 and the fourth conductive portion 61; a fourth connection channel 623 is provided in the fourth through hole 622, and the fourth connection channel 623 is directly connected to the fourth metal wiring 621 and the first metal wiring 611.
  • the length direction of the fourth metal wiring 621 may be parallel to the length direction of the first metal wiring 611.
  • the fourth through hole 622 penetrates the dielectric layer 70 between the fourth wiring layer 84 and the first conductive portion 61, and the fourth connection channel 623 is directly connected to the fourth metal wiring 621 and the first metal wiring 611.
  • the fourth wiring layer 84 is disposed adjacent to the first wiring layer 81 in the direction of the substrate 20, and the fourth wiring layer 84 is disposed on the side of the first wiring layer 81 away from the substrate 20.
  • the fourth wiring layer 84 is disposed adjacent to the first wiring layer 81, that is, no other wiring layer is provided between the fourth wiring layer 84 and the first wiring layer 81.
  • first conductive portions 61 regardless of the number of the first conductive portions 61, all the first conductive portions 61 should be considered as a whole, and the second conductive portions 62 are provided between the first conductive portions 61 and the MTJ storage element. Between 50. That is, when there are a plurality of first conductive portions 61, the second conductive portion 62 is disposed between the first conductive portion 61 and the MTJ storage element 50 closest to the MTJ storage element 50.
  • the second conducting portions 62 there are at least two second conducting portions 62, and all the second conducting portions 62 are disposed along the thickness direction of the substrate 20. Among all the second conducting portions 62, the most The fourth connection channel 623 in one of the second conducting portions 62 near the first conducting portion 61 is directly connected to the fourth metal wiring 621 and the first metal wiring 611. Any adjacent second conducting portions 62 belong to the phase. The fourth metal wiring 621 and the fourth connection channel 623 adjacent to the second conducting portion 62 are directly connected.
  • two second conducting portions 62 are provided in the conducting structure 60 as an example for illustration.
  • the first through hole 613 penetrates one layer of the second wiring layer 82 (shown in FIG. 23) or two layers of the second wiring layer 82 (shown in FIG. 27) between the first wiring layer 81 and the transistor 40. ).
  • the first connection channel 614 and the first metal wiring 611 directly connected to the first connection channel 614 are an integrated structure; on this basis, diffusion
  • the barrier layer 65 is disposed on the side and the bottom surface of the integrated structure, and the bottom surface is close to the substrate 20.
  • the diffusion barrier layer 65 is located on the side and the bottom portion of the first connection channel 614 and is located in the first through hole 613.
  • diffusion barrier layer 65 Since some interconnected metal materials (such as Cu) are easily diffused, resulting in degradation or failure of the circuit performance, it is necessary to prevent the diffusion by providing a diffusion barrier layer 65. Among them, for different metal conductive materials, different materials of the diffusion barrier layer 65 need to be used in combination to ensure the barrier effect of the diffusion barrier layer 65, the adhesion with the integrated structure, and the dielectric layer 90.
  • a TaN / Ta double-layer structure may be used as the diffusion barrier layer 65, or a TaN / Co double-layer structure may be used as the diffusion barrier layer 65.
  • interconnect metal material used in the memory of the present application may also be Co, Ru, W, and the like, and whether to provide a diffusion barrier layer 65 may be selected according to the diffusivity of these materials.
  • the conducting structure 60 further includes a second conducting portion 62, as shown in FIG. 29, the fourth connection channel 623 and the fourth metal wiring 621 are an integrated structure; on this basis, the diffusion barrier The layer 65 may also be disposed on the side and bottom surfaces of the integrated structure composed of the fourth connection channel 623 and the fourth metal wiring 621, and the bottom surface is close to the substrate 20; wherein the diffusion barrier layer 65 is located on the side and bottom portions of the fourth connection channel 623 Is located in the fourth through hole 622.
  • the diffusion barrier layer 65 is disposed at the position of the conductive structure 60.
  • a corresponding diffusion barrier layer 65 can also be provided according to the interconnect metal material used. In this application, Will not repeat them in detail.
  • FIG. 28 it can be seen in this cross-sectional view that the first wiring layer 81 also has circuit wiring. Therefore, as shown in FIG. 30, the circuit wiring side and bottom surfaces of the third wiring layer 83 can be provided.
  • a diffusion barrier layer 65 is provided.
  • the dielectric layer 70 disposed between adjacent wiring layers includes at least a first sublayer 71 and a second sublayer 72, and the second sublayer 72 is an etch barrier layer and is disposed on The first sub-layer 71 is close to one side of the substrate 20.
  • the dielectric layer 70 include a first sub-layer 71 and a second sub-layer 72
  • the second sub-layer 72 is an etch stop layer, and is disposed on a side of the first sub-layer 71 close to the substrate 20, it is possible to avoid forming the When the wiring layer is above the dielectric layer 70 (that is, away from the substrate 20), the wiring layer that has been formed is affected.
  • the material of the first sub-layer 71 is a material with a low dielectric constant or an ultra-low dielectric constant.
  • the parasitic capacitance between adjacent wiring layers can be reduced.

Abstract

本申请提供一种存储器，涉及半导体技术领域，可提升存储器的集成密度。一种存储器，存储区中每个存储单元包括晶体管和MTJ存储元件；MTJ存储元件的底电极与晶体管的漏电极通过导通结构电连接；存储区在晶体管和MTJ存储元件之间设置有多层布线层，相邻的布线层之间填充有介质层；导通结构包括第一导通部，第一导通部包括第一金属布线、第二金属布线以及第一通孔；多层布线层包括第一布线层，第二布线层和第三布线层；第一通孔贯穿处于第一布线层和第二布线层之间的介质层以及第三布线层；第一通孔中设置有第一连接通道，第一连接通道与第一布线层上的第一金属布线和第而布线层上的第二金属布线直接连接，第一连接通道不与第三布线层上的金属布线直接连接。

Description

存储器 技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器。
背景技术
自旋转移力矩磁阻随机访问存储器(Spin Transfer Torque-Magnetic Random Access Memory，STT-MRAM)为具有非易失性、工作速度快、擦写次数无限次等优势的新型存储器。相较于静态随机访问存储器(Static Random Access Memory，SRAM)，STT-MRAM除具有SRAM的高性能外，在静态功耗方面和面积方面都有着巨大的优势。而随着半导体工艺的进步，STT-MRAM面临着越来越高的集成度需求，以及高集成度带来的各种电性问题。
发明内容
本申请提供一种存储器，可提升存储器的集成密度。
为达到上述目的，本申请采用如下技术方案：
本申请的第一方面，提供一种存储器，包括存储区，存储区包括设置于衬底上的若干存储单元；每个存储单元均包括设置于衬底上的晶体管和与其电连接的MTJ存储元件；MTJ存储元件包括底电极、顶电极和位于二者之间的MTJ，底电极与晶体管的漏电极通过导通结构电连接；存储区在晶体管和MTJ存储元件之间设置有多层布线层，且相邻的布线层之间填充有介质层；导通结构包括第一导通部，第一导通部包括第一金属布线、第二金属布线以及位于第一金属布线和第二金属布线之间的第一通孔；多层布线层包括第一布线层，第二布线层和第三布线层，第三布线层设置于第一布线层和第二布线层之间；第一布线层包括第一金属布线，第二布线层包括第二金属布线，第一通孔贯穿处于第一布线层和第二布线层之间的介质层以及第三布线层；第一通孔中设置有第一连接通道，第一连接通道与第一金属布线和第二金属布线直接连接，第一连接通道不与第三布线层上的金属布线直接连接。
由于用于使晶体管的漏电极与MTJ存储元件的底电极电连接的导通结构中，第一导通部的第一通孔贯穿处于第一布线层和第二布线层之间的第三布线层，而使设置于第一通孔中的第一连接通道与第一金属布线和第二金属布线直接连接，因而，相对于第一金属布线与第二金属布线通过位于二者之间且设置于第三布线层上第三金属布线电连接，本申请省去了第三金属布线，从而可释放出第三金属布线所占用的空间。基于此，一方面，可将第三金属布线释放出来的空间，用于电路布线，从而缓解整体电路布线的拥挤度；另一方面，由于第三金属布线省去后，在满足布线最小间距的情况下，可降低每个存储单元所占用的面积，因此，可提升存储器的集成密度；再一方面，通孔的电阻主要来自通孔与其下方(靠近衬底)接触的金属布线之间的界面，本申请中由于第一通孔跨过了第三布线层，因而也就不存在第一通孔与第三布线层上金属布线之间的界面，具有更小的电阻，而且可减小寄生电容，进而可提升存储器的整体性能。
结合第一方面，在一种可能的实现方式中，晶体管用于控制对存储单元中信息的写入、更改或读取。
结合第一方面，在另一种可能的实现方式中，存储区设置有第二通孔，第二通孔贯穿第三布线层；第一通孔和第二通孔相邻，第三布线层的处于第一通孔和第二通孔之间的部分上没有金属布线。
结合第一方面，在另一种可能的实现方式中，存储区设置有第三通孔，第三通孔的一端起始于第三布线层，第三通孔中的第三连接通道与第三布线层上的金属布线连接，第三通孔和第一通孔相邻。
结合第一方面，在另一种可能的实现方式中，相邻两个存储单元中的晶体管共用漏电极。从而可进一步提升存储器的集成密度。
结合第一方面，在另一种可能的实现方式中，第一导通部为至少两个，且所有第一导通部沿衬底的厚度方向设置。
在此基础上，可选的，任意相邻的两个第一导通部共用第二金属布线或第一金属布线。
结合第一方面，在另一种可能的实现方式中，导通结构还包括第二导通部，第二导通部设置于第一导通部与MTJ存储元件之间；第二导通部包括第四金属布线和第四通孔；多层布线层还包括第四布线层，第四布线层包括第四金属布线；第四通孔贯穿处于第四布线层和第一导通部之间的介质层；第四通孔中设置有第四连接通道，第四连接通道与第四金属布线、第四金属布线相邻的第一金属布线或第二金属布线直接连接。
结合第一方面，在另一种可能的实现方式中，导通结构还包括第三导通部，第三导通部设置于第一导通部与晶体管之间；第三导通部包括第五通孔，第五通孔贯穿处于第一导通部与晶体管漏电极之间的介质层；第五通孔中设置有第五连接通道，第五连接通道与晶体管的漏电极、晶体管的漏电极相邻的第一金属布线或第二金属布线直接连接。
结合第一方面以及上述可能的实现方式，在另一种可能的实现方式中，第一通孔贯穿处于第一布线层和第二布线层之间的一层或两层第三布线层；其中，在导通结构的第一导通部为至少两个的情况下，每个第一导通部的第一通孔贯穿一层或两层第三布线层。
结合第一方面以及上述可能的实现方式，在另一种可能的实现方式中，每个第一导通部中，第一连接通道、位于第一连接通道远离衬底一侧且与第一连接通道直接连接的第一金属布线或第二金属布线为一体结构；扩散阻挡层设置于该一体结构的侧面和底面，底面靠近衬底；其中，扩散阻挡层位于第一连接通道侧面和底面的部分，位于第一通孔中。
在此基础上，可选的，在导通结构还包括第二导通部的情况下，第四连接通道和第四金属布线为一体结构；在此基础上，扩散阻挡层还可设置于第四连接通道和第四金属布线构成的一体结构的侧面和底面，底面靠近衬底；其中，扩散阻挡层位于第四连接通道侧面和底面的部分，位于第四通孔中。
可选的，在导通结构还包括第三导通部的情况下，第五连接通道、位于第五连接 通道远离衬底一侧且与第五连接通道直接连接的第一金属布线或第二金属布线为一体结构；扩散阻挡层还可设置于由第五连接通道与第一金属布线和第二金属布线中的一者构成的一体结构的侧面和底面，底面靠近衬底；其中，扩散阻挡层位于第五连接通道侧面和底面的部分，位于第五通孔中。
结合第一方面，在另一种可能的实现方式中，设置于相邻布线层之间的介质层至少包括第一子层和第二子层，第二子层为刻蚀阻挡层，且设置于第一子层靠近衬底的一侧。
在此基础上，可选的，第一子层的材料为低介电常数或超低介电常数的介质材料。
结合第一方面以及上述可能的实现方式，在另一种可能的实现方式中，第一金属布线和第二金属布线的长度方向平行。
进一步可选的，第四金属布线的长度方向与第一金属布线和第二金属布线的长度方向平行。基于此，在沿第一金属布线和第二金属布线的宽度方向，使存储单元的尺寸减小，从而提升存储器的集成密度。
本申请的第二方面，提供另一种存储器，包括存储区，存储区包括设置于衬底上的若干存储单元；每个存储单元均包括设置于衬底上的晶体管和与其电连接的MTJ存储元件；MTJ存储元件包括底电极、顶电极和位于二者之间的MTJ，底电极与晶体管的漏电极通过导通结构电连接；存储区在晶体管和MTJ存储元件之间设置有多层布线层，且相邻的布线层之间、最靠近晶体管的布线层与晶体管之间均填充有介质层；导通结构包括第一导通部；第一导通部包括第一金属布线和第一通孔；多层布线层包括第一布线层和第二布线层，第二布线层设置于第一布线层和晶体管之间；第一布线层包括第一金属布线，第一通孔贯穿处于第一布线层和晶体管之间的介质层以及第二布线层；第一通孔中设置有第一连接通道，第一连接通道与第一金属布线和晶体管的漏电极直接连接，第一连接通道不与第二布线层上的金属布线直接连接。
由于用于使晶体管的漏电极与MTJ存储元件的底电极电连接的导通结构中，第一导通部的第一通孔贯穿处于第一布线层和晶体管之间的第二布线层，而使设置于第一通孔中的第一连接通道与第一金属布线和晶体管的漏电极直接连接，因而，相对于第一金属布线与晶体管的漏电极通过位于二者之间且设置于第二布线层上金属布线电连接，本申请可释放出第二布线层上这部分金属布线所占用的空间。基于此，一方面，可将第二布线层释放出来的空间，用于电路布线，从而缓解整体电路布线的拥挤度；另一方面，由于第二布线层上用于连接漏电极与第一金属布线的金属布线省去后，在满足布线最小间距的情况下，可降低每个存储单元所占用的面积，因此，可提升存储器的集成密度；再一方面，通孔的电阻主要来自通孔与其下方(靠近衬底)接触的金属之间的界面，本申请中由于第一通孔跨过了第二布线层，因而也就不存在第一通孔与第二布线层上金属布线之间的界面，具有更小的电阻，而且可减小寄生电容，进而可提升存储器的整体性能。
结合第二方面，在一种可能的实现方式中，晶体管用于控制对存储单元中信息的写入、更改或读取。
结合第二方面，在另一种可能的实现方式中，相邻两个存储单元中的晶体管共用漏电极。从而可进一步提升存储器的集成密度。
结合第二方面，在另一种可能的实现方式中，第一导通部为至少两个，且所有第一导通部沿衬底的厚度方向设置；任意相邻第一导通部直接连接。
结合第二方面，在另一种可能的实现方式中，导通结构还包括第二导通部；第二导通部设置于第一导通部远离衬底的一侧；第二导通部包括第四金属布线和第四通孔；多层布线层还包括第四布线层，第四布线层包括第四金属布线；第四通孔贯穿处于第四布线层和第一导通部之间的介质层；第四通孔中设置有第四连接通道，第四连接通道与第四金属布线和第一金属布线直接连接。
在此基础上，可选的，第二导通部为至少两个，且所有第二导通部沿衬底的厚度方向设置；其中，所有第二导通部中，最靠近第一导通部的一个第二导通部中第四连接通道与第四金属布线和第一金属布线直接连接；任意相邻第二导通部中，分别属于相邻第二导通部的第四金属布线和第四连接通道直接连接。
可选的，第四金属布线的长度方向与第一金属布线的长度方向平行。基于此，在沿第一金属布线的宽度方向，使存储单元的尺寸减小，从而提升存储器的集成密度。
结合第二方面以及上述可能的实现方式，在另一种可能的实现方式中，第一通孔贯穿处于第一布线层和晶体管之间的一层或两层第二布线层。
结合第二方面以及上述可能的实现方式，在另一种可能的实现方式中，每个第一导通部中，第一连接通道、与第一连接通道直接连接的第一金属布线为一体结构；扩散阻挡层设置于该一体结构的侧面和底面，底面靠近衬底；其中，扩散阻挡层位于第一连接通道侧面和底面的部分，位于第一通孔中。
在此基础上，在导通结构还包括第二导通部的情况下，第四连接通道和第四金属布线为一体结构；在此基础上，扩散阻挡层还可设置于第四连接通道和第四金属布线构成的一体结构的侧面和底面，底面靠近衬底；其中，扩散阻挡层位于第四连接通道侧面和底面的部分，位于第四通孔中。
结合第二方面，在另一种可能的实现方式中，设置于相邻布线层之间的介质层至少包括第一子层和第二子层，第二子层为刻蚀阻挡层，且设置于第一子层靠近衬底的一侧。
在此基础上，可选的，第一子层的材料为低介电常数或超低介电常数的材料。
附图说明
图1本申请提供的一种存储器的俯视示意图；
图2为一个存储单元中晶体管和MTJ存储元件连接的示意图；
图3为本申请提供的一种存储器中存储单元的剖视示意图；
图4为晶体管的漏电极与MTJ存储元件的底电极连接的剖视示意图；
图5(a)为图4中第一布线层、第二布线层和第三布线层在一个存储单元的布线立体示意图；
图5(b)为图2中第一布线层、第二布线层和第三布线层在一个存储单元的布线立体示意图；
图6为金属线最短长度随技术节点的变化趋势；
图7为本申请提供的另一种存储器中存储单元的剖视示意图；
图8为本申请提供的另一种存储器中存储单元的剖视示意图；
图9为本申请提供的另一种存储器中存储单元的剖视示意图；
图10为本申请提供的另一种存储器中存储单元的剖视示意图；
图11为本申请提供的另一种存储器中存储单元的剖视示意图；
图12为本申请提供的另一种存储器中存储单元的剖视示意图；
图13为本申请提供的另一种存储器中存储单元的剖视示意图；
图14为本申请提供的另一种存储器中存储单元的剖视示意图；
图15为本申请提供的另一种存储器中存储单元的剖视示意图；
图16为本申请提供的另一种存储器中存储单元的剖视示意图；
图17为本申请提供的另一种存储器中存储单元的剖视示意图；
图18为本申请提供的另一种存储器中存储单元的剖视示意图；
图19为本申请提供的另一种存储器中存储单元的剖视示意图；
图20为本申请提供的另一种存储器中存储单元的剖视示意图；
图21为本申请提供的另一种存储器中存储单元的剖视示意图；
图22为本申请提供的另一种存储器中存储单元的剖视示意图；
图23为本申请提供的另一种存储器中存储单元的剖视示意图；
图24为本申请提供的另一种存储器中存储单元的剖视示意图；
图25为本申请提供的另一种存储器中存储单元的剖视示意图；
图26为本申请提供的另一种存储器中存储单元的剖视示意图；
图27为本申请提供的另一种存储器中存储单元的剖视示意图；
图28为本申请提供的另一种存储器中存储单元的剖视示意图；
图29为本申请提供的另一种存储器中存储单元的剖视示意图；
图30为本申请提供的另一种存储器中存储单元的剖视示意图；
图31为本申请提供的另一种存储器中存储单元的剖视示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
另外，在本申请的描述中，除非另有说明，“若干”、“多个”的含义是两个或两个以上。
本申请提供一种存储器，如图1所示，包括存储区10，存储区10包括设置于衬底20上的若干存储单元；如图2所示，每个存储单元30，均包括设置于衬底20上的晶体管40和与其电连接的磁隧道结(Magnetic Tunnel Junction，MTJ)存储元件50。
如图3所示，MTJ存储元件50包括底电极51、顶电极52和位于二者之间的MTJ53，底电极51与晶体管40的漏电极42通过导通结构60电连接；存储区10在晶体管40和MTJ存储元件50之间设置有多层布线层，且相邻的布线层之间填充有介质层70。
继续参考图3，导通结构60包括第一导通部61，第一导通部61包括第一金属布线611、第二金属布线612以及位于第一金属布线611和第二金属布线612之间的第一通孔613；多层布线层包括第一布线层81，第二布线层82和第三布线层83，第三布线层83设置于第一布线层81和第二布线层82之间；第一布线层81包括第一金属布线611，第二布线层82包括第二金属布线612，第一通孔613贯穿处于第一布线层81和第二布线层82之间的介质层70以及第三布线层83；第一通孔613中设置有第一连接通道614，第一连接通道614与第一金属布线611和第二金属布线612直接连接，第一连接通道614不与第三布线层83上的金属布线直接连接。
需要说明的是，如图2所示，存储区10中还设置有字线91和位线93。字线92用于控制晶体管40的导通或关闭，位线93则用于在晶体管40导通时向对应的MTJ存储元件50中读写数据。通常来说，每个存储单元30中的晶体管40的栅电极44与字线91电连接，源电极41与源极线92电连接，MTJ存储元件50的顶电极52与位线93电连接。
对于本申请的存储器而言，除包括存储单元30外，还包括外围电路，例如读出放大电路、读取/写入电路等。其中，电路布线可位于存储区10的外围区域，在存储区10也会设置外围电路的布线(包括上述的字线91、源极线92、位线93等)。外围电路的电路布线分布于各布线层中。
此外，本申请中，将除晶体管40和MTJ存储元件50外，存储区10中处于介质层70的同一平面(该平面与衬底20的上表面平行或基本平行)上的所有金属布线称为一层布线层；而对于构成同一层布线层的金属布线而言，不同金属布线之间具有间距，间距处填充有介质材料。其中，介质层70覆盖存储区10。
对于第三布线层83而言，第一通孔613贯穿第三布线层83，但设置于第一通孔613中的第一连接通道614不与第三布线层83上的金属布线直接连接，也就是说，可使第三布线层83中，对应第一通孔613的位置处，不设置金属布线，以满足此条件。“直接连接”是指不通过其他结构，物理上的直接接触。
其中，由于第一通孔613贯穿处于第一布线层81和第二布线层82之间的介质层70以及第三布线层83，且设置于第一通孔613中的第一连接通道614与第一金属布线611和第二金属布线612直接连接，因此，可知第一通孔613的两端分别与第一金属布线611和第二金属布线612直接连接。
在上述基础上，本领域技术人员应该明白，用于连接MTJ存储元件底电极51和晶体管漏电极42的导通结构60，在各存储单元30中，其结构是相同的。
参考图3所示，晶体管40除包括漏电极42外，还包括源电极41，栅介质层43和栅电极44。为区分晶体管40的除栅电极44之外的两极，将其中一电极称为源电极41，另一电极称为漏电极42，因此本申请中的源电极41和漏电极42仅用于互相区分，并不代表当晶体管40被实际接入电路时，漏电极42只能作为晶体管40在电路中的漏极与电路其他器件相连。
示例的，参考图3所示，晶体管40还可包括源极区45和漏极区46，源极区45与源电极41接触，漏极区46与漏电极42接触，源极区45和漏极区46之间的区域为沟道区。源极区45和漏极区46可通过对衬底20进行掺杂工艺得到，在此情况下，衬底20材料为半导体材料，例如硅。
可选的，晶体管40用于控制对存储单元30中信息的写入、更改或读取。即，晶体管40作为选择器件，可控制对存储单元30中信息的写入、更改或读取。
其中，晶体管40和与其最靠近的布线层(例如图3中所示的第一布线层81)之间也填充有介质材料。
MTJ存储元件50通常在中间或后道工艺中集成，而存储区10在晶体管40和MTJ存储元件50之间会设置多层布线层(多层布线层沿衬底20厚度方向设置)。
以晶体管40和MTJ存储元件50之间设置一层第一布线层81，一层第二布线层82和 一层第三布线层83，且第一布线层81靠近衬底20、第三布线层83设置于第一布线层81和第二布线层82之间为例。如图4所示，各存储单元30中，晶体管40的漏电极42与MTJ存储元件50的底电极51可通过如下方式实现电连接：第二布线层82中的第二金属布线612与MTJ存储元件50的底电极直接连接，并且，第二布线层82中的第二金属布线612与第三布线层83中的第三金属布线831，通过贯穿位于第二布线层82和第三布线层83之间介质层70的通孔以及设置于该通孔中的连接通道直接连接；第三布线层83中的第三金属布线831又与第一布线层81中的第一金属布线611，通过贯穿位于第三布线层83和第一布线层81之间介质层70的通孔以及设置于该通孔中的连接通道直接连接；第一布线层81中的第一金属布线611又与晶体管40的漏电极42，通过贯穿位于第一布线层81和晶体管40之间介质层70的通孔以及设置于该通孔中的连接通道直接连接，从而实现晶体管40的漏电极42与MTJ存储元件50的底电极51电连接。
随着半导体技术工艺节点的演进，集成电路中金属互连线逐渐从二维布线变为严格的一维布线，因此，图4中用于使晶体管40的漏电极42与MTJ存储元件50的底电极51电连接的第二金属布线612、第三金属布线831和第一金属布线611，可按如图5(a)所示的方式设置，每层的金属布线按一维方式布线。
由于金属线制备工艺的限制，布线层中的金属布线尺寸都需要满足最小面积(平面面积)的要求。金属布线最小面积的要求可以转化为金属布线宽度为最小线宽时，对金属布线最短长度L(如图5(a)所示)的要求，而金属布线的末端之间还有最短间距d的要求(如图5(a)所示)。基于此，基于图4中晶体管漏电极42与MTJ存储元件底电极51的电连接方式，金属布线最短长度要求以及同一布线层上相邻金属布线末端之间最短间距要求，限制了存储器的集成度。
其中，金属线最小面积的要求随着技术节点的发展还在不断恶化。从图6可以看出，从65nm节点到16nm节点，为了满足最小面积的要求，对金属布线最短长度的要求已从最小金属线宽的3.6倍增加至6倍。即，随着技术节点的发展，金属布线最短长度在逐渐增加，故而，金属布线最短长度的要求正在逐渐成为阻碍存储器集成密度进一步提升的瓶颈。
而本申请中，参考图5(b)所示，由于第一通孔613贯穿第三布线层83，即第三布线层83在对应第一通孔613的位置处，不设置金属布线，因此，对比图5(a)和图5(b)，图5(b)中由于第一通孔613的设置，可省去图5(a)中位于第一金属布线611和第二金属线612之间且设置于第三布线层83的第三金属布线831。而第一金属布线611和第二金属线612之间设置于第三布线层83的第三金属布线831的省去，可释放出由于金属布线最短长度要求而占用的相应空间。
本申请提供的一种存储器，由于用于使晶体管40的漏电极42与MTJ存储元件50的底电极51电连接的导通结构60中，第一导通部61的第一通孔613贯穿处于第一布线层81和第二布线层82之间的第三布线层83，而使设置于第一通孔613中的第一连接通道614与第一金属布线611和第二金属布线612直接连接，因而，相对于图4中的中第一金属布线611与第二金属布线612通过位于二者之间且设置于第三布线层83的第三金属布线831电连接，本申请省去了第三金属布线831，从而可释放出第三金属布线831所占用的空间。基于此，一方面，可将第三金属布线831释放出来的空间，用于电路布线，从而 缓解整体电路布线的拥挤度；另一方面，由于第三金属布线831省去后，在满足布线最小间距的情况下，可降低每个存储单元30所占用的面积，因此，可提升存储器的集成密度；再一方面，通孔的电阻主要来自通孔与其下方(靠近衬底20)接触的金属布线之间的界面，本申请中由于第一通孔613跨过了第三布线层83，因而也就不存在第一通孔613与第三布线层83上金属布线之间的界面，具有更小的电阻，而且可减小寄生电容，进而可提升存储器的整体性能。
可选的，本申请中第一金属布线611和第二金属布线612的长度方向平行。基于此，在沿第一金属布线611和第二金属布线612的宽度方向，使存储单元30的尺寸减小，从而进一步提升存储器的集成密度。
可选的，由于在晶体管40的源电极41和漏电极42对称的情况下，源电极41和漏电极42是没有区别，因此，如图7所示，可使相邻两个存储单元30中的晶体管40共用漏电极42。从而可进一步提升存储器的集成密度。
可选的，如图8所示，存储区10设置有第二通孔615，第二通孔615贯穿第三布线层83；第一通孔613和第二通孔615相邻，第三布线层83的处于第一通孔613和第二通孔615之间的部分上没有金属布线。
此处，第一通孔613和第二通孔615相邻，即，第一通孔613和第二通孔615之间不穿插有其他通孔。其中，不对第二通孔615的作用进行限定，可用于连接位于不同布线层上的电路布线。
需要说明的是，对比图7所示的截面图，图8所示的截面图为从存储区10另一方向截取的截面图。图8中第二通孔615与第二布线层82和第一布线层81中的金属布线连接仅为示意。
由于第三布线层83在第一通孔613和第二通孔615对应位置都没有设置金属布线，且在第一通孔613和第二通孔615之间也没有第三布线层83的金属布线的情况下，第一通孔613和第二通孔615在设置时仅需满足通孔间距的要求即可，因而，可使存储器的集成密度做的更高。
可选的，如图9所示，存储区10设置有第三通孔616，第三通孔616的一端起始于第三布线层83，第三通孔616中的第三连接通道617与第三布线层83上的金属布线连接，第三通孔616和第一通孔613相邻。
此处，第三通孔616和第一通孔613相邻，即，第三通孔616和第一通孔613之间不穿插有其他通孔。其中，不对第三通孔616的作用进行限定，可用于连接位于不同布线层上的电路布线。
需要说明的是，对比图7所示的截面图，图9所示的截面图为从存储区10另一方向截取的截面图。图9中第三通孔616与第一布线层81上的金属布线连接仅为示意。
由于相对图4的技术方案，本申请方案省去了第三金属布线831，因此，相应的释放出来的空间，则可用作电路布线。
可选的，如图10和图11所示，第一导通部61为至少两个，且所有第一导通部61沿衬底20的厚度方向设置。
需要说明的是，相邻的两个第一导通部61可按如图10所示，通过第六通孔641以及位于第六通孔641中的第六连接通道642连接；也可按如图11所示，直接连接。
根据MTJ存储元件50所处位置的不同，尤其是MTJ存储元件50在后道工艺中集成时，可通过在导通结构60中设置至少两个第一导通部61，来提升存储器的集成密度。
进一步可选的，如图11所示，任意相邻的两个第一导通部61共用第二金属布线612或第一金属布线611。
其中，图11中以第一导通部61为两个进行示意。以此为例，若存储区10在晶体管40和MTJ存储元件50之间设置的多层布线层，从最靠近衬底20开始，依次为第一布线层81、第三布线层83、第二布线层82、第三布线层83和第一布线层81，则，两个第一导通部61共用第二金属布线612。
可以理解的是，若存储区10在晶体管40和MTJ存储元件50之间设置的多层布线层，从最靠近衬底20开始，依次为第二布线层82、第三布线层83、第一布线层81、第三布线层83和第二布线层82，则，两个第一导通部61共用第一金属布线611。
当第一导通部61为三个，且位于中间的第一导通部61沿垂直衬底20方向上分别与其两侧的第一导通部61相邻时，位于中间的第一导通部61与其一侧的第一导通部61共用第二金属布线612，位于中间的第一导通部61与其另一侧的第一导通部61共用第一金属布线611。
可选的，如图12所示，导通结构60还包括第二导通部62，第二导通部62设置于第一导通部61与MTJ存储元件50之间；第二导通部62包括第四金属布线621和第四通孔622；多层布线层还包括第四布线层84，第四布线层84包括第四金属布线621；第四通孔622贯穿处于第四布线层84和第一导通部61之间的介质层70；第四通孔622中设置有第四连接通道623，第四连接通道623与第四金属布线621、第四金属布线621相邻的第一金属布线611或第二金属布线612直接连接。
其中，第四金属布线621的长度方向可与第一金属布线611和第二金属布线612的长度方向平行。
图12中以第四布线层84与第二布线层82相邻设置为例进行示意，在此情况下，第四连接通道623与第四金属布线621和第二金属布线612直接连接。第四布线层84与第二布线层82相邻，即第四布线层84与第二布线层82之间不存在其他布线层。
若第四布线层84与第一布线层81相邻设置，则，第四连接通道623与第四金属布线621和第一金属布线611直接连接。第四布线层84与第一布线层81相邻，即第四布线层84与第一布线层81之间不存在其他布线层。
需要说明的是，不管第一导通部61的个数为几个，所有第一导通部61都应看作一个整体，而将第二导通部62设置于第一导通部61与MTJ存储元件50之间。即，当第一导通部61为多个时，第二导通部62设置于最靠近MTJ存储元件50的第一导通部61与MTJ存储元件50之间。
此外，本申请涉及的附图中，“81”、“82”、“83”、“84”旁边带箭头的线用于指示一层布线层。
可选的，参考图10-图12所示，导通结构60还包括第三导通部63，第三导通部63设置于第一导通部61与晶体管40之间；第三导通部63包括第五通孔631，第五通孔631贯穿处于第一导通部61与晶体管漏电极42之间的介质层70；第五通孔631中设置有第五连接通道632，第五连接通道632与晶体管40的漏电极42、晶体管40的 漏电极42相邻的第一金属布线611或第二金属布线612直接连接。
其中，图10-图12中以第一布线层81更靠近晶体管40为例进行示意，在此情况下，第五连接通道632与晶体管40的漏电极42和第一金属布线611直接连接。
若第二布线层82更靠近晶体管40，则，第五连接通道632与晶体管40的漏电极42和第二金属布线612直接连接。
需要说明的是，不管第一导通部61的个数为几个，所有第一导通部61都应看作一个整体，而将第三导通部63设置于第一导通部61与晶体管40之间。即，当第一导通部61为多个时，第三导通部63设置于最靠近衬底20的第一导通部61与晶体管40之间。
可选的，第一通孔613贯穿处于第一布线层81和第二布线层82之间的一层或两层第三布线层83。
其中，在导通结构60的第一导通部61为至少两个的情况下，每个第一导通部61的第一通孔613贯穿一层或两层第三布线层83。
即，以导通结构60包括两个第一导通部61为例，其中一个第一导通部61的第一通孔613可贯穿一层第三布线层83，另一个第一导通部61的第一通孔613可贯穿两层第三布线层83(如图13所示)；或者，两个第一导通部61的第一通孔613均贯穿一层第三布线层83(如图11所示)；或者，两个第一导通部61的第一通孔613均贯穿两层第三布线层8。
可选的，如图14-图16所示，每个第一导通部61中，第一连接通道614、位于第一连接通道614远离衬底20一侧且与第一连接通道614直接连接的第一金属布线611或第二金属布线612为一体结构；在此基础上，扩散阻挡层65设置于该一体结构的侧面和底面，底面靠近衬底20；其中，扩散阻挡层65位于第一连接通道614侧面和底面的部分，位于第一通孔613中。
图14中以设置有一个第一导通部61为例进行示意。由于该第一导通部61中，第二金属布线612位于第一连接通道614远离衬底20的一侧，因此，第一连接通道614和与其直接连接的第二金属布线612为一体结构。在此基础上，扩散阻挡层65设置于一体结构的第一连接通道614和第二金属布线612的侧面和底面，且扩散阻挡层65位于第一连接通道614侧面和底面的部分，位于第一通孔613中。
图15-图16中均以设置有两个第一导通部61为例进行示意。对于更靠近衬底20的一个第一导通部61而言，由于第二金属布线612位于第一连接通道614远离衬底20的一侧，因此，在该第一导通部61中，第一连接通道614和与其直接连接的第二金属布线612为一体结构。扩散阻挡层65设置于该一体结构的第一连接通道614和第二金属布线612的侧面和底面，且扩散阻挡层65位于第一连接通道614侧面和底面的部分，位于第一通孔613中。对于另一个第一导通部61而言，由于第一金属布线611位于第一连接通道614远离衬底20的一侧，因此，在该第一导通部61中，第一连接通道614和与其直接连接的第一金属布线611为一体结构。扩散阻挡层65设置于该一体结构的第一连接通道614和第一金属布线611的侧面和底面，且扩散阻挡层65位于第一连接通道614侧面和底面的部分，位于第一通孔613中。
其中，“一体结构”即，构成一体结构的两部分材料相同且同时形成。具体的， 当第一连接通道614和位于第一连接通道614远离衬底20一侧且与第一连接通道614直接连接的第一金属布线611为一体结构时，第一连接通道614和位于第一连接通道614远离衬底20一侧且与第一连接通道614直接连接的第一金属布线611同时形成。当第一连接通道614和位于第一连接通道614远离衬底20一侧且与第一连接通道614直接连接的第二金属布线612为一体结构时，第一连接通道614和位于第一连接通道614远离衬底20一侧且与第一连接通道614直接连接的第二金属布线612同时形成。
由于某些互连金属材料，例如铜(Cu)，容易扩散，而导致电路性能降低或失效，因此，需要通过设置扩散阻挡层65阻挡其扩散。其中，针对不同的互连金属材料，需搭配使用不同的扩散阻挡层65材料，以保证扩散阻挡层65的阻挡作用、与一体化结构以及介质层90的粘附性等。
示例的，当上述一体化结构的材料为Cu时，可采用氮化钽(TaN)/钽(Ta)双层结构作为扩散阻挡层65，或者也可采用TaN/钴(Co)双层结构作为扩散阻挡层65。
需要说明的是，应用于本申请存储器中的互连金属材料还可以为Co、钌(Ru)、钨(W)等，可根据这些材料的扩散性，选择是否设置扩散阻挡层65。
进一步可选的，在导通结构60还包括第二导通部62的情况下，如图17所示，第四连接通道623和第四金属布线621为一体结构；在此基础上，扩散阻挡层65还可设置于由第四连接通道623和第四金属布线621构成的一体结构的侧面和底面，底面靠近衬底20；其中，扩散阻挡层65位于第四连接通道623侧面和底面的部分，位于第四通孔622中。
可选的，在导通结构60还包括第三导通部63的情况下，如图18所示，第五连接通道632、位于第五连接通道632远离衬底20一侧且与第五连接通道632直接连接的第一金属布线611或第二金属布线612为一体结构；扩散阻挡层65还可设置于由第五连接通道632与第一金属布线611和第二金属布线612中的一者构成的一体结构的侧面和底面，底面靠近衬底20；其中，扩散阻挡层65位于第五连接通道632侧面和底面的部分，位于第五通孔631中。
图18以第五连接通道632和第一金属布线611构成一体结构进行示意。
需要说明的是，上述仅描述了扩散阻挡层65设置于导通结构60位置处的情况，对于电路布线以及涉及的通孔也可根据采用的互连金属材料设置相应的扩散阻挡层65，在本申请中不再赘述。示例的，以图14为例，在此截面图中可以看出，第三布线层83中具有电路布线，因而，如图19所示，也可在第三布线层83的电路布线侧面以及底面设置扩散阻挡层65。
可选的，如图20和图21所示，设置于相邻布线层之间的介质层70至少包括第一子层71和第二子层72，第二子层72为刻蚀阻挡层，且设置于第一子层71靠近衬底20的一侧。
第二子层72设置于第一子层71靠近衬底20的一侧，即，先形成第二子层72，再形成第一子层71。
通过使介质层70包括第一子层71和第二子层72，第二子层72为刻蚀阻挡层，且设置于第一子层71靠近衬底20的一侧，可避免在形成该介质层70上方(即远离衬底20一侧)的布线层时，对已经形成的布线层产生影响。
进一步可选的，第一子层71的材料为低介电常数或超低介电常数的材料。
需要说明的是，低介电常数和超低介电常数介质是指介电常数的值小于二氧化硅的介电常数(介电常数为3.9～4)的介质材料。
当第一子层71的材料为低介电常数或超低介电常数的材料时，可降低相邻布线层之间的寄生电容。
本申请还提供一种存储器，参图1所示，包括存储区10，存储区10包括设置于衬底20上的若干存储单元30；如图2所示，每个存储单元30，均包括设置于衬底20上的晶体管40和与其电连接的MTJ存储元件50。
如图22所示，MTJ存储元件50包括底电极51、顶电极52和位于二者之间的MTJ53，底电极51与晶体管40的漏电极42通过导通结构60电连接；存储区10在晶体管40和MTJ存储元件50之间设置有多层布线层，且相邻的布线层之间、最靠近晶体管40的布线层与晶体管40之间均填充有介质层70。
继续参考图22，导通结构60包括第一导通部61；第一导通部61包括第一金属布线611和第一通孔613；多层布线层包括第一布线层81和第二布线层82，第二布线层82设置于第一布线层81和晶体管40之间；第一布线层81包括第一金属布线611，第一通孔613贯穿处于第一布线层81和晶体管40之间的介质层70以及第二布线层82；第一通孔613中设置有第一连接通道614，第一连接通道614与第一金属布线611和晶体管40的漏电极42直接连接，第一连接通道614不与第二布线层82上的金属布线直接连接。
需要说明的是，对于第二布线层82而言，第一通孔613贯穿第二布线层82，但设置于第一通孔613中的第一连接通道614不与第二布线层82上的金属布线直接连接，也就是说，可使第二布线层82中，对应第一通孔613的位置处，不设置金属布线，以满足此条件。
参考图22所示，晶体管40除包括漏电极42外，还包括源电极41，栅介质层43和栅电极44。为区分晶体管40的除栅电极44之外的两极，将其中一电极称为源电极41，另一电极称为漏电极42。
示例的，参考图22所示，晶体管40还可包括源极区45和漏极区46，源极区45与源电极41接触，漏极区46与漏电极42接触，源极区45和漏极区46之间的区域为沟道区。源极区45和漏极区46可通过对衬底20进行掺杂工艺得到，在此情况下，衬底20材料为半导体材料。
可选的，晶体管40控制对存储单元30中信息的写入、更改或读取。即，晶体管40作为选择器件，可控制对存储单元30中信息的写入、更改或读取。
该存储器中由于用于使晶体管40的漏电极42与MTJ存储元件50的底电极51电连接的导通结构60中，第一导通部61的第一通孔613贯穿处于第一布线层81和晶体管40之间的第二布线层82，而使设置于第一通孔613中的第一连接通道614与第一金属布线611和晶体管40的漏电极42直接连接，因而，相对于第一金属布线611与晶体管40的漏电极42通过位于二者之间且设置于第二布线层82上金属布线电连接，本申请可释放出第二布线层82上这部分金属布线所占用的空间。基于此，一方面，可将第二布线层82释放出来的空间，用于电路布线，从而缓解整体电路布线的拥挤度；另一方面，由于第二布 线层82上用于连接漏电极42与第一金属布线611的金属布线省去后，在满足布线最小间距的情况下，可降低每个存储单元30所占用的面积，因此，可提升存储器的集成密度；再一方面，通孔的电阻主要来自通孔与其下方(靠近衬底20)接触的金属之间的界面，本申请中由于第一通孔613跨过了第二布线层82，因而也就不存在第一通孔613与第二布线层82上金属布线之间的界面，具有更小的电阻，而且可减小寄生电容，进而可提升存储器的整体性能。
可选的，由于在晶体管40的源电极41和漏电极42对称的情况下，源电极41和漏电极42是没有区别，因此，如图23所示，可使相邻两个存储单元30中的晶体管40共用漏电极42。从而可进一步提升存储器的集成密度。
可选的，如图24所示，第一导通部61为至少两个，且所有第一导通部61沿衬底20的厚度方向设置；任意相邻的第一导通部61直接连接。
根据MTJ存储元件50所处位置的不同，尤其是MTJ存储元件50在后道工艺中集成时，可通过在导通结构60中设置至少两个第一导通部61，来提升存储器的集成密度。
可选的，如图25所示，导通结构60还包括第二导通部62；第二导通部62设置于第一导通部61远离衬底20的一侧；第二导通部62包括第四金属布线621和第四通孔622；多层布线层还包括第四布线层84，第四布线层84包括第四金属布线621；第四通孔622贯穿处于第四布线层84和第一导通部61之间的介质层70；第四通孔622中设置有第四连接通道623，第四连接通道623与第四金属布线621和第一金属布线611直接连接。
其中，第四金属布线621的长度方向可与第一金属布线611的长度方向平行。
需要说明的是，由第四通孔622贯穿处于第四布线层84和第一导通部61之间的介质层70，第四连接通道623与第四金属布线621和第一金属布线611直接连接，可知，第四布线层84与第一布线层81沿衬底20方向相邻设置，且第四布线层84设置于第一布线层81远离衬底20一侧。第四布线层84与第一布线层81相邻设置，即第四布线层84与第一布线层81之间不设置其他布线层。
此外，不管第一导通部61的个数为几个，所有第一导通部61都应看作一个整体，而将第二导通部62设置于第一导通部61与MTJ存储元件50之间。即，当第一导通部61为多个时，第二导通部62设置于最靠近MTJ存储元件50的第一导通部61与MTJ存储元件50之间。
可选的，如图26所示，第二导通部62为至少两个，且所有第二导通部62沿衬底20的厚度方向设置；其中，所有第二导通部62中，最靠近第一导通部61的一个第二导通部62中第四连接通道623与第四金属布线621和第一金属布线611直接连接；任意相邻第二导通部62中，分别属于相邻第二导通部62的第四金属布线621和第四连接通道623直接连接。
图26中以导通结构60中设置两个第二导通部62为例进行示意。
可选的，第一通孔613贯穿处于第一布线层81和晶体管40之间的一层第二布线层82(如图23所示)或两层第二布线层82(如图27所示)。
可选的，如图28所示，每个第一导通部61中，第一连接通道614、与第一连接通道614直接连接的第一金属布线611为一体结构；在此基础上，扩散阻挡层65设置 于该一体结构的侧面和底面，底面靠近衬底20；其中，扩散阻挡层65位于第一连接通道614侧面和底面的部分，位于第一通孔613中。
由于某些互连金属材料(例如Cu)容易扩散，而导致电路性能降低或失效，因此，需要通过设置扩散阻挡层65阻挡其扩散。其中，针对不同的金属导电材料，需搭配使用不同的扩散阻挡层65材料，以保证扩散阻挡层65的阻挡作用、与一体化结构以及介质层90的粘附性等。
示例的，当上述一体化结构的材料为Cu时，可采用TaN/Ta双层结构作为扩散阻挡层65，或者也可采用TaN/Co双层结构作为扩散阻挡层65。
需要说明的是，应用于本申请存储器中的互连金属材料还可以为Co、Ru、W等，可根据这些材料的扩散性，选择是否设置扩散阻挡层65。
进一步可选的，在导通结构60还包括第二导通部62的情况下，如图29所示，第四连接通道623和第四金属布线621为一体结构；在此基础上，扩散阻挡层65还可设置于由第四连接通道623和第四金属布线621构成的一体结构的侧面和底面，底面靠近衬底20；其中，扩散阻挡层65位于第四连接通道623侧面和底面的部分，位于第四通孔622中。
需要说明的是，上述仅描述了扩散阻挡层65设置于导通结构60位置处，对于电路布线以及涉及的通孔也可根据采用的互连金属材料设置相应的扩散阻挡层65，在本申请中不再赘述。示例的，以图28为例，在此截面图中可以看出，第一布线层81中还具有电路布线，因而，如图30所示，可在第三布线层83的电路布线侧面以及底面设置扩散阻挡层65。
可选的，如图31所示，设置于相邻布线层之间的介质层70至少包括第一子层71和第二子层72，第二子层72为刻蚀阻挡层，且设置于第一子层71靠近衬底20的一侧。
通过使介质层70包括第一子层71和第二子层72，第二子层72为刻蚀阻挡层，且设置于第一子层71靠近衬底20的一侧，可避免在形成该介质层70上方(即远离衬底20一侧)的布线层时，对已经形成的布线层产生影响。
进一步可选的，第一子层71的材料为低介电常数或超低介电常数的材料。
当第一子层71的材料为低介电常数或超低介电常数的材料时，可降低相邻布线层之间的寄生电容。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种存储器，其特征在于，包括存储区，所述存储区包括设置于衬底上的若干存储单元；每个所述存储单元均包括设置于所述衬底上的晶体管和与其电连接的磁隧道结MTJ存储元件；
    所述MTJ存储元件包括底电极、顶电极和位于二者之间的MTJ，所述底电极与所述晶体管的漏电极通过导通结构电连接；
    所述存储区在所述晶体管和所述MTJ存储元件之间设置有多层布线层，且相邻的布线层之间填充有介质层；
    所述导通结构包括第一导通部，所述第一导通部包括第一金属布线、第二金属布线以及位于所述第一金属布线和所述第二金属布线之间的第一通孔；所述多层布线层包括第一布线层，第二布线层和第三布线层，所述第三布线层设置于所述第一布线层和所述第二布线层之间；所述第一布线层包括所述第一金属布线，所述第二布线层包括所述第二金属布线，所述第一通孔贯穿处于所述第一布线层和所述第二布线层之间的介质层以及所述第三布线层；所述第一通孔中设置有第一连接通道，所述第一连接通道与所述第一金属布线和所述第二金属布线直接连接，所述第一连接通道不与所述第三布线层上的金属布线直接连接。
  2. 根据权利要求1所述的存储器，其特征在于，所述存储区设置有第二通孔，所述第二通孔贯穿所述第三布线层；
    所述第一通孔和所述第二通孔相邻，所述第三布线层的处于所述第一通孔和所述第二通孔之间的部分上没有金属布线。
  3. 根据权利要求1所述的存储器，其特征在于，所述存储区设置有第三通孔，所述第三通孔的一端起始于所述第三布线层，所述第三通孔中的第三连接通道与所述第三布线层上的金属布线连接，所述第三通孔和所述第一通孔相邻。
  4. 根据权利要求1所述的存储器，其特征在于，所述第一导通部为至少两个，且所有所述第一导通部沿所述衬底的厚度方向设置。
  5. 根据权利要求4所述的存储器，其特征在于，任意相邻的两个所述第一导通部共用所述第二金属布线或所述第一金属布线。
  6. 根据权利要求1所述的存储器，其特征在于，所述导通结构还包括第二导通部，所述第二导通部设置于所述第一导通部与所述MTJ存储元件之间；
    所述第二导通部包括第四金属布线和第四通孔；所述多层布线层还包括第四布线层，所述第四布线层包括所述第四金属布线；所述第四通孔贯穿处于所述第四布线层和所述第一导通部之间的所述介质层；
    所述第四通孔中设置有第四连接通道，所述第四连接通道与所述第四金属布线、所述第四金属布线相邻的所述第一金属布线或所述第二金属布线直接连接。
  7. 根据权利要求1所述的存储器，其特征在于，所述导通结构还包括第三导通部，所述第三导通部设置于所述第一导通部与所述晶体管之间；
    所述第三导通部包括第五通孔，所述第五通孔贯穿处于所述第一导通部与所述晶体管漏电极之间的介质层；
    所述第五通孔中设置有第五连接通道，所述第五连接通道与所述晶体管的漏电极、 所述晶体管的漏电极相邻的所述第一金属布线或所述第二金属布线直接连接。
  8. 根据权利要求1-7任一项所述的存储器，其特征在于，所述第一通孔贯穿处于所述第一布线层和所述第二布线层之间的一层或两层所述第三布线层；
    其中，在所述导通结构的所述第一导通部为至少两个的情况下，每个所述第一导通部的所述第一通孔贯穿一层或两层所述第三布线层。
  9. 根据权利要求1-7任一项所述的存储器，其特征在于，每个所述第一导通部中，所述第一连接通道、位于所述第一连接通道远离所述衬底一侧且与所述第一连接通道直接连接的所述第一金属布线或所述第二金属布线为一体结构；
    扩散阻挡层设置于该一体结构的侧面和底面，所述底面靠近所述衬底；其中，所述扩散阻挡层位于所述第一连接通道侧面和底面的部分，位于所述第一通孔中。
  10. 一种存储器，其特征在于，包括存储区，所述存储区包括设置于衬底上的若干存储单元；每个所述存储单元均包括设置于所述衬底上的晶体管和与其电连接的磁隧道结MTJ存储元件；
    所述MTJ存储元件包括底电极、顶电极和位于二者之间的MTJ，所述底电极与所述晶体管的漏电极通过导通结构电连接；
    所述存储区在所述晶体管和所述MTJ存储元件之间设置有多层布线层，且相邻的布线层之间、最靠近所述晶体管的布线层与所述晶体管之间均填充有介质层；
    所述导通结构包括第一导通部；所述第一导通部包括第一金属布线和第一通孔；所述多层布线层包括第一布线层和第二布线层，所述第二布线层设置于所述第一布线层和所述晶体管之间；所述第一布线层包括所述第一金属布线，所述第一通孔贯穿处于所述第一布线层和所述晶体管之间的介质层以及所述第二布线层；所述第一通孔中设置有第一连接通道，所述第一连接通道与所述第一金属布线和所述晶体管的漏电极直接连接，所述第一连接通道不与所述第二布线层上的金属布线直接连接。
  11. 根据权利要求10所述的存储器，其特征在于，所述第一导通部为至少两个，且所有所述第一导通部沿所述衬底的厚度方向设置；任意相邻所述第一导通部直接连接。
  12. 根据权利要求10所述的存储器，其特征在于，所述导通结构还包括第二导通部；所述第二导通部设置于所述第一导通部远离所述衬底的一侧；
    所述第二导通部包括第四金属布线和第四通孔；所述多层布线层还包括第四布线层，所述第四布线层包括所述第四金属布线；所述第四通孔贯穿处于所述第四布线层和所述第一导通部之间的介质层；
    所述第四通孔中设置有第四连接通道，所述第四连接通道与所述第四金属布线和所述第一金属布线直接连接。
  13. 根据权利要求12所述的存储器，其特征在于，所述第二导通部为至少两个，且所有所述第二导通部沿所述衬底的厚度方向设置；
    其中，所有所述第二导通部中，最靠近所述第一导通部的一个所述第二导通部中所述第四连接通道与所述第四金属布线和所述第一金属布线直接连接；任意相邻所述第二导通部中，分别属于相邻所述第二导通部的所述第四金属布线和所述第四连接通道直接连接。
  14. 根据权利要求10-13任一项所述的存储器，其特征在于，所述第一通孔贯穿处于所述第一布线层和所述晶体管之间的一层或两层所述第二布线层。
  15. 根据权利要求10-13任一项所述的存储器，其特征在于，每个所述第一导通部中，所述第一连接通道、与所述第一连接通道直接连接的所述第一金属布线为一体结构；
    扩散阻挡层设置于该一体结构的侧面和底面，所述底面靠近所述衬底；其中，所述扩散阻挡层位于所述第一连接通道侧面和底面的部分，位于所述第一通孔中。
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