WO2019174099A1 - 一种阵列基板及oled显示面板 - Google Patents

一种阵列基板及oled显示面板 Download PDF

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Publication number
WO2019174099A1
WO2019174099A1 PCT/CN2018/083312 CN2018083312W WO2019174099A1 WO 2019174099 A1 WO2019174099 A1 WO 2019174099A1 CN 2018083312 W CN2018083312 W CN 2018083312W WO 2019174099 A1 WO2019174099 A1 WO 2019174099A1
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Prior art keywords
test
area
array substrate
layer
disposed
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PCT/CN2018/083312
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English (en)
French (fr)
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李雪
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武汉华星光电半导体显示技术有限公司
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Priority to US15/993,963 priority Critical patent/US10707288B2/en
Publication of WO2019174099A1 publication Critical patent/WO2019174099A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Definitions

  • the present invention relates to the field of OLED display, and in particular to an array substrate and an OLED display panel.
  • OLED organic light-emitting diode
  • an Array segment In the preparation process of the OLED display device, generally four stages are included: an Array segment, an EL layer segment, a package (TFE) segment, and a Module segment.
  • TFE package
  • Module segment In the preparation process, the testing of the array substrate in the Array segment of the product is particularly important, which determines the product yield, reliability and many other problems.
  • a test module 11 for testing the array substrate 12 is designed outside the array substrate 12 , wherein the test module 11 is connected to the array substrate 12 through the connection line 13 . .
  • the connection line 13 is cut. In this way, the test pad of the test module 11 does not appear exposed. However, the cut wire 13 is still exposed to metal, causing corrosion and electrostatic discharge (Electro-Static) Discharge, ESD) problem.
  • the technical problem to be solved by the present invention is to provide an array substrate and an OLED display panel, which can avoid metal leakage of the test pads and the connecting wires, thereby avoiding corrosion and ESD problems caused by metal leakage.
  • the present invention adopts a technical solution to provide an array substrate, which includes a display area, a non-display area surrounding the display area, a COF binding area, and a test area; wherein, the COF binding area And the test area is spaced apart from the non-display area; wherein the test area comprises a plurality of test pads arranged at intervals; wherein the array substrate further comprises a fanout trace area, the fanout trace area and the COF binding area are disposed on the same side of the display area The test area is disposed between the COF binding area and the fanout routing area; wherein the test pads are uniformly arranged in a "one" shape in the test area.
  • an array substrate including a display area, a non-display area surrounding the display area, a COF binding area, and a test area; wherein, the COF binding The zone and the test zone are spaced apart from each other in the non-display zone; wherein the test zone includes a plurality of test pads spaced apart.
  • another technical solution adopted by the present invention is to provide an OLED display panel, which includes the above array substrate.
  • the array substrate and the OLED display panel of the present invention include a display area, a non-display area surrounding the display area, a COF binding area, and a test area; wherein the COF binding area and the test area are spaced apart from each other.
  • the test pad of the present invention is disposed on the array substrate, and the connection line between the test pad and the array substrate does not need to be cut, so that the problem of metal leakage occurring after the connection line is cut can be avoided.
  • the insulating material covers the test pad, so that the problem of metal leakage of the test pad can be avoided.
  • 1 is a schematic view showing the connection of a prior art array substrate and a test module
  • FIG. 2 is a schematic structural view of an array substrate according to a first embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a test area in the array substrate shown in FIG. 2;
  • Figure 4 is a schematic cross-sectional view of the A-A position in the test zone shown in Figure 3;
  • FIG. 5 is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a test area in the array substrate shown in FIG. 5;
  • Figure 7 is a schematic cross-sectional view of the B-B position in the test zone shown in Figure 6;
  • Figure 8 is a schematic cross-sectional view of the C-C position in the test zone shown in Figure 6;
  • FIG. 9 is a schematic structural diagram of an OLED display panel according to an embodiment of the present invention.
  • the array substrate 20 includes a COF binding area 21, a test area 22, a fanout area 23, a display area AA, and a non-display area BB area surrounding the display area AA area.
  • the test area 22 is disposed between the COF binding area 21 and the fanout trace area 23. Specifically, the COF binding area 21, the test area 22, and the fanout routing area 23 are disposed in the non-display area BB area, and the COF binding area 21, the test area 22, and the fanout routing area 23 are disposed in the display area AA area. The same side, wherein the fan-out routing area 23 is disposed near the display area AA area, and the COF binding area 21 is disposed away from the display area AA area.
  • the COF bonding area 21, the test area 22, and the fan-out wiring area 23 are located at the bottom end of the array substrate 20.
  • the test area 22 includes a test circuit 221 and a plurality of test pads 222.
  • the plurality of test pads 222 and the test circuit 221 are electrically connected, wherein the test pads 222 are uniformly arranged in a "one" shape in the test area 22. .
  • FIG. 4 is a schematic cross-sectional view of the A-A position in the test area shown in FIG.
  • the test area 22 includes a buffer layer 212, a first inorganic insulating layer 213, a second inorganic insulating layer 214, and a first metal layer 215, which are sequentially disposed on the substrate 211, wherein the first metal layer 215 includes spaces.
  • a plurality of test pads 222 are provided.
  • the test area 22 further includes an organic insulation layer 216 that covers the plurality of test pads 222.
  • the test pad 222 is configured to receive or transmit signals to test the array substrate 20 for the Array segment process, and determine whether there is an abnormality in each pixel point in the array substrate 20. If there is any problem, judge whether it can be repaired, and then test and judge again. In order to decide whether it is necessary to enter the next process, through the Array
  • the test method of the segment can improve the yield and reduce the waste of materials to a certain extent and reduce the cost.
  • the upper layer of the test pad 222 is covered by an insulating material, that is, the organic insulating layer 216, so that the occurrence of metal exposure corrosion is avoided. That is to say, in this embodiment, after the end of the process of the Array section TFT device, that is, the metal process of the test pad 222, the test of the array substrate 20 is performed, and then the process of other layers such as the organic isolation layer 216 is performed.
  • test area 22 is located between the COF bonding area 21 and the fan-out wiring area 23, so that the space of the array substrate 20 can be fully utilized.
  • FIG. 5 is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • the array substrate 30 includes a COF binding region 31, a test region 32, a display region AA' region, a non-display region BB' region surrounding the display region AA' region, and a cathode layer 33.
  • the COF binding area 31 and the test area 32 are located in the non-display area BB' area.
  • the COF binding area 31 and the test area 32 are disposed on opposite sides of the display area AA' area.
  • the COF binding zone 31 is located at the bottom end of the array substrate 30, and the test zone 32 is located at the top end of the array substrate 30.
  • the cathode layer 33 covers the display area AA' area, and the edge position of the cathode layer 33 overlaps with the test area 32.
  • the test area 32 includes a test circuit 321 and a plurality of test pads 322 , and the plurality of test pads 322 and the test circuit 321 are electrically connected, wherein The test pads 322 are evenly arranged in a "one" shape in the test area 32.
  • the test area 32 includes a buffer layer 312, a first inorganic insulating layer 313, a second inorganic insulating layer 314, a first metal layer 315, an organic insulating layer 316, and a second metal layer 317 which are sequentially disposed on the substrate 311.
  • the first metal layer 315 includes a plurality of test pads 322 located in the test area 32 and signal lines 323 spaced from the test pads 322.
  • the organic insulation layer 316 includes a first opening 41
  • the second metal layer 317 includes a second opening 42 corresponding to the first opening 41 to expose a plurality of test pads 322 through the second opening 42 and the first opening 41.
  • the signal line 323 is connected to the cathode layer 33 through the second metal layer 317.
  • the cathode layer 33 covers the display area AA', and the edge of the cathode layer 33 is in contact with the second metal layer 317, wherein the signal line 323 is a power signal line that supplies the cathode layer 33 with a voltage VSS.
  • the other portion of the first metal layer 315 that is, the signal line 323, transmits a power signal of the voltage VSS to the cathode layer 33 through the second metal layer 317.
  • the array substrate 30 is allowed to operate normally.
  • the voltage VSS is provided by the signal line 323 in the first metal layer 315, and the cathode layer 33 is electrically connected to the signal line 323 through the transition metal layer, that is, the second metal layer 317, thus being the cathode layer. 33 provides a power supply for the voltage VSS.
  • the metal film layer of the test pad 322 is the first metal layer 315. To avoid short circuit with the signal line 323 of the first metal layer 315, the test pad 322 needs to be designed on the signal line 323 and the cathode layer 33.
  • the organic insulating layer 316 and the second metal layer 317 are designed in the form of openings to expose the test pad 322.
  • the array substrate 30 can be normally tested by the test pad 322 after the end of the TFT process or after the end of the entire Array segment. And in the TFE section, the test pad 322 can be packaged inside, that is, the test pad 322 is covered with an insulating material, so that the problem of metal exposure does not occur.
  • FIG. 9 is a schematic structural diagram of an OLED display panel according to an embodiment of the present invention.
  • the OLED display panel 1 includes an array substrate 2, which is the array substrate 20 or the array substrate 30 described above.
  • the array substrate and the OLED display panel of the present invention include a display area, a non-display area surrounding the display area, a COF binding area, and a test area; wherein the COF binding area and the test area are spaced apart from each other.
  • the test pad of the present invention is disposed on the array substrate, and the connection line between the test pad and the array substrate does not need to be cut, so that the problem of metal leakage occurring after the connection line is cut can be avoided.
  • the insulating material covers the test pad, so that the problem of metal leakage of the test pad can be avoided.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种阵列基板(20)及OLED显示面板。该阵列基板(20)包括显示区域(AA)、围绕显示区域(AA)的非显示区域(BB)、COF绑定区(21)和测试区(22)；其中，COF绑定区(21)和测试区(22)间隔设置于非显示区域(BB)；其中，测试区(22)包括间隔设置的多个测试垫(222)。通过上述方式，由于测试垫(222)设置在阵列基板(20)上，不需要切断测试垫(222)与阵列基板(20)的连接线，从而可以避免连接线被切断后出现的金属外漏的问题。进一步，当阵列基板(20)完成测试后，绝缘材料覆盖测试垫(222)，从而可以避免测试垫(222)出现金属外漏的问题。

Description

一种阵列基板及OLED显示面板
【技术领域】
本发明涉及OLED显示领域，特别是涉及一种阵列基板及OLED显示面板。
【背景技术】
随着科技的不断发展，人们对显示器件的要求越来越高。众所周知，有机发光二极管（OLED）显示器件，因其边框窄、制成重量轻、可卷曲、易于携带等诸多优势，受到了人们的广泛关注，成为时代的主流。
在OLED显示器件制备过程中，一般包括四个阶段：阵列（Array）段、发光层（EL）段、封装（TFE）段和模组（Module）段。其中，在制备过程中，对产品Array段中的阵列基板的测试，显得尤为重要，这决定着产品的良率、可靠性等诸多问题。
在传统的柔性OLED结构中，对于覆晶薄膜（Chip On Film，COF）类型的显示面板，如图1所示，一般是将对阵列基板12进行测试的测试模块11设计在阵列基板12的外侧，其中，测试模块11通过连接线13与阵列基板12连接。当完成阵列基板12的测试后，将连接线13切断。采用这种方式，不会出现测试模块11的测试垫外露的现象。但是，被切断的连接线13还是会存在金属外露，从而出现腐蚀及静电释放（Electro-Static discharge，ESD）的问题。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及OLED显示面板，能够避免出现测试垫和连接线的金属外漏，进而避免由于金属外漏而出现的腐蚀及ESD问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，该阵列基板包括显示区域、围绕显示区域的非显示区域、COF绑定区和测试区；其中，COF绑定区和测试区间隔设置于非显示区域；其中，测试区包括间隔设置的多个测试垫；其中，阵列基板进一步包括扇出走线区，扇出走线区和COF绑定区设置在显示区域的同一侧，测试区设置于COF绑定区和扇出走线区之间；其中，测试垫在测试区呈“一”字型均匀排列。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括显示区域、围绕显示区域的非显示区域、COF绑定区和测试区；其中，COF绑定区和测试区间隔设置于非显示区域；其中，测试区包括间隔设置的多个测试垫。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种OLED显示面板，该显示面板包括上述的阵列基板。
本发明的有益效果是：本发明的阵列基板及OLED显示面板包括显示区域、围绕显示区域的非显示区域、COF绑定区和测试区；其中，COF绑定区和测试区间隔设置于非显示区域；其中，测试区包括间隔设置的多个测试垫。通过上述方式，本发明的测试垫设置在阵列基板上，不需要切断测试垫与阵列基板的连接线，从而可以避免连接线被切断后出现的金属外漏的问题。进一步，当阵列基板完成测试后，绝缘材料覆盖测试垫，从而可以避免测试垫出现金属外漏的问题。
【附图说明】
图1是现有技术的阵列基板和测试模块的连接示意图；
图2是本发明第一实施例的阵列基板的结构示意图；
图3是图2所示阵列基板中测试区的结构示意图；
图4是图3所示测试区中A-A位置的剖面示意图；
图5是本发明第二实施例的阵列基板的结构示意图；
图6是图5所示阵列基板中测试区的结构示意图；
图7是图6所示测试区中B-B位置的剖面示意图；
图8是图6所示测试区中C-C位置的剖面示意图；
图9是本发明实施例的OLED显示面板的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明第一实施例的阵列基板的结构示意图。如图2所示，阵列基板20包括COF绑定区21、测试区22、扇出走线（Fanout）区23、显示区域AA和围绕显示区域AA区的非显示区域BB区
其中，测试区22设置于COF绑定区21和扇出走线区23之间。具体来说，COF绑定区21、测试区22和扇出走线区23设置在非显示区域BB区，且COF绑定区21、测试区22和扇出走线区23设置在显示区域AA区的同一侧，其中，扇出走线区23靠近显示区域AA区设置，COF绑定区21远离显示区域AA区设置。
在本实施例中，COF绑定区21、测试区22和扇出走线区23位于阵列基板20的底端。
请一并参考图3，测试区22包括测试电路221和多个测试垫222，多个测试垫222和测试电路221电连接，其中，测试垫222在测试区22呈“一”字型均匀排列。
请一并参考图4，图4是图3所示测试区中A-A位置的剖面示意图。如图4所示，测试区22包括依次设置在基板211上的缓冲层212、第一无机绝缘层213、第二无机绝缘层214和第一金属层215，其中，第一金属层215包括间隔设置的多个测试垫222。进一步，当完成对阵列基板20的检测后，测试区22进一步包括有机隔绝层216，有机隔绝层216覆盖多个测试垫222。
在本实施例中，测试垫222用于接收或传送讯号，以对Array段制程得到阵列基板20进行测试，判定阵列基板20中的各个像素点是否存在异常。如有问题，判断可否进行修复，修复后可再进行测试判定。以此来决定是否有必要进入下一段制程，通过该种Array 段的测试手段，可提高良率，并且在一定程度上减少材料的浪费，降低成本。
另外，在完整的Array段结束后，测试垫222的上层由绝缘材料也即有机隔绝层216覆盖，这样就会避免金属外露腐蚀现象的发生。也就是说，本实施例要求在Array段TFT器件制程结束也即测试垫222的金属制程结束后，进行阵列基板20的测试，随后再进行其它层别例如有机隔绝层216的制程。
在本实施例中，测试区22位于COF绑定区21和扇出走线区23之间，可使阵列基板20的空间得到充分的利用。另外，与现有技术相比，不需要切割掉位于阵列基板外侧的测试模块，可以提高玻璃基板的利用率。
图5是本发明第二实施例的阵列基板的结构示意图。如图5所示，阵列基板30包括COF绑定区31、测试区32、显示区域AA’区、围绕显示区域AA’区的非显示区域BB’区和阴极层33。
其中，COF绑定区31和测试区32位于非显示区域BB’区, COF绑定区31和测试区32设置在显示区域AA’区的相对两侧。优选地，COF绑定区31位于阵列基板30的底端，测试区32位于阵列基板30的顶端。
其中，阴极层33覆盖显示区AA’区，阴极层33的边缘位置与测试区32有重叠区域。
请一并参考图6、7和图8，如图6、7、8所示，测试区32包括测试电路321和多个测试垫322，多个测试垫322和测试电路321电连接，其中，测试垫322在测试区32呈“一”字型均匀排列。
测试区32包括依次设置在基板311上的缓冲层312、第一无机绝缘层313、第二无机绝缘层314、第一金属层315、有机隔绝层316、第二金属层317。
第一金属层315包括位于测试区32的多个测试垫322以及与测试垫322间隔设置的信号线323。
有机隔绝层316包括第一开口41，第二金属层317包括与第一开口41对应设置的第二开口42，以通过第二开口42和第一开口41暴露出多个测试垫322。
信号线323通过第二金属层317与阴极层33连接。其中，阴极层33覆盖显示区域AA’，阴极层33的边缘与第二金属层317相接触，其中信号线323为向阴极层33提供电压VSS的电源信号线。
从图7和图8可以看出，除了测试垫322部分之外，第一金属层315的其它部分也即信号线323都会通过第二金属层317将电压VSS的电源信号传送给阴极层33，使阵列基板30正常工作。
在传统的阵列基板的设计中，电压VSS由第一金属层315中的信号线323提供，通过过渡金属层也即第二金属层317使阴极层33与信号线323导通，这样为阴极层33提供了电压VSS的电源。在本实施例中，测试垫322的金属膜层为第一金属层315，为避免与第一金属层315的信号线323发生短路，需将测试垫322设计在信号线323与阴极层33之间，并将有机隔绝层316和第二金属层317设计成开孔的形式，以露出测试垫322。这样在TFT制程结束后或在整个Array段结束后，都可以利用测试垫322正常对阵列基板30进行测试。并且在TFE段，可以将测试垫322封装在内部也即利用绝缘材料覆盖测试垫322，从而不会出现金属外露的问题。
图9是本发明实施例的OLED显示面板的结构示意图。如图9所示，OLED显示面板1包括阵列基板2，阵列基板2为上述的阵列基板20或阵列基板30。
本发明的有益效果是：本发明的阵列基板及OLED显示面板包括显示区域、围绕显示区域的非显示区域、COF绑定区和测试区；其中，COF绑定区和测试区间隔设置于非显示区域；其中，测试区包括间隔设置的多个测试垫。通过上述方式，本发明的测试垫设置在阵列基板上，不需要切断测试垫与阵列基板的连接线，从而可以避免连接线被切断后出现的金属外漏的问题。进一步，当阵列基板完成测试后，绝缘材料覆盖测试垫，从而可以避免出现测试垫的金属外漏的问题。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括显示区域、围绕所述显示区域的非显示区域、COF绑定区和测试区；
    其中，所述COF绑定区和所述测试区间隔设置于所述非显示区域；
    其中，所述测试区包括间隔设置的多个测试垫；
    其中，所述阵列基板进一步包括扇出走线区，所述扇出走线区和所述COF绑定区设置在所述显示区域的同一侧，所述测试区设置于所述COF绑定区和所述扇出走线区之间；
    其中，所述测试垫在所述测试区呈“一”字型均匀排列。
  2. 根据权利要求1所述的阵列基板，其中，所述测试区包括依次设置在基板上的缓冲层、第一无机绝缘层、第二无机绝缘层和第一金属层，其中，所述第一金属层包括间隔设置的多个所述测试垫。
  3. 一种阵列基板，其中，所述阵列基板包括显示区域、围绕所述显示区域的非显示区域、COF绑定区和测试区；
    其中，所述COF绑定区和所述测试区间隔设置于所述非显示区域；
    其中，所述测试区包括间隔设置的多个测试垫。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板进一步包括扇出走线区，所述扇出走线区和所述COF绑定区设置在所述显示区域的同一侧，所述测试区设置于所述COF绑定区和所述扇出走线区之间。
  5. 根据权利要求4所述的阵列基板，其中，所述测试区包括依次设置在基板上的缓冲层、第一无机绝缘层、第二无机绝缘层和第一金属层，其中，所述第一金属层包括间隔设置的多个所述测试垫。
  6. 根据权利要求5所述的阵列基板，其中，所述测试区进一步包括有机隔绝层，所述有机隔绝层覆盖多个所述测试垫。
  7. 根据权利要求3所述的阵列基板，其中，所述COF绑定区和所述测试区设置在所述显示区域的相对两侧。
  8. 根据权利要求7所述的阵列基板，其中，所述测试区包括依次设置在基板上的缓冲层、第一无机绝缘层、第二无机绝缘层、第一金属层和有机隔绝层；
    其中，所述第一金属层包括位于所述测试区的多个所述测试垫；
    其中，所述有机隔绝层包括多个第一开口，以通过所述第一开口暴露出多个所述测试垫。
  9. 根据权利要求8所述的阵列基板，其中，所述测试区进一步包括设置在所述有机隔绝层上的第二金属层；
    所述第一金属层进一步包括与所述测试垫间隔设置的信号线；
    所述信号线通过所述第二金属层与阴极层连接；
    所述第二金属层包括多个与所述第一开口对应设置的第二开口，以通过多个所述第二开口和所述第一开口暴露出多个所述测试垫。
  10. 根据权利要求9所述的阵列基板，其中，所述信号线为向所述阴极层提供电压的电源信号线。
  11. 根据权利要求3所述的阵列基板，其中，所述测试垫在所述测试区呈“一”字型均匀排列。
  12. 一种OLED显示面板，其中，所述OLED显示面板包括阵列基板，所述阵列基板包括显示区域、围绕所述显示区域的非显示区域、COF绑定区和测试区；
    其中，所述COF绑定区和所述测试区间隔设置于所述非显示区域；
    其中，所述测试区包括间隔设置的多个测试垫。
  13. 根据权利要求12所述的OLED显示面板，其中，所述阵列基板进一步包括扇出走线区，所述扇出走线区和所述COF绑定区设置在所述显示区域的同一侧，所述测试区设置于所述COF绑定区和所述扇出走线区之间。
  14. 根据权利要求13所述的OLED显示面板，其中，所述测试区包括依次设置在基板上的缓冲层、第一无机绝缘层、第二无机绝缘层和第一金属层，其中，所述第一金属层包括间隔设置的多个所述测试垫。
  15. 根据权利要求14所述的OLED显示面板，其中，所述测试区进一步包括有机隔绝层，所述有机隔绝层覆盖多个所述测试垫。
  16. 根据权利要求12所述的OLED显示面板，其中，所述COF绑定区和所述测试区设置在所述显示区域的相对两侧。
  17. 根据权利要求16所述的OLED显示面板，其中，所述测试区包括依次设置在基板上的缓冲层、第一无机绝缘层、第二无机绝缘层、第一金属层和有机隔绝层；
    其中，所述第一金属层包括位于所述测试区的多个所述测试垫；
    其中，所述有机隔绝层包括多个第一开口，以通过所述第一开口暴露出多个所述测试垫。
  18. 根据权利要求17所述的OLED显示面板，其中，所述测试区进一步包括设置在所述有机隔绝层上的第二金属层；
    所述第一金属层进一步包括与所述测试垫间隔设置的信号线；
    所述信号线通过所述第二金属层与阴极层连接；
    所述第二金属层包括多个与所述第一开口对应设置的第二开口，以通过多个所述第二开口和所述第一开口暴露出多个所述测试垫。
  19. 根据权利要求18所述的OLED显示面板，其中，所述信号线为向所述阴极层提供电压的电源信号线。
  20. 根据权利要求12所述的OLED显示面板，其中，所述测试垫在所述测试区呈“一”字型均匀排列。
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