WO2019173624A1 - A method for si gap fill by pecvd - Google Patents

A method for si gap fill by pecvd Download PDF

Info

Publication number
WO2019173624A1
WO2019173624A1 PCT/US2019/021205 US2019021205W WO2019173624A1 WO 2019173624 A1 WO2019173624 A1 WO 2019173624A1 US 2019021205 W US2019021205 W US 2019021205W WO 2019173624 A1 WO2019173624 A1 WO 2019173624A1
Authority
WO
WIPO (PCT)
Prior art keywords
amorphous silicon
silicon layer
substrate
feature
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2019/021205
Other languages
English (en)
French (fr)
Inventor
Xin Liu
Fei Wang
Rui CHENG
Abhijit Basu Mallick
Robert Jan Visser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to CN201980023731.9A priority Critical patent/CN112335032B/zh
Priority to KR1020207028877A priority patent/KR102714970B1/ko
Priority to SG11202008150VA priority patent/SG11202008150VA/en
Priority to US16/975,794 priority patent/US11361991B2/en
Priority to JP2020546333A priority patent/JP7319288B2/ja
Publication of WO2019173624A1 publication Critical patent/WO2019173624A1/en
Anticipated expiration legal-status Critical
Priority to US17/839,170 priority patent/US11848232B2/en
Priority to JP2023117932A priority patent/JP7580540B2/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/01—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes on temporary substrates, e.g. substrates subsequently removed by etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536—Use of plasma, radiation or electromagnetic fields
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps

Definitions

  • Embodiments of the present disclosure relate to methods of forming gap fill materials on a substrate.
  • STI shallow trench isolation
  • ILD inter-metal dielectric layers
  • PMD pre-metal dielectrics
  • passivation layers patterning applications, etc.
  • Gap fill materials may be deposited by various deposition processes, for example fiowable chemical vapor deposition (FCVD).
  • FCVD fiowable chemical vapor deposition
  • the as-deposited gap fill materials by FCVD are usually of poor quality, characterized by high wet etch rate ratio (WERR) and high stress, and require subsequent processes, such as curing and/or annealing, to improve the quality of the gap fill materials.
  • WERR wet etch rate ratio
  • subsequent processes such as curing and/or annealing
  • a method includes heating a substrate disposed in a process chamber to a temperature ranging from about 150 degrees Celsius to about 650 degrees Celsius, flowing a silane-containing precursor into the process chamber, and depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate and a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer and a second portion of each sidewall is exposed. The method further includes removing the second amorphous silicon layer.
  • a method in another embodiment, includes heating a substrate disposed in a process chamber to a temperature ranging from about 200 degrees Celsius to about 550 degrees Celsius, flowing silane or disiiane into the process chamber, forming a plasma in the process chamber, and depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate and a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer and a second portion of each sidewall is exposed.
  • a method in another embodiment, includes depositing a first amorphous silicon layer on a bottom of a feature formed in a substrate and a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer and a second portion of each sidewall is exposed.
  • the depositing the first and second amorphous silicon layers includes heating the substrate disposed in a process chamber to a temperature ranging from about 150 degrees Celsius to about 650 degrees Celsius, and flowing a silane-containing precursor into the process chamber.
  • the method further includes removing the second amorphous silicon layer, and repeating the depositing the first and second amorphous silicon layers and removing the second amorphous silicon layer until the feature is filled with amorphous silicon.
  • Figures 1A - 1 F schematically illustrate a process for forming gap fill materials on a substrate according to one embodiment described herein.
  • Embodiments of the present disclosure relate to processes for filling trenches.
  • the process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed.
  • the first amorphous silicon layer is removed.
  • the process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer.
  • the third amorphous silicon layer is removed.
  • the deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers.
  • a “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process.
  • a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application.
  • Substrates include, without limitation, semiconductor wafers.
  • Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxyiate, anneal and/or bake the substrate surface.
  • any of the film processing steps disclosed may also be performed on an under- layer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such under-layer as the context indicates.
  • the exposed surface of the newly deposited fiim/layer becomes the substrate surface.
  • Figures 1A - 1 F schematically illustrate a process for forming gap fill materials on a substrate according to one embodiment described herein.
  • a substrate 100 includes a feature 102.
  • the Figures show substrates having a single feature for illustrative purposes; however, those skilled in the art will understand that there can be more than one feature.
  • the shape of the feature 102 can be any suitable shape including, but not limited to, trenches and cylindrical vias.
  • the term “feature” means any intentional surface irregularity. Suitable examples of features include, but are not limited to trenches and vias which have a bottom and two sidewalls.
  • Features can have any suitable aspect ratio (ratio of the depth of the feature to the width of the feature).
  • the aspect ratio is greater than or equal to about 5:1 , 10: 1 , 15:1 , 20:1 , 25: 1 , 30: 1 , 35:1 or 40: 1.
  • the substrate 100 includes a surface 101 , and the feature 102 is an opening formed in the surface 101.
  • the substrate 100 includes a STI region that is fabricated from a dielectric material, such as silicon oxide or silicon nitride, and the feature 102 is formed in the STI region.
  • the feature 102 includes a bottom 104 and sidewalls 106.
  • a first amorphous silicon layer 108 is deposited on the bottom 104 of the feature 102, and a second amorphous silicon layer 1 10 is deposited on the surface 101 of the substrate 100.
  • the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 are deposited by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the PECVD process for depositing the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 includes flowing a silicon-containing precursor into a process chamber, and forming a plasma in the process chamber in one embodiment, the process chamber is the Producer® XP PrecisionTM chamber, available from Applied Materials Inc. of Santa Clara, California.
  • the plasma may be formed in-situ or in a remote location and then flowed into the process chamber.
  • the silicon- containing precursor may be a silane-containing precursor, such as silane, disiiane, trisiiane, or tetrasiiian.
  • the silicon-containing precursor is a lower order silane-containing precursor, such as silane or disiiane.
  • the plasma power density ranges from about 0.14 W/cm 2 to about 2.83 W/cm 2
  • the processing temperature i.e., the temperature of the substrate during processing, ranges from about 150 degrees Celsius to about 650 degrees Celsius, for example 200 degrees Celsius to about 550 degrees Celsius if has been discovered that when a silane-containing precursor, such as a lower order silane-containing precursor, is used at the above mentioned processing conditions, the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 as deposited are not flowable.
  • first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 are not flowable, material is not disposed on the sidewalls 106 during the deposition process, likelihood of bridging of sidewall material (and corresponding void formation) is reduced.
  • the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 as deposited have improved quality compared to the fiowable amorphous silicon layer. Furthermore, no subsequent curing and/or annealing processes are necessary.
  • the first amorphous silicon layer 108 is formed on the bottom 104 of the feature 102 and in contact with a first portion 1 12 of each sidewall 106. A second portion 1 14 of each sidewall 106 is exposed and not covered by the first amorphous silicon layer 108.
  • the second amorphous silicon layer 1 10 which is formed simultaneously as the first amorphous silicon layer 108, is formed on the surface 101 and not on the second portion 1 14 of each sidewall 106 of the feature 102.
  • the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 are formed on the bottom 104 and the surface 101 , respectively, and the bottom 104 is substantially parallel to the surface 101
  • the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 form on substantially parallel surfaces and have generally the same thickness or approximately the same thicknesses.
  • the first amorphous silicon layer 108 and the second amorphous silicon layer 1 10 form on horizontal surfaces, while not forming on vertical surfaces.
  • the only portion of the sidewall 106 (vertical surface) that is covered is the portion that corresponds to the thickness of the first amorphous silicon layer 108 that is disposed on the bottom 104
  • the second amorphous silicon layer 1 10 is removed from the surface 101
  • the removal process may be a plasma etch process that is performed in the same process chamber as the process chamber in which the first and second amorphous silicon layers 108, 1 10 are formed.
  • the chamber pressure of the plasma etch process may be the same as the chamber pressure during the PECVD process or different from the chamber pressure during the PECVD process.
  • the processing temperature may be the same processing temperature as the PECVD process that deposits the first and second amorphous siiicon layers 108, 110. Utilization of the same process temperature for the deposition and etch processes facilitates rapid transition between deposition and etch processes, which increases substrate throughput.
  • the plasma power density ranges from about 0.14 W/cm 2 to about 2.83 W/cm 2
  • the second amorphous siiicon layer 1 10 is removed while the first amorphous siiicon layer 108 is substantially unaffected because plasma ions losing energy due to collision to the sidewalls 106, radicals quenched/ioss before reaching the bottom 104, and/or the plasma power density is controlled to minimize ion bombardment to the bottom 104.
  • the etchant used for the removal process may be any suitable etchant in one embodiment, the removal process is a physical plasma etch process, and the etchant used is helium.
  • the removal process is a chemical plasma etch process using a halogen containing etchant, such as a fluorine- or chlorine-containing etchant or hydrogen gas as the etchant, and the plasma is formed remotely.
  • a halogen containing etchant such as a fluorine- or chlorine-containing etchant or hydrogen gas as the etchant
  • the halogen containing etchant and the hydrogen gas have a high selectivity of etching amorphous silicon over the material of the substrate 100, for example silicon oxide
  • the removal process is a physical and chemical plasma etch process using a halogen containing etchant or hydrogen gas as the etchant, and the plasma is formed in-situ, such as a capacitively coupled plasma.
  • a second PECVD process is performed to form a third amorphous siiicon layer 1 16 on the first amorphous siiicon layer 108 and a fourth amorphous silicon layer 1 18 on the surface 101 , as shown in Figure 1 D.
  • the second PECVD process may be performed under the same process conditions as the PECVD process for forming the first and second amorphous siiicon layers 108, 1 10.
  • the third amorphous silicon layer 1 16 is in contact with a portion 120 of each sidewall 106, and a portion 122 of each sidewall 106 is exposed.
  • the third and fourth amorphous silicon layers 1 16, 1 18 have the same properties as the first and second amorphous silicon layers 108, 1 10, respectively.
  • the fourth amorphous silicon layer 1 18 is removed from the surface 101.
  • the removal process may be the same as the removal process for removing the second amorphous silicon layer 1 10.
  • the feature 102 is filled with the first amorphous silicon layer 108 and the third amorphous silicon layer 1 16.
  • the entire bottom 104 is in contact with the first amorphous silicon layer 108 and the entire sidewalls 106 are in contact with the first amorphous silicon layer 108 and the third amorphous silicon layer 1 16.
  • additional deposition/removal cyclic processes may be performed to fill the feature 102.
  • additional amorphous silicon layers 124, 126, 128 are deposited on the third amorphous silicon layer 1 16, and no amorphous silicon layer is left remaining on the surface 101 as the result of the removal processes followed by each deposition process. Because the plasma power for the removal process is low, ion bombardment info the feature 102 is minimized. Furthermore, the feature 102 is overfilled at the last deposition process of the deposition/remova! cycles, and the last removal process removes the amorphous silicon layers on the surface 101 and over the feature 102. For each deposition/removal cycle (one cycle includes one deposition process and one removal process), the ratio of deposition time to the etch time may range from about 1 to 3 to about 1 to 16.
  • the etch time is substantially longer than the deposition time.
  • the number of cycles depends on the depth of the feature 102 and/or the thickness of each amorphous silicon layer deposited in the feature 102. In one embodiment, the number of deposition/removal cycles ranges from about 60 to about 200, and the thickness of each amorphous silicon layer formed during a respective deposition cycle is between about 250 Angstroms to about 1000 Angstroms.
  • the multiple amorphous silicon layers 108, 1 16, 124, 126, 128 formed in the feature 102 are formed from bottom up. Thus, there is no seam, or void, formed in the amorphous silicon layers 108, 1 16, 124, 126, 128.
  • a feature such as a trench
  • a feature can be filled seamlessly from bottom up.
  • the amorphous silicon layers formed in the feature is not flowable, the quality of the amorphous silicon layers are improved over the conventional flowable amorphous silicon gap fill.
  • subsequent curing and/or annealing processes typically performed after forming the flowable amorphous silicon gap fill are not necessary.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Chemical Vapour Deposition (AREA)
PCT/US2019/021205 2018-03-09 2019-03-07 A method for si gap fill by pecvd Ceased WO2019173624A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN201980023731.9A CN112335032B (zh) 2018-03-09 2019-03-07 用于通过PECVD进行Si间隙填充的方法
KR1020207028877A KR102714970B1 (ko) 2018-03-09 2019-03-07 Pecvd에 의한 si 갭 충전을 위한 방법
SG11202008150VA SG11202008150VA (en) 2018-03-09 2019-03-07 A method for si gap fill by pecvd
US16/975,794 US11361991B2 (en) 2018-03-09 2019-03-07 Method for Si gap fill by PECVD
JP2020546333A JP7319288B2 (ja) 2018-03-09 2019-03-07 Ｐｅｃｖｄによるｓｉギャップ充填の方法
US17/839,170 US11848232B2 (en) 2018-03-09 2022-06-13 Method for Si gap fill by PECVD
JP2023117932A JP7580540B2 (ja) 2018-03-09 2023-07-20 Ｐｅｃｖｄによるｓｉギャップ充填の方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862640853P 2018-03-09 2018-03-09
US62/640,853 2018-03-09

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/975,794 A-371-Of-International US11361991B2 (en) 2018-03-09 2019-03-07 Method for Si gap fill by PECVD
US17/839,170 Division US11848232B2 (en) 2018-03-09 2022-06-13 Method for Si gap fill by PECVD

Publications (1)

Publication Number Publication Date
WO2019173624A1 true WO2019173624A1 (en) 2019-09-12

Family

ID=67845756

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2019/021205 Ceased WO2019173624A1 (en) 2018-03-09 2019-03-07 A method for si gap fill by pecvd

Country Status (6)

Country Link
US (2) US11361991B2 (https=)
JP (2) JP7319288B2 (https=)
KR (1) KR102714970B1 (https=)
CN (1) CN112335032B (https=)
SG (1) SG11202008150VA (https=)
WO (1) WO2019173624A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7319288B2 (ja) * 2018-03-09 2023-08-01 アプライド マテリアルズ インコーポレイテッド Ｐｅｃｖｄによるｓｉギャップ充填の方法
US20240420950A1 (en) * 2023-06-14 2024-12-19 Applied Materials, Inc. Densified seam-free silicon-containing material gap fill processes
US20250125145A1 (en) * 2023-10-11 2025-04-17 Applied Materials, Inc. Methods to improve oxide sidewall quality
WO2025248744A1 (ja) * 2024-05-31 2025-12-04 東京エレクトロン株式会社 埋め込み方法及び成膜装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030162363A1 (en) * 2002-02-22 2003-08-28 Hua Ji HDP CVD process for void-free gap fill of a high aspect ratio trench
US20040079632A1 (en) * 2002-10-23 2004-04-29 Applied Materials, Inc. High density plasma CVD process for gapfill into high aspect ratio features
KR20120099243A (ko) * 2009-12-09 2012-09-07 노벨러스 시스템즈, 인코포레이티드 신규한 갭 충진 집적화
WO2014107290A1 (en) * 2013-01-02 2014-07-10 Applied Materials, Inc. Silicon nitride gapfill implementing high density plasma
US20140248754A1 (en) * 2013-03-04 2014-09-04 Applied Materials Inc. Controlled air gap formation

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer
US4676847A (en) * 1985-01-25 1987-06-30 American Telephone And Telegraph Company At&T Bell Laboratories Controlled boron doping of silicon
JP3222615B2 (ja) * 1993-03-31 2001-10-29 株式会社東芝 表面処理装置
JP2565131B2 (ja) * 1994-04-22 1996-12-18 日本電気株式会社 半導体装置の製造方法
JP2636796B2 (ja) * 1995-05-24 1997-07-30 日本電気株式会社 半導体装置の製造方法
US6670235B1 (en) * 2001-08-28 2003-12-30 Infineon Technologies Ag Process flow for two-step collar in DRAM preparation
JP5692763B2 (ja) * 2010-05-20 2015-04-01 東京エレクトロン株式会社 シリコン膜の形成方法およびその形成装置
US10011920B2 (en) * 2011-02-23 2018-07-03 International Business Machines Corporation Low-temperature selective epitaxial growth of silicon for device integration
US8940388B2 (en) * 2011-03-02 2015-01-27 Micron Technology, Inc. Insulative elements
CN104163398B (zh) * 2013-05-17 2017-02-08 无锡华润上华半导体有限公司 半导体器件中深槽的填充结构及其填充方法
JP6267374B2 (ja) * 2013-07-31 2018-01-24 東京エレクトロン株式会社 シリコン膜の成膜方法
JP6082712B2 (ja) * 2013-07-31 2017-02-15 東京エレクトロン株式会社 シリコン膜の成膜方法および薄膜の成膜方法
CN105336670B (zh) * 2014-07-14 2018-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
JP6392683B2 (ja) * 2015-02-18 2018-09-19 東京エレクトロン株式会社 凹部を充填する方法及び処理装置
US9565488B2 (en) * 2015-05-20 2017-02-07 Infineon Technologies Ag Micro-electro-mechanical system devices
TWI715645B (zh) * 2015-10-22 2021-01-11 美商應用材料股份有限公司 正形及縫隙填充非晶矽薄膜的沉積
US10115601B2 (en) * 2016-02-03 2018-10-30 Tokyo Electron Limited Selective film formation for raised and recessed features using deposition and etching processes
JP6541591B2 (ja) * 2016-03-07 2019-07-10 東京エレクトロン株式会社 凹部内の結晶成長方法および処理装置
US10192775B2 (en) 2016-03-17 2019-01-29 Applied Materials, Inc. Methods for gapfill in high aspect ratio structures
WO2017223323A1 (en) * 2016-06-25 2017-12-28 Applied Materials, Inc. Flowable amorphous silicon films for gapfill applications
JP6606476B2 (ja) * 2016-08-02 2019-11-13 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
JP7319288B2 (ja) * 2018-03-09 2023-08-01 アプライド マテリアルズ インコーポレイテッド Ｐｅｃｖｄによるｓｉギャップ充填の方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030162363A1 (en) * 2002-02-22 2003-08-28 Hua Ji HDP CVD process for void-free gap fill of a high aspect ratio trench
US20040079632A1 (en) * 2002-10-23 2004-04-29 Applied Materials, Inc. High density plasma CVD process for gapfill into high aspect ratio features
KR20120099243A (ko) * 2009-12-09 2012-09-07 노벨러스 시스템즈, 인코포레이티드 신규한 갭 충진 집적화
WO2014107290A1 (en) * 2013-01-02 2014-07-10 Applied Materials, Inc. Silicon nitride gapfill implementing high density plasma
US20140248754A1 (en) * 2013-03-04 2014-09-04 Applied Materials Inc. Controlled air gap formation

Also Published As

Publication number Publication date
US11361991B2 (en) 2022-06-14
US20200411371A1 (en) 2020-12-31
JP2021515405A (ja) 2021-06-17
KR102714970B1 (ko) 2024-10-07
CN112335032B (zh) 2025-04-11
US20220310448A1 (en) 2022-09-29
CN112335032A (zh) 2021-02-05
SG11202008150VA (en) 2020-09-29
US11848232B2 (en) 2023-12-19
JP7319288B2 (ja) 2023-08-01
JP2023145565A (ja) 2023-10-11
JP7580540B2 (ja) 2024-11-11
KR20200120750A (ko) 2020-10-21

Similar Documents

Publication Publication Date Title
KR102722942B1 (ko) 순차적인 증착-에칭-처리 프로세싱을 사용한 실리콘 산화물 및 실리콘 질화물의 상향식 성장
US11848232B2 (en) Method for Si gap fill by PECVD
TWI744522B (zh) 高深寬比結構中的間隙填充的方法
KR101615814B1 (ko) 얕은 트렌치 격리 구조물의 형성 방법
US20120282756A1 (en) Thin Film Filling Method
US20130260564A1 (en) Insensitive dry removal process for semiconductor integration
WO2019036158A1 (en) METHOD OF FORMING A BARRIER LAYER FOR INTERCONNECTION HOLE APPLICATIONS
WO2018038922A1 (en) Manufacturing methods to protect ulk materials from damage during etch processing to obtain desired features
TW202140837A (zh) 低溫無蒸汽氧化物間隙填充
KR102860754B1 (ko) 자체 정렬 다중 패턴화에서 스페이서 프로파일을 재성형하기 위한 방법
KR20040100767A (ko) 저압 실리콘 질화막 형성 방법
CN105931982A (zh) 制造浅沟槽隔离的方法以及使用浅沟槽隔离的半导体结构
KR20230129520A (ko) Cd 의존 갭 충전 및 컨포멀 막들
KR20160146565A (ko) 갭 충진 애플리케이션들에서 실리콘 다이옥사이드 막의 원자층 증착에서의 심들을 제거하기 위한 시스템들 및 방법들
CN102157430B (zh) 形成浅沟槽隔离结构的方法
CN107026113B (zh) 半导体装置的制造方法和系统
CN104851834A (zh) 一种半导体器件的制备方法
US20120220130A1 (en) Method for fabricating semiconductor device
JP2000100926A (ja) 半導体装置の製造方法及び半導体装置
CN112750753A (zh) 半导体器件及其制作方法
KR19980077341A (ko) 반도체소자의 소자분리막 형성방법
KR20080013269A (ko) 반도체 소자 제조를 위한 박막형성방법
KR20080074660A (ko) 반도체 소자의 트렌치 매립방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19765130

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020546333

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20207028877

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 19765130

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 201980023731.9

Country of ref document: CN