WO2019159736A1 - 基板処理装置 - Google Patents

基板処理装置 Download PDF

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Publication number
WO2019159736A1
WO2019159736A1 PCT/JP2019/003826 JP2019003826W WO2019159736A1 WO 2019159736 A1 WO2019159736 A1 WO 2019159736A1 JP 2019003826 W JP2019003826 W JP 2019003826W WO 2019159736 A1 WO2019159736 A1 WO 2019159736A1
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WO
WIPO (PCT)
Prior art keywords
exposure
substrate
processing
resist
time
Prior art date
Application number
PCT/JP2019/003826
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English (en)
French (fr)
Japanese (ja)
Inventor
真任 田所
正志 榎本
志村　悟
真一路 川上
Original Assignee
東京エレクトロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Priority to JP2020500399A priority Critical patent/JP7117366B2/ja
Publication of WO2019159736A1 publication Critical patent/WO2019159736A1/ja

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C—APPARATUS FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C11/00—Component parts, details or accessories not specifically provided for in groups B05C1/00 - B05C9/00
    • B05C11/02—Apparatus for spreading or distributing liquids or other fluent materials already applied to a surface ; Controlling means therefor; Control of the thickness of a coating by spreading or distributing liquids or other fluent materials already applied to the coated surface
    • B05C11/08—Spreading liquid or other fluent material by manipulating the work, e.g. tilting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C—APPARATUS FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C13/00—Means for manipulating or holding work, e.g. for separate articles
    • B05C13/02—Means for manipulating or holding work, e.g. for separate articles for particular articles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C—APPARATUS FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05C9/00—Apparatus or plant for applying liquid or other fluent material to surfaces by means not covered by any preceding group, or in which the means of applying the liquid or other fluent material is not important
    • B05C9/08—Apparatus or plant for applying liquid or other fluent material to surfaces by means not covered by any preceding group, or in which the means of applying the liquid or other fluent material is not important for applying liquid or other fluent material and performing an auxiliary operation
    • B05C9/14—Apparatus or plant for applying liquid or other fluent material to surfaces by means not covered by any preceding group, or in which the means of applying the liquid or other fluent material is not important for applying liquid or other fluent material and performing an auxiliary operation the auxiliary operation involving heating or cooling
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

Definitions

  • the present invention relates to a substrate processing apparatus that performs predetermined processing on a substrate.
  • a resist coating process for coating a resist solution on a wafer to form a resist film an exposure process for exposing the resist film to a predetermined pattern, and developing the exposed resist film
  • a series of processing such as development processing is sequentially performed to form a predetermined resist pattern on the wafer.
  • These series of processes are performed by a coating / development processing apparatus, which is a substrate processing apparatus equipped with various processing units for processing wafers and a transport mechanism for transporting wafers, and an exposure apparatus connected to the coating / development processing apparatus. ing.
  • a resist film has been formed in order to eliminate the waiting time of the exposure apparatus, that is, to fully operate the exposure apparatus. It has been required that the wafer be carried into the exposure apparatus without interruption. Therefore, the processes up to the exposure process such as the resist coating process are sequentially performed on the wafer in the coating and developing processing apparatus, and the wafers for which the processes before the exposure process are completed are kept waiting at a predetermined place until the exposure process starts.
  • the exposure apparatus is fully operated by adjusting the time from the end of the process before the exposure process to the start of the exposure process. For example, when the configuration as disclosed in Patent Document 1 is adopted, the predetermined place where the wafer is waiting is the standby portion of the interface block.
  • Patent Document 1 does not disclose this point.
  • the present invention has been made in view of the above circumstances, and provides a substrate processing apparatus capable of obtaining a desired resist film pattern even with a resist film requiring a long exposure time or a resist film having a large film thickness. Is the purpose.
  • One embodiment of the present invention that solves the above problems is a substrate processing apparatus that performs a series of processes for forming a resist pattern on a substrate, including a resist coating process in which a resist solution is applied to form a resist film.
  • a plurality of processing units that perform the series of processing, a standby unit that temporarily waits for a substrate before the series of processing is performed, and a control unit that controls at least the transfer of the substrate, The unit obtains information on the time of the exposure process performed on the substrate on which the resist film is formed in the exposure apparatus to which the substrate is transferred from the substrate processing apparatus, and the exposure process is started from the resist coating process.
  • the standby unit waits for the substrate so that the time until completion is constant for each substrate.
  • Another embodiment of the present invention is a substrate processing apparatus that performs a series of processes for forming a resist pattern on a substrate, including a resist coating process in which a resist solution is applied to form a resist film.
  • a plurality of processing units that perform a series of processing, and a control unit that controls at least the transfer of the substrate, the control unit has a time length during which the substrate stays in each of the plurality of processing units, Control of substrate transport so that the length of time that the substrate stays in each of the multiple processing units is equal to the length of time that the substrate stays in the exposure apparatus that performs exposure processing on the substrate on which the resist film is formed To do.
  • a desired resist film pattern can be obtained even with a resist film requiring a long exposure time or a resist film having a large thickness.
  • FIG. 1 is an explanatory diagram showing an outline of the configuration of the substrate processing apparatus according to the first embodiment.
  • 2 and 3 are a front view and a rear view, respectively, schematically showing an outline of the internal configuration of the substrate processing system.
  • the substrate processing apparatus in the present embodiment is a coating and developing processing apparatus that performs resist coating processing and development processing.
  • a resist film for EUV (Extreme Ultra-Violet) lithography is formed as a resist film that requires a long exposure time.
  • a resist film having a thickness of 10 ⁇ m or more, such as a resist film used for manufacturing a 3D NAND type semiconductor device is formed as a resist film having a large thickness.
  • a resist film for EUV lithography is referred to as an “EUV resist film”
  • a resist solution used for forming the EUV resist film is referred to as an “EUV resist solution”.
  • the substrate processing apparatus 1 includes a cassette station 10 into which a cassette C containing a plurality of wafers W is loaded and unloaded, and a processing station 11 having a plurality of various processing units that perform predetermined processing on the wafers W. And an interface station 13 that transfers the wafer W to and from the exposure apparatus 12 adjacent to the processing station 11 is integrally connected.
  • the exposure apparatus 12 of this example performs an exposure process using EUV light.
  • the cassette station 10 is provided with a cassette mounting table 20.
  • the cassette mounting table 20 is provided with a plurality of cassette mounting plates 21 on which the cassette C is mounted when the cassette C is carried into and out of the substrate processing apparatus 1.
  • the cassette station 10 is provided with a wafer transfer mechanism 23 that is movable on a transfer path 22 extending in the X direction.
  • the wafer transfer mechanism 23 is also movable in the vertical direction and the vertical axis ( ⁇ direction), and includes a cassette C on each cassette mounting plate 21 and a delivery unit of a third block G3 of the processing station 11 described later.
  • the wafer W can be transferred between the two.
  • the processing station 11 is provided with a plurality of, for example, first to fourth four blocks G1, G2, G3, and G4.
  • the first block G1 is provided on the front side of the processing station 11 (X direction negative direction side in FIG. 1), and the second block is provided on the back side of the processing station 11 (X direction positive direction side in FIG. 1).
  • Block G2 is provided.
  • a third block G3 is provided on the cassette station 10 side (Y direction negative direction side in FIG. 2) of the processing station 11, and the interface station 13 side (Y direction positive direction side in FIG. 1) of the processing station 11 is provided. Is provided with a fourth block G4.
  • a plurality of liquid processing units for example, a development processing unit 30 that develops the wafer W exposed by the exposure apparatus 12, and an EUV resist solution is applied to the wafer W and EUV resist liquid is applied.
  • a resist coating processing section 31 for forming a resist film is provided side by side in the vertical direction and the horizontal direction. The number and arrangement of the development processing unit 30 and the resist coating processing unit 31 can be arbitrarily selected.
  • spin coating for coating a predetermined coating solution on the wafer W is performed.
  • the coating liquid is discharged onto the wafer W from a coating nozzle, and the wafer W is rotated to diffuse the coating liquid to the surface of the wafer W, so that the coating liquid is applied to the entire surface of the wafer W.
  • a heat treatment unit 40 for performing heat treatment such as heating and cooling of the wafer W and an adhesion unit 41 for improving the fixability between the resist solution and the wafer W are provided in the vertical direction. They are arranged side by side in the horizontal direction. The number and arrangement of the heat treatment units 40 and the adhesion units 41 can be arbitrarily selected.
  • the heat treatment unit 40 performs pre-baking (PAB) processing, which is a heat treatment for the wafer W after resist coating and before exposure, post-baking processing, which is a heat treatment for the wafer W after development processing, and heating the wafer W before development after exposure processing.
  • PAB pre-baking
  • PEB post-exposure bake
  • a plurality of delivery units 50, 51, 52, 53, 54, 55, and 56 are provided in order from the bottom.
  • the fourth block G4 is provided with a plurality of delivery units 60, 61, 62 in order from the bottom.
  • the delivery units 50 to 56 and 60 to 62 can function as standby units for waiting the wafer W.
  • a wafer transfer area D is formed in an area surrounded by the first block G1 to the fourth block G4.
  • a plurality of wafer transfer mechanisms 70 having transfer arms 70a that are movable in the Y direction, X direction, ⁇ direction, and vertical direction are arranged.
  • the wafer transfer mechanism 70 moves in the wafer transfer area D, and transfers the wafer W to a predetermined portion in the surrounding first block G1, second block G2, third block G3, and fourth block G4. it can.
  • the shuttle transport mechanism 80 is linearly movable, for example, in the Y direction in FIG.
  • the shuttle transfer mechanism 80 moves in the Y direction while supporting the wafer W, and can transfer the wafer W between the transfer unit 52 of the third block G3 and the transfer unit 62 of the fourth block G4.
  • a wafer transfer mechanism 100 is provided next to the third block G3 on the positive side in the X direction.
  • the wafer transfer mechanism 100 has a transfer arm 100a that is movable in the X direction, the ⁇ direction, and the vertical direction, for example.
  • the wafer transfer mechanism 100 can move up and down while the wafer W is supported by the transfer arm 100a, and can transfer the wafer W to each transfer section in the third block G3.
  • the interface station 13 is provided with a wafer transfer mechanism 110 and a delivery unit 111.
  • the wafer transfer mechanism 110 has a transfer arm 110a that is movable in the Y direction, the ⁇ direction, and the vertical direction, for example.
  • the wafer transfer mechanism 110 supports, for example, the wafer W on the transfer arm 110a, and between each transfer unit 60, 61, 62 and the exposure apparatus 12 in the fourth block G4, or between the transfer unit 111 and the exposure apparatus 12.
  • the wafer W can be transferred between the two.
  • the above substrate processing apparatus 1 is provided with a control unit 200 as shown in FIG.
  • the control unit 200 is a computer, for example, and has a program storage unit (not shown).
  • the program storage unit stores a program for controlling the processing of the wafer W in the substrate processing apparatus 1.
  • the program storage unit also stores a program for controlling the operation of the drive system such as the above-described various processing units and the transport mechanism to realize processing in the substrate processing apparatus 1.
  • the program is recorded on a computer-readable storage medium H such as a computer-readable hard disk (HD), a flexible disk (FD), a compact disk (CD), a magnetic optical desk (MO), or a memory card. May have been installed in the control unit 200 from the storage medium.
  • HD computer-readable hard disk
  • FD flexible disk
  • CD compact disk
  • MO magnetic optical desk
  • the control unit 200 is communicably connected to the control unit 300 of the exposure apparatus 12 and can acquire information related to the exposure process in the exposure apparatus 12 from the control unit 300.
  • the control unit 300 of the exposure apparatus 12 controls the exposure apparatus 12, and, like the control unit 200, is configured from, for example, a computer and includes a program storage unit.
  • the wafers W in the cassette C carried into the cassette station 10 of the substrate processing apparatus 1 are sequentially transferred to the transfer unit 53 of the processing station 11 and set in a standby state.
  • the wafer W is transferred to the resist coating processing section 31 of the first block G1. Then, an EUV resist film is formed on the wafer W by the resist coating processing unit 31. Thereafter, the wafer W is transferred to the heat treatment unit 40. Then, the PAB process is performed on the wafer W on which the resist film is formed by the heat treatment unit 40. Next, the wafer W is transferred to the delivery unit 60 of the fourth block G4 and is set in a standby state.
  • the wafer W is transferred to a predetermined loading position in the exposure apparatus 12.
  • exposure processing is performed on the wafer W after processing before exposure processing such as transfer processing from the predetermined loading position to the exposure processing position is performed.
  • the wafer W is subjected to a post-exposure process such as a transfer process from the exposure process position to a predetermined unloading position.
  • the wafer W is transferred from the predetermined unloading position of the exposure apparatus 12 to the heat treatment unit 40 of the substrate processing apparatus 1. Then, the PEB process is performed on the wafer W by the heat treatment unit 40. Next, the wafer W is transferred to the development processing unit 30. Then, development processing is performed on the wafer W by the development processing unit 30.
  • the wafer W is transferred to the heat treatment unit 40. Then, the post-baking process is performed on the wafer W by the heat treatment unit 40. Thereafter, the wafer W is transferred to the cassette C of the cassette mounting plate 21, and a series of photolithography steps is completed.
  • the above processing is performed by the substrate processing apparatus 1 of the present embodiment and the conventional substrate processing apparatus. Further, the substrate processing apparatus 1 of this embodiment and the conventional substrate processing apparatus can adopt the same structure itself, but the control by the control unit 200 is different, specifically, the transfer timing of the wafer W. Is different. Hereinafter, this point will be described. In addition, since the same structure can be employ
  • FIG. 4 is a time chart of conventional wafer processing.
  • the first processed wafer among the wafers is “# 1”
  • the second processed wafer is “# 2”
  • numbers are assigned in the order of processing.
  • the wafer W is in the same state, it is shown in the same color, and the portion described as “CPL” indicates a state where the wafer W stays in the delivery unit 53 of the processing station 11.
  • COT indicates a state in which the wafer W stays in the resist coating processing unit 31.
  • PAB indicates a state in which the wafer W stays in the heat treatment unit 40 for PAB processing
  • ICPL indicates a state in which the wafer W stays in the delivery unit 60 of the fourth block G4. Yes.
  • Before exposure is a state in which a process before the exposure process in the exposure apparatus 12 is being performed
  • Exposure is a state in which the exposure process is being performed
  • After exposure is a process after the exposure process in the exposure apparatus 12
  • PEB indicates a state in which the wafer W stays in the heat treatment section 40 for PEB processing. The other portions indicate the state where the wafer W is being transferred.
  • the processing time before the exposure processing in the exposure apparatus 12 is lengthened as in # 2, or the first time as in # 5.
  • the time for the wafer W to stay in the transfer unit 60 of the fourth block G4 is lengthened, or the time for transporting from the PAB processing heat treatment unit 40 to the transfer unit 60 is increased as in # 6. Therefore, in the conventional wafer processing, the time from the resist coating process to the start of the exposure process differs for each wafer W. In this case, according to studies by the present inventors, when an EUV resist film is used, a desired resist pattern may not be obtained.
  • FIG. 5 is a conceptual diagram showing the state of the EUV resist film and the state of reaction from the end of the coating process to the end of the development process when an EUV resist film is used.
  • a negative type metal-containing resist solution is used as the EUV resist solution
  • the ligand L of the metal complex in the EUV resist film F1 is hydrolyzed in the exposed portion of the film during the exposure process.
  • the hydrolyzed metal complex becomes a metal oxide film F2 by dehydration condensation, and remains when the metal oxide film F2 is developed using the developer J.
  • the unexposed portion of the EUV resist film F1 during the exposure process reacts with water in the atmosphere when heated by the PEB process, and is flowed by the developer J during the development process.
  • the unexposed portion of the EUV resist film F1 reacts with water without heating.
  • moisture exists in the atmosphere around the wafer W from the resist coating process to the start of the exposure process. Therefore, a portion that is exposed by the exposure process and should remain as a resist pattern after development may become soluble in the developer J as a result of being exposed to an atmosphere containing moisture, and may not remain as a resist pattern after development.
  • EUV light because the exposure time is long, the difference between the wafers W in the time from the resist coating process to the start of the exposure process may become very large. It grows big.
  • FIG. 6 is a time chart of wafer processing according to the present embodiment. 6 is illustrated in the same manner as FIG.
  • the control unit 200 acquires information related to the exposure processing time in the exposure apparatus 12 for the n-th wafer W. Specifically, for example, information on the end time of the exposure process in the exposure apparatus 12 for the n-th wafer W is acquired from the control unit 300 of the exposure apparatus 12. Next, based on the acquired information, the control unit 200 makes the time from the resist coating process to the start of the exposure process constant for each wafer W as shown in FIG. The length of time for which the wafer W is made to wait on the transfer unit 53 of the processing station 11 is adjusted / determined.
  • control unit 200 may determine the waiting time length.
  • control unit 200 acquires information on the time length of the exposure process in the exposure apparatus 12 so that the time length for which the transfer unit 53 of the processing station 11 waits is equal to the time length of the exposure process. Good.
  • FIG. 7 is a conceptual diagram showing the state of the thick film and the state of reaction from the end of the coating process to the end of the development process when a resist film having a large thickness (hereinafter referred to as a thick film) is used.
  • the exposure amount in the exposure process in the exposure apparatus 12 is not described above, the pattern of the resist film subjected to the exposure process and the development process based on the information related to the exposure process already performed in the exposure apparatus 12 is described.
  • the size may be predicted, and the control unit 200 may output a control signal to the control unit 300 of the exposure apparatus 12 so that the exposure amount is corrected based on the prediction result.
  • the information related to the exposure process performed by the exposure apparatus 12 is, for example, information related to the time of the exposure process in the first embodiment and information related to the length of time spent in the exposure apparatus 12 in the second embodiment. .
  • the exposure amount is corrected so that the predicted pattern dimension becomes the target pattern dimension. This correction is performed, for example, for each lot, and specifically, the prediction result for a certain lot is fed back to the exposure amount of the next lot.
  • the processing conditions during the PEB processing for the wafer W and the processing conditions (development temperature and development time) during the development processing for the wafer W may be feedforward controlled.
  • a line width (CD: Critical Dimension), which is an example of the dimension of the resist pattern, can be expressed as a linear function from the resist coating process to the start of the exposure process. Such feedforward control is possible.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Paper (AREA)
  • Coating Apparatus (AREA)
PCT/JP2019/003826 2018-02-16 2019-02-04 基板処理装置 WO2019159736A1 (ja)

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JP2018026455 2018-02-16
JP2018-026455 2018-02-16

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JPH09283424A (ja) * 1996-04-10 1997-10-31 Canon Inc 露光システム
JPH10270316A (ja) * 1997-03-25 1998-10-09 Nec Corp 電子線露光装置及びレジスト塗布現像装置並びにレジストパターン形成方法
JP2001338865A (ja) * 2000-05-30 2001-12-07 Nec Corp 半導体露光方法及び半導体製造装置
JP2003272991A (ja) * 2002-03-12 2003-09-26 Semiconductor Leading Edge Technologies Inc 露光及びレジスト塗布現像方法並びに装置
JP2006165187A (ja) * 2004-12-06 2006-06-22 Dainippon Screen Mfg Co Ltd 基板処理装置
JP2007250746A (ja) * 2006-03-15 2007-09-27 Tokyo Ohka Kogyo Co Ltd 厚膜レジスト膜の形成方法およびレジストパターン形成方法
JP2008205394A (ja) * 2007-02-22 2008-09-04 Canon Inc 露光装置、製造システム及びデバイスの製造方法

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JP2003022964A (ja) 2001-07-10 2003-01-24 Nikon Corp デバイス製造方法およびデバイス製造装置
JP2005317686A (ja) 2004-04-28 2005-11-10 Matsushita Electric Ind Co Ltd レジスト処理方法およびレジスト処理装置
JP2010141063A (ja) 2008-12-11 2010-06-24 Panasonic Corp 半導体基板の露光方法及び半導体装置製造システム
JP2011221225A (ja) 2010-04-08 2011-11-04 Ushio Inc 露光方法および露光装置
JP5588469B2 (ja) * 2012-02-09 2014-09-10 東京エレクトロン株式会社 基板処理装置
JP5886935B1 (ja) * 2014-12-11 2016-03-16 東京エレクトロン株式会社 塗布処理方法、コンピュータ記憶媒体及び塗布処理装置
JP6352230B2 (ja) * 2015-10-09 2018-07-04 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記録媒体
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Publication number Priority date Publication date Assignee Title
JPH09283424A (ja) * 1996-04-10 1997-10-31 Canon Inc 露光システム
JPH10270316A (ja) * 1997-03-25 1998-10-09 Nec Corp 電子線露光装置及びレジスト塗布現像装置並びにレジストパターン形成方法
JP2001338865A (ja) * 2000-05-30 2001-12-07 Nec Corp 半導体露光方法及び半導体製造装置
JP2003272991A (ja) * 2002-03-12 2003-09-26 Semiconductor Leading Edge Technologies Inc 露光及びレジスト塗布現像方法並びに装置
JP2006165187A (ja) * 2004-12-06 2006-06-22 Dainippon Screen Mfg Co Ltd 基板処理装置
JP2007250746A (ja) * 2006-03-15 2007-09-27 Tokyo Ohka Kogyo Co Ltd 厚膜レジスト膜の形成方法およびレジストパターン形成方法
JP2008205394A (ja) * 2007-02-22 2008-09-04 Canon Inc 露光装置、製造システム及びデバイスの製造方法

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JP7117366B2 (ja) 2022-08-12
JPWO2019159736A1 (ja) 2021-01-28
TW201940242A (zh) 2019-10-16
TWI804574B (zh) 2023-06-11

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