WO2019134475A1 - 薄膜晶体管及其制备方法以及阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法以及阵列基板和显示装置 Download PDF

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WO2019134475A1
WO2019134475A1 PCT/CN2018/119099 CN2018119099W WO2019134475A1 WO 2019134475 A1 WO2019134475 A1 WO 2019134475A1 CN 2018119099 W CN2018119099 W CN 2018119099W WO 2019134475 A1 WO2019134475 A1 WO 2019134475A1
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layer
insulating layer
light shielding
active layer
forming
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PCT/CN2018/119099
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English (en)
French (fr)
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班圣光
曹占锋
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京东方科技集团股份有限公司
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Priority to US16/618,936 priority Critical patent/US20200144297A1/en
Publication of WO2019134475A1 publication Critical patent/WO2019134475A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, an array substrate, and a display device.
  • LTPS low temperature poly-silicon
  • a-Si amorphous silicon
  • a thin film transistor including: a light shielding layer; a first insulating layer; an active layer, the first insulating layer being disposed between the light shielding layer and the active layer; An insulating layer; a gate, the second insulating layer is disposed between the gate and the active layer, the active layer includes a source region and a drain region; an interlayer insulating layer; a source and a drain a pole, respectively connected to the source region and the drain region of the active layer; and at least one conductive connection member for respectively shielding the light shielding layer from at least one of the source region and the drain region Connected.
  • the at least one electrically conductive connection comprises two electrically conductive connections, each passing through the first insulating layer to connect the light shielding layer to the source region and the drain, respectively Area.
  • the at least one electrically conductive connection comprises two electrically conductive connections, each passing through the first insulating layer to connect the respective light shielding layers to the source and the drain, respectively.
  • the at least one electrically conductive connection passes through the first insulating layer to connect at least one portion of the light shielding layer to at least one of the source region and the drain region or to connect To at least one of the source and the drain.
  • the light shielding layer comprises amorphous silicon. In some embodiments, the active layer comprises polysilicon.
  • the first insulating layer is on the light shielding layer; the active layer is on the first insulating layer; the second insulating layer is on the active layer; a pole is disposed on the second insulating layer; the interlayer insulating layer is located on the gate; the source and the drain are respectively connected to the active layer and the light shielding layer through corresponding via holes
  • the via hole penetrates through the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer;
  • the at least one conductive connection member includes two conductive connectors respectively disposed at The via holes are formed integrally with the source electrode and the drain electrode, respectively.
  • the first insulating layer is on the gate; the active layer is on the first insulating layer; the second insulating layer is on the active layer; a layer is disposed on the second insulating layer; the interlayer insulating layer is located on the light shielding layer; and the source electrode and the drain electrode are respectively connected to the active layer and the light shielding layer through via holes
  • the via hole penetrates through the interlayer insulating layer, the light shielding layer and the second insulating layer;
  • the at least one conductive connection member includes two conductive connectors respectively disposed in the via holes, and respectively A unitary structure is formed with each of the source electrode and the drain electrode.
  • the thin film transistor further includes: a light transmissive substrate layer disposed on one side of the light transmissive substrate layer.
  • each of the vias includes a first sub via and a second sub via, the first sub via penetrating through the interlayer insulating layer and the second insulating layer to the a source layer, and a lateral dimension of the first sub-via is greater than a lateral dimension of the corresponding second sub-via.
  • a method of fabricating a thin film transistor comprising: providing a multilayer structure including a light shielding layer, a first insulating layer, and an active layer, wherein the first insulating layer is disposed on the light shielding layer and Between the active layers; forming a second insulating layer covering the active layer, and forming a gate on the second insulating layer; forming a layer over the gate and the second insulating layer Inter-insulating layer; forming a first via hole and a second via hole, each of the first via hole and the second via hole penetrating through the interlayer insulating layer, the second insulating layer, the active layer, a first insulating layer; a source electrode and a drain electrode, wherein the source electrode and the drain electrode fill the first via and the second via, respectively, and pass the first pass The hole and the second via are electrically connected to the active layer and the light shielding layer.
  • the forming the first via and the second via comprises: forming two first sub vias penetrating the interlayer insulating layer and the second insulating layer; forming through the active a layer and two second sub-vias of the first insulating layer.
  • the lateral dimension of the first sub-via is greater than the lateral dimension of the corresponding second sub-via.
  • forming the first via and the second via comprises: forming a patterned mask on the interlayer insulating layer; performing a first etching process using the mask to form a through-cut
  • the two openings of the interlayer insulating layer, the second insulating layer, the active layer and the first insulating layer are such that a part of the surface of the light shielding layer is exposed; and the mask is subjected to a shrinkage treatment,
  • a second etching process is performed using the reduced mask such that at least the lateral dimensions of the respective portions of the two openings above the active layer are enlarged.
  • the light shielding layer comprises amorphous silicon
  • the active layer comprises polysilicon
  • the light shielding layer is configured to block light to prevent light from being incident on the active layer.
  • providing a multilayer structure including a light shielding layer, a first insulating layer, and an active layer includes forming the multilayer structure on a light transmissive substrate layer.
  • a method of fabricating a thin film transistor comprising: providing a multilayer structure including a gate electrode, a first insulating layer, and an active layer, wherein the first insulating layer is disposed at the gate electrode and Between the active layers; forming a second insulating layer covering the active layer; forming a light shielding layer on the second insulating layer; forming an interlayer on the light shielding layer and the second insulating layer An insulating layer; a first via hole and a second via hole are formed, each of the first via hole and the second via hole penetrating through the interlayer insulating layer, the light shielding layer, and the second insulating layer to respectively Exposing a portion of the surface of the active layer; forming a source electrode and a drain electrode, the source electrode and the drain electrode filling the first via and the second via, respectively, and The first via and the second via are electrically connected to the active layer and the light shielding layer.
  • forming the first via and the second via comprises: forming a patterned mask on the forming an interlayer insulating layer; performing an etching process using the mask to form through the The first via and the second via of the interlayer insulating layer, the light shielding layer, and the second insulating layer.
  • the light shielding layer comprises amorphous silicon
  • the active layer comprises polysilicon
  • the light shielding layer is configured to block light to prevent light from being incident on the active layer.
  • providing a multilayer structure including a gate layer, a first insulating layer, and an active layer includes forming the multilayer structure on a light transmissive substrate layer.
  • an array substrate comprising a plurality of thin film transistors according to any of the embodiments of the present application arranged in an array.
  • a display device including the array substrate according to any of the embodiments of the present application is provided.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present application.
  • FIG. 2A is a schematic structural view of a thin film transistor according to an embodiment of the present application.
  • 2B is a schematic structural view of a thin film transistor according to another embodiment of the present application.
  • FIG. 3 is a block diagram showing the structure of a thin film transistor according to an embodiment of the present application.
  • FIG. 4 shows an exemplary flow chart of a method of fabricating a thin film transistor according to an embodiment of the present application
  • FIG. 5A shows an exemplary flowchart of a method of fabricating a thin film transistor according to an embodiment of the present application
  • FIG. 5B illustrates an exemplary flowchart of forming a via according to an embodiment of the present application
  • FIG. 5C illustrates An exemplary flow chart for forming a via of one embodiment is applied;
  • FIG. 6A shows an exemplary flowchart of a method of fabricating a thin film transistor according to an embodiment of the present application
  • FIG. 6B illustrates an exemplary flowchart of forming a via according to an embodiment of the present application
  • FIG. 7 shows an exemplary block diagram of a display device in accordance with one embodiment of the present application.
  • the light shielding layer is affected by the gate voltage when the thin film transistor operates, and generates an induced charge on the surface close to the gate.
  • the light shielding layer is isolated on the array substrate, causing the induced charge to be eliminated or requiring a relatively long time to be eliminated. Therefore, the channel region of the active layer of the thin film transistor is affected, causing the threshold voltage drift of the thin film transistor.
  • the inventors of the present application have proposed a novel thin film transistor, a method of fabricating the same, an array substrate, and a display device in view of the above-mentioned drawbacks or deficiencies in the prior art.
  • the induced charge of the light shielding layer can be effectively eliminated, and the characteristics of the thin film transistor can be improved.
  • the manufacturing cost can be reduced.
  • a thin film transistor which may include: a light shielding layer; a first insulating layer; an active layer, the first insulating layer being disposed on the light shielding layer and the active layer between.
  • the thin film transistor may further include: a second insulating layer; a gate, the second insulating layer being disposed between the gate and the active layer, the active layer may include a source region and a drain a region; an interlayer insulating layer; a source electrode and a drain electrode, respectively connected to the source region and the drain region of the active layer.
  • the thin film transistor may further include: at least one conductive connection for connecting the light shielding layer to at least one of the source region and the drain region, respectively.
  • the at least one conductive connector can include two conductive connectors, each passing through the first insulating layer to connect the light shielding layer to the source region and the drain, respectively. Polar zone.
  • the at least one conductive connector includes two conductive connectors, each passing through the first insulating layer to connect the light shielding layer to the source and the drain, respectively.
  • the thin film transistor may further include: at least one conductive connection through the first insulating layer to connect at least one portion of the light shielding layer to the source region and the drain At least one of the regions is connected to at least one of the source electrode and the drain electrode.
  • the at least one electrically conductive connection can include two electrically conductive connections that each form a unitary structure with the source and drain electrodes.
  • the conductive connections can be corresponding to the source electrode or a portion of the drain electrode, respectively. It should be understood that the present disclosure is not limited thereto.
  • FIG. 1 shows a schematic structural view of a thin film transistor according to an embodiment of the present application.
  • the thin film transistor can be used in a display panel (for example, a liquid crystal display panel).
  • a thin film transistor comprising: a light shielding layer 12, a first insulating layer 13, an active layer 14, a second insulating layer 15, a gate electrode 16, an interlayer insulating layer 17, and an active layer.
  • the source 18 and the drain 19 are respectively connected to the source 14; the source 18 and the drain 19 are also connected to the light shielding layer 12.
  • the light shielding layer 12, the first insulating layer 13, the active layer 14, the second insulating layer 15, the gate 16, the interlayer insulating layer 17, the source 18 and the drain 19 may each be located on the substrate layer. 11 on.
  • Figure 1 shows a transistor of a top gate structure. The positional relationship between the respective layers is not limited to that shown in FIG.
  • the thin film transistor can also be a bottom gate structure or other structure.
  • the first insulating layer 13, the second insulating layer 15, and the interlayer insulating layer 17 may each include an insulating material such as any one of the following: silicon oxide, silicon nitride, a mixture of the two, and the like.
  • one or more of the first insulating layer 13, the second insulating layer 15, and the interlayer insulating layer 17 may be configured to allow light to pass therethrough.
  • the light shielding layer may include amorphous silicon.
  • the active layer may include polysilicon.
  • the light shielding layer may be configured to block light to prevent light from being incident on the active layer.
  • a voltage for example, a positive voltage
  • a negative charge is induced on the side of the active layer near the gate side, and away from the gate side.
  • a positive charge is induced on one side.
  • the thickness of the insulating layer between the light shielding layer and the active layer is usually small, so that the side of the light shielding layer close to the side of the active layer may induce a negative charge, thereby affecting the charge distribution of the active layer when the next thin film transistor operates, so that The threshold voltage is biased.
  • P-type transistors except that the polarity of the induced charge is reversed.
  • the source/drain electrodes are connected to the active layer while being connected to the light shielding layer, the induced charges of the light shielding layer can be derived. Thereby, the influence of the light-sensitive layer induced charge on the thin film transistor can be avoided. It also improves the stability of the threshold voltage of the thin film transistor. Therefore, the performance of the thin film transistor is improved.
  • the active region may include a channel formation region and a source region and a drain region adjacent to the channel formation region, respectively.
  • the channel formation region corresponds to the gate and is used to form a channel therein.
  • the gate voltage reverses some or all of the conductivity types of the channel formation regions in the active region, thereby forming a channel.
  • the source region corresponds to and is connected to the source electrode.
  • the drain region corresponds to and is connected to the drain electrode.
  • the material of the light shielding layer is, for example, but not limited to, a silicon simple substance or an oxide semiconductor.
  • the silicon element may be, for example, but not limited to, a non-transparent silicon elemental material such as single crystal silicon or amorphous silicon.
  • the oxide semiconductor may be, for example, but not limited to, a non-transparent oxide semiconductor material such as alumina or titania.
  • the substrate layer can comprise a light transmissive substrate such as a glass substrate.
  • the substrate layer can include other types of substrates.
  • the base layer may further include a substrate and other functional layers on the substrate, such as a buffer layer or the like.
  • the source/drain electrodes are connected to the active layer while being connected to the light shielding layer, so that the potential of the light shielding layer can be relatively stabilized.
  • the source drain electrode and the amorphous silicon light shielding layer are connected, but the surface in contact with the amorphous silicon layer does not form an ohmic contact. Therefore, no channel is formed in the amorphous silicon.
  • the resistance of amorphous silicon is generally large. Therefore, the presence of the amorphous silicon light shielding layer does not cause a significant increase in the leakage current of the thin film transistor. After the thin film transistor is turned off, the OFF current can be on the order of E -12 or even lower.
  • the material of the active layer may be polysilicon.
  • the first insulating layer is located on the light shielding layer; the active layer is on the first insulating layer; the second insulating layer is on the active layer; the gate is on the second insulating layer; the interlayer insulating layer is located at the gate
  • the source and the drain are respectively connected to the active layer and the light shielding layer through the via hole; the via hole penetrates the interlayer insulating layer, the second insulating layer, the active layer and the first insulating layer.
  • the light shielding layer 12, the first insulating layer 13, the active layer 14, the second insulating layer 15, the gate 16, the interlayer insulating layer 17, the source 18 and the drain 19 may be formed as shown in FIG.
  • the bottom-up stacked positional relationship is shown, that is, it can be a top gate structure.
  • a via hole (not indicated by a reference numeral in the drawing) penetrates the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer.
  • the vias can have any suitable shape and size.
  • a portion of each of the source and the drain is filled in the corresponding via, as shown in the figure, to form the aforementioned conductive connectors, respectively.
  • the at least one conductive connection member may include two conductive connectors, which are respectively a part of each of the source electrode and the drain electrode, and are respectively disposed in corresponding via holes.
  • FIG. 2A is a schematic view showing the structure of a thin film transistor according to another embodiment of the present application.
  • each via 28 (29) can include a first sub via 281 (291) and a second sub via 282 (292).
  • the first sub via 281 (291) penetrates the interlayer insulating layer and the second insulating layer
  • the second sub via 282 (292) penetrates the active layer and the first insulating layer.
  • each via actually includes two sub vias, which can reduce the process difficulty, while increasing the contact area between the source and drain and the active layer, and improving the characteristics of the thin film transistor. It will be appreciated that the vias may include two or more sub vias.
  • the lateral dimension of the first sub-via is greater than the lateral dimension of the corresponding second sub-via.
  • the thin film transistor may include: a light shielding layer 12; a first insulating layer 13; and an active layer 14, the first insulating layer being disposed between the light shielding layer and the active layer.
  • the thin film transistor may further include: a second insulating layer 15; a gate electrode 16, the second insulating layer being disposed at least between the gate electrode and the active layer, the active layer may include a source region And a drain region; an interlayer insulating layer 17; a source electrode 18/19 and a drain electrode 19/18, and a source region and a drain region of the active layer (not indicated by reference numerals in the drawing) Connect separately.
  • the thin film transistor may further include: at least one conductive connection 201/203 passing through the first insulating layer to connect at least one portion of the light shielding layer to the source region and the drain region At least one of them.
  • first conductive connector 201 and a second conductive connector 203 two conductive connectors are shown: a first conductive connector 201 and a second conductive connector 203. In other embodiments, more or fewer conductive connectors may be included.
  • first conductive connection 201 and the second conductive connection 203 are disposed at positions away from the end faces in the first insulating layer 13, the present disclosure is not limited thereto.
  • first conductive connection 201 and the second conductive connection 203 may be disposed near an end or end in the first insulating layer 13.
  • the materials and processes for the first conductive connecting member 201 and the second conductive connecting member 203 are not particularly limited as long as they are compatible with the employed process for forming a thin film transistor.
  • doped Poly-Si polysilicon
  • FIG. 3 shows a schematic structural view of a thin film transistor according to an embodiment of the present application.
  • the first insulating layer 33 is on the gate 32; the active layer 34 is on the first insulating layer 33; the second insulating layer 35 is on the active layer 34; the light shielding layer 36 Located on the second insulating layer 35; the interlayer insulating layer 37 is located on the light shielding layer 36; the source 38 and the drain electrode 39 are respectively connected to the active layer 34 and the light shielding layer 36 through via holes; the via holes penetrate the interlayer insulating layer 37.
  • a light shielding layer 36 and a second insulating layer 35 is provided.
  • the gate electrode 32, the first insulating layer 33, the active layer 34, the second insulating layer 35, the light shielding layer 36, the interlayer insulating layer 37, the source electrode 38 and the drain electrode 39 may be formed as shown in FIG.
  • the bottom-up stacked positional relationship is shown. That is, the thin film transistor is a bottom gate structure.
  • a via (not indicated by a reference numeral in the drawing) penetrates the interlayer insulating layer and the second insulating layer. Thereby the via exposes a portion of the active layer.
  • the vias can have any suitable shape and size.
  • the at least one conductive connection member may include two conductive connectors, which are respectively a part of each of the source electrode and the drain electrode, and are respectively disposed in corresponding via holes.
  • the vias may include two or more sub vias.
  • FIG. 4 shows a method of fabricating a thin film transistor provided by an embodiment of the present application.
  • the method can include one or more of the following steps.
  • Step S10 forming a multilayer structure of a light shielding material layer, a first insulating material layer, and an active material layer.
  • the light shielding material layer may be formed on the base substrate by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
  • the first insulating material layer and the material source layer may be sequentially formed on the light shielding material layer by the PEVCD method.
  • Step S20 The multilayer structure is processed by one patterning process to form a light shielding layer and an active layer.
  • the multilayer structure formed in step S10 may be etched by one patterning process to form a light shielding layer, a first insulating layer, and an active layer.
  • Step S30 forming a second insulating layer.
  • the second insulating layer can be formed on the active using a PECVD method.
  • Step S40 forming a gate.
  • the gate material layer may be formed by sputtering on the second insulating layer, and then the gate electrode may be formed by one patterning process.
  • Step S50 forming an interlayer insulating layer.
  • an interlayer insulating layer may be formed on the gate using a PECVD method.
  • Step S60 forming a first via hole and a second via hole penetrating the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer.
  • the first via and the second via may be formed by one-step etching or may be formed by multi-step etching.
  • the multi-step etching may include: first forming an inter-layer insulating layer, a second insulating layer, an active layer, a first intermediate via of the first insulating layer, and a second intermediate via by etching; Etching widens the vias of the first intermediate via and the second intermediate via through the interlayer insulating layer and the second insulating layer portion. Thereby, the effect of increasing the contact area between the source and the drain and the active layer is achieved.
  • step S60 further includes:
  • two first sub vias are formed through the interlayer insulating layer and the second insulating layer, two second sub vias that penetrate the active layer and the first insulating layer are formed.
  • Step S70 forming a source and a drain, and the source and the drain are connected to the first active layer and the light shielding layer through the first via and the second via, respectively.
  • the light shielding layer and the active layer can be formed by one patterning process, which reduces the patterning process and reduces the generation cost.
  • the source and the drain are connected to the light shielding layer, and the light shielding layer is induced The charge is conducted to an external circuit.
  • the first via and the second via that penetrate the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer may be formed by etching by one mask formation, thereby Simplifies the process, reduces manufacturing costs, and/or increases production efficiency.
  • the influence of the induced charge of the light shielding layer can be alleviated or eliminated, the stability of the threshold voltage is improved, and the characteristics of the thin film transistor are improved.
  • FIG. 5A illustrates an exemplary flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present application.
  • a multilayer structure including a light shielding layer, a first insulating layer, and an active layer is provided.
  • the first insulating layer is disposed between the light shielding layer and the active layer.
  • step S503 a second insulating layer covering the active layer is formed, and a gate is formed on the second insulating layer.
  • step S505 an interlayer insulating layer is formed over the gate electrode and the second insulating layer.
  • step S507 a first via and a second via are formed.
  • the first via and the second via each penetrate the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer.
  • a source electrode and a drain electrode are formed.
  • the source electrode and the drain electrode fill the first via and the second via, respectively.
  • the source electrode and the drain electrode are electrically connected to the active layer and the light shielding layer through the first via and the second via.
  • FIG. 5B illustrates an exemplary flow chart for forming vias in accordance with one embodiment of the present application.
  • the first via and the second via may be formed by.
  • a patterned mask is formed on the interlayer insulating layer.
  • a first etching process is performed using the mask to form two openings penetrating through the interlayer insulating layer, the second insulating layer, the active layer, and the first insulating layer to Part of the surface of the light shielding layer is exposed.
  • the mask is subjected to a reduction process to form a reduced mask.
  • a second etching process is performed using the reduced mask such that the lateral dimension of each of the at least two openings above the active layer is enlarged (as can be seen from FIG. 2A).
  • FIG. 5C illustrates an exemplary flow chart for forming vias in accordance with another embodiment of the present application.
  • the first via and the second via may also be formed in the following manner.
  • step S519 two first sub vias penetrating the interlayer insulating layer and the second insulating layer are formed.
  • step S521 two second sub vias penetrating the active layer and the first insulating layer are formed.
  • FIG. 6A illustrates an exemplary flow chart of a method of fabricating a thin film transistor in accordance with another embodiment of the present application.
  • a multilayer structure including a gate electrode, a first insulating layer, and an active layer is provided.
  • the first insulating layer is disposed between the gate and the active layer.
  • a second insulating layer covering the active layer is formed.
  • a light shielding layer is formed on the second insulating layer.
  • an interlayer insulating layer is formed over the light shielding layer and the second insulating layer.
  • a first via and a second via are formed.
  • the first via hole and the second via hole each penetrate the interlayer insulating layer, the light shielding layer, and the second insulating layer to respectively expose a part of the surface of the active layer.
  • a source electrode and a drain electrode are formed.
  • the source electrode and the drain electrode fill the first via and the second via, respectively.
  • the source electrode and the drain electrode are electrically connected to the active layer and the light shielding layer through the first via and the second via.
  • FIG. 6B illustrates an exemplary flow chart for forming vias in accordance with one embodiment of the present application.
  • the first via and the second via may be formed by.
  • a patterned mask is formed on the formation of the interlayer insulating layer.
  • an etching process is performed using the mask to form the first via and the second via extending through the interlayer insulating layer, the light shielding layer, and the second insulating layer.
  • etchants, processes, and the like can be selected for different materials to be etched during the etching process.
  • FIG. 7 shows an exemplary block diagram of a display device in accordance with one embodiment of the present application.
  • an embodiment of the present application further provides an array substrate, including a plurality of thin film transistors provided in an array according to any embodiment of the present application.
  • the embodiment of the present application further provides a display device, which includes the array substrate provided by the embodiments of the present application.
  • a novel thin film transistor is provided.
  • the charge induced by the light shielding layer can be conducted to an external circuit, and the influence of the induced charge of the light shielding layer can be alleviated or eliminated, and the stability of the threshold voltage can be improved.
  • the performance of the thin film transistor can be improved.

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Abstract

一种薄膜晶体管及其制备方法以及阵列基板和显示装置。该薄膜晶体管，包括：遮光层(12)；第一绝缘层(13)；有源层(14)，所述第一绝缘层(13)设置在所述遮光层(12)和所述有源层(14)之间；第二绝缘层(15)；栅极(16)，所述第二绝缘层(15)设置在所述栅极(16)和所述有源层(14)之间，所述有源层(14)包括源极区和漏极区；层间绝缘层(17)；源极(18)和漏极(19)，与所述有源层(14)的源极区和漏极区分别连接；以及至少一个导电连接件(201/203)，穿过所述第一绝缘层(13)以将所述遮光层(12)的至少一个部分连接到所述源极区和所述漏极区中的至少一个或者连接到所述源极(18)和所述漏极(19)中的至少一个。

Description

薄膜晶体管及其制备方法以及阵列基板和显示装置
相关申请的交叉引用
本申请要求与2018年1月2日提交的中国专利申请No.201810001897.8的优先权，通过引用将其全文并入在此。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
随着显示技术的发展，低温多晶硅(Low Temperature Poly-silicon，LTPS)技术越来越受到广泛的重视。由于LTPS技术其能够实现器件的高迁移率以及可以实现阵列基板栅极驱动(Gate Driver on Array，GOA)，因此基于该技术的显示面板相比于非晶硅(a-Si)技术的显示面板在开口率、亮度及反应速度等方面具有更加优良的显示效果。
发明内容
根据本公开一个方面，提供了一种薄膜晶体管，包括：遮光层；第一绝缘层；有源层，所述第一绝缘层设置在所述遮光层和所述有源层之间；第二绝缘层；栅极，所述第二绝缘层设置在所述栅极和所述有源层之间，所述有源层包括源极区和漏极区；层间绝缘层；源极和漏极，与所述有源层的源极区和漏极区分别连接；以及至少一个导电连接件，用于将所述遮光层分别与所述源极区和所述漏极区中的至少一个相连。
在一些实施例中，所述至少一个导电连接件包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极区和所述漏极区。
在一些实施例中，所述至少一个导电连接件包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极和所述漏极。
在一些实施例中，所述至少一个导电连接件穿过所述第一绝缘层以将所述遮光层的至少一个部分连接到所述源极区和所述漏极区中的至少一个或者连接到所述源极和所述漏极中的至少一个。
在一些实施例中，所述遮光层包括非晶硅。在一些实施例中，所述有源层包括多晶硅。
在一些实施例中：所述第一绝缘层位于所述遮光层上；所述有源层位于所述第一绝缘层上；所述第二绝缘层位于所述有源层上；所述栅极位于所示第二绝缘层上；所述层间绝缘层位于所述栅极上；所述源极和所述漏极分别通过对应的过孔与所述有源层和所述遮光层连接；所述过孔贯穿所述层间绝缘层、所述第二绝缘层、所述有源层和所述第一绝缘层；所述至少一个导电连接件包括两个导电连接件，分别设置在所述过孔中，并且分别与所述源极电极和所述漏极电极形成一体结构。
在一些实施例中：所述第一绝缘层位于所述栅极上；所述有源层位于所述第一绝缘层上；所述第二绝缘层位于所述有源层上；所述遮光层位于所示第二绝缘层上；所述层间绝缘层位于所述遮光层上；所述源极电极和所述漏极电极分别通过过孔与所述有源层和所述遮光层连接；所述过孔贯穿所述层间绝缘层、所述遮光层和所述第二绝缘层；所述至少一个导电连接件包括两个导电连接件，分别设置在所述过孔中，并且分别与所述源极电极和所述漏极电极各自的一部分形成一体结构。
在一些实施例中，所述薄膜晶体管还包括：透光基底层，所述遮光层设置在所述透光基底层的一侧上。
在一些实施例中：每个所述过孔包括第一子过孔和第二子过孔，所述第一子过孔贯穿所述层间绝缘层和所述第二绝缘层到所述有源层，并且所述第一子过孔的横向尺寸大于对应的第二子过孔的横向尺寸。
根据本公开一个方面，提供了一种薄膜晶体管的制备方法，包括：提供包括遮光层、第一绝缘层和有源层的多层结构，其中所述第一绝缘层设置在所述遮光层和所述有源层之间；形成覆盖所述有源层的第二绝缘层，并在所述第二绝缘层上形成栅极；在所述栅极和所述第二绝缘层之上形成层间绝缘层；形成第一过孔和第二过孔，所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所述第二绝缘层、所述有源层、所述第一绝缘层；形成源极电极和漏极电极，所述源极电极和所述漏极电极分别填充所述第一过孔和所述第二过孔，并通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
在一些实施例中，所述形成第一过孔和第二过孔包括：形成贯穿所述层间绝缘层和所述第二绝缘层的两个第一子过孔；形成贯穿所述有源层和所述第一绝缘层的两个第二子过孔。
在一些实施例中，所述第一子过孔的横向尺寸大于对应的第二子过孔的横向尺寸。
在一些实施例中，形成所述第一过孔和第二过孔包括：在所述层间绝缘层上形成图案化的掩模；利用所述掩模进行第一蚀刻处理，以形成贯穿所述层间绝缘层、所述第二绝缘层、所述有源层和所述第一绝缘层的两个开口，以使得所述遮光层的部分表面露出；对所 述掩模进行减缩处理，以形成减缩的掩模；利用减缩的掩模进行第二蚀刻处理，以使得至少所述两个开口各自的在所述有源层之上的部分的横向尺寸被扩大。
在一些实施例中，所述遮光层包括非晶硅，所述有源层包括多晶硅，所述遮光层被配置用于遮挡光以避免光入射到所述有源层。
在一些实施例中，提供包括遮光层、第一绝缘层和有源层的多层结构包括：在透光基底层上形成所述多层结构。
根据本公开一个方面，提供了一种薄膜晶体管的制备方法，包括：提供包括栅极、第一绝缘层和有源层的多层结构，其中所述第一绝缘层设置在所述栅极和所述有源层之间；形成覆盖所述有源层的第二绝缘层；在所述第二绝缘层上形成遮光层；在所述遮光层和所述第二绝缘层之上形成层间绝缘层；形成第一过孔和第二过孔，所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所述遮光层、所述第二绝缘层，以分别露出所述有源层的部分表面；形成源极电极和漏极电极，所述源极电极和所述漏极电极分别填充所述第一过孔和所述第二过孔，并通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
在一些实施例中，形成所述第一过孔和第二过孔包括：在所述形成层间绝缘层上形成图案化的掩模；利用所述掩模进行蚀刻处理，以形成贯穿所述层间绝缘层、所述遮光层和所述第二绝缘层的所述第一过孔和第二过孔。
在一些实施例中，所述遮光层包括非晶硅，所述有源层包括多晶硅，所述遮光层被配置用于遮挡光以避免光入射到所述有源层。
在一些实施例中，提供包括栅极层、第一绝缘层和有源层的多层结构包括：在透光基底层上形成所述多层结构。
根据本公开一个方面，提供了一种阵列基板，包括阵列设置的多个如本申请任一实施例所述的薄膜晶体管。
根据本公开一个方面，提供了一种显示装置，包括如本申请任意实施例所述的阵列基板。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1示出了根据本申请一实施例的薄膜晶体管的结构示意图；
图2A示出了根据本申请一实施例的薄膜晶体管的结构示意图；
图2B示出了根据本申请另一实施例的薄膜晶体管的结构示意图；
图3示出了根据本申请一实施例的薄膜晶体管的结构示意图；以及
图4示出了根据本申请一个实施例的薄膜晶体管制备方法的示例性流程图；
图5A示出了根据本申请一个实施例的薄膜晶体管制备方法的示例性流程图，图5B示出了根据本申请一个实施例的形成过孔的示例性流程图，图5C示出了根据本申请一个实施例的形成过孔的示例性流程图；
图6A示出了根据本申请一个实施例的薄膜晶体管制备方法的示例性流程图，图6B示出了根据本申请一个实施例的形成过孔的示例性流程图；以及
图7示出了根据本申请一个实施例的显示装置的示例性框图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性连接或信号连接，不管是直接的还是间接的。
在现有的LTPS工艺中，往往需要制作遮光层来避免有源层受到光照而影响薄膜晶体管的开关性能。本申请的发明人发现，遮光层在薄膜晶体管工作时会受到栅极电压的影响，在其靠近栅极的表面产生感应电荷。而遮光层在阵列基板上被隔离设置，造成感应电荷无法消除或者需要相对长的时间来消除。因此，会影响薄膜晶体管有源层的沟道区域，造成薄膜晶体管阈值电压漂移。
本申请的发明人鉴于对于现有技术中的上述缺陷或不足的认识，提出了提供一种新颖的薄膜晶体管及其制备方法、阵列基板、显示装置。根据本公开的技术，可以有 效排除遮光层的感应电荷，改善薄膜晶体管特性。另外，根据本公开的技术，可以降低制备成本。
根据本公开的一个实施例，提供了一种薄膜晶体管，其可以包括：遮光层；第一绝缘层；有源层，所述第一绝缘层设置在所述遮光层和所述有源层之间。所述薄膜晶体管还可以包括：第二绝缘层；栅极，所述第二绝缘层设置在所述栅极和所述有源层之间，所述有源层可以包括源极区和漏极区；层间绝缘层；源极电极和漏极电极，与所述有源层的源极区和漏极区分别连接。所述薄膜晶体管还可以包括：至少一个导电连接件，用于将所述遮光层分别与所述源极区和所述漏极区中的至少一个相连。
在一些实现方式中，所述至少一个导电连接件可以包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极区和所述漏极区。
在另一实现方式中，所述至少一个导电连接件包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极和所述漏极。
在一些实现方式中，所述薄膜晶体管还可以包括：至少一个导电连接件，穿过所述第一绝缘层以将所述遮光层的至少一个部分连接到所述源极区和所述漏极区中的至少一个或者连接到所述源极电极和所述漏极电极中的至少一个。
另外，在一些实施例中，所述至少一个导电连接件可以包括两个导电连接件，其各自与所述源极电极和所述漏极电极形成一体结构。换而言之，在一些实施例中，导电连接件可以分别是对应的所述源极电极或所述漏极电极的一部分。应理解，本公开并不限于此。
图1示出了根据本申请一个实施例的薄膜晶体管的结构示意图。该薄膜晶体管可以用于显示面板(例如，液晶显示面板)中。
如图1所示，提供了一种薄膜晶体管，包括：遮光层12，第一绝缘层13，有源层14，第二绝缘层15，栅极16，层间绝缘层17，与有源层14分别连接的源极18和漏极19；源极18和漏极19还与遮光层12连接。本实施例中，遮光层12、第一绝缘层13、有源层14、第二绝缘层15、栅极16、层间绝缘层17、源极18和漏极19各个层可以均位于基底层11上。图1示出了顶栅结构的晶体管。各个层之间的位置关系并不局限于图1所示。在其他实施例中，薄膜晶体管也可以是底栅结构或其他结构。第一绝缘层13、第二绝缘层15及层间绝缘层17每一个可以包括绝缘材料，诸如下列中任一项：氧化硅、氮化硅以及两者的混合物等。在一些实施例中，第一绝缘层13、第二绝缘层15及层间绝缘层17中的一个或多个可以被配置为允许光从其通过。
在一些实施例中，所述遮光层可以包括非晶硅。所述有源层可以包括多晶硅。所述遮光层可以被配置用于遮挡光以避免光入射到所述有源层。
在现有技术的薄膜晶体管(例如N型晶体管)工作过程中，对栅极加电压(例如，正电压)后，有源层靠近栅极侧的一面感应出负电荷，而远离栅极侧的一面感应出正电荷。而遮光层与有源层之间的绝缘层厚度通常较小，因此遮光层靠近有源层侧的一面可能会感应出负电荷，从而影响下次薄膜晶体管工作时有源层的电荷分配，使得阈值电压偏负。对于P型晶体管也是如此，只是感生电荷的极性反转。
本实施例中，由于源漏电极与有源层连接的同时还与遮光层相连接，因此可以将遮光层的感应电荷导出去。从而可以避免遮光层感生电荷对薄膜晶体管的影响。还可以提升薄膜晶体管阈值电压的稳定性。因此，改善了薄膜晶体管的性能。
另外，本领域技术人员将容易理解，对于MOS晶体管，有源区可以包括沟道形成区以及与分别与沟道形成区相邻的源极区和漏极区。沟道形成区与栅极对应，并用于在其中形成沟道。在晶体管操作时，栅极电压使得有源区中的沟道形成区的部分或全部导电类型反转，从而形成沟道。源极区对应于并连接到源极电极。漏极区对应于并连接到漏极电极。
进一步地，遮光层的材料为例如(但不限于)硅单质或氧化物半导体。具体地，硅单质可以为例如(但不限于)单晶硅、非晶硅等非透明硅单质材料。具体地，氧化物半导体可以为例如(但不限于)氧化铝、氧化钛等非透明氧化物半导体材料。
在具体实现中，基底层可以包括例如玻璃基板的透光基板。在另一些实施例中，基底层可以包括其他类型的基板。另外，基底层还可以包括基板和在基板上的其他功能层，例如缓冲层等。
根据本实施例，源漏电极与有源层连接的同时还与遮光层相连接，可以使得遮光层的电位相对变得稳定。另外，还可以使得至少部分的遮光层(例如，与源极区或源极电极连接的部分以及附近的部分)与有源层的对应的部分的电势基本相同或者接近，从而可以降低在遮光层中引发感生电荷的可能性。因此，可以进一步提升薄膜晶体管的稳定性。
进一步地，在遮光层的材料为非晶硅的情况下，在一些实施例中，源漏电极和非晶硅遮光层连接，但其与非晶硅层接触的表面并不形成欧姆接触。所以，在非晶硅中不会形成沟道。此外，非晶硅的阻值一般很大。因此，非晶硅遮光层的存在不会造成薄膜晶体管的漏电流的显著增加。在薄膜晶体管关闭后，关闭(OFF)电流可以在E -12甚至更低的量级。
进一步地，有源层的材料可以为多晶硅。进一步地，第一绝缘层位于遮光层上；有源层位于第一绝缘层上；第二绝缘层位于有源层上；栅极位于所示第二绝缘层上； 层间绝缘层位于栅极上；源极和漏极分别通过过孔与有源层和遮光层连接；过孔贯穿层间绝缘层、第二绝缘层、有源层和第一绝缘层。
本申请实施例中，遮光层12、第一绝缘层13、有源层14、第二绝缘层15、栅极16、层间绝缘层17、源极18和漏极19可以形成如图1所示由下而上的层叠位置关系，也就是说可以是顶栅结构。过孔(在图中未以标号指示)贯穿层间绝缘层、第二绝缘层、有源层和第一绝缘层。所述过孔可以具有任意适合的形状和尺寸。如图中所示，源极和漏极各自的一部分填充在对应的过孔中，如图中所示，从而分别形成前述的导电连接件。在图1所示的示例，所述至少一个导电连接件可以包括两个导电连接件，分别是所述源极电极和所述漏极电极各自的一部分，并分别设置在对应的过孔中。
图2A示出了根据本申请另一实施例的薄膜晶体管的结构示意图。
在该实施例中，如图2A所示，每个过孔28(29)可以包括第一子过孔281(291)和第二子过孔282(292)。第一子过孔281(291)贯穿层间绝缘层和第二绝缘层，第二子过孔282(292)贯穿有源层和第一绝缘层。根据本实施例，每个过孔实际上包括两个子过孔，可以减小工艺难度，同时增大源极和漏极与有源层的接触面积，改善薄膜晶体管的特性。可以理解的是，过孔可以包括两个或更多个子过孔。
在一些实施例中，所述第一子过孔的横向尺寸大于对应的第二子过孔的横向尺寸。从而提高过孔与有源层的接触面积，并降低电极与有源层的接触电阻和体电阻。
图2B示出了根据本申请另一实施例的薄膜晶体管的结构示意图。如图2B所示，薄膜晶体管可以包括：遮光层12；第一绝缘层13；和有源层14，所述第一绝缘层设置在所述遮光层和所述有源层之间。所述薄膜晶体管还可以包括：第二绝缘层15；栅极16，所述第二绝缘层至少设置在所述栅极和所述有源层之间，所述有源层可以包括源极区和漏极区；层间绝缘层17；源极电极18/19和漏极电极19/18，与所述有源层的源极区和漏极区(在图中未以附图标记标示)分别连接。所述薄膜晶体管还可以包括：至少一个导电连接件201/203，其穿过所述第一绝缘层以将所述遮光层的至少一个部分连接到所述源极区和所述漏极区中的至少一个。
在图2B所示的实施例中，示出了两个导电连接件：第一导电连接件201和第二导电连接件203。在其他实施例中，可以包括更多或更少的导电连接件。另外，尽管在图2B所示的实施例中，第一导电连接件201和第二导电连接件203并设置在第一绝缘层13中的远离端面的位置，然而本公开不限于此。例如，第一导电连接件201和第二导电连接件203可以在设置在第一绝缘层13中的端部或端部附近的位置。对于第一导电连接件201和第二导电连接件203的材料和工艺过程没有特别的限制，只要其能够与所采用的形成薄膜 晶体管的工艺兼容即可。例如，在适合时，可以采用掺杂的Poly-Si(多晶硅)来形成所述导电连接件。
图3示出了根据本申请一实施例的薄膜晶体管的结构示意图。如图3所示，在该实施例中，第一绝缘层33位于栅极32上；有源层34位于第一绝缘层33上；第二绝缘层35位于有源层34上；遮光层36位于所示第二绝缘层35上；层间绝缘层37位于遮光层36上；源极38和漏极39分别通过过孔与有源层34和遮光层36连接；过孔贯穿层间绝缘层37、遮光层36和第二绝缘层35。
本申请实施例中，栅极32、第一绝缘层33、有源层34、第二绝缘层35、遮光层36、层间绝缘层37、源极38和漏极39可以形成如图3所示由下而上的层叠位置关系。也就是说，该薄膜晶体管是底栅结构。过孔(在图中未以标号指示)贯穿层间绝缘层、第二绝缘层。从而所述过孔使得有源层的一部分露出。所述过孔可以具有任意适合的形状和尺寸。如图中所示，源极和漏极各自的一部分填充在对应的过孔中，如图中所示，从而分别形成前述的导电连接件。在图3所示的示例，所述至少一个导电连接件可以包括两个导电连接件，分别是所述源极电极和所述漏极电极各自的一部分，并分别设置在对应的过孔中。可以理解的是，过孔可以包括两个或更多个子过孔。
图4示出了本申请实施例提供的一种薄膜晶体管的制备方法。所述方法可以包括以下步骤中的一个或多个。
步骤S10：形成遮光材料层、第一绝缘材料层和有源材料层的多层结构。，可以在基底基板上采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积)方法形成遮光材料层。同样，可采用PEVCD方法在遮光材料层上依次形成第一绝缘材料层和有材料源层。
步骤S20：通过一次构图工艺对所述多层结构进行化处理，形成遮光层和有源层。在示例实现方式中，可以对步骤S10中所形成的多层结构通过一次构图工艺进行蚀刻，从而形成遮光层、第一绝缘层和有源层。
步骤S30：形成第二绝缘层。在示例实现方式中，可以在有源上采用PECVD方法形成第二绝缘层。
步骤S40：形成栅极。在示例实现方式中，可以先在第二绝缘层上通过溅射形成栅极材料层，再通过一次构图工艺形成栅极。
步骤S50：形成层间绝缘层。在示例实现方式中，可以在栅极上采用PECVD方法形成层间绝缘层。
步骤S60：形成贯穿层间绝缘层、第二绝缘层、有源层、第一绝缘层的第一过孔和第二过孔。在示例实现方式中，第一过孔和第二过孔可以通过一步蚀刻形成，也可以通过多步蚀刻形成。在一具体实例中，多步蚀刻可以包括：先通过蚀刻形成贯穿层间绝缘层、第二绝缘层、有源层、第一绝缘层的第一中间过孔和第二中间过孔；再通过蚀刻对所述第一中间过孔和第二中间过孔贯穿层间绝缘层和第二绝缘层部分的过孔进行拓宽。从而实现增大源极和漏极与有源层的接触面积的效果。
进一步地，步骤S60还包括：
形成贯穿层间绝缘层和第二绝缘层的两个第一子过孔后，再形成差贯穿有源层和第一绝缘层的两个第二子过孔。
步骤S70：形成源极和漏极，源极和漏极分别通过第一过孔和第二过孔与第一有源层以及遮光层连接。
上述实施例中，可以通过一次构图工艺形成遮光层和有源层，减少了构图工艺，降低了生成成本。另外，通过形成贯穿层间绝缘层、第二绝缘层、有源层、第一绝缘层的第一过孔和第二过孔，使得源极和漏极与遮光层连接，将遮光层感生的电荷传导至外部电路。此外，在不同实施例中，可以通过一次掩模形成，来利用蚀刻形成贯穿层间绝缘层、第二绝缘层、有源层、第一绝缘层的第一过孔和第二过孔，从而简化了工艺，降低了制造成本，和/或提高了生产效率。
根据本公开的实施例，可以减轻或者消除遮光层感生电荷的影响，提升阈值电压的稳定性，改善薄膜晶体管的特征。
图5A示出了根据本申请一个实施例的薄膜晶体管制备方法的示例性流程图。如图5A所示，根据该实施例的薄膜晶体管的制备方法，在步骤S501，提供包括遮光层、第一绝缘层和有源层的多层结构。所述第一绝缘层设置在所述遮光层和所述有源层之间。
在步骤S503，形成覆盖所述有源层的第二绝缘层，并在所述第二绝缘层上形成栅极。
在步骤S505，在所述栅极和所述第二绝缘层之上形成层间绝缘层。
在步骤S507，形成第一过孔和第二过孔。所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所述第二绝缘层、所述有源层、所述第一绝缘层。
在步骤S509，形成源极电极和漏极电极。所述源极电极和所述漏极电极分别填充所述第一过孔和所述第二过孔。所述源极电极和所述漏极电极通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
图5B示出了根据本申请一个实施例的形成过孔的示例性流程图。在一个实施例中，可以通过如下形成所述第一过孔和第二过孔。如图5B所示，在步骤S511，在所述 层间绝缘层上形成图案化的掩模。在步骤S513，利用所述掩模进行第一蚀刻处理，以形成贯穿所述层间绝缘层、所述第二绝缘层、所述有源层和所述第一绝缘层的两个开口，以使得所述遮光层的部分表面露出。在步骤S515，对所述掩模进行减缩(recessing)处理，以形成减缩的掩模。在步骤S517，利用减缩的掩模进行第二蚀刻处理，以使得至少所述两个开口各自的在所述有源层之上的部分的横向尺寸被扩大(如从图2A可以见的)。
图5C示出了根据本申请另一个实施例的形成过孔的示例性流程图。在一个实施例中，还可以通过如下方式形成所述第一过孔和第二过孔。在步骤S519，形成贯穿所述层间绝缘层和所述第二绝缘层的两个第一子过孔。在步骤S521，形成贯穿所述有源层和所述第一绝缘层的两个第二子过孔。
图6A示出了根据本申请另一个实施例的薄膜晶体管制备方法的示例性流程图。如图6A所示，在步骤S601，提供包括栅极、第一绝缘层和有源层的多层结构。所述第一绝缘层设置在所述栅极和所述有源层之间。在步骤S603，形成覆盖所述有源层的第二绝缘层。在步骤S605，在所述第二绝缘层上形成遮光层。在步骤S607，在所述遮光层和所述第二绝缘层之上形成层间绝缘层。在步骤S609，形成第一过孔和第二过孔。所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所述遮光层、所述第二绝缘层，以分别露出所述有源层的部分表面。在步骤S611，形成源极电极和漏极电极。所述源极电极和所述漏极电极分别填充所述第一过孔和所述第二过孔。所述源极电极和所述漏极电极通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
图6B示出了根据本申请一个实施例的形成过孔的示例性流程图。在一个实施例中，可以通过如下形成所述第一过孔和第二过孔。如图6B所示，在步骤S613，在所述形成层间绝缘层上形成图案化的掩模。在步骤S615，利用所述掩模进行蚀刻处理，以形成贯穿所述层间绝缘层、所述遮光层和所述第二绝缘层的所述第一过孔和第二过孔。本领域技术人员将容易理解，在蚀刻过程中可以针对不同的待蚀刻的材料选择不同的蚀刻剂以及工艺等。
进一步地，图7示出了根据本申请一个实施例的显示装置的示例性框图。如图7所示，本申请实施例还提供了一种阵列基板，包括多个阵列设置的本申请任意实施例提供的薄膜晶体管。进一步地，本申请实施例还提供了一种显示装置，该显示装置包括本申请各实施例提供的阵列基板。
根据本申请的实施例，提供了一种新颖的薄膜晶体管。通过将源极和漏极与遮光层连接，可以将遮光层感生的电荷传导至外部电路，可以减轻或消除遮光层感生电荷的影响，提升阈值电压的稳定性。根据本公开的实施例，可以改善薄膜晶体管的性能。
应理解，上述操作之间的边界仅仅是说明性的。多个操作可以结合成单个操作，单个操作可以分布于附加的操作中，并且操作可以在时间上至少部分重叠地执行。而且，另选的实施例可以包括特定操作的多个实例，并且在其他各种实施例中可以改变操作顺序。但是，其它的修改、变化和替换同样是可能的。因此，本说明书和附图应当被看作是说明性的，而非限制性的。
应理解，以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。以上已经描述了本公开的各种实施例，但是上述说明仅仅是示例性的，并非穷尽性的，并且本发明也不限于所公开的各种实施例。在此公开的各实施例可以任意地适当组合，而不脱离本发明的精神和范围。根据本发明在此的教导，相关技术领域的普通技术人员可以容易地想到许多修改和变化，这些修改和变化也被涵盖在本发明的精神和范围内。本发明的范围由所附权利要求来限定。

Claims (20)

  1. 一种薄膜晶体管，包括：
    遮光层；
    有源层；
    第一绝缘层，所述第一绝缘层设置在所述遮光层和所述有源层之间；
    栅极；
    第二绝缘层，所述第二绝缘层设置在所述栅极和所述有源层之间；
    源极，与所述有源层的源极区连接；
    漏极，与所述有源层的漏极区连接；以及
    至少一个导电连接件，用于将所述遮光层分别与所述源极区和所述漏极区中的至少一个相连。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述至少一个导电连接件包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极区和所述漏极区。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述至少一个导电连接件包括两个导电连接件，各自分别穿过所述第一绝缘层以将所述遮光层的分别连接到所述源极和所述漏极。
  4. 根据权利要求1-3中任一项所述的薄膜晶体管，其中，所述遮光层包括非晶硅，所述有源层包括多晶硅。
  5. 根据权利要求1-3中任一项所述的薄膜晶体管，其中：
    所述第一绝缘层位于所述遮光层上；
    所述有源层位于所述第一绝缘层上；
    所述第二绝缘层位于所述有源层上；
    所述栅极位于所示第二绝缘层上；
    所述层间绝缘层位于所述栅极上；
    所述源极和所述漏极分别通过对应的过孔与所述有源层和所述遮光层连接；
    所述过孔贯穿所述层间绝缘层、所述第二绝缘层、所述有源层和所述第一绝缘层；
    所述至少一个导电连接件包括两个导电连接件，分别设置在所述过孔中，并且分别与所述源极电极和所述漏极电极形成一体结构。
  6. 根据权利要求1-3中任一项所述的薄膜晶体管，其中：
    所述第一绝缘层位于所述栅极上；
    所述有源层位于所述第一绝缘层上；
    所述第二绝缘层位于所述有源层上；
    所述遮光层位于所示第二绝缘层上；
    所述层间绝缘层位于所述遮光层上；
    所述源极电极和所述漏极电极分别通过过孔与所述有源层和所述遮光层连接；
    所述过孔贯穿所述层间绝缘层、所述遮光层和所述第二绝缘层；
    所述至少一个导电连接件包括两个导电连接件，分别设置在所述过孔中，并且分别与所述源极电极和所述漏极电极形成一体结构。
  7. 根据权利要求1所述的薄膜晶体管，还包括：
    透光基底层，所述遮光层设置在所述透光基底层的一侧上。
  8. 根据权利要求5所述的薄膜晶体管，其中：
    每个所述过孔包括第一子过孔和第二子过孔，
    所述第一子过孔贯穿所述层间绝缘层和所述第二绝缘层到所述有源层，并且
    所述第一子过孔的横向尺寸大于对应的第二子过孔的横向尺寸。
  9. 一种薄膜晶体管的制备方法，包括：
    提供包括遮光层、第一绝缘层和有源层的多层结构，其中所述第一绝缘层设置在所述遮光层和所述有源层之间；
    形成覆盖所述有源层的第二绝缘层，并在所述第二绝缘层上形成栅极；
    在所述栅极和所述第二绝缘层之上形成层间绝缘层；
    形成第一过孔和第二过孔，所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所述第二绝缘层、所述有源层、所述第一绝缘层；
    形成源极电极和漏极电极，所述源极电极和所述漏极电极分别填充所述第一过孔和所 述第二过孔，并通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
  10. 根据权利要求9所述的制备方法，所述形成第一过孔和第二过孔包括：
    形成贯穿所述层间绝缘层和所述第二绝缘层的两个第一子过孔；
    形成贯穿所述有源层和所述第一绝缘层的两个第二子过孔。
  11. 根据权利要求9所述的制备方法，其中所述第一子过孔的横向尺寸大于对应的第二子过孔的横向尺寸。
  12. 根据权利要求9所述的制备方法，其中形成所述第一过孔和第二过孔包括：
    在所述层间绝缘层上形成图案化的掩模；
    利用所述掩模进行第一蚀刻处理，以形成贯穿所述层间绝缘层、所述第二绝缘层、所述有源层和所述第一绝缘层的两个开口，以使得所述遮光层的部分表面露出；
    对所述掩模进行减缩处理，以形成减缩的掩模；
    利用减缩的掩模进行第二蚀刻处理，以使得至少所述两个开口各自的在所述有源层之上的部分的横向尺寸被扩大。
  13. 根据权利要求9所述的制备方法，其中所述遮光层包括非晶硅，所述有源层包括多晶硅，所述遮光层被配置用于遮挡光以避免光入射到所述有源层。
  14. 根据权利要求9所述的制备方法，其中提供包括遮光层、第一绝缘层和有源层的多层结构包括：
    在透光基底层上形成所述多层结构。
  15. 一种薄膜晶体管的制备方法，包括：
    提供包括栅极、第一绝缘层和有源层的多层结构，其中所述第一绝缘层设置在所述栅极和所述有源层之间；
    形成覆盖所述有源层的第二绝缘层；
    在所述第二绝缘层上形成遮光层；
    在所述遮光层和所述第二绝缘层之上形成层间绝缘层；
    形成第一过孔和第二过孔，所述第一过孔和第二过孔每个都贯穿所述层间绝缘层、所 述遮光层、所述第二绝缘层，以分别露出所述有源层的部分表面；
    形成源极电极和漏极电极，所述源极电极和所述漏极电极分别填充所述第一过孔和所述第二过孔，并通过所述第一过孔和所述第二过孔与所述有源层以及遮光层电连接。
  16. 根据权利要求15所述的制备方法，其中形成所述第一过孔和第二过孔包括：
    在所述形成层间绝缘层上形成图案化的掩模；
    利用所述掩模进行蚀刻处理，以形成贯穿所述层间绝缘层、所述遮光层和所述第二绝缘层的所述第一过孔和第二过孔。
  17. 根据权利要求15所述的制备方法，其中所述遮光层包括非晶硅，所述有源层包括多晶硅，所述遮光层被配置用于遮挡光以避免光入射到所述有源层。
  18. 根据权利要求15所述的制备方法，其中提供包括栅极层、第一绝缘层和有源层的多层结构包括：
    在透光基底层上形成所述多层结构。
  19. 一种阵列基板，包括阵列设置的多个如权利要求1-8中任一所述的薄膜晶体管。
  20. 一种显示装置，包括如权利要求19所述的阵列基板。
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