WO2019124119A1 - 基板支持部材、基板処理装置及び基板搬送装置 - Google Patents
基板支持部材、基板処理装置及び基板搬送装置 Download PDFInfo
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- WO2019124119A1 WO2019124119A1 PCT/JP2018/045120 JP2018045120W WO2019124119A1 WO 2019124119 A1 WO2019124119 A1 WO 2019124119A1 JP 2018045120 W JP2018045120 W JP 2018045120W WO 2019124119 A1 WO2019124119 A1 WO 2019124119A1
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- substrate
- wafer
- inductor
- support member
- conductive
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67742—Mechanical parts of transfer devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67766—Mechanical parts of transfer devices
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68707—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a robot blade, or gripped by a gripper for conveyance
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
Definitions
- the present invention relates to a substrate support member for supporting a substrate when delivering a substrate on a mounting table in a substrate processing apparatus, a substrate processing apparatus using the substrate support member, and a substrate transfer apparatus.
- a predetermined coating solution is applied on a semiconductor wafer (hereinafter referred to as "wafer") as a substrate to form a coating film such as an antireflective film or a resist film.
- a coating film such as an antireflective film or a resist film.
- An application process is performed.
- the coating solution is supplied from the nozzle to the central portion of the rotating wafer, and the coating solution is diffused on the wafer by centrifugal force to form a coating film on the wafer.
- Spin coating is widely used.
- Patent Document 1 discloses a wafer, a transport mechanism or a processing mechanism in contact with the wafer, and a material having a predetermined resistance or a predetermined resistance value. It is described that static elimination is carried out by grounding through.
- ESD current waveforms generated on the wafer.
- One is that although the amount of discharge charge is small, a current with a sharp peak flows in a short period (for example, several ns or less), and the time constant is small, so the ESD protection elements (resistors, diodes, transistors, etc.) can respond.
- Current that may cause a potential malfunction even if a sudden potential change occurs in the internal circuit to be protected, for example, even if the aforementioned oxide film breakage or complete destruction does not occur. It is a waveform.
- the other one is one in which the amount of discharge charge is large and a large current flows for a long time (for example, about 100 ns) and the ESD protection element can sufficiently respond, but a large current flows to the ESD protection element. It is a current waveform which generates heat and may cause breakage of the above-mentioned junction or melting of the wiring film due to thermal destruction.
- the present invention has been made in view of the foregoing points, and it is an object of the present invention to make it easy for the charge on the wafer to leak and to prevent the occurrence of electrical characteristic failure while limiting the ESD current.
- one aspect of the present invention is a substrate support member for supporting a substrate, comprising: a conductive portion having conductivity, and an inductor portion provided outside the conductive portion.
- the conductive portion is formed with a contact support portion for supporting the substrate in contact with the substrate, and the opposite side of the contact support portion across the inductor portion in the conductive portion is directly or indirectly It is grounded.
- FIG. 1 is a plan view schematically showing the outline of the configuration of a substrate processing system 1.
- 2 and 3 are a front view and a rear view schematically showing the outline of the internal configuration of the substrate processing system 1, respectively.
- the substrate processing system 1 performs predetermined processing on the wafer W as a substrate.
- the substrate processing system 1 includes a cassette station 10 for loading and unloading a cassette C containing a plurality of wafers W as shown in FIG. 1, and a processing station 11 comprising a plurality of various processing apparatuses for performing predetermined processing on the wafers W. And an interface station 13 for transferring the wafer W between the exposure apparatus 12 adjacent to the processing station 11 are integrally connected.
- the cassette mounting table 20 is provided in the cassette station 10.
- a plurality of cassette mounting plates 21 for mounting the cassette C is provided on the cassette mounting table 20.
- the cassette station 10 is provided with a wafer transfer apparatus 23 movable on the transfer path 22 extending in the X direction.
- the wafer transfer device 23 is also movable in the vertical direction and around the vertical axis ( ⁇ direction), and the cassette C on each cassette mounting plate 21 and the delivery device of the third block G3 of the processing station 11 described later
- the wafer W can be transferred between the two.
- the processing station 11 is provided with a plurality of, for example, four blocks provided with various devices, that is, a first block G1 to a fourth block G4.
- a first block G1 is provided on the front side (the negative side in the X direction of FIG. 1) of the processing station 11.
- a second block G2 is provided on the back side (the X direction positive direction side in FIG. 1, the upper side of the drawing) of the processing station 11.
- the third block G3 described above is provided on the cassette station 10 side (the negative side in the Y direction in FIG. 1) of the processing station 11.
- a fourth block G4 is provided on the interface station 13 side (the positive side in the Y direction of FIG. 1) of the processing station 11.
- a plurality of liquid processing devices for example, a development processing device 30 for developing the wafer W, an antireflective film under the resist film of the wafer W (hereinafter referred to as “lower antireflective film Lower antireflection film forming apparatus 31 for forming a film, resist coating apparatus 32 for applying a resist solution to a wafer W to form a resist film, and an antireflection film on the upper layer of the resist film of the wafer W (hereinafter referred to as “upper reflection” An upper anti-reflection film forming device 33 for forming a “preventive film” is disposed in this order from the bottom.
- a development processing device 30 for developing the wafer W an antireflective film under the resist film of the wafer W
- resist coating apparatus 32 for applying a resist solution to a wafer W to form a resist film
- an antireflection film on the upper layer of the resist film of the wafer W hereinafter referred to as “upper reflection
- the development processing unit 30, the lower antireflection film forming unit 31, the resist coating unit 32, and the upper antireflection film forming unit 33 are arranged side by side in the horizontal direction.
- the number and arrangement of the development processing unit 30, the lower antireflection film forming unit 31, the resist coating unit 32, and the upper antireflection film forming unit 33 can be arbitrarily selected.
- a heat treatment apparatus 40 for performing heat treatment such as heating or cooling of the wafer W or a hydrophobic treatment for performing a hydrophobization treatment to improve the fixability between the resist solution and the wafer W
- the conversion processing unit 41 and the peripheral exposure unit 42 for exposing the outer peripheral portion of the wafer W are provided side by side vertically and horizontally.
- the number and arrangement of the heat treatment apparatus 40, the hydrophobization apparatus 41, and the peripheral exposure apparatus 42 can be arbitrarily selected.
- a plurality of delivery devices 50, 51, 52, 53, 54, 55, 56 are provided in order from the bottom.
- a plurality of delivery devices 60, 61, 62 are provided in order from the bottom.
- a wafer transfer area D is formed in an area surrounded by the first block G1 to the fourth block G4.
- a plurality of wafer transfer devices 70 each having a transfer arm 70a movable in, for example, the Y direction, the X direction, the ⁇ direction, and the vertical direction are disposed.
- the wafer transfer apparatus 70 moves in the wafer transfer area D and transfers the wafer W to the predetermined apparatus in the surrounding first block G1, second block G2, third block G3 and fourth block G4. it can.
- a shuttle transfer apparatus 80 for transferring the wafer W linearly between the third block G3 and the fourth block G4 is provided.
- the shuttle transfer device 80 is, for example, linearly movable in the Y direction in FIG.
- the shuttle transfer device 80 moves in the Y direction while supporting the wafer W, and can transfer the wafer W between the delivery device 52 of the third block G3 and the delivery device 62 of the fourth block G4.
- a wafer transfer apparatus 81 is provided next to the third block G3 on the positive direction side in the X direction.
- the wafer transfer apparatus 81 has a transfer arm 81a movable in, for example, the X direction, the ⁇ direction, and the vertical direction.
- the wafer transfer apparatus 81 can move up and down while supporting the wafer W to transfer the wafer W to each delivery apparatus in the third block G3.
- the interface station 13 is provided with a wafer transfer apparatus 90 and a delivery apparatus 91.
- the wafer transfer apparatus 90 has a transfer arm 90a movable in, for example, the Y direction, the ⁇ direction, and the up and down direction.
- the wafer transfer apparatus 90 can, for example, support the wafer W by the transfer arm 90 a and transfer the wafer W among the delivery devices in the fourth block G4, the delivery device 91, and the exposure device 12.
- the control unit 100 is, for example, a computer and has a program storage unit (not shown).
- the program storage unit stores a program for controlling the processing of the wafer W in the substrate processing system 1.
- the program storage unit also stores a program for realizing the liquid processing described later in the substrate processing system 1 by controlling the operation of drive systems such as the above-described various processing apparatuses and transport apparatuses.
- the program is stored in a computer readable storage medium such as a computer readable hard disk (HD), a flexible disk (FD), a compact disk (CD), a magnet optical desk (MO), and a memory card. And may be installed in the control unit 100 from the storage medium.
- a cassette C containing a plurality of wafers W is carried into the cassette station 10 of the substrate processing system 1 and placed on the cassette placing plate 21. Thereafter, the wafers W in the cassette C are sequentially taken out by the wafer transfer device 23 and transferred to the delivery device 53 of the third block G3 of the processing station 11.
- the wafer W is transferred by the wafer transfer apparatus 70 to the heat treatment apparatus 40 of the second block G2 and subjected to temperature adjustment processing. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to, for example, the lower antireflective film forming apparatus 31 of the first block G1, and the lower antireflective film is formed on the wafer W. Thereafter, the wafer W is transferred to the heat treatment apparatus 40 of the second block G2 and heat treatment is performed. Thereafter, the wafer W is returned to the delivery device 53 of the third block G3.
- the wafer W is transferred by the wafer transfer apparatus 81 to the delivery apparatus 54 of the same third block G3. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the hydrophobization processing apparatus 41 of the second block G2, and the hydrophobization processing is performed.
- the wafer W is transferred by the wafer transfer apparatus 70 to the resist coating apparatus 32, and a resist film is formed on the wafer W. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the heat treatment apparatus 40 and subjected to prebaking. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the delivery apparatus 55 of the third block G3.
- the wafer W is transferred by the wafer transfer apparatus 70 to the upper antireflective film forming apparatus 33, and the upper antireflective film is formed on the wafer W. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the heat treatment apparatus 40 and heated, and then the temperature is adjusted. Thereafter, the wafer W is transferred to the peripheral exposure device 42 and subjected to peripheral exposure processing.
- the wafer W is transferred by the wafer transfer apparatus 70 to the delivery apparatus 56 of the third block G3.
- the wafer W is transferred by the wafer transfer apparatus 81 to the delivery apparatus 52 and transferred by the shuttle transfer apparatus 80 to the delivery apparatus 62 of the fourth block G4. Thereafter, the wafer W is transferred by the wafer transfer apparatus 90 of the interface station 13 to the exposure apparatus 12 and exposed in a predetermined pattern.
- the wafer W is transferred by the wafer transfer apparatus 90 to the delivery apparatus 60 of the fourth block G4. Thereafter, the wafer is transferred by the wafer transfer apparatus 70 to the heat treatment apparatus 40 and subjected to post-exposure bake processing.
- the wafer W is transferred by the wafer transfer apparatus 70 to the development processing apparatus 30 and developed.
- the wafer W is transferred by the wafer transfer apparatus 70 to the heat treatment apparatus 40 and subjected to post-baking process.
- the wafer W is transferred by the wafer transfer apparatus 70 to the delivery apparatus 50 of the third block G3, and then transferred by the wafer transfer apparatus 23 of the cassette station 10 to the cassette C of the predetermined cassette mounting plate 21.
- a series of photolithography steps are completed.
- FIG. 4 is a longitudinal sectional view schematically showing the outline of the configuration of the resist coating unit 32
- FIG. 5 is a horizontal sectional view schematically showing the outline of the configuration of the resist coating unit 32. As shown in FIG. 4
- the resist coating unit 32 is provided with a spin chuck 200 as a substrate holding unit for holding the wafer W as shown in FIG.
- the spin chuck 200 has a horizontal upper surface, and a suction port (not shown) for suctioning the wafer W, for example, is provided on the upper surface.
- the wafer W can be adsorbed and held on the spin chuck 200 by suction from the suction port.
- the spin chuck 200 is made of, for example, 10 5 ⁇ , which is made of, for example, a conductive resin having a resistance value region that is electrostatically dissipative, which is made of, for example, polyetheretherketone (PEEK) and carbon fiber (CF). It has a resistance value of ⁇ 10 9 ⁇ and has a resistance value range that is electrostatic dissipative.
- the spin chuck 200 is connected to a drive unit 202 provided below the spin chuck 200 via a shaft 201, and the drive unit 202 is connected to an earth wire 203.
- the spin chuck 200 can be rotated at a predetermined speed by the drive unit 202, and the spin chuck 200 can be moved up and down.
- the substrate support portion 210 is constituted of, for example, three elevating pins 211a, 211b, and 211c as a substrate support member according to the present embodiment, a ring member 212, an elevating portion 213, and a ground connection portion 214.
- the lift pins 211a, 211b, and 211c as substrate support members are connected to the lift portion 213 via the ring member 212, and can be lifted and lowered.
- the elevating pins 211a, 211b, and 211c can protrude upward from the spin chuck 200, and can transfer the wafer W with the transfer arm 70a of the wafer transfer apparatus 70 described above.
- FIG. 6 is an explanatory view schematically showing an outline of the configuration of the elevation pin 211a.
- the raising and lowering pins 211 a have a main body 220 made of a conductive resin made of, for example, polybenzimidazole (PBI) and carbon fiber (CF).
- the top portion of the main body 220 is a contact support portion 220 a that directly contacts and supports the wafer W.
- a conductive material portion 221 made of, for example, a bar of SUS is provided below the main body 220.
- the main body 220 and the conductive material portion 221 constitute a conductive portion.
- the conductive material portion 221 is electrically conducted to the ground connection portion 214 described above, and is thereby grounded.
- a magnetic core 222 serving as an inductor portion is provided on the lower periphery of the main body 220 and on the upper outer periphery of the conductive material portion 221.
- a soft magnetic toroidal core is used, and as the soft magnetic material, for example, a Ni—Zn ferrite core is used.
- the lift pins 211a having such a configuration function as low resistance pins for leaking residual charges and induced charges on the wafer W after application of a treatment liquid described later, and via the ring member 212, the earth connection portion 214 and electricity are Because of the communication, the charge on the wafer W can be leaked to the ground side.
- the low resistance refers to a resistance value of, for example, 10 5 ⁇ or less, which is the upper limit of electrostatic conductivity.
- the remaining two of the three raising and lowering pins ie, the raising and lowering pins 211b and 211c, are made of an insulating material having insulation as a whole, for example, an insulating resin such as polyetheretherketone (PEEK).
- having insulation means, for example, having a resistance value of 10 11 ⁇ or more.
- the contact support portion 223 at the top of the lift pins 211b and 211c which contacts and supports the wafer W is made of, for example, insulating rubber such as perfluoro rubber, and directly contacts the wafer W to support the wafer W
- the holding power at the time of A nut 226 for height adjustment is provided at the upper end portion of the lower conductive member portion 225 in the raising and lowering pins 211 b and 211 c.
- the length from the contact support part 223 in the raising / lowering pin 211b, 211c to the nut 226 is set so that the insulation distance which creeping discharge does not occur may be maintained.
- one of the three lifting pins ie, the lifting pin 211a
- the number of low resistance pins is not limited to this
- At least one or more of the plurality of lifting pins provided in the lifting unit 210 may be a low resistance pin having the magnetic core 222.
- a processing liquid nozzle 230 for supplying a processing liquid, for example, a resist liquid, to the surface of the wafer W is provided.
- a discharge port 230a for supplying the processing liquid is formed.
- the treatment liquid nozzle 230 is connected to the drive unit 232 via an arm 231.
- the arm 231 extends outward in the negative Y direction (left direction in FIG. 5) of a cup body 240 described later along a guide rail 233 extending in the Y direction (left and right direction in FIG. 5) by the drive portion 232.
- the wafer W can be moved to the upper side of the wafer W from the provided standby portion 234, and a resist solution, which is a processing solution, can be supplied to the central position of the wafer W.
- the arm 231 can be moved up and down by the drive unit 232, and the height of the processing liquid nozzle 230 can be adjusted.
- a cup body 240 is provided on the side of the spin chuck 200 so as to surround the wafer W held by the spin chuck 200.
- a lift mechanism (not shown) is connected to the cup body 240, and by raising the cup body 240, it is possible to receive a processing liquid such as a resist liquid or a solvent that is scattered from the wafer W.
- a liquid receiving portion 250 for collecting and discharging the processing liquid collected by the cup body 240 is provided below the cup body 240 and the spin chuck 200.
- a discharge pipe 251 for discharging the gas and liquid in the liquid receiving portion 250 is connected to the bottom surface of the liquid receiving portion 250, and a gas-liquid separator (not shown) provided on the downstream side of the discharge pipe 251 is connected. Liquid separation is performed. The drainage after gas-liquid separation is collected in a drainage tank (not shown).
- a circular cup mounting base 260 is provided below the spin chuck 200, and outside the cup mounting base 260, an annular guide member 261 having a mountain-shaped vertical cross section is provided.
- the guide member 261 guides the processing liquid that has fallen from the wafer W to the liquid receiving portion 250 provided outside the cup mounting base 260.
- the cup mounting base 260 is provided with a through hole (not shown) which penetrates the shaft 201 and the elevation pins 211a, 211b and 211c.
- the treatment liquid nozzle 230 of the standby unit 234 is moved to the upper side of the central portion of the wafer W by the arm 231, and the spin chuck 200 is rotated.
- the supplied resist solution is diffused over the entire surface of the wafer W by centrifugal force and uniformly applied to the surface by spin coating.
- spin chuck 200 has a resistance value range that is, for example, 10 5 ⁇ to 10 9 ⁇ , which is an electrostatic diffusive property.
- the portion can be leaked from the ground wire 203 connected via the spin chuck 200, the shaft 201, and the drive portion 202 without causing a rapid discharge.
- the spin chuck 200 still has a high resistance to the degree of electrostatic diffusion, part of the charge remains on the wafer W without leaking through the spin chuck 200.
- the DC resistance between the wafer contact point and the ground point is increased as in the conventional method, that is, as the insulation property is increased, the current flowing through devices on the wafer W can be restricted. Charge on the wafer W is less likely to leak. Therefore, as in the embodiment, the DC resistance value is reduced as much as possible to the extent that charges are likely to leak slowly, and at the same time the impedance is increased such that a steep (ps to several ns order) current does not easily flow in the inductor portion. Also, it is possible to appropriately cope with a case where an ESD current having a sharp peak flows in a short period of time, and it is possible to prevent the occurrence of electrical characteristic failure due to it.
- FIG. 7 shows an equivalent circuit diagram of the elevation pin 211a according to the present embodiment.
- the magnetic core 222 can limit the current having a large current change rate. Therefore, for example, while the steep ESD current whose rise time is ps to several ns or less is limited, it can be leaked from the ground connection portion 214 to the ground side before being transported to the next process. Of course, the charge on the wafer W can be leaked to the ground side while limiting this also for a long-term ESD current. Therefore, it is possible to prevent the destruction of the junction of the device and the melting of the wiring film.
- FIG. 8 is a graph showing a comparison of ESD discharge voltages generated in the elevation pin 211a having the magnetic core 222 as the inductor portion and the elevation pin not having the inductor portion.
- the solid line in the graph has the magnetic core 222
- the broken line shows the discharge voltage at the elevation pin not having the inductor portion.
- the peak of the first discharge voltage having a sharp voltage change is cut by about 40% as compared with the elevation pin having no inductor portion.
- the second peak after the first peak is also relaxed in the configuration having the inductor portion as in the present embodiment as compared with the case where the inductor portion is not included. Therefore, the voltage change on the wafer W can be minimized by providing the raising and lowering pins 211a having the inductor portion.
- the present invention is not limited to the resist coating device 32, but other liquid processing devices, such as the development processing device 30, lower anti-reflection film
- the present invention is also applicable to the forming device 31 and the upper anti-reflection film forming device 33. Further, the present invention is applicable not only to the liquid processing apparatus but also to an apparatus for performing heat processing and cooling processing including the heat processing apparatus 40, and the hydrophobization processing apparatus 41, and applicable to a substrate processing apparatus for processing a substrate on a mounting table. It is.
- the raising / lowering pin 211a adopts the magnetic core 222 as the inductor part, but instead of this, as shown in FIG. 9, for example, silicon carbide (SiC) in the upper part of the main body 220.
- SiC silicon carbide
- the spiral inductor 293 can also limit steep ESD current.
- both the spiral inductor 293 and the magnetic core 222 described above may be employed.
- inductors having different characteristics By combining inductors having different characteristics in this way, an effect of attenuating a plurality of components of the ESD current can be obtained.
- the wafer W is unloaded from the resist coating unit 32 by the transfer arm 70 a of the wafer transfer unit 70 when resist coating by the liquid processing unit, for example, the resist coating unit 32 is completed.
- the transfer arm 70a itself is charged, a slight electric charge remaining on the wafer W may be inductively charged again to cause ESD. .
- the transfer arm 70a is connected to ground at 10 9 ⁇ or less, which is the upper limit of the electrostatic diffusion property, via the device group 300 such as a transfer arm drive mechanism. It is preferable to do.
- the entire surface of the transfer arm 70a may be coated with a conductive resin.
- support pads made of synthetic resin or the like are provided at a plurality of places, for example, three places so as to support the wafer W so as not to be easily displaced during transfer. Therefore, if the wafer W to be transported has residual electric charge, as in the case of the elevating pins described above, an ESD current is generated at the time of contact with the wafer W, and destruction of junctions or melting of wiring film due to ESD current Can occur.
- the minute contact electrification with the wafer W can be surely leaked also from the support pads 301a to 301c which are the contact portions with the wafer W during the transfer of the wafer W.
- the material of the support pads 301a to 301c it is preferable to use a material having electrostatic conductivity of 10 5 ⁇ or less. With such a configuration, the residual charge or the induced charge on the wafer W can be leaked through the surface portions of the support pads 301a to 301c and the transfer arm 70a.
- the transport arm 70a itself may have a configuration of an inductor portion, and an inductor effect similar to that of the elevation pins 211a may be exhibited.
- one arm portion 71a of the arm portions 71a and 71b of the arm main body 71 called a so-called fork in the transport arm 70a has a configuration as an inductor portion.
- FIG. 12 is an enlarged view of the broken line area X in FIG. 11, and FIGS. 12 (a) to 12 (d) are side views of the arm portion 71a in the broken line area X of FIG. The front, the side, and the back are shown respectively. Further, portions indicated by a large number of dots in FIG. 12 indicate conductive regions 310 coated with a conductive resin, and white portions indicate insulating regions 311. The right side of the support pad 301a in the figure is the tip direction of the transfer arm 70a, and the left side of the support pad 301 in the figure is the device group 300 and the ground connection side.
- a spiral inductor is formed by forming a spiral pattern on the surface of the insulating member on the surface of the insulating member on the outer periphery of the arm 71a from the support pad 301a to the device group 300 side. It comprises 312.
- a chip 313 as an inductor member may be bridged between the conductive region 310 and the insulating region 311 which are adjacent to each other.
- the chip 313 can have the same function as that of the magnetic core 222 in the elevation pin 211a. Thereby, an effect of attenuating a plurality of components of the ESD current can be obtained.
- the spiral inductor 312 is provided only in the arm portion 71a having the support pad 301a, but the spiral inductor 312 may of course be provided also in the arm portion 71b having the support pad 301b.
- the wafer W When the wafer W is unloaded by the transfer arm 70a of the wafer transfer apparatus 70 and then the next wafer W is loaded by the transfer arm 70a, the wafer W is placed on the elevating pins 211a, 211b and 211c described above from the transfer arm 70a. At the same time, minute ESD may occur due to induced charge. However, even when the ESD occurs in this way, since the inductor portion of the magnetic material core 222 is provided on the elevation pin 211a, the generated weak ESD can be prevented also in this case.
- the present invention is useful for a support member that contacts and supports a substrate, and is useful for an elevation pin that raises and lowers the substrate and a transport arm that supports the substrate when transporting the substrate.
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Abstract
Description
本願は、2017年12月21日に日本国に出願された特願2017-244724号に基づき、優先権を主張し、その内容をここに援用する。
Static Discharge)耐性の低下とあいまって、ウェハ上に形成された酸化膜の破壊、接合部の破壊、配線膜の溶断等といった問題が発生するおそれがある。
ひとつは、放電電荷量は少ないものの、急峻なピークを持つ電流が短期間(例えば数ns以下)に流れるもので、時定数が少ないためにESD保護素子(抵抗やダイオード、トランジスタ等)が応答できず、保護対象である内部回路に急峻な電位変化が発生し、例えば前述の酸化膜の破壊や、あるいは完全な破壊が発生しなくとも、潜在的な機能不良の原因となる可能性がある電流波形である。
他のひとつは、放電電荷量が多く、大電流が長時間(例えば100ns程度)流れるもので、ESD保護素子が十分に応答できる時定数であるものの、ESD保護素子へ大電流が流れることでジュール発熱が生じ、熱的破壊によって前述の接合部の破壊や配線膜の溶断を発生させる可能性がある電流波形である。
先ず、本実施形態にかかる液処理装置を備えた基板処理システムの構成について説明する。図1は、基板処理システム1の構成の概略を模式的に示す平面図である。図2及び図3は、各々基板処理システム1の内部構成の概略を模式的に示す正面図と背面図である。基板処理システム1では、基板としてのウェハWに所定の処理を行う。
次に、以上のように構成された基板処理システム1を用いて行われるウェハ処理について説明する。
次に本発明の実施形態にかかる液処理装置、例えばレジスト塗布装置32の構成について説明する。図4は、レジスト塗布装置32の構成の概略を模式的に示す縦断面図、図5はレジスト塗布装置32の構成の概略を模式的に示す水平断面図である。
ウェハ搬送装置70の搬送アーム70aによってウェハWがレジスト塗布装置32に搬入されると、搬入されたウェハWは、搬送アーム70aから予め昇降して待機していた昇降ピン211a、211b、211cに受け渡される。続いて、昇降ピン211a、211b、211cが下降し、ウェハWはスピンチャック200に保持される。
このように、インダクタ部を設けることにより、ウェハW接触点と接地点の間のインピーダンスは大きくなり、ウェハW上のデバイスを流れる電流も制限される。これに対し従来手法のようにウェハ接触点と接地点の間の直流抵抗値を大きくするほど、つまり極端にいえば絶縁性を高めるほど、ウェハW上のデバイスを流れる電流を制限できるが、他方でウェハW上の電荷は漏洩しづらくなる。したがって実施の形態のように、電荷がゆっくり漏洩しやすい程度まで、直流抵抗値をなるべく小さくすると同時に、インダクタ部で急峻(ps~数nsオーダー)な電流が流れにくいようにインピーダンスを大きくすることで、急峻なピークを持つESD電流が短期間に流れる場合に対しても適切に対応でき、それに起因する電気特性不良の発生を防止することができる。
70 ウェハ搬送装置
70a 搬送アーム
210 基板支持部
211a、211b、211c 昇降ピン
212 リング体
214 アース接続部
220 接触支持部
221 導電材部
222 磁性体コア
240 カップ体
W ウェハ
Claims (8)
- 基板を支持する基板支持部材であって、
導電性を有する導電部と、
前記導電部の外側に設けられたインダクタ部と、を有し、
前記導電部には、前記基板と接触して前記基板を支持する接触支持部が形成され、
前記導電部における、前記インダクタ部を挟んだ前記接触支持部の反対側は、直接的または間接的に接地される基板支持部材。 - 請求項1に記載の基板支持部材において、
前記インダクタ部は、前記導電部の外周に設けられた磁性体コアである。 - 請求項1に記載の基板支持部材において、
前記インダクタ部は、絶縁部材の表面上に導電部材でスパイラルパターンを形成した、スパイラルインダクタである。 - 請求項1に記載の基板支持部材において、
前記インダクタ部は、前記導電部の外周に設けられた磁性体コアと、絶縁部材の表面上に導電部材でスパイラルパターンを形成した、スパイラルパターンを有するスパイラルインダクタと、を有する。 - 請求項1に記載の基板支持部材において、
前記基板支持部材は、基板の載置台上で基板を昇降させる昇降ピンであり、
前記導電部は前記昇降ピンの本体であり、
前記接触支持部は当該昇降ピンの頂上部である。 - 請求項1に記載の基板支持部材において、
前記基板支持部材は、基板の搬送に用いられる搬送アームであり、
前記導電部は前記搬送アームの本体であり、
前記接触支持部は前記搬送アームの上面に設けられたパッドである。 - 基板を載置台上で処理する基板処理装置であって、
前記基板の載置台上で前記基板を昇降させる複数の昇降ピンを有し、
前記昇降ピンのうちの少なくとも1本は、導電性を有する本体と、前記本体の外側に設けられたインダクタ部と、を有し、
前記本体には、前記基板と接触して前記基板を支持する頂上部が形成され、
前記本体における、前記インダクタ部を挟んだ前記頂上部の反対側は、直接的または間接的に接地される。 - 基板を搬送する際に用いられる搬送アームを有する基板搬送装置であって、
前記搬送アームは導電性を有する本体と、前記本体の外側に設けられたインダクタ部と、前記搬送アームの上面に設けられた複数の支持パッドを備え、
これら支持パッドのうち、少なくとも1つの支持パッドは、前記基板と接触して前記基板を支持するパッドであり、かつ前記本体における、前記インダクタ部を挟んだ前記パッドの反対側は、直接的または間接的に接地される。
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US16/771,878 US20210173306A1 (en) | 2017-12-21 | 2018-12-07 | Substrate support member, substrate treatment apparatus, and substrate transfer apparatus |
KR1020207019727A KR102652636B1 (ko) | 2017-12-21 | 2018-12-07 | 기판 지지 부재, 기판 처리 장치 및 기판 반송 장치 |
JP2019560969A JP7050090B2 (ja) | 2017-12-21 | 2018-12-07 | 基板搬送装置 |
CN201880080654.6A CN111466017B (zh) | 2017-12-21 | 2018-12-07 | 基板支承构件、基板处理装置以及基板输送装置 |
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