WO2019061852A1 - Mram与其制作方法 - Google Patents

Mram与其制作方法 Download PDF

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Publication number
WO2019061852A1
WO2019061852A1 PCT/CN2017/116137 CN2017116137W WO2019061852A1 WO 2019061852 A1 WO2019061852 A1 WO 2019061852A1 CN 2017116137 W CN2017116137 W CN 2017116137W WO 2019061852 A1 WO2019061852 A1 WO 2019061852A1
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layer
substrate
top electrode
storage structure
mtj
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PCT/CN2017/116137
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English (en)
French (fr)
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左正笏
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中电海康集团有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

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  • the present application relates to the field of memory, and in particular to an MRAM and a method of fabricating the same.
  • Magnetic Random Access Memory is considered to be the most widely used “universal” processor in the future due to its high density, long life and non-volatile properties. Its core unit of work is a magnetic tunnel junction (MTJ) consisting of a "magnetic reference layer / isolation layer / magnetic free layer” sandwich structure.
  • MTJ magnetic tunnel junction
  • the main functional unit in MRAM is the MTJ unit, and its structure mainly includes magnetic free layer/nonmagnetic oxide layer (MgO)/magnetic pinning layer. Driven by an external magnetic field or current, the magnetic moment direction of the magnetic free layer is reversed, and the direction of the magnetic moment of the magnetic pinning layer is parallel or anti-parallel, so that the MRAM exhibits a low-high resistance state, which can be respectively defined as a storage state. "0" and "1", thereby realizing the storage of information.
  • MgO magnetic free layer/nonmagnetic oxide layer
  • an insulating protective layer 2' is deposited on the exposed surface of the MTJ unit 1'. As shown in FIG. 1, in the subsequent fabrication process, the MTJ unit 1 is required. 'The upper portion of the protective layer 2' is removed to form a structure as shown in FIG. 2 to facilitate connection of the MTJ unit 1' to the top electrode, or to expose the structure formed by the protective layer on the MTJ unit and the top electrode above it. On the surface, it facilitates the electrical connection of the top electrode to other structures.
  • this part of the protective layer has a relatively large dielectric constant, which will reduce the processing speed of the device; and the remaining protective layer other than the portion on the sidewall of the MTJ will cause some stress problems to the device, thereby reducing the device's reliability.
  • the main purpose of the present application is to provide an MRAM and a manufacturing method thereof to solve the problem of excessive capacitance effect of the protective layer around the MTJ and stress caused by the protective layer in the prior art.
  • a method for fabricating an MRAM includes: Step S1, setting a pre-storage structure on a substrate, the pre-storage structure including at least an MTJ unit; and step S2, a protective layer material is disposed on the exposed surface of the pre-storage structure, or a protective layer material is disposed on the exposed surface of the pre-stored structure and the exposed surface of the substrate; and step S3, self-aligned etching by anisotropic etching A portion of the protective layer material is removed to form at least a portion of the sidewalls of the pre-storage structure.
  • the step S1 includes: Step S11, sequentially laying a bottom electrode layer and an MTJ structure layer on the substrate; Step S12, etching and removing a portion of the MTJ structure layer, and the remaining MTJ structure layer forming the MTJ unit, The above pre-storage structure including the above MTJ unit is obtained.
  • the etching in the above step S12 is performed by an anisotropic etching method.
  • the step S11 further includes: providing a first top electrode layer on a surface of the MTJ structural layer remote from the bottom electrode layer, and before etching the MTJ structural layer, the above steps S12 further includes: etching and removing a portion of the first top electrode layer, the remaining first top electrode layer forming a first top electrode, and the pre-storage structure further comprising the first top electrode.
  • the bottom electrode layer is retained, the pre-storage structure includes a bottom electrode layer, and in the step S3, the protective layer is located on the sidewalls of the MTJ unit and the first top electrode.
  • the method further includes: disposing an X+1 dielectric layer on the substrate or the exposed surface of the bottom electrode layer, and separating the X+1th dielectric layer
  • the surface of the substrate and the surface of the first top electrode remote from the substrate form a first plane; a second top electrode layer is disposed on the first plane; and a portion of the second top electrode layer and a portion of the Xth portion are sequentially etched away +1 dielectric layer and a part of the bottom electrode layer, the remaining second top electrode layer forms a second top electrode, and the remaining bottom electrode layer forms a bottom electrode, the bottom electrode, the MTJ unit, and the first top electrode And the second top electrodes are arranged in series.
  • the manufacturing method further includes: disposing an Xth dielectric layer on the substrate; and providing an Xth metal interconnection on the substrate, wherein the Xth dielectric layer is located above Two sides of the Xth metal interconnection, and a surface of the Xth dielectric layer remote from the substrate and a surface of the Xth metal interconnection away from the substrate constitute a second plane; An etch barrier layer is disposed on the surface; and the etch barrier layer on the surface of the Xth metal interconnection portion is removed to form the substrate.
  • the bottom electrode is disposed on a surface of the Xth metal interconnection portion away from the substrate and a portion of the etch barrier layer on the two sides of the Xth metal interconnection portion away from the substrate .
  • the manufacturing method further includes: setting the X+2 on the exposed surface of the X+1th dielectric layer and the exposed surface of at least part of the second top electrode a dielectric layer; an X+1th metal interconnection is disposed on a surface of the second top electrode that is away from the substrate, and the X+2 dielectric layer is located at the X+1th metal inter
  • the two sides of the connecting portion, and the surface of the X+2 dielectric layer away from the substrate are on the same plane as the surface of the X+1th metal interconnection away from the substrate.
  • an MRAM comprising: a substrate; a pre-storage structure disposed on the substrate, the pre-storage structure including at least one MTJ unit; and a protective layer disposed on the pre-storage structure At least part of the side wall.
  • the method does not need to provide a mask layer, the method is simple and easy to control, and the method is disposed on the surface of the substrate on both sides of the MTJ unit.
  • the protective layer material on the surface of the partial pre-storage structure is removed, leaving only the protective layer material on the sidewalls of the pre-storage structure to form a protective layer, avoiding the surface of the substrate on both sides of the MTJ unit or the surface of a part of the pre-storage structure
  • the capacitive effect and stress effect brought by the protective material on the top ensure the better performance of the device.
  • FIG. 1 is a schematic structural view of a prior art after a protective layer is disposed on a surface of an MTJ unit;
  • Figure 2 is a schematic view showing the structure after removing a part of the protective layer of Figure 1;
  • FIG. 3 to FIG. 12 are schematic diagrams showing the structure of a process for fabricating an MRAM according to an embodiment of the present application.
  • the present application proposes an MRAM and a manufacturing method thereof.
  • a method for fabricating an MRAM includes: Step S1, providing a pre-storage structure 2 on a substrate 1, the pre-storage structure 2 including at least an MTJ unit 22, forming a structure as shown in FIG. 5; step S2, providing a protective layer material 30 on the exposed surface of the pre-storage structure 2, forming a structure as shown in FIG.
  • a protective layer material 30 is disposed on the exposed surface of the first layer; in step S3, a portion of the protective layer material 30 is removed by an anisotropic etching self-aligned etching, and the remaining protective layer material 30 is located at least part of the pre-storage structure 2 On the side wall, the protective layer 3 shown in Fig. 7 is formed.
  • the self-aligned etching technique is used to etch the protective layer material, the method does not need to provide a mask layer, the method is simple and easy to control, and the method is to provide the surface of the substrate on both sides of the MTJ unit.
  • the protective layer material on the surface of the upper or part of the pre-storage structure is removed, leaving only the protective layer material on the sidewalls of the pre-storage structure to form a protective layer, avoiding the surface of the substrate on both sides of the MTJ unit or a part of the pre-storage structure.
  • the capacitive effect and stress effect brought by the protective material on the surface ensure the better performance of the device.
  • deposition of the protective layer material 30 is performed under vacuum conditions to prevent the structure of the MTJ unit 22 from being exposed to contamination in the air.
  • the material of the protective layer of the present application may be a combination of one or more of silicon nitride, silicon dioxide, and nitrogen-doped silicon oxide.
  • the material of the protective layer is silicon nitride, and the protective layer material may be provided by chemical vapor deposition or atomic layer deposition techniques.
  • the step S1 includes: Step S11, sequentially laying a bottom electrode layer 210 and an MTJ structure layer 220 on the substrate 1 to form the structure shown in FIG. 4; and step S12, etching and removing A portion of the MTJ structure layer 220, the remaining MTJ structure layer 220 forms the MTJ unit 22, that is, the pre-storage structure 2 including the MTJ unit 22 as shown in FIG.
  • the etching in the above step S12 is performed by an anisotropic etching method.
  • the anisotropic etching method of the present application may be dry etching or wet etching.
  • dry etching reactive ion beam etching, ion beam etching, etc. are commonly used, and those skilled in the art.
  • a suitable anisotropic etching method can be selected according to the actual situation.
  • the etching in the above step S12 can be performed by masking with a hard mask layer, and a corresponding hard mask layer is formed before etching.
  • the step S11 further includes: first, as shown in FIG. 4, setting a first surface of the MTJ structural layer 220 away from the bottom electrode layer 210.
  • the first top electrode 23, the pre-storage structure 2 further includes the first top electrode 23 described above.
  • the top electrode has been disposed on the MTJ unit 22, so that the protective layer material 30 can also protect the top electrode and the metal in which the top electrode is placed diffuses into other structures, further ensuring the performance of the device.
  • the first top electrode layer 230 may not be disposed, and only the bottom electrode layer 210 and the MTJ structure layer 220 are disposed, that is, the two form the pre-storage structure 2, and then directly exposed in the pre-storage structure 2.
  • a protective layer material 30 is disposed on the surface or on the exposed surface of the substrate 1, and then a portion of the protective layer material 30 is removed by self-aligned etching to form a protective layer 3, and then a top electrode is disposed on the exposed surface of the MTJ, specifically
  • process engineering There are generally two kinds of process engineering, one is to provide a dielectric layer on the exposed surface of the pre-storage structure 2 and the exposed surface of the protective layer 3 or also on the exposed surface of the substrate 1, and planarize, and make the MTJ away from the substrate.
  • the surface of 1 is exposed, and then a top electrode layer is disposed on the planarized surface,
  • the top electrode is then formed by an etching process; the other is to provide a dielectric layer on the exposed surface of the pre-storage structure 2 and the exposed surface of the protective layer 3 or also on the exposed surface of the substrate 1, and planarize, and the MTJ
  • the surface away from the substrate 1 is covered, and then a hole is opened in the dielectric layer such that the lower end of the hole is connected to the MTJ, and then a top electrode layer is provided in the hole and planarized to form a top electrode.
  • the material of the bottom electrode layer 210 may be a metal or an alloy. A person skilled in the art may select a suitable metal or the like to form the bottom electrode layer 210 according to actual conditions. In one embodiment, the material of the bottom electrode layer 210 is tantalum.
  • the MTJ structural layer 220 includes a wide variety of material compositions. In one embodiment, it includes a pinned layer, a tunneling layer, and a free layer disposed in series. However, it is not limited to the above-described three-layer structure, and may be other structures such as a structure including an artificial antiferromagnetic layer.
  • the pinning layer may be a PtMn layer
  • the tunneling layer is a MgO layer
  • the free layer is a CoFeB layer.
  • the pinning layer may be a PtMn layer
  • the tunneling layer is a MgO layer
  • the free layer is a CoFeB layer.
  • it is not limited to the above material layer, and may be a corresponding structural layer formed of other materials.
  • the bottom electrode layer 210 is left, that is, the bottom electrode layer 210 is not etched, and the bottom electrode layer 210 is used as the etch stop layer 13 in step S12, such as
  • the pre-storage structure 2 includes a bottom electrode layer 210, and in the above step S2, on the exposed surface of the bottom electrode layer 210, the exposed surface of the MTJ unit 22, and the exposed surface of the first top electrode 23
  • the protective layer material 30 is provided, and the protective layer 3 formed in the above step S3 is located on the sidewalls of the MTJ unit 22 and the first top electrode 23.
  • the bottom electrode layer 210 may be etched to form a pre-storage structure 2 including a bottom electrode 21, an MTJ unit 22, and a top electrode disposed in this order.
  • the protective layer 3 is disposed on the pre-storage structure 2 and the exposed surface of the substrate 1, and, in the self-aligned etching, the protective layer 3 on the surface of the substrate 1 and the protective layer material of the surface of the MTJ unit 22 away from the substrate 1 are removed. 30.
  • the remaining protective layer material 30 is disposed on the bottom electrode 21, the MTJ unit 22, and the sidewalls of the top electrode to form a protective layer 3.
  • the manufacturing method further includes: on the substrate 1 on the two sides of the protective layer 3 or the bottom An X+1 dielectric layer 4 is disposed on the exposed surface of the electrode layer 210, as shown in FIG. 8, and the surface of the X+1th dielectric layer 4 on both sides of the protective layer 3 away from the substrate 1 Forming a first plane with the surface of the first top electrode 23 remote from the substrate 1 described above, the step is actually to first correspond to the dielectric material and then planarize, considering that the planarization process causes the first electrode to lose a certain thickness.
  • the embodiment further includes: providing a second top electrode layer 240 on the first plane to form the structure shown in FIG. 9; A portion of the second top electrode layer 240, a portion of the X+1th dielectric layer 4, and a portion of the bottom electrode layer 210 are removed, and the remaining second top electrode layer 240 forms a second top electrode 24, as shown in FIG. The rest The bottom electrode layer 210 forms a bottom electrode 21, and the bottom electrode 21, the MTJ unit 22, the first top electrode 23, and the second top electrode 24 are sequentially stacked.
  • the material of the top electrode of the present application is a metal or an alloy, and may specifically include tantalum, tantalum nitride, titanium, and/or titanium nitride.
  • the person skilled in the art may select a suitable material to form a top electrode according to actual conditions. If it is necessary to form the first top electrode 23 and the second top electrode 24 in the fabrication process, the materials of the two may be independently selected from the above materials.
  • the structure generally only needs to provide a top electrode layer to form the top electrode, and it is not necessary to form two contact top electrodes, and it is not necessary to provide two top electrode layers.
  • the manufacturing method further includes: on the substrate (not shown) The Xth dielectric layer 11 is disposed on the substrate; the Xth metal interconnection is disposed on the substrate, and the Xth dielectric layer 11 is located on both sides of the Xth metal interconnection, and the above a surface of the Xth dielectric layer 11 remote from the substrate and a surface of the Xth metal interconnection away from the substrate to form a second plane; an etch barrier layer 13 is disposed on the second plane; The above-described etch barrier layer 13 on the surface of the X metal interconnections forms the above-described substrate 1 shown in FIG.
  • the material of the etch stop layer 13 described above may be an inorganic material including a combination of one or more of silicon nitride, silicon oxide-doped silicon oxide, and nitrogen-doped silicon carbide. In some embodiments, it can also be an organic material.
  • the material of the etch barrier layer 13 is nitrogen-doped silicon carbide, which is prepared by chemical vapor deposition, and the chemical formula of the deposited material is Si a C b N c H d (where a, b, c, and d all represent the number of atoms in the molecule, and the specific data is determined according to chemical feasibility). Patterning is performed on the etch barrier layer 13 by a photolithography process, and then a barrier etch process is performed to form a trench to expose the bottom metal material.
  • the process of forming the Xth metal interconnection portion in FIG. 3 and the Xth dielectric layer 11 on both sides thereof has various specific embodiments. The following is described in two specific manners. One mode is as follows: An Xth dielectric layer 11 is disposed on the surface of the substrate, and then a hole or a groove is formed in the Xth dielectric layer 11. Finally, the hole is filled with metal and planarized to form a partial structure in FIG. And, in this embodiment, the Xth dielectric layer 11 is also located below the Xth metal interconnection, this embodiment is more conventional and generally referred to as the Damascene process; the other way is: lining The bottom surface is provided with a metal and etched to form an Xth metal interconnection shown in FIG. 3. Then, a dielectric material is disposed on the exposed surface of the substrate and the Xth metal interconnection, and planarized to form The Xth dielectric layer 11 in FIG.
  • the distance of the surface of the pre-stored structure 2 away from the substrate 1 from the substrate 1 is greater than or equal to the etch barrier layer 13 in the present application.
  • the distance from the surface of the substrate 1 to the substrate 1 that is, the surface of the pre-storage structure 2 that is the largest distance from the substrate 1 is higher than the surface of the etch barrier layer 13 that is the largest distance from the substrate 1 , which can simplify the subsequent fabrication process. It can also reduce the difficulty of the subsequent manufacturing process, and can further ensure that the fabricated device has good performance.
  • a person skilled in the art can select an appropriate method to form the Xth metal interconnection portion 12 and the Xth dielectric layer 11 in FIG. 3 according to actual conditions.
  • the bottom electrode layer 210 is disposed on a surface of the Xth metal interconnection portion away from the substrate and the Xth metal interconnection portion 12 A portion of the side of the etch stop layer 13 is away from the surface of the substrate. This can further prevent the metal of the X metal interconnections from diffusing upward into other structural layers, thereby ensuring good performance of the formed MRAM.
  • the manufacturing method further includes: in the X+1th dielectric layer 4 On the exposed surface and at least in part The X+2 dielectric layer 5 is disposed on the exposed surface of the second top electrode 24 to form the structure shown in FIG. 11; and the Xth surface is disposed on the surface of the second top electrode 24 away from the substrate 1 at least partially exposed.
  • +1 metal interconnections 6 form the structure shown in FIG. 12, and the X+2 dielectric layers 5 are located on both sides of the X+1th metal interconnection 6 and the X+2
  • the surface of the dielectric layer 5 away from the substrate 1 is on the same plane as the surface of the X+1th metal interconnection 6 away from the substrate 1.
  • the forming process of forming the X+1th metal interconnection 6 and the X+2 dielectric layers 5 on both sides thereof may refer to forming the Xth metal interconnection and the X+ on both sides thereof.
  • the formation process of one dielectric layer 4 will not be described here.
  • the above-described substrate of the present application includes all necessary structures and devices of the prior art, including, for example, CMOS, X-1 dielectric layers, and X-1 metal interconnections, and the like.
  • the materials of the Xth dielectric layer 11, the X+1th dielectric layer 4, and the X+2 dielectric layer 5 in the present application may be independently selected from silicon dioxide, low dielectric constant dielectric or ultra low Dielectric constant dielectric.
  • a person skilled in the art can select an appropriate material and a suitable method to form X dielectric layers, an X+1 dielectric layer 4, and an X+2 dielectric layer 5 according to actual conditions.
  • an MRAM is provided. As shown in FIG. 10 and FIG. 12, the MRAM includes a substrate 1, a pre-storage structure 2, and a protective layer 3.
  • the pre-storage structure 2 is disposed on the substrate.
  • the pre-storage structure 2 includes at least one MTJ unit 22; and the protective layer 3 is disposed on at least a portion of the side wall of the pre-storage structure 2.
  • the protective layer is disposed only on the sidewall of the pre-storage structure, avoiding the surface of the substrate on both sides of the MTJ unit or The capacitive effect and stress effect brought by the protective layer material on the surface of the partial pre-storage structure ensure the better performance of the device.
  • the substrate 1 in the above application further includes an Xth dielectric layer 11 and an Xth metal interconnection 12, and the specific positional relationship may refer to the figure. 12 and FIG. 3 and the like, but are not limited to such a positional relationship.
  • the pre-storage structure 2 includes a bottom electrode layer 210, an MTJ unit 22, and a first top electrode 23, as shown in FIG. 12, and of course, is not limited to the pre-storage structure 2,
  • the pre-storage structure 2 may further include a bottom electrode 21, an MTJ unit 22, and a first top electrode 23, or a bottom electrode 21 and an MTJ unit 22, or a bottom electrode layer 210 and an MTJ unit 22.
  • Those skilled in the art can pre-store the structure 2 to be a suitable film layer structure according to actual conditions.
  • the MRAM is further ensured.
  • the bottom electrode 21 is disposed on the Xth. A portion of the metal interconnection portion away from the substrate and a portion of the etch barrier layer 13 on both sides of the X-th metal interconnection portion 12 away from the substrate.
  • the MRAM includes two connected top electrodes, that is, a first top electrode 23 and a second top electrode 24.
  • the positional relationship is as shown in FIG. 2, and the two top electrodes can be better. Ensure the electrical performance of the MRAM.
  • the MRAM further includes an X+1th dielectric layer 4, and the specific position is shown in FIG. 12 and the like.
  • the MRAM further includes an X+2 dielectric layer 5 and an X+1th metal interconnection 6.
  • the specific positional relationship may refer to FIG. 12 and FIG. 3, etc., but Not limited to this kind of positional relationship. This can further electrically connect the top electrode of the MTJ to other structures.
  • the self-aligned etching technique is used to etch the protective layer material, the method does not need to provide a mask layer, the method is simple and easy to control, and the method is set in the MTJ unit two
  • the protective layer material on the surface of the side substrate or on the surface of a portion of the pre-storage structure is removed, leaving only the protective layer material on the sidewalls of the pre-storage structure to form a protective layer, avoiding the surface of the substrate on both sides of the MTJ unit or partially
  • the capacitive and stress effects of the protective material on the surface of the pre-storage structure ensure better performance of the device.

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Abstract

一种MRAM与其制作方法。该制作方法包括：步骤S1，在基底（1）上设置预存储结构（2），预存储结构（2）至少包括MTJ单元（22）；步骤S2，在预存储结构（2）的裸露表面上设置保护层材料，或者在预存储结构（2）的裸露表面上以及基底（1）的裸露表面上设置保护层材料；步骤S3，采用各向异性刻蚀法自对准刻蚀去除部分保护层材料，形成位于预存储结构（2）的至少部分侧壁上的保护层（3）。采用自对准刻蚀技术刻蚀保护层，该方法无需设置掩膜层，方法简单，容易控制，且只留下预存储结构侧壁上的保护层材料，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料带来的电容效应和应力效应，保证了器件具有较好的性能。

Description

MRAM与其制作方法 技术领域
本申请涉及存储器领域，具体而言，涉及一种MRAM与其制作方法。
背景技术
磁性随机存储器(Magnetic Random Access Memory，简称MRAM)由于具有高密度、寿命长以及非易失等优点，被认为是未来最广泛应用的“通用”处理器。它的核心工作单元是由“磁参考层/隔离层/磁自由层”三明治结构组成的磁隧道结(MTJ)。
MRAM中的主要功能单元为MTJ单元，其结构主要包括磁性自由层/非磁性氧化层(MgO)/磁性钉扎层。在外加磁场或电流等驱动下，磁性自由层的磁矩方向发生翻转，与磁性钉扎层的磁矩方向呈现平行态或反平行态，使得MRAM出现低高电阻态，可分别定义为存储态“0”和“1”，从而实现信息的存储。
现有技术中在刻蚀形成MTJ单元后，会在MTJ单元1'的裸露表面上沉积一层绝缘的保护层2'，如图1所示，在后续的制作过程中，需要将MTJ单元1'上方的那一部分保护层2'去除，形成如图2所示的结构，以方便MTJ单元1'与顶电极相连，或者当保护层设置在MTJ单元以及其上方的顶电极形成的结构的裸露表面上时，方便顶电极与其他结构的电连接。但是，这一部分保护层的介电常数比较大，会降低器件的处理速度；并且，剩余的除了MTJ侧壁上的部分之外的保护层会给器件带来一定的应力问题，从而降低器件的可靠性。
发明内容
本申请的主要目的在于提供一种MRAM与其制作方法，以解决现有技术中MTJ周围保护层过多的电容效应和保护层带来的应力问题。
为了实现上述目的，根据本申请的一个方面，提供了一种MRAM的制作方法，该制作方法包括：步骤S1，在基底上设置预存储结构，上述预存储结构至少包括MTJ单元；步骤S2，在上述预存储结构的裸露表面上设置保护层材料，或者在上述预存储结构的裸露表面上以及上述基底的裸露表面上设置保护层材料；步骤S3，采用各向异性刻蚀法自对准刻蚀去除部分上述保护层材料，形成位于上述预存储结构的至少部分侧壁上。
进一步地，上述步骤S1包括：步骤S11，在上述基底上依次叠置设置底电极层与MTJ结构层；步骤S12，刻蚀去除部分上述MTJ结构层，剩余的上述MTJ结构层形成上述MTJ单元，得到包括上述MTJ单元的上述预存储结构。
进一步地，采用各向异性刻蚀法实施上述步骤S12中的刻蚀。
进一步地，在设置上述MTJ结构层之后，上述步骤S11还包括：在上述MTJ结构层的远离上述底电极层的表面上设置第一顶电极层，且在刻蚀上述MTJ结构层之前，上述步骤S12还包括：刻蚀去除部分上述第一顶电极层，剩余的上述第一顶电极层形成第一顶电极，上述预存储结构还包括上述第一顶电极。
进一步地，上述步骤S12中，保留上述底电极层，上述预存储结构包括底电极层，且上述步骤S3中，上述保护层位于上述MTJ单元以及上述第一顶电极的侧壁上。
进一步地，在上述步骤S3之后，上述制作方法还包括：在上述基底上或者上述底电极层的裸露表面上设置第X+1个介电层，且上述第X+1个介电层的远离上述基底的表面与上述第一顶电极的远离上述基底的表面构成第一平面；在上述第一平面上设置第二顶电极层；依次刻蚀去除部分上述第二顶电极层、部分上述第X+1个介电层以及部分上述底电极层，剩余的上述第二顶电极层形成第二顶电极，剩余的上述底电极层形成底电极，上述底电极、上述MTJ单元、上述第一顶电极以及上述第二顶电极依次叠置设置。
进一步地，在上述步骤S1之前，上述制作方法还包括：在衬底上设置第X个介电层；在上述衬底上设置第X个金属互连部，上述第X个介电层位于上述第X个金属互连部的两侧，且上述第X个介电层的远离上述衬底的表面与上述第X个金属互连部远离上述衬底的表面构成第二平面；在上述第二平面上设置刻蚀阻挡层；去除上述第X个金属互连部表面上的上述刻蚀阻挡层，形成上述基底。
进一步地，上述底电极设置在上述第X个金属互连部的远离上述衬底的表面上以及上述第X个金属互连部两侧的部分上述刻蚀阻挡层的远离上述衬底的表面上。
进一步地，在形成上述第二顶电极后，上述制作方法还包括：在上述第X+1个介电层的裸露表面上以及至少部分上述第二顶电极的裸露表面上设置第X+2个介电层；在至少部分裸露上述第二顶电极的远离上述基底的表面上设置第X+1个金属互连部，且上述第X+2个介电层位于上述第X+1个金属互连部的两侧，且上述第X+2个介电层远离上述基底的表面与上述第X+1个金属互连部的远离上述基底的表面在同一个平面上。
根据本申请的另一方面，提供了一种MRAM，该MRAM包括：基底；预存储结构，设置在上述基底上，上述预存储结构至少包括一个MTJ单元；保护层，设置在上述预存储结构的至少部分侧壁上。
应用本申请的技术方案，采用自对准刻蚀技术刻蚀保护层材料，该方法无需设置掩膜层，方法简单，容易控制，并且，该方法中将设置在MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料去除，只留下预存储结构侧壁上的保护层材料形成保护层，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护材料带来的电容效应和应力效应，从而保证了器件具有较好的性能。
附图说明
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1示出了现有技术中的在MTJ单元的表面上设置保护层后的结构示意图；
图2示出了将图1中的部分保护层去除后的结构示意图；以及
图3至图12示出了本申请的一种实施例提供的MRAM的制作方法过程的结构示意图。
其中，上述附图包括以下附图标记：
1'、MTJ单元；2'、保护层；1、基底；11、第X个介电层；12、第X个金属互连部；13、刻蚀阻挡层；2、预存储结构；21、底电极；22、MTJ单元；23、第一顶电极；24、第二顶电极；3、保护层；4、第X+1个介电层；5、第X+2个介电层；6、第X+1个金属互连部；30、保护层材料；210、底电极层；220、MTJ结构层；230、第一顶电极层；240、第二顶电极层。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本申请提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本申请所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及下面的权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“电连接”至该另一元件。
正如背景技术所介绍的，现有技术中，在MTJ的表面上设置的保护层的去除较难控制，为了解决如上的技术问题，本申请提出了一种MRAM与其制作方法。
本申请的一种典型的实施方式中，提供了一种MRAM的制作方法，该制作方法包括：步骤S1，在基底1上设置预存储结构2，上述预存储结构2至少包括MTJ单元22，形成如图5所示的结构；步骤S2，在上述预存储结构2的裸露表面上设置保护层材料30，形成如图6所示的结构，或者在上述预存储结构2的裸露表面上以及上述基底1的裸露表面上设置保护层材料30；步骤S3，采用各向异性刻蚀法自对准刻蚀去除部分上述保护层材料30，剩余的上述保护层材料30位于上述预存储结构2的至少部分侧壁上，形成图7所示的保护层3。
本申请的上述制作方法中，采用自对准刻蚀技术刻蚀保护层材料，该方法无需设置掩膜层，方法简单，容易控制，并且，该方法中将设置在MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料去除，只留下预存储结构侧壁上的保护层材料形成保护层，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护材料带来的电容效应和应力效应，从而保证了器件具有较好的性能。
在形成预存储结构2后，在真空条件下进行保护层材料30的沉积，以防止MTJ单元22等结构暴露在空气中被污染损坏。
本申请的保护层的材料可以为氮化硅、二氧化硅与氮掺杂的氧化硅中的一种或者多种的组合。
一种具体的实施例中，保护层的材料为氮化硅，可以由化学气相沉积或者原子层沉积技术设置保护层材料。
本申请的一种实施例中，上述步骤S1包括：步骤S11，在上述基底1上依次叠置设置底电极层210与MTJ结构层220，形成图4所示的结构；步骤S12，刻蚀去除部分上述MTJ结构层220，剩余的上述MTJ结构层220形成上述MTJ单元22，即形成如图5所示的包括上述MTJ单元22的上述预存储结构2。
为了进一步保证形成的预存储结构2是预定的形状，进而保证该MRAM具有良好的性能，本申请的一种实施例中，采用各向异性刻蚀法实施上述步骤S12中的刻蚀。
本申请的各向异性刻蚀法可以是干法刻蚀也可以是湿法刻蚀，对于干法刻蚀来说，常用的有反应离子束刻蚀和离子束刻蚀等，本领域技术人员可以根据实际情况选择合适的各向异性刻蚀法。上述步骤S12中的刻蚀可以采用硬掩膜层掩蔽进行刻蚀，在刻蚀前，先形成对应的硬掩膜层。
本申请的另一种实施例中，在设置上述MTJ结构层220之后，上述步骤S11还包括：如图4所示，在上述MTJ结构层220的远离上述底电极层210的表面上设置第一顶电极层230，且在刻蚀上述MTJ结构层220之前，上述步骤S12还包括：刻蚀去除部分上述第一顶电极层230，如图5所示，剩余的上述第一顶电极层230形成第一顶电极23，上述预存储结构2还包括上述第一顶电极23。这样在设置保护层材料30之前，在MTJ单元22上已经设置了顶电极，使得保护层材料30还可以保护顶电极且放置顶电极的金属扩散到其他结构中，进一步保证了器件的性能。
当然，本申请的步骤S11中也可以不设置第一顶电极层230，只设置底电极层210与MTJ结构层220，即二者形成预存储结构2，之后，直接在预存储结构2的裸露表面上或者还有基底1的裸露表面上设置保护层材料30，然后再自对准刻蚀去除部分保护层材料30，形成保护层3，接着，在MTJ裸露的表面上设置顶电极，具体的工艺工程一般有两种，一种是在预存储结构2的裸露表面与保护层3的裸露表面上或者还有基底1的裸露表面上设置介电层，并且平坦化，且使得MTJ的远离基底1的表面露出，然后再在平坦化后的表面上设置顶电极层， 随后通过刻蚀工艺形成顶电极；另一种是在预存储结构2的裸露表面与保护层3的裸露表面上或者还有基底1的裸露表面上设置介电层，并且平坦化，且MTJ的远离基底1的表面被覆盖，然后，在介电层中开孔，使得该孔的下端与MTJ连接上，随后，在该孔中设置顶电极层并平坦化形成顶电极。
底电极层210的材料可以是金属或者合金，本领域技术人员可以根据实际情况选择合适的金属等形成底电极层210。一种实施例中，底电极层210的材料为钽。
MTJ结构层220包括很多种材料组分。一种实施例中，其包括依次叠置设置的钉扎层、隧穿层和自由层。但并不限于上述的三层结构，还可以是其他的结构，例如包括人工反铁磁层等的结构。
一种具体的实施例中，钉扎层可以是PtMn层，隧穿层为MgO层，自由层为CoFeB层。当然并不限于上述的材料层，还可以是其他材料形成的对应结构层。
本申请的再一种实施例中，上述步骤S12中，保留上述底电极层210，即不对底电极层210进行刻蚀，且该底电极层210作为步骤S12中的刻蚀阻挡层13，如图5所示，上述预存储结构2包括底电极层210，且上述步骤S2中，在上述底电极层210的裸露表面、上述MTJ单元22的裸露表面以及上述第一顶电极23的裸露表面上设置上述保护层材料30，且上述步骤S3中，形成的上述保护层3位于上述MTJ单元22以及上述第一顶电极23的侧壁上。
当然，在上述步骤S12中，也可以对上述底电极层210进行刻蚀，进而形成包括依次叠置设置的底电极21、MTJ单元22以及顶电极的预存储结构2，后续的工艺中，在预存储结构2以及基底1的裸露表面上设置保护层3，并且，自对准刻蚀时，去除的是基底1表面上的保护层3以及MTJ单元22的远离基底1的表面的保护层材料30，剩余的保护层材料30设置在底电极21、MTJ单元22以及顶电极的侧壁上，形成保护层3。
为了进一步保证形成的MRAM具有良好的电性能，本申请的一种实施例中，上述在上述步骤S3之后，上述制作方法还包括：在上述保护层3的两侧的上述基底1上或者上述底电极层210的裸露表面上设置第X+1个介电层4，如图8所示，且上述保护层3的两侧的上述第X+1个介电层4的远离上述基底1的表面与上述第一顶电极23的远离上述基底1的表面构成第一平面，该步骤实际上是先设施对应介电材料然后再平坦化，考虑到平坦化的工艺会使得第一电极损失一定的厚度，所以，为了形成良好的电接触，保证器件具有良好的电性能，该实施例中还包括：在上述第一平面上设置第二顶电极层240，形成图9所示的结构；依次刻蚀去除部分上述第二顶电极层240、部分上述第X+1个介电层4以及部分上述底电极层210，剩余的上述第二顶电极层240形成第二顶电极24，如图10所示，剩余的上述底电极层210形成底电极21，上述底电极21、上述MTJ单元22、上述第一顶电极23以及上述第二顶电极24依次叠置设置。
本申请的顶电极的材料为金属或者合金，具体可以包括钽，氮化钽，钛和/或氮化钛等，本领域技术人员可以根据实际情况选择合适的材料形成顶电极。如果制作工艺中需要形成第一顶电极23与第二顶电极24，则二者的材料可以独立地选自上述材料。
当然，如果顶电极在保护层3刻蚀之后设置，该结构一般只需要设置一层顶电极层来形成顶电极，不需要形成两个接触的顶电极，也无需设置两个顶电极层。
为了方便MTJ与其他结构电连接，以进一步保证形成的MRAM具有良好的电学性能，本申请的一种实施例中，在上述步骤S1之前，上述制作方法还包括：在衬底(图中未示出)上设置第X个介电层11；在上述衬底上设置第X个金属互连部，且上述第X个介电层11位于上述第X个金属互连部的两侧，且上述第X个介电层11的远离上述衬底的表面与上述第X个金属互连部远离上述衬底的表面构成第二平面；在上述第二平面上设置刻蚀阻挡层13；去除上述第X个金属互连部表面上的上述刻蚀阻挡层13，形成图3所示的上述基底1。
上述的刻蚀阻挡层13的材料可以是无机材料，包括氮化硅、二氧化硅氮掺杂的氧化硅与氮掺杂的碳化硅中的一种或者多种的组合。在某些实施例中，也可以是有机材料。
本申请的一种具体的实施例中，刻蚀阻挡层13的材料为氮掺杂的碳化硅，采用化学气相沉积法制备，所沉积材料的化学式为SiaCbNcHd(其中，a、b、c以及d均表示分子中该原子的个数，具体数据根据化学可行性来确定)。采用光刻工艺在刻蚀阻挡层13上进行图案化，然后进行阻挡层刻蚀工艺形成沟道，露出底部金属材料。
形成图3中的上述第X个金属互连部以及其两侧的第X个介电层11的过程有多种具体的实施方式，以下以两种具体的方式来说明，一种方式为：在衬底的表面上设置第X个介电层11，然后，在该第X个介电层11中开孔或槽，最后，在孔中填充金属并平坦化，形成图3中的部分结构，并且，这种实施方式中，第X个介电层11还位于第X个金属互连部的下方，该种实施方式比较常规，且一般称为大马士革工艺；另一种方式为：在衬底的表面设置金属并且刻蚀形成图3所示的第X个金属互连部，然后，在衬底以及该第X个金属互连部的裸露表面上设置介电材料，并平坦化，形成图3中的第X个介电层11。
无论是预存储结构2中包括还是不包括第一顶电极层230，本申请中优选本申请中优选预存储结构2的远离基底1的表面与基底1的距离大于或者等于刻蚀阻挡层13的远离基底1的表面与基底1的距离，即预存储结构2的与基底1距离最大的表面高于刻蚀阻挡层13的与基底1距离最大的表面，这样可以既可以简化后续的制作工艺，也可以降低后续制作工艺的难度，还可以进一步保证制作得到的器件具有良好的性能。
本领域技术人员可以根据实际情况选择合适的方法形成图3中的第X个金属互连部12以及第X个介电层11。
本申请的另一种实施例中，如图10所示，上述底电极层210设置在上述第X个金属互连部的远离上述衬底的表面上以及上述第X个金属互连部12两侧的部分上述刻蚀阻挡层13的远离上述衬底的表面上。这样可以更进一步地防止X个金属互连部的金属向上扩散到其他结构层中，进而保证了形成的MRAM具有良好的性能。
为了将MTJ上方的电极与其他的金属层电连接，本申请的一种实施例中，在形成上述第二顶电极24后，上述制作方法还包括：在上述第X+1个介电层4的裸露表面上以及至少部分 上述第二顶电极24的裸露表面上设置第X+2个介电层5，形成图11所示的结构；在至少部分裸露上述第二顶电极24的远离上述基底1的表面上设置第X+1个金属互连部6，形成图12所示的结构，且上述第X+2个介电层5位于上述第X+1个金属互连部6的两侧，且上述第X+2个介电层5远离上述基底1的表面与上述第X+1个金属互连部6的远离上述基底1的表面在同一个平面上。
上述的形成第X+1个金属互连部6以及其两侧的第X+2个介电层5的形成过程可以参照上述的形成第X个金属互连部以及其两侧的第X+1个介电层4的形成过程，此处就不再赘述了。
本申请的上述衬底包含前道工艺所有必要的结构以及器件，例如包括CMOS、X-1个介电层、以及X-1个金属互连部等。
本申请中的第X个介电层11、第X+1个介电层4以及第X+2个介电层5的材料可以独立地选自二氧化硅、低介电常数电介质或者超低介电常数电介质。本领域技术人员可以根据实际情况选择合适的材料以及合适的方法形成X个介电层、第X+1个介电层4以及第X+2个介电层5。
本申请的另一种典型的实施方式中，提供了一种MRAM，如图10以及图12所示，该MRAM包括基底1、预存储结构2以及保护层3，预存储结构2设置在上述基底1上，上述预存储结构2至少包括一个MTJ单元22；保护层3设置在上述预存储结构2的至少部分侧壁上。
该MRAM中，MTJ单元两侧的基底表面上或者是部分预存储结构的表面上没有设置保护材料，保护层只设置在预存储结构侧壁上，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料带来的电容效应和应力效应，从而保证了器件具有较好的性能。
本申请的另一种实施例中，如图12所示，上述本申请中的基底1中还包括第X个介电层11与第X个金属互连部12，具体的位置关系可以参照图12以及图3等，但是并不限于该种位置关系。
本申请的再一种实施例中，上述预存储结构2包括底电极层210、MTJ单元22以及第一顶电极23，如图12所示，当然，并不限于该种预存储结构2，上述预存储结构2还可以包括底电极21、MTJ单元22以及第一顶电极23，或者包括底电极21与MTJ单元22，再或者包括底电极层210与MTJ单元22。本领域技术人员可以根据实际情况预存储结构2设置为合适的膜层结构。
为了进一步避免第X个金属互连部中的金属向上方扩散出去，进一步保证MRAM具有良好的性能，本申请的一种实施例中，如图12所示，上述底电极21设置在上述第X个金属互连部的远离上述衬底的表面上以及上述第X个金属互连部12两侧的部分上述刻蚀阻挡层13的远离上述衬底的表面上。
本申请的再一种实施例中，上述MRAM包括两个连接的顶电极，即第一顶电极23与第二顶电极24，位置关系如图2所示，通过两个顶电极可以更好地保证该MRAM的电学性能。
为了进一步保证MRAM具有良好的性能，本申请的一种实施例中，上述MRAM还包括第X+1个介电层4，具体的位置见图12等。
本申请的又一种实施例中，上述MRAM还包括第X+2个介电层5与第X+1个金属互连部6，具体的位置关系可以参照图12以及图3等，但是并不限于该种位置关系。这样可以进一步将MTJ的顶电极与其他的结构电连接。
从以上的描述中，可以看出，本申请上述的实施例实现了如下技术效果：
1)、本申请的MRAM的制作方法中，采用自对准刻蚀技术刻蚀保护层材料，该方法无需设置掩膜层，方法简单，容易控制，并且，该方法中将设置在MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料去除，只留下预存储结构侧壁上的保护层材料形成保护层，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护材料带来的电容效应和应力效应，从而保证了器件具有较好的性能。
2)、本申请的MRAM中，MTJ单元两侧的基底表面上或者是部分预存储结构的表面上没有设置保护材料，保护层只设置在预存储结构侧壁上，避免了MTJ单元两侧的基底表面上或者是部分预存储结构的表面上的保护层材料带来的电容效应和应力效应，从而保证了器件具有较好的性能。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种MRAM的制作方法，其特征在于，所述制作方法包括：
    步骤S1，在基底上设置预存储结构，所述预存储结构至少包括MTJ单元；
    步骤S2，在所述预存储结构的裸露表面上设置保护层材料，或者在所述预存储结构的裸露表面上以及所述基底的裸露表面上设置保护层材料；以及
    步骤S3，采用各向异性刻蚀法自对准刻蚀去除部分所述保护层材料，形成位于所述预存储结构的至少部分侧壁上的保护层。
  2. 根据权利要求1所述的制作方法，其特征在于，所述步骤S1包括：
    步骤S11，在所述基底上依次叠置设置底电极层与MTJ结构层；以及
    步骤S12，刻蚀去除部分所述MTJ结构层，剩余的所述MTJ结构层形成所述MTJ单元，得到包括所述MTJ单元的所述预存储结构。
  3. 根据权利要求2所述的制作方法，其特征在于，采用各向异性刻蚀法实施所述步骤S12中的刻蚀。
  4. 根据权利要求2所述的制作方法，其特征在于，
    在设置所述MTJ结构层之后，所述步骤S11还包括：
    在所述MTJ结构层的远离所述底电极层的表面上设置第一顶电极层，
    且在刻蚀所述MTJ结构层之前，所述步骤S12还包括：
    刻蚀去除部分所述第一顶电极层，剩余的所述第一顶电极层形成第一顶电极，所述预存储结构还包括所述第一顶电极。
  5. 根据权利要求4所述的制作方法，其特征在于，所述步骤S12中，保留所述底电极层，所述预存储结构包括底电极层，且所述步骤S3中，所述保护层位于所述MTJ单元以及所述第一顶电极的侧壁上。
  6. 根据权利要求4所述的制作方法，其特征在于，在所述步骤S3之后，所述制作方法还包括：
    在所述基底上或者所述底电极层的裸露表面上设置第X+1个介电层，且所述第X+1个介电层的远离所述基底的表面与所述第一顶电极的远离所述基底的表面构成第一平面；
    在所述第一平面上设置第二顶电极层；以及
    依次刻蚀去除部分所述第二顶电极层、部分所述第X+1个介电层以及部分所述底电极层，剩余的所述第二顶电极层形成第二顶电极，剩余的所述底电极层形成底电极，所述底电极、所述MTJ单元、所述第一顶电极以及所述第二顶电极依次叠置设置。
  7. 根据权利要求6所述的制作方法，其特征在于，在所述步骤S1之前，所述制作方法还包括：
    在衬底上设置第X个介电层；
    在所述衬底上设置第X个金属互连部，所述第X个介电层位于所述第X个金属互连部的两侧，且所述第X个介电层的远离所述衬底的表面与所述第X个金属互连部远离所述衬底的表面构成第二平面；
    在所述第二平面上设置刻蚀阻挡层；以及
    去除所述第X个金属互连部表面上的所述刻蚀阻挡层，形成所述基底。
  8. 根据权利要求7所述的制作方法，其特征在于，所述底电极设置在所述第X个金属互连部的远离所述衬底的表面上以及所述第X个金属互连部两侧的部分所述刻蚀阻挡层的远离所述衬底的表面上。
  9. 根据权利要求6所述的制作方法，其特征在于，在形成所述第二顶电极后，所述制作方法还包括：
    在所述第X+1个介电层的裸露表面上以及至少部分所述第二顶电极的裸露表面上设置第X+2个介电层；以及
    在至少部分裸露所述第二顶电极的远离所述基底的表面上设置第X+1个金属互连部，且所述第X+2个介电层位于所述第X+1个金属互连部的两侧，且所述第X+2个介电层远离所述基底的表面与所述第X+1个金属互连部的远离所述基底的表面在同一个平面上。
  10. 一种MRAM，其特征在于，所述MRAM包括：
    基底(1)；
    预存储结构(2)，设置在所述基底(1)上，所述预存储结构(2)至少包括一个MTJ单元(22)；以及
    保护层(3)，设置在所述预存储结构(2)的至少部分侧壁上。
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