WO2019042014A1 - 一种阵列基板、显示面板、显示装置及其制作方法 - Google Patents

一种阵列基板、显示面板、显示装置及其制作方法 Download PDF

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Publication number
WO2019042014A1
WO2019042014A1 PCT/CN2018/094879 CN2018094879W WO2019042014A1 WO 2019042014 A1 WO2019042014 A1 WO 2019042014A1 CN 2018094879 W CN2018094879 W CN 2018094879W WO 2019042014 A1 WO2019042014 A1 WO 2019042014A1
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WIPO (PCT)
Prior art keywords
wiring
substrate
array substrate
layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/094879
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English (en)
French (fr)
Inventor
艾雨
谢学武
吴键
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/335,332 priority Critical patent/US11315999B2/en
Publication of WO2019042014A1 publication Critical patent/WO2019042014A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, a display device, and a method of fabricating the same.
  • OLED Organic Light-Emitting Diode
  • the current array substrate includes a display region and a non-display region, and a thin film transistor layer, a metal anode layer, a color film layer, an organic light emitting material layer and a metal cathode layer are formed in the display region, and data lines are formed in the non-display area and covered in the data.
  • the passivation layer on the line, the passivation layer protects the data line.
  • inventions of the present disclosure provide an array substrate.
  • the substrate includes: a substrate, a wiring on the substrate, a first insulating layer covering the wiring, and a protrusion on the first insulating layer and located in a non-display area of the array substrate.
  • the raised portion is adjacent to the wiring, and wherein a surface of the raised portion away from the base substrate is away from the base substrate than a portion of the first insulating layer covering the wiring The surface is further away from the substrate substrate.
  • At least a portion of the positive projection of the signal line on the substrate of the array substrate does not overlap the orthographic projection of the raised portion on the substrate.
  • the protective layer is disposed on both sides of the wiring.
  • the orthogonal projection of the wiring on the base substrate does not overlap the orthographic projection of the raised portion on the base substrate.
  • the array substrate further includes a circuit board disposed on the convex portion, and a conductive portion disposed on a side of the circuit board facing the wiring.
  • the conductive portion is electrically connected to the wiring through a via provided on the first insulating layer.
  • An orthographic projection of the conductive portion on the base substrate is between an orthographic projection of the raised portion on the base substrate.
  • the thickness of the raised portion is greater than the thickness of the wiring.
  • an encapsulation layer is formed on the display area of the array substrate, and the distance between the protrusion and the encapsulation layer is greater than a preset distance.
  • the array substrate includes a pixel defining layer that defines a sub-pixel in a display region, wherein the pixel defining layer is disposed in the same layer as the protective layer.
  • the array substrate further includes a metal layer between the substrate and the wiring; and a second insulating layer between the metal layer and the wiring.
  • the shape of the raised portion is selected from the group consisting of a sphere, a cylinder, and a cuboid.
  • the raised portion comprises a resin.
  • the wiring comprises a data line.
  • the first insulating layer includes a passivation layer.
  • inventions of the present disclosure provide a display panel.
  • the display panel includes the above array substrate.
  • inventions of the present disclosure provide a display device.
  • the display device includes the above display panel.
  • inventions of the present disclosure provide a method of fabricating the array substrate described above.
  • the method for fabricating the array substrate includes: forming an array wiring on a base substrate, forming a first insulating layer covering the wiring on the wiring, on the first insulating layer and located on the array substrate A raised portion is formed in the display area.
  • the raised portion is adjacent to the wiring, and wherein a surface of the raised portion away from the base substrate is more than a surface of the portion of the first insulating layer covering the wiring away from the base substrate Moving away from the base substrate, forming a raised portion above the first insulating layer includes:
  • a raised portion is formed over the first insulating layer by a patterning process, the raised portions being located on both sides of the wiring.
  • the forming the protrusion above the first insulating layer comprises:
  • a convex portion is formed over the first insulating layer in the non-display region while forming the pixel defining layer located in the display region and defining sub-pixels by one patterning process.
  • FIG. 1 is a schematic structural view of a non-display area of an array substrate according to an embodiment
  • FIG. 2 is a schematic view showing a process of attaching a strip of adhesive tape when fabricating an array substrate according to an embodiment
  • FIG. 3 is a schematic view showing a hot pressing process of a package strip when fabricating an array substrate according to an embodiment
  • FIG. 4 is a schematic structural view of a non-display area of an array substrate after being damaged by external pressure according to an embodiment
  • FIG. 5 is a schematic structural diagram of a non-display area of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a module of the array substrate and the circuit board shown in FIG. 5;
  • FIG. 7 is a first schematic structural diagram of a protective layer in a non-display area of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a second schematic structural diagram of a protective layer in a non-display area of an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a third schematic structural diagram of a protective layer in a non-display area of an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a display panel according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a display device according to an embodiment of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • the attaching process of the package strip and the hot pressing process may subject the array substrate to a large pressure, and the encapsulation adhesive of the display area of the array substrate
  • the strip can buffer the external force to protect the normal use of the lines in the display area; the data lines and the passivation layer in the non-display area are subject to greater pressure, and the passivation layer outside the data line is easily destroyed.
  • the data lines in the passivation layer are corroded by the intrusion of external water vapor, thereby affecting the normal use of the array substrate.
  • the embodiment of the invention provides an array substrate, which can be applied to a display panel and a display device.
  • the structure includes a base substrate 1, a gate insulating layer 2 formed on the base substrate 1, a data line 3 on the gate insulating layer 2, and a data line covered in the non-display area of the array substrate.
  • the material of the base substrate 1 may be selected from the group consisting of a plurality of materials.
  • the base substrate may include a glass rigid substrate, a flexible substrate.
  • the passivation layer 4 may be selected from the group consisting of a plurality of materials.
  • the passivation layer may include a silicon nitride layer, a resin layer, or the like.
  • FIG. 2 is a schematic view showing a process of attaching a strip of adhesive tape in an embodiment of an array substrate.
  • the array substrate includes a display area A and a non-display area B, and the encapsulation layer 5 is disposed on the display area A.
  • the roller a will repeatedly roll over the array substrate.
  • the horizontal arrow in Fig. 2 indicates the rolling direction of the drum a, and the vertical downward arrow indicates the direction of the force of the roller a on the array substrate.
  • the data line 3 in the non-display area B is subjected to an external force.
  • the passivation layer 4 outside the data line 3 in the non-display area B is easily broken by an external force, and the structure after the damage is shown in FIG. 4, and the direction of the arrow in FIG. 4 is the direction in which the outside water vapor invades.
  • the encapsulation layer 5 can alleviate the effect of external force on the lines and devices in the display area A, thereby protecting the normal use of the lines and devices in the display area A.
  • FIG. 3 is a schematic diagram of a thermal compression process of an encapsulation layer when fabricating an array substrate according to an embodiment.
  • the array substrate includes a display area A and a non-display area B, and the encapsulation layer 5 is disposed on the display area A.
  • the hot pressing device c applies pressure on the array substrate, and the arrows in FIG. 3 indicate the moving direction of the hot pressing device c and the pressure applying direction to the array substrate.
  • the data line 3 in the non-display area B is subjected to an external force, and the passivation layer 4 outside the data line 3 of the B in the non-display area is easily damaged by an external force to form a passivation layer 4
  • the damaged portion b and the structure after the damage are shown in Fig. 4.
  • the array substrate provided by the embodiment of the invention includes a substrate substrate, a wiring on the substrate substrate, a first insulating layer covering the wiring, and a convex portion on the first insulating layer and located in the non-display area of the array substrate.
  • the raised portion is adjacent to the wiring, and wherein a surface of the raised portion away from the base substrate is farther away from the base substrate than a surface of the portion of the first insulating layer covering the wiring away from the base substrate.
  • the arrangement of the protrusions effectively prevents the first insulating layer (for example, the passivation layer) outside the wiring (for example, the data line) from being damaged by being pressed by an external force, thereby effectively preventing the wiring (for example, the data line) from being squeezed by an external force.
  • the pressure and corrosion by external water vapor ensure the normal use of wiring (for example, data lines).
  • a plurality of devices are disposed on the non-display area of the array substrate, and the first insulating layer 4 (eg, a passivation layer) and the protrusions may be disposed correspondingly according to actual positions of the wiring (eg, data lines) in the non-display area.
  • the position of the portion 6 in the non-display area As shown in FIG. 11, for example, a metal layer 13 for discharging static electricity may be disposed in a non-display area of the array substrate, and a second insulating layer 12 may be disposed on the metal layer. At this time, the wiring 3 such as the data line may be disposed on the second insulating layer 12 on the metal layer 13.
  • the first insulating layer 4 such as a passivation layer may be covered on the wiring 3 and the second insulating layer 12 such as data lines, and the bumps 6 are disposed on the first insulating layer 4 (for example, a passivation layer).
  • the wiring 3 such as the data line
  • the first insulating layer 4 such as the passivation layer
  • the boss portion 6 can be used.
  • a first insulating layer eg, a passivation layer
  • a wiring eg, a data line
  • a raised portion which may also be referred to as a "protective layer”
  • the passivation layer There may be a variety of positional relationships between the raised portions and the wiring (eg, data lines). For example, at least a portion of the orthogonal projection of the wiring on the substrate substrate of the array substrate does not overlap with the orthographic projection of the convex portion on the substrate.
  • a first insulating layer (eg, a passivation layer) outside the wiring (eg, a data line) not covered by the bump may be provided with a via hole through which the wiring may pass and other conductive structures (eg, a metal layer structure) )connection.
  • FIG. 5 is a schematic structural diagram of a non-display area of an array substrate according to an embodiment of the present invention. As shown in FIG. 5, the bosses 6 are provided on both sides of the wiring 3. The orthographic projection of the raised portion 6 on the base substrate 1 does not overlap with the orthographic projection of the wiring 3 on the base substrate 1.
  • the height of the convex portion 6 is higher than the height of the first insulating layer (for example, the passivation layer) 4 (that is, the surface of the convex portion 6 away from the base substrate 1 is farther away from the portion of the first insulating layer 4 covering the wiring 3
  • the surface of the base substrate 1 is further away from the base substrate 1).
  • the convex portion 6 on both sides of the wiring 3 forms a groove with the first insulating layer 4 outside the wiring 3.
  • the convex portion 6 on both sides of the wiring 3 such as the data line in the non-display region is higher than the first insulating layer 4 on the outer side of the wiring 3, the convex portion 6 can buffer the external force applied by the process.
  • the function of protecting the structure of the first insulating layer 4 is ensured, and the normal use of the wiring 3 in the first insulating layer 4 is ensured.
  • the array substrate may further include a circuit board 8 disposed on the boss portion 6.
  • a conductive portion 11 is provided on the side of the circuit board 8 facing the wiring 3 (see the broken line frame of Fig. 6).
  • the conductive portion 11 may include a metal wire 9 and a conductive paste 10, wherein the metal wire 9 may be fixed in the groove formed by the boss portion 6 and the first insulating layer 4 by the conductive paste 10.
  • the orthographic projection of the conductive portion 11 on the base substrate 1 is located between the orthographic projections of the convex portion 6 on the base substrate 1.
  • a via hole V is disposed on the first insulating layer 4 outside the wiring 3, and the metal line 9 fixed in the recess is connected to the wiring 3 through the conductive paste 10 and the via hole V on the passivation layer 4.
  • the metal wires 9 for example, the gold fingers of the circuit board
  • the conductive paste 10 are blocked by the protective layer 6 on both sides of the wiring 3 when bonding is performed.
  • the protective layer 6 serves as a fixing function to prevent the metal wires 9 from being displaced from the wiring 3, thereby improving the offset and misalignment occurring at the time of bonding, and ensuring the positional accuracy at the time of bonding.
  • the raised portions are formed on both sides of the data line.
  • the raised portions may be in a variety of pattern shapes.
  • the raised portion can be a sphere, a cylinder, or a rectangular parallelepiped.
  • the plurality of raised portions may be continuous or islanded.
  • the plurality of raised portions may be arranged in a regular or irregular arrangement.
  • 7 to 9 are schematic views showing the structure of the convex portion 6 in the non-display area of the array substrate.
  • the bosses 6 shown in Figs. 7 to 9 are formed on both sides of the wiring 3 and are regularly arranged.
  • the boss portion 6 shown in Fig. 7 has a cylindrical structure.
  • the boss portion 6 shown in Fig. 8 has a continuous rectangular parallelepiped structure.
  • the boss portion 6 shown in Fig. 9 has a rectangular parallelepiped structure.
  • the first insulating layer 4 may include a passivation layer.
  • the wiring 3 may include a data line.
  • the thickness of the convex portion may be greater than the thickness of the wiring, so that the convex portion protects the wiring regardless of the positional relationship between the convex portion and the wiring.
  • an encapsulation layer is disposed on the display region of the array substrate.
  • the distance between the raised portion and the encapsulation layer 5 is greater than a predetermined distance (the "distance” of the two herein refers to the minimum of the distance between the point on the raised portion and the point on the encapsulation layer) .
  • the above structure is arranged to ensure the encapsulation effect of the encapsulation layer and the array substrate of the display area, and prevent external water vapor from entering the display area to corrode the line structure.
  • the preset distance can be set according to the actual situation. As shown in FIGS. 7-9, the distance between the protective layer 6 and the encapsulation layer 5 is D. At the distance D, the encapsulation layer 5 can form a sealing structure with a good sealing property with the array substrate, thereby effectively preventing outside water vapor from entering the display area A, and ensuring the safety of the lines and devices in the display area A.
  • the array substrate provided by the embodiment of the present invention may further include a pixel defining layer 14 that is located in the display area of the array substrate and defines the sub-pixel SP.
  • an organic light emitting diode structure layer may be disposed in a display area of the array substrate, and an organic light emitting diode structure layer is disposed in a display area of the array substrate of the OLED display.
  • the organic light emitting diode structure layer includes a pixel defining layer, and the pixel defining layer may be disposed in the same layer as the convex portion in the non-display area.
  • a TFT control layer In fabricating the structure in the display region of the array substrate, a TFT control layer, an anode layer, a color film, an organic light-emitting layer, and a cathode layer are formed on the base substrate.
  • a pixel definition layer is required to be formed when the color film is prepared, and the pixel definition layer is used to separate sub-pixel (eg, RGB) pixels.
  • the protective layer can be simultaneously formed in the non-display region by one patterning process. Compared with the existing array substrate fabrication process, the embodiment of the present invention only needs to change the pattern of the mask of the pixel definition layer, and does not increase the preparation process.
  • the protective layer and the passivation layer may be selected from the group consisting of a plurality of materials.
  • the protective layer may be a resin layer.
  • the convex portion in the non-display area and the pixel defining layer in the display area are formed by one patterning process, and the pixel defining layer is a polyimide (PDL) material layer, the convex portion is also a PDL layer; such as a passivation layer
  • the first insulating layer may be a silicon nitride layer or a resin layer.
  • a display panel 2000 of an embodiment of the present invention includes an array substrate 1000.
  • Array substrate 1000 can include an array substrate as shown in Figures 5-9.
  • the display panel 2000 has the advantages of the above array substrate, and the present invention will not be described herein.
  • Embodiments of the present invention also provide a display device.
  • a display device 3000 of an embodiment of the present invention includes a display panel 2000.
  • the display panel 2000 may include a display panel as shown in FIG.
  • the display device 3000 has the advantages of the above display panel, and the present invention will not be described herein.
  • the embodiment of the invention further provides a method for fabricating the above array substrate.
  • 10 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention. Referring to FIG. 10, the method for fabricating the array substrate includes:
  • the arrangement of the convex portion effectively prevents the first insulating layer (for example, the passivation layer) and the wiring (for example, the data line) from being pressed by the external force, thereby effectively preventing the data line caused by the breakage of the passivation layer.
  • the problem of corrosion by the external water vapor occurs to ensure the normal use of the data line.
  • the step of forming the protrusion above the first insulating layer may include:
  • a raised portion is formed over the first insulating layer by a patterning process, wherein the raised portions are located on both sides of the wiring.
  • the array substrate may also include a circuit board.
  • a metal wire is formed on the circuit board. Metal wires can be placed in the grooves to prevent the board from shifting.
  • the step of forming the convex portion over the first insulating layer may include: forming the display region by one patterning process While the pixel defines the layer, a convex portion is formed over the first insulating layer in the non-display region.
  • the raised portion can be selected to include a plurality of sets of materials.
  • the raised portion may include a resin.
  • the embodiment of the present invention only needs to change the pattern of the mask of the pixel definition layer, and does not increase the preparation process.
  • the entire convex portion may be formed in the non-display region, and then the entire convex portion is processed by an exposure etching process to obtain a convex portion structure of a desired pattern.

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  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

提供一种阵列基板、显示面板、显示装置及其制作方法。阵列基板包括：衬底基板（1）；位于衬底基板上的布线（3）；覆盖布线的绝缘层（4）；在绝缘层上且位于阵列基板的非显示区域中的凸起部（6），其中，凸起部邻近布线，并且其中，凸起部的远离衬底基板的表面比绝缘层覆盖布线的部分的远离衬底基板的表面更远离衬底基板。

Description

一种阵列基板、显示面板、显示装置及其制作方法
相关申请的交叉引用
本申请要求于2017年08月31日递交的中国专利申请第201710774897.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，特别是涉及阵列基板、显示面板、显示装置及其制作方法。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light-Emitting Diode,OLED)因具有自发光、广视角、高对比度、低耗电以及高反应速度等优点，而被制作成阵列基板，应用于显示设备中。
目前的阵列基板包括显示区域和非显示区域，显示区域内形成有薄膜晶体管层、金属阳极层、彩膜层、有机发光材料层和金属阴极层，非显示区域内形成有数据线以及覆盖在数据线上的钝化层，钝化层对数据线起到保护作用。
发明内容
一方面，本公开文本的实施例提供了一种阵列基板。包括：衬底基板、位于所述衬底基板上的布线、覆盖所述布线的第一绝缘层、在所述第一绝缘层上且位于所述阵列基板的非显示区域中的凸起部。其中，所述凸起部邻近所述布线，并且其中，所述凸起部的远离所述衬底基板的表面比所述第一绝缘层覆盖所述布线的部分的远离所述衬底基板的表面更远离所述衬底基板。
在一个实施例中，所述信号线在所述阵列基板的所述衬底基板上的正投影的至少一部分与所述凸起部在所述衬底基板上的正投影不交叠。
在一个实施例中，所述保护层设置在所述布线的两侧。
所述布线在所述衬底基板上的正投影与所述凸起部在所述衬底基板上的正投影不交叠。
在一个实施例中，所述阵列基板还包括设置在所述凸起部上的电路板，所设置在所述电路板的朝向所述布线的一侧上的导电部。所述导电部通过所述第一绝缘层上设置的过孔与所述布线电。所述导电部在所述衬底基板上的正投影位于所述凸起部在所述衬底基板上的正投影之间。
在一个实施例中，所述凸起部的厚度大于所述布线的厚度。
在一个实施例中，所述阵列基板的显示区域上形成有封装层，所述凸起部与所述封装层的距离大于预设距离。
在一个实施例中，所述阵列基板包括位于显示区域内切限定子像素的像素定义层，其中所述像素定义层与所述保护层同层设置。
在一个实施例中，所述阵列基板还包括位于所述衬底基板和所述布线之间的金属层；以及位于所述金属层和所述布线之间的第二绝缘层。
在一个实施例中，所述凸起部的形状选自包括球体、柱体和长方体的组。
在一个实施例中，所述凸起部包括树脂。
在一个实施例中，所述布线包括数据线。
在一个实施例中，所述第一绝缘层包括钝化层。
另一方面，本公开文本的实施例提供了一种显示面板。所述显示面板包括上述的阵列基板。
另一方面，本公开文本的实施例提供了一种显示装置。所述显示装置包括上述的显示面板。
另一方面，本公开文本的实施例提供了一种上述的阵列基板的制作方法。所述阵列基板的制作方法包括：在衬底基板上形成阵列布线，在所述布线上形成覆盖所述布线的第一绝缘层，在所述第一绝缘层上且位于所述 阵列基板的非显示区域中形成凸起部。所述凸起部邻近所述布线，并且其中，所述凸起部的远离所述衬底基板的表面比所述第一绝缘层覆盖所述布线的部分的远离所述衬底基板的表面更远离所述衬底基板，在所述第一绝缘层上方形成凸起部包括：
通过图案化处理在所述第一绝缘层上方形成凸起部，所述凸起部位于所述布线的两侧。
在一个实施例中，所述在所述第一绝缘层上方形成凸起部包括：
通过一次构图工艺在形成位于所述显示区域内且限定子像素的所述像素定义层的同时，在所述非显示区域内的所述第一绝缘层上方形成凸起部。
附图说明
图1是根据一种实施方式的阵列基板的非显示区域内的结构示意图；
图2是根据一种实施方式的在制作阵列基板时封装胶条贴附工艺的示意图；
图3是根据一种实施方式的在制作阵列基板时封装胶条热压工艺的示意图；
图4是根据一种实施方式的阵列基板的非显示区域受到外界压力破损后的结构示意图；
图5是本发明实施例提供的一种阵列基板的非显示区域的结构示意图；
图6是图5所示的阵列基板与电路板的模组结构示意图；
图7是本发明实施例提供的阵列基板的非显示区域内的保护层的第一结构示意图；
图8是本发明实施例提供的阵列基板的非显示区域内的保护层的第二结构示意图；
图9是本发明实施例提供的阵列基板的非显示区域内的保护层的第三结构示意图；
图10是本发明实施例提供的阵列基板的制作方法的方法流程图；
图11为本发明实施例提供的阵列基板的示意图；
图12为本发明实施例提供的阵列基板的示意图；
图13为本发明实施例提供的显示面板的示意图；
图14为本发明实施例提供的显示装置的示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的机或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
下面结合附图和实施例对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
在制作阵列基板的过程中，需要在阵列基板的显示区域的边缘形成封装胶条，封装胶条的贴附工艺和热压工艺会使阵列基板受到较大压力，阵列基板的显示区域的封装胶条可以对外力起到缓冲作用，从而保护显示区域内的线路的正常使用；而非显示区域内的数据线及钝化层会受到较大的压力作用，数据线外侧的钝化层易被破坏，导致钝化层内的数据线因受到 外界水汽侵入而腐蚀，从而影响阵列基板的正常使用。
为了减少高温高湿实验或工作中出现的线腐蚀，本发明实施例提供了一种阵列基板，可以应用于显示面板、显示装置。
图1是一种实施方式中阵列基板的非显示区域内的结构示意图。由图1可知，在阵列基板的非显示区域内结构包括衬底基板1、形成在衬底基板1上的栅极绝缘层2、位于栅极绝缘层上2的数据线3以及覆盖在数据线3上的绝缘层(例如，钝化层)4。衬底基板1的材料可以选自多种材料组成的组。例如，衬底基板可以包括玻璃刚性基板、柔性基板。钝化层4的可以选自为多种材料组成的组。例如，钝化层可以包括氮化硅层、树脂层等。
图2是一种实施方式在制作阵列基板时封装胶条贴附工艺的示意图。由图2可知，阵列基板包括显示区域A和非显示区域B，显示区域A上设置有封装层5。在封装胶条贴附工艺过程中，滚筒a会在阵列基板上反复滚动。图2中的横向箭头表示滚筒a的滚动方向，竖直向下箭头表示滚筒a对阵列基板的作用力方向。非显示区域B内的数据线3会受到外力作用。非显示区域B内的数据线3外侧的钝化层4受到外力作用后易破损，破损后的结构参照图4所示，图4中的箭头方向为外界水汽的入侵方向。
钝化层4破损后，外界水汽易从钝化层4的破损处b进入与数据线3接触，导致数据线3被腐蚀。由于显示区域内A设置有封装层5，因此封装层5可以减缓外力对显示区域A内线路和器件的作用，从而保护了显示区域A内的线路和器件的正常使用。
图3是根据一种实施方式的在制作阵列基板时封装层热压工艺的示意图，由图3可知，阵列基板包括显示区域A和非显示区域B，显示区域A上设置有封装层5。在封装层热压工艺过程中，热压装置c会在阵列基板上施加压力，图3中的箭头表示热压装置c的运动方向和对阵列基板的压力施加方向。
在封装层热压工艺过程中，非显示区域B内的数据线3会受到外力作用，非显示区域内B的数据线3外侧的钝化层4受到外力作用后易破损，形成钝化层4的破损处b，破损后的结构参照图4所示。
在该实施方式中存在阵列基板在制作过程中非显示区域内的数据线外侧的钝化层易被破坏、数据线易被腐蚀的问题。
本发明实施例提供的阵列基板包括衬底基板、位于衬底基板上的布线、覆盖布线的第一绝缘层、在第一绝缘层上且位于阵列基板的非显示区域中的凸起部。其中，凸起部邻近所述布线，并且其中，凸起部的远离所述衬底基板的表面比第一绝缘层覆盖布线的部分的远离衬底基板的表面更远离衬底基板。凸起部的设置有效防止了布线(例如，数据线)外侧的第一绝缘层(例如，钝化层)因受外力挤压而被破坏，有效防止了布线(例如，数据线)被外力挤压和被外界水汽腐蚀，保证了布线(例如，数据线)的正常使用。
阵列基板的非显示区域上设置有多种器件，可以根据实际设置布线(例如，数据线)在非显示区域内的位置，相应地设置第一绝缘层4(例如，钝化层)和凸起部6在非显示区域内的位置。如图11所示，例如，阵列基板的非显示区域内可以设置有用于释放静电的金属层13，金属层上设置有第二绝缘层12。这时诸如数据线的布线3可以设置在金属层13上的第二绝缘层12上。相应地诸如钝化层的第一绝缘层4可以覆盖在诸如数据线的布线3和第二绝缘层12上，凸起部6设置在该第一绝缘层4(例如，钝化层)上。诸如数据线的布线3、诸如钝化层的第一绝缘层4和凸起部6的其他适用位置均可行。
本公开文本的实施例中，第一绝缘层(例如，钝化层)覆盖在布线(例如，数据线)上，凸起部(也可以被称为“保护层”)设置在第一绝缘层(例如，钝化层)上方。凸起部与布线(例如，数据线)可以存在多种位置关系。例如，布线在阵列基板的衬底基板上的正投影的至少一部分与凸起部在衬底基板上的正投影不交叠。未被凸起部覆盖的布线(例如，数据线)外侧的第一绝缘层(例如，钝化层)上可以设置有过孔，布线可以通过该过孔与其他导电结构(例如，金属层结构)连接。
进一步，凸起部可以设置在布线的两侧，布线在衬底基板上的正投影与凸起部在衬底基板上的正投影不交叠。图5是本发明实施例提供的一种 阵列基板的非显示区域的结构示意图。图5所示，凸起部6设置在布线3的两侧。凸起部6在衬底基板1上的正投影与布线3在衬底基板1上的正投影不交叠。凸起部6的高度高于第一绝缘层(例如，钝化层)4的高度(即，凸起部6的远离衬底基板1的表面比第一绝缘层4覆盖布线3的部分的远离衬底基板1的表面更远离衬底基板1)。布线3两侧的凸起部6与布线3外侧的第一绝缘层4形成凹槽。
在制备阵列基板时，由于非显示区域内的诸如数据线的布线3两侧的凸起部6高于布线3外侧的第一绝缘层4，因此凸起部6可以对工艺施加的外力起缓冲作用，保护第一绝缘层4的结构安全，保证第一绝缘层4内的布线3的正常使用。
如图6所示，阵列基板还可以包括设置在凸起部6上的电路板8。电路板8的朝向布线3的一侧上设置有导电部11(参见图6的虚线框)。导电部11可以包括金属线9和导电胶10，其中金属线9可以通过导电胶10固定在凸起部6和第一绝缘层4形成的凹槽内。这时导电部11在衬底基板1上的正投影位于凸起部6在衬底基板1上的正投影之间。布线3外侧的第一绝缘层4上设置有过孔V，固定在凹槽内的金属线9通过导电胶10和钝化层4上的过孔V与布线3连接。上述结构实现了金属线9与凹槽的对位设置，有效防止电路板8移动。
由阵列基板和上述电路板形成的模组结构参照图6所示，在进行接合时，金属线9(例如，电路板的金手指)和导电胶10会被布线3两侧的保护层6挡住，保护层6起到固定作用，防止金属线9偏离布线3，从而改善接合时出现的偏移和错位，保证了接合时的位置准确性。
凸起部形成在数据线的两侧。凸起部可以是多种图案形状。例如，凸起部可以为球体、柱体或长方体。多个凸起部可以是连续式，也可以是孤岛式。多个凸起部可以呈规则排列或非规则排列。图7-图9是阵列基板的非显示区域内的凸起部6的结构示意图。图7-图9所示的凸起部6形成在布线3两侧，并呈规则排列。图7所示的凸起部6为柱体结构。图8所示的凸起部6为连续式的长方体结构。图9所示的凸起部6为长方体结构。
第一绝缘层4可以包括钝化层。布线3可以包括数据线。
本发明实施例提供的阵列基板中，凸起部的厚度可以大于布线的厚度，这样无论凸起部与布线具有何种位置关系，凸起部都会对布线起到保护作用。
在制作阵列基板时，阵列基板的显示区域上设置有封装层。在本发明的实施例中，凸起部与封装层5的距离大于预设距离(这里的二者的“距离”是指凸起部上的点到封装层上的点的间距的最小值)。上述结构的设置可以保证封装层与显示区域的阵列基板的封装效果，防止外界水汽进入显示区域内腐蚀线路结构。预设距离可以根据实际进行设置。如图7-图9所示，保护层6与封装层5之间的距离为D。在该距离D下，封装层5可以与阵列基板形成密封性较好的封装结构，从而可以有效防止外界水汽进入显示区域A内，保证了显示区域A内的线路和器件安全。
本发明实施例提供的阵列基板还可以包括位于阵列基板的显示区域内且限定子像素SP的像素定义层14。在本发明的实施例中，阵列基板的显示区域中可以设置有有机发光二极管结构层，如OLED显示器的阵列基板的显示区域内设置有有机发光二极管结构层。有机发光二极管结构层包括像素定义层，像素定义层可以与非显示区域内的凸起部同层设置。
具体地，在制作阵列基板的显示区域内的结构时，在衬底基板上形成TFT控制层、阳极层、彩膜、有机发光层和阴极层。在制备彩膜时需要形成像素定义层，像素定义层用于将子像素(例如，RGB)像素隔开。在显示区域内形成像素定义层时，可以通过一次构图工艺同时在非显示区域内形成保护层。相比于现有的阵列基板制作工艺，本发明实施例只需更改像素定义层的掩膜板的图案即可，并未增加制备工艺。
本发明实施例提供的阵列基板中，保护层和钝化层可以选自包括多种材料组成的组。如保护层可以为树脂层。当非显示区域内凸起部与显示区域内的像素定义层通过一次构图工艺形成、像素定义层为聚酰亚胺(PDL)材料层时，凸起部也为PDL层；诸如钝化层的第一绝缘层可以为氮化硅层或树脂层。
本发明实施例还提供了一种显示面板。如图13所示，本发明的实施例的显示面板2000包括阵列基板1000。阵列基板1000可以包括如图5-9中所示的阵列基板。该显示面板2000具有上述阵列基板的优点，本发明在此不再赘述。
本发明实施例还提供了一种显示装置。如图14所示，本发明的实施例的显示装置3000包括显示面板2000。显示面板2000可以包括如图13所示的显示面板。该显示装置3000具有上述显示面板的优点，本发明在此不再赘述。
本发明实施例还提供了一种上述阵列基板的制作方法。图10是本发明实施例提供的阵列基板的制作方法的方法流程图，参照图10，所述阵列基板的制作方法包括：
101、在衬底基板上形成布线；
102、在布线上形成覆盖布线的第一绝缘层；
103、在第一绝缘层上且位于阵列基板的非显示区域中形成凸起部，其中，凸起部邻近所述布线，并且其中，凸起部的远离衬底基板的表面比第一绝缘层覆盖布线的部分的远离衬底基板的表面更远离衬底基板。
本发明实施例中，凸起部的设置有效防止了第一绝缘层(例如，钝化层)和布线(例如，数据线)被外力挤压，有效防止了钝化层破损后导致的数据线被外界水汽腐蚀的问题发生，保证了数据线的正常使用。
在第一绝缘层上方形成凸起部的步骤可以包括：
经过图案化处理在第一绝缘层上方形成凸起部，其中，凸起部位于布线的两侧。
这时布线两侧的凸起部和布线外侧的第一绝缘层形成凹槽结构。阵列基板还可以包括电路板。电路板上形成有金属线。金属线可以放置在凹槽内，从而防止电路板发生偏移。
当阵列基板的显示区域内形成有有机发光二极管结构层，有机发光二极管结构层包括像素定义层时，在第一绝缘层上方形成凸起部的步骤可以包括：通过一次构图工艺在形成显示区域内的像素定义层的同时，在非显 示区域内的第一绝缘层上方形成凸起部。凸起部可以选择包括多种材料的组。例如，凸起部可以包括树脂。
相比于现有的阵列基板制作工艺，本发明实施例只需更改像素定义层的掩膜板的图案即可，并未增加制备工艺。在形成凸起部时，可以先在非显示区域内形成整层的凸起部，再通过曝光刻蚀工艺对整层凸起部进行处理，得到所需图案的凸起部结构。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上对本发明所提供的阵列基板、显示面板、显示装置及其制备方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (18)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板上的布线；
    覆盖所述布线的第一绝缘层；
    在所述第一绝缘层上且位于所述阵列基板的非显示区域中的凸起部，其中，所述凸起部邻近所述布线，并且其中，所述凸起部的远离所述衬底基板的表面比所述第一绝缘层覆盖所述布线的部分的远离所述衬底基板的表面更远离所述衬底基板。
  2. 根据权利要求1所述的阵列基板，其中，所述信号线在所述衬底基板上的正投影的至少一部分与所述凸起部在所述衬底基板上的正投影不交叠。
  3. 根据权利要求2所述的阵列基板，其中，所述凸起部设置在所述布线的两侧；
    所述布线在所述衬底基板上的正投影与所述凸起部在所述衬底基板上的正投影不交叠。
  4. 根据权利要求2所述的阵列基板，还包括：
    设置在所述凸起部上的电路板；
    设置在所述电路板的朝向所述布线的一侧上的导电部，所述导电部通过所述第一绝缘层上设置的过孔与所述布线电连接，其中所述导电部在所述衬底基板上的正投影位于所述凸起部在所述衬底基板上的正投影之间。
  5. 根据权利要求1所述的阵列基板，其中，所述凸起部的厚度大于所述布线的厚度。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板的显示区域上设置有封装层，所述凸起部与所述封装层的距离大于预设距离。
  7. 根据权利要求1所述的阵列基板，进一步包括位于显示区域内且限定子像素的像素定义层，其中，所述像素定义层与所述保护层同层设置。
  8. 根据权利要求1所述的阵列基板，进一步包括：位于所述衬底基板 和所述布线之间的金属层；以及位于所述金属层和所述布线之间的第二绝缘层。
  9. 根据权利要求1所述的阵列基板，其中，所述凸起部的形状选自包括球体、柱体和长方体的组。
  10. 根据权利要求1所述的阵列基板，其中，所述凸起包括树脂。
  11. 根据权利要求1-10中任一项所述的阵列基板，其中，所述布线包括数据线。
  12. 根据权利要求1-10中任一项所述的阵列基板，其中，所述第一绝缘层包括钝化层。
  13. 一种显示面板，其中，包括权利要求1-12任一项所述的阵列基板。
  14. 一种显示装置，其中，包括权利要求13所述的显示面板。
  15. 一种阵列基板的制作方法，包括：
    在衬底基板上形成布线；
    在所述布线上形成覆盖所述布线的第一绝缘层；
    在所述第一绝缘层上且位于所述阵列基板的非显示区域中形成凸起部，其中，所述凸起部邻近所述布线，并且其中，所述凸起部的远离所述衬底基板的表面比所述第一绝缘层覆盖所述布线的部分的远离所述衬底基板的表面更远离所述衬底基板。
  16. 根据权利要求15所述的方法，其中，在所述第一绝缘层上方形成凸起部包括：
    经过图案化处理在所述第一绝缘上方形成凸起部，所述凸起部位于所述布线的两侧。
  17. 根据权利要求15所述的方法，在所述第一绝缘层上方形成凸起部包括：
    通过一次构图工艺在形成位于显示区域内且限定子像素的像素定义层的同时，在所述非显示区域内的所述第一绝缘层上方形成凸起部。
  18. 根据权利要求15-17中任一项所述的方法，其中所述布线包括数据线，所述第一绝缘层包括钝化层。
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