WO2019034028A1 - 一种基于深槽腐蚀的空腔形成方法 - Google Patents

一种基于深槽腐蚀的空腔形成方法 Download PDF

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WO2019034028A1
WO2019034028A1 PCT/CN2018/100330 CN2018100330W WO2019034028A1 WO 2019034028 A1 WO2019034028 A1 WO 2019034028A1 CN 2018100330 W CN2018100330 W CN 2018100330W WO 2019034028 A1 WO2019034028 A1 WO 2019034028A1
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semiconductor substrate
cavity
microns
array
annealing
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PCT/CN2018/100330
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English (en)
French (fr)
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苏佳乐
夏长奉
周国平
张新伟
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无锡华润上华科技有限公司
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Priority to US16/646,946 priority Critical patent/US20200243342A1/en
Priority to JP2020520014A priority patent/JP2021508604A/ja
Priority to KR1020207007253A priority patent/KR20200051637A/ko
Publication of WO2019034028A1 publication Critical patent/WO2019034028A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
    • G01L9/0045—Diaphragm associated with a buried cavity
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B81C1/00404—Mask characterised by its size, orientation or shape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate

Definitions

  • the present invention relates to a semiconductor fabrication process, and more particularly to a cavity formation method based on deep trench etching.
  • the method of forming a cavity on a silicon substrate is as follows: 1) etching a back surface of a silicon substrate with KOH to form a cavity; 2) a silicon-on-insulator (Cavity-SOI) process; and 3) an epitaxial cavity process.
  • the KOH etching process is deep groove etching from the back side, and the silicon remaining at the bottom of the deep groove forms a silicon film.
  • the side wall of the deep groove due to KOH corrosion is inclined at an angle of 54 degrees, and the side of the deep groove is inverted trapezoid, so the area of the die is larger than the actual one.
  • the area of the silicon film required is large, so that the number of cores produced by a single piece is small and the cost is high.
  • the cavity SOI process the cavity is dried by dry etching, and the die area is greatly reduced.
  • the number of cores produced per chip is more than that of the KOH etching process, but because of the need for Si-Si bonding, the process cost is high and the production cycle is long.
  • the epitaxial cavity process is a surface process. The process is to first engrave the deep trench, and then seal the top by long epitaxy. The process is simpler than the cavity SOI process, and the cost is low.
  • the extended silicon is polysilicon, the piezoresistive film The quality is not as good as the quality of single crystal silicon.
  • a cavity forming method based on deep trench etching comprising: providing a semiconductor substrate, performing the deep trench etching on the semiconductor substrate to form in the semiconductor substrate An array of a plurality of trenches, a spacing between the outermost trenches in the array being greater than a spacing between the remaining trenches in the array; annealing the semiconductor substrate to the semiconductor A cavity is formed in the substrate.
  • 1A-1D are schematic cross-sectional views of devices respectively obtained in accordance with steps performed in a conventional cavity forming process
  • 2A-2C are schematic cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an exemplary embodiment of the present invention
  • Figure 3 is a plan view of the slot 201 shown in Figure 2A;
  • FIG. 5 is a flow diagram of steps sequentially performed by a method in accordance with an exemplary embodiment of the present invention.
  • a silicon substrate 100 is provided which is doped with p-impurities, and an n+ impurity implantation region 101 is formed on the upper portion of the silicon substrate 100 by an ion implantation process.
  • the n+ impurity implantation region 101 is formed on the upper portion of the silicon substrate 100 by an ion implantation process, and then the ion implantation window pattern is removed by a lift-off process.
  • the silicon substrate 100 is immersed in a concentrated HF solution and a voltage-current is applied to the surface of the silicon substrate 100.
  • the n+ impurity implantation region 101 forms a porous silicon having a relatively small aperture, below the n+ impurity implantation region 101.
  • the p-doped region forms porous silicon having a relatively large pore diameter.
  • the silicon substrate 100 is taken out from the concentrated HF solution, and annealed at a high temperature in a hydrogen atmosphere, and the porous silicon formed in the n+ impurity implantation region 101 is fused together, and under the n+ impurity implantation region 101.
  • the porous silicon formed by the p-doped region forms a cavity 102.
  • a silicon layer 103 of a certain thickness is epitaxially grown on the surface of the silicon substrate 100 to meet product requirements.
  • the main disadvantage of the above process is that the silicon wafer needs to be immersed in concentrated HF and energized.
  • the process is complicated and dangerous, and requires special equipment and processes, and the cost is high.
  • the present invention provides a cavity forming method based on deep trench etching, the method comprising:
  • step 501 a semiconductor substrate is provided, and the semiconductor substrate is subjected to deep trench etching to form an array of a plurality of trenches in the semiconductor substrate, wherein a spacing between the outermost trenches in the array is greater than The spacing between the remaining slots in the array;
  • step 502 the semiconductor substrate is annealed to form a cavity in the semiconductor substrate.
  • the die area can be reduced, the process difficulty can be reduced, and the cost can be reduced.
  • FIGS. 2A-2C there are shown schematic cross-sectional views of devices respectively obtained in accordance with the steps sequentially performed by the method of the exemplary embodiment of the present invention.
  • a semiconductor substrate 200 is provided.
  • the constituent material of the semiconductor substrate 200 contains silicon, such as undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), Silicon (SSOI) is laminated on the insulator, silicon germanium (S-SiGeOI) is deposited on the insulator, and silicon germanium (SiGeOI) is formed on the insulator.
  • silicon such as undoped single crystal silicon, monocrystalline silicon doped with impurities
  • SOI silicon-on-insulator
  • SSOI Silicon
  • SiGeOI silicon germanium
  • SiGeOI silicon germanium
  • the constituent material of the semiconductor substrate 200 is selected from single crystal silicon.
  • the semiconductor substrate 200 is subjected to deep trench etching to form an array composed of a plurality of trenches 201 in the semiconductor substrate 200.
  • a mask layer having the array pattern is formed on the semiconductor substrate 200, and the semiconductor substrate 200 is etched by using the mask layer as a mask to form a plurality of trenches 201 in the semiconductor substrate 200.
  • the array is constructed, the etching is a conventional dry etching, and then the mask layer is removed using a conventional lift-off process.
  • the trench 201 has a feature size of from 0.5 micron to 1.0 micron, a etch depth of from 1.0 micron to 20.0 micron, and a pitch of from 0.5 micron to 1.0 micron.
  • the topography of the groove 201 may be a circle as shown in FIG. 3, or may be square or other shapes. As an example, if the shape of the groove 201 is circular, the feature size refers to the diameter, and if the shape of the groove 201 is square, the feature size refers to a diagonal.
  • the semiconductor substrate 200 is annealed to form a cavity 202 in the semiconductor substrate 200.
  • the annealing is performed in a non-oxygen environment (e.g., under an atmosphere of hydrogen, nitrogen, etc.) at a temperature above 800 °C. Due to the high temperature and non-oxygen environment, silicon atoms in the semiconductor substrate 200 migrate, eventually forming a cavity 202.
  • a non-oxygen environment e.g., under an atmosphere of hydrogen, nitrogen, etc.
  • the pitch D2 between the grooves 201 constituting the array, after performing the above annealing treatment, a single cavity 202 having different feature sizes can be formed.
  • the spacings D2 and D1 vary from 0.5 microns to 1.0 microns. The larger the spacing D2, the higher the annealing temperature and the duration of the annealing process does not exceed 20 minutes. While changing the pitch D2, the pitch D1 needs to be adjusted so that D1 is larger than D2 to ensure that the notch 204 as shown in Fig. 4(a) is not formed at the edge of the finally formed cavity 202.
  • an epitaxial material layer 203 is formed on the semiconductor substrate 200 to meet the requirements of the product, and the epitaxial material layer 203 contains silicon in the constituent material.
  • the epitaxial material layer 203 is formed by a conventional epitaxial growth process having a thickness of 10.0 micrometers to 50.0 micrometers, ensuring a film layer having a certain thickness above the cavity 202 as a piezoresistive film of the pressure sensor.
  • the deep groove etching based cavity forming method according to the present invention can reduce the die area, is compatible with the existing CMOS process, and does not need to add new equipment, thereby reducing the process difficulty and reducing the cost.
  • the method for fabricating the semiconductor device of the present embodiment includes not only the above steps, but also other necessary steps before, during or after the above steps, which are included in the scope of the method of the present embodiment.
  • a front end device is formed on the semiconductor substrate 200, which is not shown in the drawings for the sake of simplicity.
  • the front end device refers to a device formed before the implementation of the back end manufacturing process (BEOL) of the semiconductor device, and the specific structure of the front end device is not limited herein.
  • the front end device includes a gate structure.
  • the gate structure includes a gate dielectric layer and a gate material layer stacked in this order from bottom to top.
  • a sidewall structure is formed on both sides of the gate structure, an active/drain region is formed in the semiconductor substrate 200 on both sides of the sidewall structure, and a channel region is between the source/drain regions; at the top of the gate structure And a salicide formed on the source/drain regions.
  • the gate dielectric layer includes an oxide layer, such as a silicon dioxide (SiO 2 ) layer.
  • the gate material layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer may be tungsten (W) Nickel (Ni) or titanium (Ti); the conductive metal nitride layer comprises a titanium nitride (TiN) layer; the conductive metal oxide layer comprises an iridium oxide (IrO 2 ) layer; and the metal silicide layer comprises titanium silicide (TiSi) )Floor.
  • the method of forming the gate dielectric layer and the gate material layer may employ any prior art familiar to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • RTCVD Rapid Thermal Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition

Abstract

一种基于深槽腐蚀的空腔形成方法，包括：提供半导体衬底（200），对半导体衬底（200）进行深槽腐蚀，以在半导体衬底（200）中形成由多个槽（201）构成的阵列，阵列中的最外围的槽之间的间距（D1）大于阵列中的其余的槽之间的间距（D2）；对半导体衬底（200）进行退火处理，以在半导体衬底（200）中形成空腔（202）。

Description

一种基于深槽腐蚀的空腔形成方法 技术领域
本发明涉及半导体制造工艺，具体而言涉及一种基于深槽腐蚀的空腔形成方法。
背景技术
压力传感器以硅薄膜作为压阻膜时，需要在硅基片上通过形成空腔的方式得到硅薄膜。在硅基片上形成空腔的方法有如下几种：1)用KOH腐蚀硅基片的背面形成空腔；2)绝缘体上硅空腔(cavity-SOI)工艺；3)外延空腔工艺。KOH腐蚀工艺从背面做深槽腐蚀，深槽底部残留的硅即形成硅薄膜，由于KOH腐蚀的深槽侧壁呈54度角度倾斜，深槽侧面呈倒梯形，所以管芯的面积比实际所需硅薄膜的面积要大，因此单片产出的管芯数少，成本高。cavity SOI工艺，空腔通过干法腐蚀，管芯面积大大缩小，单片产出管芯数比KOH腐蚀工艺要多，但是因为需要做Si-Si键合，工艺成本高而且产出周期长。外延空腔工艺是表面工艺，工艺过程是先刻深槽，然后通过长外延将顶部封口，工艺过程相比于cavity SOI工艺简单，而且成本低，但由于外延长的硅是多晶硅，所以压阻膜的质量没有单晶硅的质量好。
因此，需要提出一种方法，以解决上述问题。
发明内容
根据本申请的各种实施例提供一种基于深槽腐蚀的空腔形成方法，包括：提供半导体衬底，对所述半导体衬底进行所述深槽腐蚀，以在所述半导体衬底中形成由多个槽构成的阵列，所述阵列中的最外围的槽之间的间距大于所述阵列中的其余的槽之间的间距；对所述半导体衬底进行退火处理，以在所述半导体衬底中形成空腔。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一副或多副附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1A-图1D为根据现有的空腔形成工艺依次实施的步骤所分别获得的器件的示意性剖面图；
图2A-图2C为根据本发明示例性实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图；
图3为图2A中示出的槽201的俯视图；
图4(a)-图4(b)为在图3中示出的槽201的间距D1＝D2和D1＞D2的情况下分别形成的空腔的示意图；
图5为根据本发明示例性实施例的方法依次实施的步骤的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本发明，将在下列的描述中提出详细步骤以及结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
传统的成本较低的硅空腔形成工艺一般包括如下实施步骤：
首先，如图1A所示，提供硅衬底100，硅衬底100中掺杂有p-杂质，通过离子注入工艺在硅衬底100的上部形成n+杂质注入区101。具体为在硅衬底100上形成具有离子注入窗口图案的掩膜之后，通过离子注入工艺在硅衬底100的上部形成n+杂质注入区101，然后，通过剥离工艺去除所述具有离子注入窗口图案的掩膜。
接着，如图1B所示，将硅衬底100浸入浓HF溶液里并在硅衬底100表面加电压通电流，n+杂质注入区101形成孔径比较小的多孔硅，n+杂质注入区101下方的p-掺杂区域形成孔径比较大的多孔硅。
接着，如图1C所示，将硅衬底100从浓HF溶液中取出，在氢气环境下高温退火，在n+杂质注入区101形成的多孔硅融合在一起，而在n+杂质注入区101下方的p-掺杂区域形成的多孔硅形成空腔102。
接着，如图1D所示，在硅衬底100表面外延生长一定厚度的硅层103以满足产品要求。
上述工艺的主要缺点是需要将硅片浸入浓HF中并通电，工艺复杂而且危险，需要使用专门的设备和工艺，成本高。
为了解决现有的硅空腔形成工艺所存在的不足之处，如图5所示，本发明提供了一种基于深槽腐蚀的空腔形成方法，该方法包括:
在步骤501中，提供半导体衬底，对半导体衬底进行深槽腐蚀，以在半导体衬底中形成由多个槽构成的阵列，所述阵列中的最外围的槽之间的间距大于所述阵列中的其余的槽之间的间距；
在步骤502中，对半导体衬底进行退火处理，以在半导体衬底中形成空腔。
根据本发明提出的基于深槽腐蚀的空腔形成方法，可以减小管芯面积，降低工艺难度并减少成本。
为了彻底理解本发明，将在下列的描述中提出详细的结构及/或步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
[示例性实施例]
参照图2A-图2C，其中示出了根据本发明示例性实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图。
首先，如图2A所示，提供半导体衬底200，半导体衬底200的构成材料 中含有硅，例如未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。
接下来，对半导体衬底200进行深槽腐蚀，以在半导体衬底200中形成由多个槽201构成的阵列。作为示例，先在半导体衬底200上形成具有所述阵列图案的掩膜层，再以所述掩膜层为掩膜，蚀刻半导体衬底200以在半导体衬底200中形成由多个槽201构成的阵列，所述蚀刻为常规的干法蚀刻，然后，采用常规的剥离工艺去除所述掩膜层。
槽201的特征尺寸为0.5微米-1.0微米，腐蚀深度为1.0微米-20.0微米，间距为0.5微米-1.0微米。槽201的形貌可以是如图3所示的圆形，也可以是方形或者其它形状。作为示例，如果槽201的形貌为圆形，其特征尺寸是指直径，如果槽201的形貌为方形，其特征尺寸是指对角线。
接着，如图2B所示，对半导体衬底200进行退火处理，以在半导体衬底200中形成空腔202。作为示例，在非氧气环境下(例如在氢气、氮气等环境下)实施所述退火，所述退火的温度为高于800℃。由于高温和非氧气的环境，半导体衬底200中的硅原子发生迁移，最终形成空腔202。
如图3所示，当所述阵列中的最外围的槽201之间的间距D1与所述阵列中的其余的槽201之间的间距D2等同时，在最终形成的空腔202的边缘处会形成如图4(a)所示的缺口204。
为了避免在最终形成的空腔202的边缘处形成如图4(a)所示的缺口204，本发明将所述阵列中的最外围的槽201之间的间距D1设置为大于所述阵列中的其余的槽201之间的间距D2，在实施上述退火处理之后，如图4(b)所示，在最终形成的空腔202的边缘处未形成如图4(a)所示的缺口204。
此外，通过改变构成所述阵列的槽201之间的间距D2的大小，在实施上述退火处理之后，可以形成具有不同特征尺寸的单一空腔202。间距D2和D1均在0.5微米-1.0微米的范围内变化，间距D2越大，退火处理的温度越高，退火处理的持续时间不超过20min。改变间距D2的同时，需调整间距D1，使D1大于D2，以确保在最终形成的空腔202的边缘处不形成如图4(a)所示的缺口204。
接着，如图2C所示，在半导体衬底200上形成外延材料层203，以满足产品的要求，外延材料层203构成材料中含有硅。作为示例，通过常规的外 延生长工艺形成外延材料层203，外延材料层203的厚度为10.0微米-50.0微米，确保空腔202上方具有一定厚度的膜层以作为压力传感器的压阻膜。
至此，完成了根据本发明示例性实施例的方法实施的工艺步骤。与传统工艺相比，根据本发明提出的基于深槽腐蚀的空腔形成方法，可以减小管芯面积，与现有的CMOS工艺兼容，无需增加新的设备，从而降低工艺难度并减少成本。
可以理解的是，本实施例半导体器件制作方法不仅包括上述步骤，在上述步骤之前、之中或之后还可包括其他需要的步骤，其都包括在本实施制作方法的范围内。
作为示例，在半导体衬底200上形成有前端器件，为了简化，图例中未予示出。所述前端器件是指实施半导体器件的后端制造工艺(BEOL)之前形成的器件，在此并不对前端器件的具体结构进行限定。所述前端器件包括栅极结构，作为一个示例，栅极结构包括自下而上依次层叠的栅极介电层和栅极材料层。在栅极结构的两侧形成有侧壁结构，在侧壁结构两侧的半导体衬底200中形成有源/漏区，在源/漏区之间是沟道区；在栅极结构的顶部以及源/漏区上形成有自对准硅化物。
作为示例，栅极介电层包括氧化物层，例如二氧化硅(SiO 2)层。栅极材料层包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种，其中，金属层的构成材料可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物层包括氮化钛(TiN)层；导电性金属氧化物层包括氧化铱(IrO 2)层；金属硅化物层包括硅化钛(TiSi)层。栅极介电层和栅极材料层的形成方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干 变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种基于深槽腐蚀的空腔形成方法，包括：
    提供半导体衬底，对所述半导体衬底进行所述深槽腐蚀，以在所述半导体衬底中形成由多个槽构成的阵列，所述阵列中的最外围的槽之间的间距大于所述阵列中的其余的槽之间的间距；
    对所述半导体衬底进行退火处理，以在所述半导体衬底中形成空腔。
  2. 根据权利要求1所述的方法，其中，在形成所述空腔之后所述方法还包括：
    在所述半导体衬底上形成外延材料层。
  3. 根据权利要求2所述的方法，其中，通过外延生长工艺形成所述外延材料层。
  4. 根据权利要求2或3所述的方法，其中，所述外延材料层的厚度为10.0微米-50.0微米。
  5. 根据权利要求2或3所述的方法，其中，所述外延材料层的材料含有硅。
  6. 根据权利要求1所述的方法，其中，所述槽的特征尺寸为0.5微米-1.0微米。
  7. 根据权利要求1所述的方法，其中，所述槽的腐蚀深度为1.0微米-20.0微米。
  8. 根据权利要求1所述的方法，其中，相邻槽的间距为0.5微米-1.0微米。
  9. 根据权利要求1所述的方法，其中，所述槽的形貌为圆形。
  10. 根据权利要求1所述的方法，其中，所述槽的形貌为方形。
  11. 根据权利要求1所述的方法，其中，在非氧气环境下实施所述退火。
  12. 根据权利要求11所述的方法，其中，在氢气环境下实施所述退火。
  13. 根据权利要求11所述的方法，其中，在氮气环境下实施所述退火。
  14. 根据权利要求1或11所述的方法，其中，所述退火的温度为高于800℃。
  15. 根据权利要求1所述的方法，其中，通过改变构成所述阵列的槽之间的间距的大小，在实施所述退火处理之后，形成具有不同特征尺寸的单一 空腔。
  16. 根据权利要求15所述的方法，其中，所述槽之间的间隙越大，所述退火处理的温度越高。
  17. 根据权利要求1所述的方法，其中，构成所述半导体衬底的材料中含有硅。
  18. 根据权利要求1所述的方法，其中，所述深槽腐蚀为干法刻蚀。
  19. 根据权利要求1所述的方法，其中，所述退火处理的持续时间不超过20min。
  20. 根据权利要求1所述的方法，其中，所述半导体衬底上形成有前端器件，所述前端器件包括栅极结构。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323056A (zh) * 1999-08-31 2001-11-21 株式会社东芝 半导体衬底及其制造方法
JP2012222092A (ja) * 2011-04-07 2012-11-12 Fuji Electric Co Ltd 半導体基板または半導体装置の製造方法
CN105428218A (zh) * 2015-12-10 2016-03-23 杭州士兰微电子股份有限公司 空腔形成方法以及半导体器件结构
CN105895501A (zh) * 2014-05-05 2016-08-24 英飞凌技术德累斯顿有限责任公司 晶片、用于处理晶片的方法、以及用于处理载体的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266613A (ja) * 1999-08-31 2007-10-11 Toshiba Corp 半導体基板および半導体装置
JP4823128B2 (ja) * 1999-08-31 2011-11-24 株式会社東芝 半導体基板の製造方法
EP1770055B1 (en) * 2005-09-28 2008-05-28 STMicroelectronics S.r.l. Process for manufacturing thick suspended structures of semiconductor material
JP5541069B2 (ja) * 2010-10-15 2014-07-09 富士電機株式会社 半導体装置の製造方法
JP5909945B2 (ja) * 2011-09-12 2016-04-27 富士電機株式会社 半導体基板の製造方法および半導体装置の製造方法
US8716050B2 (en) * 2012-02-24 2014-05-06 The Hong Kong University Of Science And Technology Oxide microchannel with controllable diameter
US9136328B2 (en) * 2012-10-09 2015-09-15 Infineon Technologies Dresden Gmbh Silicon on nothing devices and methods of formation thereof
CN105036059B (zh) * 2015-06-24 2017-01-25 上海芯赫科技有限公司 一种电容式mems传感器的加工方法及传感器结构
CN106365106B (zh) * 2016-09-23 2018-09-04 杭州士兰集成电路有限公司 Mems器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323056A (zh) * 1999-08-31 2001-11-21 株式会社东芝 半导体衬底及其制造方法
JP2012222092A (ja) * 2011-04-07 2012-11-12 Fuji Electric Co Ltd 半導体基板または半導体装置の製造方法
CN105895501A (zh) * 2014-05-05 2016-08-24 英飞凌技术德累斯顿有限责任公司 晶片、用于处理晶片的方法、以及用于处理载体的方法
CN105428218A (zh) * 2015-12-10 2016-03-23 杭州士兰微电子股份有限公司 空腔形成方法以及半导体器件结构

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